DE102017103310A1 - SUBSTRATE OF AN ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THEREOF - Google Patents

Abstract

Method for producing a wafer. The method includes providing a wafer having a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance that selectively configures a circuit element in at least one of the plurality of semiconductor device structures is provided on a selected portion of the wafer.

Description

FIELD OF THE INVENTION

The present disclosure relates to the manufacture of electronic devices, such as semiconductor devices, for example, integrated circuit chips.

BACKGROUND

Nowadays, integrated circuit sensors can require a level of precision that can not be achieved with current ultra-large scale integration (ULSI) manufacturing techniques.

A conventional approach is to measure device deviations with respect to a target value after wafer fabrication has been completed and compensate for the deviations by additional processing. Depending on the device type, different solutions are currently used. For example, via security concepts with a fine tuning of the electrical properties of the product after its final wafer-level electrical test, digital coding is applied. In another example, current sensors are embedded in many ICs to ensure constant monitoring and protection of the device during turn-on or malfunction of the circuit. At least some of the effects of implementing the teachings disclosed herein are as follows: An alternative to the conventional laser fuses is provided, which allows the use of fuses where a conventional laser fuse can not be used, thereby opening up a wider range of applications. During wafer processing, the techniques disclosed herein allow to make chip-selective modifications that are provided on a wafer, whereby individual chips can be made although lithography masks are used that are designed to produce multiple non-individual chips on the same wafer.

At least some of the effects associated with the introduction of post-processing of printed structures can be as follows: Conventional process technologies, according to some implementations, can be easily adapted or completed to perform digital encoding without the need for laser tools. Thus, negative effects such as alignment problems typically associated with use of a conventional laser can be avoided.

In the manufacture of electronic devices, electronic devices are manufactured using wafers. Many wafers may form part of a batch of wafers having a lot number to uniquely identify the wafer lot. Wafers of the wafer batch can be used to make multiple dies. The wafers may have wafer numbers to uniquely identify the wafers of a batch. Each die may form the basis for an electronic device provided, for example, for providing a semiconductor chip. Each of the die may have an identification number, sometimes called a chip identifier, to uniquely identify die's of a wafer. After separating the dies from the wafer, for example, if a product based on the separated die is inspected prior to initial operation of the product, but possibly even after many years of use of the product, sometimes a need may arise for the identity of this semiconductor device, d. H. to find out where this semiconductor device came from.

BRIEF DESCRIPTION OF THE DRAWINGS

A full understanding of the present invention may be obtained by reference to the accompanying drawings, taken in conjunction with the following detailed description:

1 FIG. 12 illustrates a flowchart of a method according to some embodiments. FIG.

2A and 2 B FIG. 4 illustrates a perspective view of a configurable circuit element structure according to some embodiments. FIG.

3A and 3B FIG. 12 illustrates cross-sectional views of a configurable circuit element structure according to some embodiments. FIG.

4 FIG. 12 illustrates a cross-sectional view of a configurable circuit element structure according to some embodiments. FIG.

5 FIG. 12 illustrates a cross-sectional view of a configurable circuit element structure according to some embodiments. FIG.

6 FIG. 12 illustrates a cross-sectional view of a configurable circuit element structure according to some embodiments. FIG.

7 FIG. 12 illustrates a schematic plan view of a wafer that includes a plurality of semiconductor device structures according to some embodiments.

8A FIG. 4 illustrates a top view of an exemplary first configurable circuit element structure according to some embodiments. FIG.

8B FIG. 4 illustrates a top view of another example of the first configurable circuit element structure according to some embodiments. FIG.

9A FIG. 4 illustrates a top view of an exemplary second configurable circuit element structure according to some embodiments. FIG.

9B FIG. 4 illustrates a top view of another example of the second configurable circuit element structure according to some embodiments. FIG.

10 FIG. 12 illustrates a schematic view of a plant for use in the manufacture of semiconductor devices according to some embodiments. FIG.

11 FIG. 12 illustrates a flowchart of a method of use in the manufacture of semiconductor devices according to some embodiments. FIG.

12A and 12B FIG. 4 illustrates a perspective view of a configurable circuit element structure according to some embodiments. FIG.

13A and 13B FIG. 12 illustrates a top view of a configurable circuit element structure according to some embodiments. FIG.

14A and 14B FIG. 12 illustrates a top view of another configurable circuit element structure according to some embodiments. FIG.

15 FIG. 12 illustrates a flowchart of another method according to some embodiments. FIG.

16 FIG. 12 illustrates a schematic plan view of a wafer that includes a plurality of semiconductor device structures according to some embodiments.

For the sake of clarity and brevity, like elements and components in all figures bear the same designations and reference numerals.

DETAILED DESCRIPTION

Hereinafter, embodiments, implementations and related effects will be disclosed with reference to the accompanying drawings.

1 FIG. 12 illustrates a flowchart of a method according to some embodiments. The method may be used in the fabrication of semiconductor device chips. For example, in some embodiments, each of the semiconductor device chips may include one or more integrated circuits. In some embodiments, the semiconductor device comprises a power transistor. In some embodiments, the semiconductor device includes a sensor. In some embodiments, at least two of the aforementioned elements are combined in the semiconductor device chip.

In S110, the method includes providing a wafer comprising a plurality of semiconductor device structures. The wafer may generally be provided for front-end processing as known in the art. In some embodiments, the semiconductor device structures form part of an integrated circuit. The semiconductor device structures may be configured to form passive circuit elements such as a resistor, an inductor, and a capacitor. The semiconductor device structures may also be configured to form active circuit elements such as transistors. When the semiconductor device structure is provided to form an integrated circuit, it will be understood by those skilled in the art that a large number of passive circuit elements and active circuit elements may be included in a single semiconductor device structure. In one example, the semiconductor device structure is provided to be inserted into a current sensor die product.

In S120, the wafer is processed and a layer or layers including, for example, a layer of metal structures and / or a dielectric layer are formed to provide the plurality of semiconductor device structures. At least one effect may be to form with each semiconductor device structure a substantially similar product, for example, an integrated circuit of the same type. The method may also include preparing the wafer for selectively receiving a conductive substance for some or each of the semiconductor device structures on the wafer, depending on the products to be manufactured from the wafer, to form a configured circuit element on the wafer. As will be shown and discussed below, the semiconductor device structures are thus fabricated to include structures of configurable elements that impart themselves to a configuration or modification according to the techniques disclosed herein. For example, a single configurable circuit element can be used when configuring digital and / or analog configurable elements such as tuning elements or when modifying digital and / or or analog configurable elements.

In some embodiments, each semiconductor device structure includes a first portion configured to provide a digital configurable element that is to form part of the integrated circuit. In some embodiments, each semiconductor device structure includes a second portion configured to provide an analog configurable element that is also to form part of the integrated circuit. In some embodiments, the semiconductor device structure includes both the first portion and the second portion. Although, for simplicity, only a digital configurable element and an analog configurable element will be referred to herein, it is to be understood that multiple configurable elements may be included per semiconductor device structure. It is understood that the configurable element provided as a tuning element serves only as a component. In another example, a particular portion of the semiconductor device structure may be configured to perform a particular signal processing or other function, and may include the switching element to be formed in accordance with the present disclosure, as discussed below with respect to configuring the tuning element , For example, in some embodiments where the semiconductor device structure is to form an integrated circuit, the integrated circuit includes a first circuit portion and a plurality of second circuit portions, wherein the configurable circuit element may be configurable to connect the first circuit portion to one or a selected one of the plurality electrically connect from second circuit sections.

It is understood that the act of providing the wafer from the front-end processing in S110 may include conventional front-end processing steps to form the plurality of semiconductor device structures. Although the action of providing the wafer in S110 and the action of processing the wafer in S120 to form the first portion and the second portion are separately discussed as being performed one after another, the order may be reversed, or an action can form part of the other action. In particular, the action of forming the first circuit portion and / or the second circuit portion may precede or be included in the action of providing the wafer. For example, if the semiconductor device structure is to be inserted into the current sensor die product, the current sensor may be configured to include a meandering trace structure that forms a resistor. The resistor may be made of a substance having a lower conductivity than another conductor material. The resistor may be embedded in various layers of the semiconductor device structure. In some implementations, the resistor may be configured as a tuning element that is configurable to compensate for variations in shunt resistance due to variations in front-end processing to the full extent when the configurable element is configured.

In S130, the method includes testing the semiconductor device structure formed on the wafer. Although testing for a semiconductor device structure or a selection of semiconductor device structures may be limited to, for example, selected ones of the integrated circuits, it is understood that the testing is performed for each of the semiconductor device structures formed on the wafer. It will also be understood that testing may be limited to a selected functionality and / or portions of the semiconductor device structure. For example, if the semiconductor device structure is to be inserted into the current sensor die product, the testing may include a measurement of shunt resistance.

For example, in S140, the test results are processed with a data processor of a test apparatus. For example, when the semiconductor device structure is to be inserted into the current sensor die product, the processing may include comparing the measured shunt resistance values to a target resistance value. The data processing may be performed to calculate a desired tuning resistor value that depends on the difference between the target resistor value and the measured shunt resistor value in the device under test. The data processing may be performed, for example, to identify one or more locations where the meandering trace structure is to be bridged by a conductive bridge that effectively shorts the bridged meander or open loop of the meandering structure. It is understood that different shunt resistance values can be measured from one semiconductor device structure to another on the same wafer, and correspondingly, different locations for bridging the meandering wiring pattern may result. In another example, the data represents information that is individually associated with a semiconductor device such as the semiconductor device that is to receive the semiconductor device structure under test. It can for example be a digital representation of the measured Value are determined. In some embodiments, the information is based on the test results. In some embodiments, the locations for selectively providing the substance on the selected portion of the wafer encode the information associated with the semiconductor device structure under test. At least one effect may be that as the wafer is further processed, digital printing methods may be used that allow for the application of flexible and / or individual print files and / or structures that can be individually generated for each chip based on the measurement data.

In S150, based on a test result, a substance stored in, for example, a container or channel of a dispensing tool is provided on a selected portion of the wafer to selectively configure the configurable element of the corresponding semiconductor device structure. In some implementations, a smallest dimension of a diameter or cross section of the area covered by the substance on the selected portion of the wafer is about one hundred micrometers or less than one hundred micrometers, for example, about ten to twenty micrometers, for example, the semiconductor device Power transistor is. In some implementations, a smallest dimension of a diameter or cross-section of the area covered by the substance on the selected portion of the wafer is about one micrometer to ten micrometers, for example, the semiconductor device is a power transistor, and wherein the substance is for use with Connecting a sensor element to the power transistor is used. In some implementations, a minimum extension of a diameter or cross-section of the area covered by the substance on the selected portion of the wafer is about one micron or less than one micron. In one implementation, for example, an approximately rectangular region of about 2 μm x 130 nm is covered; In another example, an approximately circular area is covered that has a diameter of approximately 1 μm, 500 nm, 250 nm, or 130 nm. Thus, to give an example of a digital configurable element, the digital configurable element may be configured to represent the measured value according to the digital representation of the measured value determined during processing of the test result. In some embodiments, at the time of providing the substance, the substance is at least one selected from a group consisting of a liquid, a suspension in a liquid, and a paste. In some embodiments, the substance comprises a metal. The liquid may be, for example, a metal that is heated above the melting temperature of the metal. In another example, the liquid may be a conductive resin, for example, a resin mixed with a conductive particle powder to provide a conductive liquid. In another embodiment, the substance is a conductive paste. The materials to be deposited may include, but are not limited to, metal inks, such as inks containing nanoparticles, or precursor metal chemical inks resulting in electrically conductive layers and / or structures. Depending on a desired resistivity of the added structure, pure metals selected from a group consisting of, for example, Cu, Ag, Au, Ni, Sri, and In, may be applied, or systems specific to specific alloys, e.g. , B. mixtures of the aforementioned metals. Other electrically conductive materials such as metal oxides, conductive organic polymers or mixtures thereof with metal particles can also be used either alone or as an additive.

The action of printing the conductive substance may include heating the liquid, for example while the liquid is stored in a container before the liquid is dispensed so that the liquid is kept liquid. In some embodiments, the method may include expelling the substance from the container. In some embodiments, the method includes providing the fluid in a lumen, sponge, or other container connected to the dispenser. For example, the dispenser may be provided as a nozzle. The act of ejecting the substance from the container may include increasing the pressure in the cavity by moving a cavity wall to reduce a void volume and / or by heating the liquid in the cavity and expelling the liquid through the dispenser include. In some embodiments, the liquid is dispensed according to control signals provided to an actuator that can deform the container. The control signals may be provided to direct the dispensed substance to the selected portion (s) on the wafer while keeping other portions free of the dispensed substance. In some embodiments, the method includes electrically charging the substance ejected from the container and controlling an electric field to conduct the substance. Accordingly, some embodiments include selectively supplying printed structures to the semiconductor device structure after measuring the device. At least one effect may be that structures can be formed for individual chips to achieve results that individually optimized for selected chips. Available printing technologies include, but are not limited to, ink jet printing and digitally controllable processes such as jet spraying or electrospray.

For example, if the substance is a paste, the dispenser may be provided as an extruder.

In S160, the wafer is treated to fix the conductive substance. In some embodiments, the substance effectively configures the circuit element as a trace element. In some embodiments, the method further comprises curing the substance. Thus, a post-pressure treatment step can be used to convert the deposited material into a final desired shape of conductive structure. This may be a drying step for removing a solvent and / or a sintering step. Energy may be provided in various ways: baking the wafer, for example, in an oven, and / or treating the wafer surface with radiation may be used. For example, if the liquid is a resin, the wafer may be treated with radiation of a predetermined spectrum, such as infrared radiation or ultraviolet radiation, as needed for curing the particular resin used in the process. Some implementations use high-energy Xe flash lamps or laser radiation. In one example, where the liquid is a metal, the wafer is cooled below the melting point of the material. In some embodiments, the action of curing the substance comprises curing the substance. An effect may be that the substance becomes solid. In another example, where the substance is a paste, the wafer may be heated to bake the paste. It is to be understood that the action of hardening the substance to solidify may include vaporizing a part of the substance such as evaporation of a solvent contained in the substance. The printing may be applied as a shorting connection in a meander winding structure, for example, on an unstructured support surface, or the printing may be provided at predetermined locations having guide structures, such as cavities and / or trenches, capable of being filled with an ink ,

In S170, the method may further include selectively providing a dielectric at least on the selected portion (s) of the wafer that received the conductive substance. At least one effect may be that the dielectric passivates the newly formed tuning element. In some implementations, further process pressure steps may be performed to selectively provide deposition of a passivating substance.

Thus, in some implementations, completion of the wafer's front-end processing is determined at S180.

In S190, the wafer may be subjected to back-end processing, for example, singulation may be performed to separate the semiconductors from the wafer comprising the configurable element (s) described above. individually configured.

In one aspect, the invention includes a method of use in manufacturing semiconductor devices that includes, as described above, testing the wafer. The wafer may include a plurality of semiconductor device structures in at least one first structural layer on the wafer. The method may also include adding another pattern layer to the wafer, completing and / or adding further circuit elements. In some implementations, the action of adding another structure layer includes a lithography process. The method includes, between the actions of testing the wafer and adding another pattern layer to the wafer, selectively depositing a substance to a selected location on a selected portion of the wafer that includes a semiconductor device structure. The method may include selectively providing the substance on the wafer to obtain a modified wafer. The modified wafer has at least one modified selected portion based on the test result.

Accordingly, if it is determined that further front-end processing is necessary to complete the semiconductor device structures on the wafer, in some implementations the wafer may again undergo the above-described processes in S180 providing a further structural layer on the wafer.

In summary, in some implementations, a method is provided that includes: testing a semiconductor device structure intended to be incorporated into a chip; on the basis of this checking, selecting a pattern of connections to be printed on the chip; and printing the connection pattern itself. After the step of printing, depending on the kind of the printed material, an after-treatment step may be aimed at be applied to convert the deposited material into an electrically conductive material. At least one effect may be selectively establishing one or more circuit connections, the selection depending on the characteristics of the individual connections determined in testing the semiconductor device structure.

An example of an embodiment may be: forming a broken conductive line on a semiconductor device structure for use in a chip; Opening a window surrounding this interruption in the insulating layer covering that line; and at least partially filling this window with a conductive ink using a printing technique such that the broken halves are electrically connected.

In some embodiments, the action of processing the wafer in S120 includes forming a cavity suitable for receiving this substance. An example of one embodiment is: forming a conductive line in a conductive layer, such as a metal layer, with the conductive line formed with a break. The embodiment may further include providing an insulating layer over the conductive layer and opening a window in the insulating layer covering the conductive layer, the window being provided to expose the interruption. 2A FIG. 12 illustrates a perspective view of a configurable circuit element structure. FIG 200 according to some embodiments. The configurable circuit element structure 200 For example, it may come from performing the processing steps described above. On a substrate 210 be a first metal line 221 and a second metal line 222 provided. The first metal line 221 and the second metal line 222 are coaxially aligned so that a terminal end 251 the first metal line 221 a terminal end 252 the second metal line 222 facing, which are separated by a gap. In some embodiments, the gap is about as wide as the width of the first metal line 221 and / or the width of the second metal line 222 , Thus, the group forms the first metal line 221 , the gap and the second metal line 222 a broken conductor line 220 , On the broken conductor track 220 In the example, an insulation layer 230 be deposited. In the insulation layer 230 becomes over the broken trace line 220 a window 240 opened so that the terminal end 251 the first metal line 221 and the terminal end 252 the second metal line 222 in the window 240 are exposed to form a pair of conductive contact webs. 2 B FIG. 12 illustrates a perspective view of a configurable circuit element structure. FIG 200 in relation to the above 2A was discussed. In the window 240 extends at the interruption of the interrupted conductor line 220 a lump of a conductive substance substantially in the gap between the terminal ends 251 . 252 centered to at least a portion of both terminal ends 251 and 252 cover, and in this way the of the gap between the terminal ends 251 . 252 caused interruption bridged to the first metal line 221 and the second metal line 222 electrically connect with each other.

In one aspect, the invention includes a die. The die includes a matrix of dielectric lands electrically separating two conductive nodes associated with the respective dielectric lands. The die may also include one or more conductive lumps, for example, a droplet or lead, each placed on a different one of the dielectric contact lands to establish an electrical connection between the two conductive nodes associated with the dielectric land, wherein one surface of the conductive lump such as a droplet or a conduit having a convex cross section. In some embodiments, the configurable circuit element at the selected location in the first semiconductor device structure elevates convexly over a plane on the contact land provided with the first semiconductor device structure. Although a circuit element is referred to as being "configurable", it will be understood that once the conductive connection is secured to electrically bridge the gap between two conductive nodes, the configurable circuit element is actually "configurable".

3A and 3B 12 depict a cross-sectional view of a configurable circuit element structure in accordance with some embodiments substantially as shown in FIG 2 B to be shown. 3A represents a view along a longitudinal axis of a first metal line 321 and a second metal line 322 that is on a substrate 310 be deployed and through a gap 323 are separated from each other to form a broken trace. On the metal becomes a dielectric layer 330 educated. The dielectric layer 330 however, is removed to form a window, with a terminal end portion of the first metal line 321 and a terminal end portion of the second metal line 322 not through the dielectric layer 330 are covered. In this example, a lump of a conductive substance in the window is applied to the substrate, causing the gap 323 fills and also a marginal portion of the first metal line 321 and a marginal portion of second metal line 322 covering to establish a conductive line. Due to the surface tension, the lumps of the conductive substance 360 a convex surface 361 , The convex surface 361 the lump 360 is by looking up 3B better appreciated, which is a cross-sectional view in a plane perpendicular to the longitudinal axis in a portion of the gap 323 represents. In this cross-sectional view, the first metal line 321 and the second metal line 322 not to be seen. The walls of the dielectric layer 330 are to be seen as they have the window on the substrate 310 form.

4 FIG. 12 illustrates a cross-sectional view of a configurable circuit element structure according to some embodiments, similar to FIG 3A and 3B shown example. In this example, a lump of a conductive substance becomes 460 in a tub 470 delivered in the substrate 410 is trained. The surface tension of the conductive substance 460 causes the lump to have a convex surface 461 having. The tub 470 For example, it may have the size of a via interconnecting interconnect lines (not shown) formed in two different metal layers.

5 FIG. 12 illustrates a cross-sectional view of a configurable circuit element structure according to some embodiments. In this example, a lump of a conductive substance becomes 560 in a tub 570 delivered in the substrate 510 is trained. The surface tension of the conductive substance 560 is smaller than the capillary force, which causes the conductive substance 560 on the wall of the tub 570 "Climbs up". Thus, the conductive substance 560 a concave surface 561 on.

6 FIG. 12 illustrates a cross-sectional view of a configurable circuit element structure according to some embodiments. As in the examples of FIGS 4 and 5 is shown in this example becomes a lump of a conductive substance 660 in a tub 670 provided in a substrate 610 is trained. Thereafter, a part of the substance that forms the lump escapes; For example, a solvent evaporates as a carrier of the conductive substance 660 is used and leaves the rest of the lump with a reduced volume. While the conductive substance is on the walls of the tub 670 sticks, a central portion of the lump drops off to a concave surface 661 to build.

In one aspect, the invention includes a mask for use in wafer lithography. The mask includes a pattern configured to project a metal structure onto the wafer. In some embodiments, the pattern includes a plurality of identical pattern sections. Each of the identical pattern sections comprises a matrix of paired conductor track terminal ends, the terminal ends each comprising a round tongue tip. The mask may be used in the method of manufacturing semiconductor devices described above with reference to FIG 1 was discussed.

7 provides a schematic plan view of a wafer 700 illustrating a variety of semiconductor device structures 711 . 712 . 721 , ..., 731 , ..., 741 . 742 according to some embodiments. It goes without saying that, though in 7 twelve semiconductor device structures, this number is for illustrative purposes only, and that the wafer may include any other number of semiconductor device structures that fit on the wafer, which is at least one area of the wafer available for the die to be fabricated, and of one face of each of the dies to be made from the wafer. The semiconductor device structures 711 , ..., 742 In some embodiments, each is configured to form part of a separate die, which in turn is incorporated into a separate semiconductor device. In some embodiments, the resulting semiconductor devices are intended to be of the same type. In these embodiments, the semiconductor device structures are 711 , ..., 742 as long as they have not been configured according to the methods disclosed herein. In other embodiments (not shown), the semiconductor device may be provided for various types. At the in 7 As shown, the semiconductor devices are provided as integrated circuits, but it is to be understood that the embodiments disclosed herein may be practiced to make other semiconductor devices that are not integrated circuits. In these embodiments, the structures of the integrated circuits may vary with each other. The structures of integrated circuits 711 , ..., 742 each comprise at least one of the circuit element structure sections configured in accordance with the teachings of the present disclosure, described below with respect to FIGS 8A and 8B , the 9A and 9B , the 13A and 13B and the 14A and 14B to be discribed.

In a further aspect, the invention includes a wafer comprising: a plurality of similar semiconductor device structures, each having a plurality of circuit elements, wherein a passive circuit element provided at a selected location between a first pair of conductor terminal ends in a first semiconductor device structure; of a another passive circuit element provided at the selected location between a second pair of conductor terminal ends in a second semiconductor device structure, characterized in that the passive circuit element in the first semiconductor device structure comprises a conductive substance, while the other passive circuit element comprises no conductive substance. At least one effect may be that one passive circuit element is more electrically conductive than the other passive circuit element. In other words, the other passive circuit element has a greater resistance than the first circuit element.

In another aspect, the invention includes a die. The die includes a plurality of dielectric lands, each dielectric land electrically separating two conductive nodes associated with the dielectric land. The die also includes a conductive substance that is digitally distributed across the plurality of dielectric lands. Wherever the conductive substance is present on a dielectric land and in contact with the conductive nodes associated with the dielectric land, the conductive substance may establish an electrical connection between the conductive nodes. In some embodiments, the plurality of dielectric contact lands are arranged in a matrix. In some embodiments, the distribution of electrical connections across the dielectric lands is a bit sequence. In some embodiments, for each dielectric land, one node of the two conductive nodes is connected to a same common node for all of the plurality of dielectric lands, while the other node the two conductive nodes are connected, for example, to a sensor element associated with the dielectric contact land.

8A FIG. 4 illustrates a top view of an exemplary first configurable circuit element structure according to some embodiments included in a first exemplary semiconductor device structure, which in the example is the structure of the integrated circuit. FIG 711 of the wafer 700 in 7 is. The first configurable circuit element structure is considered a matrix 800 of the groups 810 . 820 . 830 , each provided as above in relation to the 2A and 2 B 5, includes a pair of trace terminal ends separated by a gap to be digitally configurable. The trace terminal ends face each other to form a broken trace. When the wafer has been processed according to the method described herein, some of the conductive line terminal pairs are electrically connected by a conductive substance, thereby actually configuring the first configurable circuit element. For example, the conductor terminal ends are 811 . 812 of the first couple 810 through a lump 816 the conductive substance, whereas a second pair of conductor terminals terminate 820 by a distance between a first terminal end 821 and a second terminal end 822 is interrupted. It goes without saying that on the same wafer 700 a pattern of connected and broken pairs of contact bars in the matrix 800 may be different from one semiconductor device structure to another.

8B FIG. 4 illustrates a top view of another example of the first configurable circuit element structure used in an exemplary second integrated circuit structure 712 of the wafer in 2 is included. While, for example, the first in 8A shown configurable circuit element structure, which forms part of the first integrated circuit structure 711 forms a pattern "010101" (where "0" represents "broken" and "1" represents "connected" or "bridged"), the first in FIG 8B shown configurable circuit element structure, which forms part of the second integrated circuit structure 712 forms a different pattern (in this example "011010"). According to the present disclosure, as for example with respect to the in 1 A method has been discussed, a test on the first integrated circuit structure 711 and the pattern "010101" of the first configurable circuit element structure forming part of the first integrated circuit structure 711 can be based on a result of this test. As the test, when connected to the second integrated circuit structure 712 may have provided a different result, the pattern formed with the array of contact lands of the first configurable circuit element structure may also form part of the second integrated circuit structure 712 forms different from the pattern associated with the first integrated circuit structure 711 is provided (as in 8B will be shown).

9A FIG. 4 illustrates a top view of an exemplary configurable circuit element structure included in the first integrated circuit structure. FIG 711 of the wafer in 7 is included. The second circuit element structure includes an arrangement 900 a conductor line coming from a first node 901 to a second node 902 runs and between the first node 901 and the second node 902 meanders to be analog configurable. The conductor line forms meandering loops 910 . 920 , ..., 960 , Between the branches 911 and 921 the loop 910 will according to the above described method, a first lump of a conductive substance 916 provided the branches 911 and 921 short circuits, which actually configures the second configurable circuit element. Similarly, between the branches 921 and 931 the loop 920 a second lump of a conductive substance 926 provided the branches 921 and 931 shorts. At least one effect may be that a resistance of the meandering trace is reduced due to the short circuits because the length of the current path between the first node 901 and the second node 902 is reduced. An effect may be that an inductance and / or a capacitance of the conductor line are changed. According to the present disclosure described above, for example, with respect to the in 1 The method illustrated examines the first integrated circuit structure 711 and the presence and position of the first lump of conductive substance 916 and the second lump of the conductive substance 926 , may be based on a result of this test. As the test, when connected to the second integrated circuit structure 712 Also, the presence and position of the lumps of conductive substance provided to effectively shorten the meandering trace could also be different than the presence and position associated with the first integrated one circuit structure 711 to be provided.

9B FIG. 12 illustrates a top view of another example of the second configurable circuit element structure included in the second integrated circuit structure. FIG 712 of the wafer in 2 is included, the arrangement 900 the conductor line the same as in 9A is. However, the configuration of the second configurable circuit element structure is different: While the in 9A shown second configurable circuit element structure 900 forming part of the first integrated circuit structure 711 forms, two lumps 916 and 926 which are set to provide two shorts in the meandering wiring, the second in FIG 9B shown configurable circuit element structure, which forms part of the second integrated circuit structure 712 forms, three lumps 916 . 926 and 936 which are set to provide three shorts in the meandering trace. In accordance with the present disclosure, testing may be performed on the first integrated circuit structure 711 be executed and the distribution pattern of lumps 916 and 926 the second configurable circuit element structure forming part of the first integrated circuit structure 711 can be based on a result of this test. As the test, when connected to the second integrated circuit structure 712 Also, the distribution pattern of the lumps formed on the meandering trace line of the second configurable circuit element structure may be part of the second integrated circuit structure 712 forms to configure the same (as in 9B ) may be different from the pattern associated with the first integrated circuit structure 711 provided.

10 FIG. 12 illustrates a schematic view of a plant for use in the manufacture of semiconductor devices according to some embodiments in an aspect encompassed by the invention. FIG. In some embodiments, the plant may include a fixture 1010 which is configured to be a wafer 700 to wear. As described above, the wafer may have a variety of semiconductor device structures 711 . 721 , ..., 742 include.

In some embodiments, the plant comprises a printing unit 103 , which is configured to print a substance on the wafer. In some embodiments, the printing unit comprises 1030 a cavity or other container to receive a substance for printing. The cavity may be configured to increase pressure within the cavity. For example, the cavity may be configured to reduce the void volume and / or to heat the substance in the cavity. In some embodiments, the printing unit comprises 1030 a dispenser 1032 such as a nozzle configured to eject a liquid or an extruder configured to release a paste from an opening. In some embodiments, the substance may be conductive. The substance may be liquid or contained in a liquid, or the substance may be a paste or contained in a paste. The printing unit may be provided, for example, as an ink jet printer. Accordingly, in some embodiments, the substance is provided as an ink.

In some embodiments, the system includes a test unit 1040 , which is configured to perform tests on the wafer 700 perform. In some embodiments, the test unit is 1040 configured to generate wafer inspection data.

In addition, the system can be a control unit 1050 include. In some embodiments, the control unit is 1050 for a data exchange with the holding device 1010 , with the printing unit 1030 and / or with the test unit 1040 connected. The control unit 1050 may be configured to process the wafer inspection data. The control unit can be configured to the printing unit 1030 and / or the test unit 1040 Provide control signals, wherein in some examples the control signals may be based on the wafer inspection data. In some embodiments, the control unit is 1050 configured to control a driver (not shown) and / or other functional units included in the test unit 1040 are included to inspections on the wafer 700 and to generate test data and to acquire measurement data representing the measurement signals received from the test unit 1040 be recorded. In some embodiments, the control unit is 1050 configured to a driver (not shown) of the holding device 1010 to steer to the wafer 700 on the holding device 1010 relative to the printing unit 1030 to move. In some embodiments, the holding device 1010 be driven to rotate, for example, about the rotational symmetry axis of the holding device or a central axis. In some embodiments, the control unit is 1050 configured by a driver of the printing unit (not shown) 1030 so control that the dispenser 1032 relative to the holding device 1010 for example, along at least one of the X, Y axes of a translating motion and / or along the Z axis of a vertical motion relative to the fixture 1010 is moved. At least one effect may be that the control unit 1050 the printing unit 1030 and / or the holding device 1010 can control the substance from the dispenser 1032 on selected sections on the wafer 700 leave.

In one variation, the system may be configured for use in fabricating semiconductor devices to deliver etchants. The system includes a printing unit configured to print an etching substance on selected portions of a wafer. In some embodiments, the printing unit is provided as an ink jet printer and the etching substance is provided as an ink. As above regarding 10 The system may also include a test unit configured to generate wafer inspection data and a controller configured to process the wafer inspection data and to provide control signals to the printing unit based on the wafer inspection data.

In one aspect, the invention includes a method of use in fabricating semiconductor device chips. The method includes providing a wafer having a plurality of semiconductor device structures. In some embodiments, the method includes configuring selected portions of the wafer to receive a liquid. In some embodiments, the act of configuring the wafer includes forming the wafer surface with a recess to receive the liquid. In some embodiments, the action of selectively providing the liquid on the selected portion of the wafer encodes the information associated with the tested semiconductor device structure on the wafer. The method includes testing a semiconductor device structure. In some embodiments, the information is based on the test results. In some embodiments, the action of configuring the wafer to pick up the liquid is performed prior to an action of checking the at least one semiconductor device structure. The method includes selectively altering a circuit element of the semiconductor device structure based on a test result by providing the liquid on the selected portions of the wafer. In some embodiments, the liquid comprises an etchant. In some embodiments, the method includes etching the at least one circuit element. In some embodiments, the circuit element is a conductive trace element. Some embodiments of the method include selectively providing a dielectric on the selected portion of the wafer that passivates at least one altered circuit element.

Some embodiments of the method include ejecting the liquid from a container, electrically charging the liquid, and controlling an electric field to conduct the liquid. Some embodiments of the method include providing the liquid in a cavity having a nozzle. The method may include increasing the pressure within the cavity. In some embodiments, the action of increasing the pressure includes decreasing a void volume and / or heating the fluid within the void. The method may include ejecting the liquid through the nozzle.

In some embodiments, each semiconductor device includes an integrated circuit that includes a first circuit portion and a plurality of second circuit portions. In some embodiments, the modified circuit element prevents the first circuit section from being electrically connected to a selected one of the plurality of second circuit sections.

11 FIG. 12 illustrates a flowchart of a method of use in the manufacture of semiconductor devices according to some embodiments in another aspect encompassed by the invention. FIG. The method in S1110 includes providing a wafer, such as the one disclosed in U.S. Pat 7 shown wafers 700 who is a variety of Semiconductor device structures has. For example, each of the semiconductor device structures is intended to be incorporated into another product of an integrated circuit chip IC1, IC2, IC3, ..., ICN. However, rather than establishing connections to individually configure the semiconductor device structures, as described above, in a variant of the method, described below, the connections are broken to configure the configurable circuit element structures included in the semiconductor device structures. Here, a configurable circuit element structure that is prepared to be interrupted may also be referred to as a fuse structure, a fuse circuit, or a fuse for short.

In S1120, the method includes forming semiconductor circuit structures, for example, the integrated circuit structures ICI, IC2, IC3, ..., ICN in the layers of the wafer. The structures may include a configurable circuit element structure, that is, structural elements of at least one tuning element in one or more of the semiconductor device structures. For example, the integrated circuit structures IC1, IC2, IC3, ..., ICN may each comprise a matrix of contact land patterns. In some embodiments, the method includes configuring selected portions of the wafer to receive a liquid. The selected portions, in some embodiments, are those portions that contain the configurable circuit element structure. In some embodiments, the act of configuring the wafer includes forming the wafer surface with a recess to receive the liquid. In some implementations, guide structures are formed on the wafer, for example cavities and / or trenches, that can be filled with an etching solution. In some embodiments, the guiding structures are configured to form a self-aligning system, such as a funnel or a concave basin, wherein an effect of the etching solution received on or in a feature is accounted for for a wider spread of the etching solution. At least one effect may be to improve accuracy of the etching processes, which will be described in more detail below, particularly with respect to the location where the etching is performed. In some embodiments, the action of configuring the wafer to receive the liquid is performed before performing an action of checking the at least one semiconductor device structure that will be described next.

In S1130, the method includes examining at least one of the semiconductor device structures to obtain information about the semiconductor device structures. In some embodiments, the information is based on the test results. The information may be, for example, resistance values of the ohmic circuit elements of the semiconductor device structure.

In S1140, the method includes processing the test results to derive a configuration that may be required for a desired operation of the semiconductor devices to be fabricated from the wafer. In particular, in the example discussed herein, the configuration of the tuning elements may be derived as configurable circuit element structures in the integrated circuits IC1, IC2, IC3, ... ICN to provide a same resistance value by compensating for variations in a measured resistance value from one semiconductor device to another to reach. In some embodiments, the action of selectively providing the liquid on the selected portion of the wafer encodes the information associated with the tested semiconductor device structure on the wafer.

In S1150, based on a test result, a configurable circuit element structure of the semiconductor device structure may be selectively changed by providing the liquid on the selected portions of the wafer. Some embodiments of the method include ejecting the liquid from a container, electrically charging the liquid, and controlling an electric field to conduct the liquid. In some embodiments, the material to be deposited is a solution suitable for etching metals. In some embodiments, the liquid comprises an etchant. In some implementations, the solution is applied in a concentration that allows ink jet printing. In some embodiments, the solution meets criteria such as viscosity, density, and surface tension for drop formation in a printhead. When the solution reacts to dissolve metal, in particular a metal of a fuse, as disclosed herein, some embodiments use an inorganic acid solution, while other embodiments use an organic acid solution, for example FeCl ₃ , to dissolve a Cu fuse structure , or use an organic base. Accordingly, the method comprises etching the at least one circuit element. In some embodiments, the circuit element is a conductive trace element. At least one effect may be to break an electrically conductive line provided by a trace element. In some embodiments, each semiconductor device includes an integrated circuit that includes a first circuit portion and a plurality of second circuit portions. In some embodiments, the modified one preserves Circuit element, the first circuit portion, before to be electrically connected to a selected one of the plurality of second circuit portions. In a pressure application according to some implementations, drops (for example in the range of 4-100 pL) are selectively placed in locations where the fuses must be removed by etching. In some embodiments, the action of printing the etchant includes a reaction phase that lasts a certain amount of time after the application of pressure, for example, an interval of a few minutes. During the reaction phase, the etching can be continued. The etching may be performed in a stable environment such as a stable temperature and / or a stable humidity, and may have a predetermined gas atmosphere. In some implementations, a stable environment is provided in a shroud formed by a reaction tunnel, a cabinet, or a room. In some implementations, a transport structure, such as a conveyor belt, configured to support the workpiece, ie, the wafer, through the enclosure is provided. A speed of the conveyor may be adjusted to provide the required etch time for the wafer.

In 1160, the etch products are removed from the wafer. For example, after the wafer has been moved through the enclosure, the wafer is subjected to treatment by a cleaning tool configured to remove an etchant solution and / or reaction products from the wafer. In some embodiments, the tool is provided as a spray tool. At least one effect may be that the wafer is rinsed with water and / or a solvent dispensed from the cleaning tool. In some implementations, the wafer is then subjected to drying.

In S1170, the dielectric is deposited on the wafer in some embodiments. In some embodiments, the dielectric is selectively provided on the selected portion of the wafer. At least one effect may be that the at least one modified circuit element is passivated.

In summary, in some implementations, a method is provided that includes providing a wafer having a plurality of semiconductor device structures, testing a semiconductor device structure intended to be integrated into a chip, and selectively varying a circuit element based on a test result the semiconductor device structure by providing a liquid on a selected portion of the wafer. At least one effect may be that one or more circuit connections are selectively interrupted. In a single semiconductor device structure, in some implementations, all of the selected circuit interconnections, which are similar to the fuses in a fuse bank, for example, form a subset of circuit interconnections that are the predetermined candidates for selective interruption.

In another aspect, the invention includes a wafer comprising a plurality of similar semiconductor devices, each having a plurality of circuit elements. A circuit element at a selected location of a first semiconductor device differs from another circuit element at the selected location in another semiconductor device in that the circuit element in the first semiconductor device is an ohmic element and is formed as an etched recess while the other circuit element is conductive , In some embodiments, the circuit element is lowered at the selected location within the first semiconductor device structure below a top plane of the first semiconductor device structure.

In another aspect, the invention includes a die comprising a plurality of fuses comprising at least one open fuse. In some embodiments, the plurality of fuses are arranged in a matrix. In some embodiments, a combination of open and unopened fuses represents a bit sequence. In FIG. 12, an interruption of the electrical connection of the at least one opened fuse is formed by a concave wet etch crater. In some embodiments, for each fuse, a fuse terminal is connected to a common node for all of the plurality of fuses, while another fuse terminal is connected to a sensor element associated with the fuse.

As described above, the action of processing the wafer in S1120 may include forming a cavity capable of receiving a substance. An example of an embodiment is: forming a conductive line in a conductive layer, such as a metal line in a metal layer on a chip, providing an insulating layer over the conductive layer, and opening a window surrounding the break in the insulating layer that lines that line covers.

12A FIG. 12 illustrates a perspective view of a variant of the exemplary configurable circuit element structure shown in FIG 2A is pictured. On a substrate 1210 becomes a trace line, such as the metal line 1220 provided. On the metal pipe 1220 becomes an insulation layer 1230 deposited. In the insulation layer 1230 becomes over the conductor line 1220 a window 1240 open. 12B FIG. 12 illustrates another top view of the variant of the configurable circuit element structure shown in FIG 12A with the configurable circuit element structure being configured as described herein: in the window 1240 has an etching substance on the metal line 1220 a section of the metal pipe 1220 etched away, causing the metal line 1220 is interrupted in a first metal line and a second metal line, which are aligned coaxially, so that a terminal end 1251 the first metal line a terminal end 1252 facing the second metal line passing through a gap 1270 are separated from each other. In some embodiments, the gap is 1270 about as long as the width of the metal line 1220 , Thus, the group of the first metal line and the second metal line forms an interrupted conductor line 1220 , The terminal end 1251 the first metal line 1221 and the terminal end 1252 the second metal line 1222 lie in the window 1240 free. Thus, while the circuit element is referred to as being "configurable", it will be understood that once the conductive connection is broken, the configurable circuit element will be around the gap 1270 between the two Kiemmenenden 1251 and 1252 to form, was actually configured. Later, for example, in S1170, when the dielectric on the window 1240 is deposited, the dielectric fills the gap 1270 and the group of two terminal ends 1251 and 1252 passing through the gap filled with the dielectric 1270 are separated from each other, forms a high-impedance element.

13A FIG. 4 illustrates a top view of a variant of the exemplary first configurable circuit element structure used in the exemplary first integrated circuit structure 711 of the wafer in 7 is included. The first configurable circuit element structure is considered a matrix 1300 of conductor lines 1310 . 1320 . 1330 , ... provided to be digitally configurable. As above regarding the 12A and 12B has been described, some of the conductor lines are interrupted, the wafer 700 in relation to 11 was subjected to the procedure described. The conductor line 1320 indicates, for example, the terminal ends 1321 . 1322 on that through a gap 1327 are separated from each other and can be electrically separated by a dielectric. It goes without saying that of a semiconductor device structure 711 to another 712 on the same wafer 700 a pattern of trace lines 1310 . 1330 and broken lines 1320 in the matrix 1300 can be different.

13B FIG. 4 illustrates a top view of a variant of another example of the first configurable circuit element structure used in the exemplary second integrated circuit structure 712 of the wafer in 7 is included. While, for example, the first in 13A shown circuit element structure portion, which is a part of the first integrated circuit structure 711 forms a pattern "010101" (where "0" represents a "broken line" and "1" represents an "intact conductor line"), the first in 13B shown circuit element structure portion, which is a part of the second integrated circuit structure 712 forms a different pattern of intact trace lines 1320 and broken lines 1310 . 1330 on (in this example "011010"). In accordance with the present disclosure, testing may be performed on the first integrated circuit structure 711 and the pattern "010101" of the first circuit element structure section, which is part of the first integrated circuit structure 711 can be based on a result of this test. As the test, when connected to the second integrated circuit structure 712 Also, the pattern formed from the matrix of terminal ends of the first circuit element structure portion may be part of the second integrated circuit structure 712 forms different from the pattern associated with the first integrated circuit structure 711 is provided (as in 13B will be shown).

14A FIG. 4 illustrates a top view of a variant of the exemplary second configurable circuit element structure used in the exemplary first integrated circuit structure of the wafer in FIG 7 is included. The second circuit element structure includes an arrangement 1400 a conductor line coming from a first node 1401 to a second node 1402 runs and between the first node 1401 and the second node 1402 meanders. The conductor line forms meandering loops 1410 . 1420 , ..., 1460 , The arrangement also includes interconnect bridges 1416 . 1417 . 1426 which bridge a gap between two branches of a trace loop, thereby shorting at least one of the trace loops. As above regarding 11 Some of the bridges were subjected to selective etching and were thus removed. Between the branches 1411 and 1421 the loop 1410 all became bridges 1416 . 1417 maintained, eliminating the trace loop 1410 at the bridge 1416 effectively short-circuited. In contrast, was between the branches 1421 and 1431 the loop 1420 a first bridge a place 1427 Effectively etched away according to the method described above, whereby the short circuit between the branches 1421 and 1431 was removed in this place. Only a second bridge 1425 was left intact where the second loop 1420 shorted. At least one effect may be that the configurable circuit element structure is changed such that a resistance of the meandering trace in the array 1400 due to the selective removal of at least some of the shorts which is the length of the current path between the first node 1401 and the second node 1402 reduce. Other properties such as capacitances and / or inductances of the device 1400 the conductor line can also be changed. In accordance with the present disclosure, testing may be performed on the first integrated circuit structure 711 and the presence and location of selective etching may be based on a result of this test. As the test, when connected to the second integrated circuit structure 712 Also, the presence and location of the trace bridges that are maintained to effectively shorten the meandering trace may also be different than the presence and location associated with the first integrated circuit structure 711 to be provided.

14B FIG. 4 illustrates a top view of a variant of another example of the second configurable circuit element structure used in the exemplary second integrated circuit structure 712 of the wafer in 7 is included, the arrangement 1400 the conductor line the same as in 14A is. However, the configuration of the second configurable circuit element structure differs. While the first circuit element structure portion is a part of the first integrated circuit structure 711 forms, in 14A with one at the place 1427 etched trace bridge is shown to be a short in the second loop 1420 to remove the meandering trace, the second points in 14B shown circuit element structure portion, which is a part of the second integrated circuit structure 712 forms, in the places 1416 and 1427 two etched bridges on, while three bridges 1417 . 1426 and 1436 are maintained to provide three shorts in the meandering trace which are to be etched away. In accordance with the present disclosure, testing may be performed on the first integrated circuit structure 711 have been executed and the distribution pattern of the removed interconnect bridges 1416 and 1427 of the second configurable circuit element structure portion forming part of the first integrated circuit structure 711 can be based on a result of this test. As the test, when connected to the second integrated circuit structure 712 may have provided a different result, the distribution pattern of the bridges etched away from the meandering trace of the second circuit element structure portion may also be part of the second integrated circuit structure 712 forms different from the pattern associated with the first integrated circuit structure 711 is provided (as in 14B will be shown).

In the process of manufacturing semiconductor devices described above, at least one effect of printing the substance due to the tests performed on selected semiconductor devices formed on the wafer may be to provide a low cost and reliable alternative that is integrated with existing devices Circuits z. For example, Structural Phase Transitions (SPT) fuses may be applied as well as in future applications with greater added-value for utmost accuracy (eg, current sensors).

15 FIG. 12 illustrates a flowchart of another method according to some embodiments. The method may be generally used in manufacturing devices from a workpiece, such as semiconductor device chips from a wafer. For example, in some embodiments, each of the semiconductor device chips may include one or more semiconductor devices, such as integrated circuits and / or micro-electro-mechanical systems (MEMSs). In some embodiments, the semiconductor device comprises a power transistor. In some embodiments, the semiconductor device includes a sensor. In some embodiments, at least two of the aforementioned elements are combined in the semiconductor device chip. In some embodiments, the semiconductor devices are particle detector devices that are configured, for example, for use in a particle detector array, such as those used in particle physics experiments performed in particle accelerators, such as those used by the Research European Council (CERN). For example, in some embodiments (not shown), the workpiece may be a plastic tape to fabricate the electronic devices as organic circuit devices based on an artificial wafer substrate provided by the plastic tape. In further implementations, a plastic board may be provided as a workpiece to manufacture the electronic devices based on printed circuit boards. In some implementations, a graphene layer may be provided on the workpiece to fabricate the electronic devices as graphene-based electronic devices.

The steps of one embodiment of the method according to the concepts generally described above will now be described with reference to FIG 15 described.

In S1510, a lot number of a wafer lot is provided with a wafer being processed as a workpiece. In addition, a wafer number of the wafer is provided.

In S1520, the number of the wafer batch and the wafer number are encoded in a digital representation. In some embodiments, the digital representation is a binary representation. In some implementations, the representation is a thermometer representation. One skilled in the art may consider other types of digital representation.

In S1530, a location of the semiconductor device on the wafer is encoded in a digital representation for each semiconductor device to be fabricated on the wafer. In some embodiments, the digital representation is a binary representation of the location coordinates of, for example, Cartesian coordinates or polar coordinates in a wafer-related coordinate system. One skilled in the art may consider other types of digital representation.

The method generally includes assembling a group of records in a data file. Each record represents information that is uniquely associated with a corresponding electronic device that is manufactured from the workpiece.

At the in 15 For example, in S1540, a print file is generated based on the digital representation of the wafer lot and wafer number and the digital representation of the locations of the semiconductor devices on the wafer and the locations for an optically readable code on the semiconductor devices. In some embodiments, the print file is configured for use in controlling a tool that is used as described herein to pattern, in particular, a particular area for each die to be fabricated on the wafer. The pattern is configured to encode the batch lot number information, the wafer number, and the location of the die on the wafer.

The method may generally include configuring configurable elements formed at a plurality of predetermined locations on the workpiece and, more particularly, on each die area of a wafer used as a workpiece to encode the information associated with the corresponding electronic device. As related below 16 In more detail, in some implementations, any semiconductor device structure may be formed to include configurable elements, such as locations configured to receive a substance, to receive a pattern, in particular, an optically readable pattern that encodes information. Accordingly, the method further includes, for example, controlling, based on the data file, a deposition of a substance at selected locations on the workpiece. At least one effect may be that the locations where the substance is deposited may form a pattern that encodes the information. Provided the pattern is read by a suitable reading device or possibly by the naked eye or a lens or microscope or other visibility enhancement device, the information associated with the corresponding electronic device can be read.

At the in 15 For example, in S1550, based on the print file, the tool is controlled to form the pattern associated with the die on the wafer. For example, where the substance is deposited, due to the deposited substance, this leads to an increased surface area of the deposited substance. This raised surface provides help for optical recognition because it differs from the surrounding surface. In some implementations, the method includes preparing the wafer at the predetermined locations so that the substance, when deposited at the selected location, can form a depression. In one embodiment, the substance deposited on the wafer is an etchant. After deposition on the wafer, in particular at selected ones of the predetermined locations, the etchant etches into the surface. The resulting pit can be optically detected because it differs from the surrounding surface. Thus, for each die to be fabricated based on the wafer, the information of the batch number, wafer number, and location of the die on the wafer is encoded on the die.

In some implementations, in S1560, at least those portions of the wafer that are being printed are passivated to protect the printed pattern, in particular, from the adverse effects of other subsequent processing steps.

In general, the method may include an analysis of the wafer. The procedure can be implemented by means of a machine to detect a code pattern on the surface of a semiconductor device contained in the semiconductor chip. The method may further include using a processor to analyze the code pattern to extract information represented by the code pattern. In an embodiment, the method further comprises using a radiation detector to detect radiation reflected from the semiconductor device. In one embodiment, the machine comprises a controllable radiation source. In some implementations, the method further includes controlling the controllable radiation source to radiate radiation to the semiconductor device. In one embodiment, the method further comprises selecting a wavelength of the radiation from a wavelength spectrum covering the visible light, ultraviolet radiation, and X-radiation to provide optimum contrast for a given surface material and / or texture pattern. In one embodiment, the method further comprises at least one of: interpreting the code pattern representing binary coded information; interpreting the code pattern representing bar coded information; and interpreting the code pattern representing qr-coded information.

As in 15 For example, in some implementations, the wafer in S1570 is optically controlled, for example. In particular, the patterns formed on the wafer by the above-described printing of the encoded information may be read and decoded to check that the decoded information corresponds to the encoded information.

It is also possible to check the consistency of the location information read on the wafer by comparing it with the locations at which this information was read on the wafer. Depending on the printing process used to encode the information on the wafer, in some implementations a reading method other than optical reading may be used.

In S1580 further process steps are carried out. These further process steps may include, for example, singulation steps for use in separating individual dies from the wafer. In one aspect, the method may include an analysis of the semiconductor chip. The method includes using a machine to detect a code pattern on the surface of a semiconductor device included in the semiconductor chip. In addition, as discussed above with respect to optical testing of the wafer, in some implementations, the method may include using a processor to analyze the code pattern to extract information represented by the code pattern.

16 provides a schematic plan view of a wafer 1600 10, which includes a plurality of semiconductor device structures SD1, SD2,..., SDN according to some embodiments. It goes without saying that, though in 16 twelve semiconductor device structures, this number is for illustrative purposes only, and that the wafer may include any other number of semiconductor device structures SD1, SD2, ..., SDN that fit onto the wafer, at least one surface of the wafer is available for the die to be produced, and is dependent on an area of each of the dies to be made from the wafer. The semiconductor device structures SD1, SD2, ..., SDN are, in some embodiments, configured to each form part of a separate die, which in turn is incorporated into a separate semiconductor device. In some embodiments, the resulting semiconductor devices are intended to be of the same type. In these embodiments, the semiconductor device structures SD1, SD2, ..., SDN are identical as long as they have not been configured according to the methods disclosed herein. In other embodiments (not shown), the semiconductor device may be provided for various types. At the in 16 For example, the semiconductor devices may be provided as integrated sensor circuits intended for use in a detector of a particle accelerator, but it is to be understood that the embodiments disclosed herein may also be used to fabricate other semiconductor devices such as integrated circuits, or microelectromechanical systems. Micro-electro-mechanical systems, MEMSs) can be implemented.

In some embodiments, at least two configurable elements are combined in the semiconductor device chip. In these embodiments, the semiconductor device structures may vary with each other. The semiconductor device structures SD1, SD2, ..., SDN each include at least one of the configurable element structure sections configured in accordance with the teachings of the present disclosure. In one embodiment, the selected locations are selected from predetermined locations that are suitable to form configurable elements that are the same in electronic devices of the same type. In one embodiment, when deposited on a selected location, the substance changes configuration of the configurable element at the selected location. At a Embodiment, the substance, when deposited, differs from the surrounding surface.

Like in 16 is shown, the plurality of predetermined locations in one embodiment is in matrices 1610 . 1620 arranged. That on the matrices 1610 . 1620 formed code pattern differs from one matrix to another. In the example, the first matrix 1610 a pattern that is a binary representation "011010" and a second matrix 1620 has a pattern that is a binary representation "010101". It goes without saying that the codes can also be complementary, ie in the example: "100101" or "101010".

For example, a configurable item is on the right side, on here as a field or least significant field 1611 the first matrix 1610 Reference is made empty, ie in the least significant field 1611 no substance was secreted. In contrast, a second field houses 1612 a spot or point of substance 1617 that on the second box 1612 was deposited, and can be optically detected as the substance 1617 differs greatly from a background passing through a surface of the second field 1612 is formed. In another example, a field or least significant field on the right contains 1621 the second matrix 1620 a droplet of substance 1626 while a second box 1622 is empty, ie on the second field 1622 no substance was secreted. At least one effect may be that in this way in the matrices of the configurable elements 1610 . 1620 coded information can be optically detected, recognized as binary code, and processed by processing the binary code to recover the unique information such as the wafer lot number, wafer number, and location of the semiconductor device structure on the wafer.

Although in terms of in 16 illustrated embodiment, the configurable elements of the code patterns 1610 . 1620 described above as being configured by substances that in turn differ from the surface of the field on which the substance is deposited, in another example, the substance etches into the surface of the field to form a depression, which differs from an unetched surface portion of the corresponding field. In this way, the configurable element may also be configured by controlled deposition of an etchant instead of a substance remaining in the field.

The sample 1610 . 1620 can be machine-readable, since in particular the matrices 1610 . 1620 on which the patterns are formed are located at the same location with respect to the corresponding slide structure. In one embodiment, the machine-readable pattern is formed on an upper metal layer. Although in the in 16 In the illustrated embodiment, the machine readable pattern is a binary code pattern, other encoding methods such as a bar code pattern and a qr code pattern may also be used.

Further implementations are disclosed below.

In one aspect, the invention includes a method of use in manufacturing semiconductor devices that includes testing a wafer. The method may also include selectively providing a substance on the wafer based on a test result to obtain a modified wafer. The modified wafer has at least one altered selected portion. The method also includes adding a structural layer to the altered wafer.

Some embodiments also include configuring a plurality of portions of the wafer to be changed prior to the action of verifying the wafer. In some implementations, the action of selectively providing the substance on the wafer includes selecting a subset of the plurality of portions to be changed.

After the action of selectively providing the substance on the wafer, in some embodiments, a subset of the plurality of sections to be modified together with other unaltered sections within a predetermined portion of the wafer form a bit sequence representing at least one value. In some embodiments, the action of selectively providing the substance on the wafer includes selecting a location on the wafer where the providing of the substance occurs.

In some embodiments, the wafer includes a plurality of semiconductor device structures. The action of testing the wafer may include testing a semiconductor device structure.

In some embodiments, the action of selectively providing the substance on the wafer includes selecting a semiconductor device structure on which the provision of the substance takes place.

In some embodiments, each of the semiconductor device structures includes circuit elements. The action of selective provisioning the substance on the wafer may include selecting a circuit element included in the semiconductor device structure and on which the provision of the substance takes place. Thus, each of the sections to be changed includes at least one configurable circuit element structure.

In some embodiments, the circuit element selected for providing the substance is passive. In some embodiments, the circuit element is a connection and the substance breaks the connection. In some embodiments, the circuit element is a pair of terminals that is separated by a dielectric and the substance establishes a connection between the terminals via the dielectric.

In some embodiments, the circuit element selected for a change is active.

Some embodiments also include a check result from checking the wafer to obtain control data. In some embodiments, the method further comprises using the control data in the action of providing the substance on the wafer.

In some embodiments, the substance is a conductive material. In some embodiments, the substance is a paste at the time of providing the substance.

In some embodiments, the substance is an etching material. In some embodiments, at the time of providing the substance, the substance is at least one of a group consisting of a liquid and a suspension in a liquid.

In some embodiments, the method further comprises ejecting the liquid from a container. The liquid can be charged electrically. The method may include controlling an electric field to direct the liquid to the wafer.

In some embodiments, the method includes providing the liquid in a cavity having a nozzle and ejecting the liquid through the nozzle. In some embodiments, the method includes increasing the pressure in the cavity. At least one effect may be that the liquid can be expelled from the cavity through the nozzle. In some embodiments, the act of increasing the pressure in the cavity includes decreasing a void volume and / or heating the liquid in the void.

In some embodiments, the action of adding the structural layer on the modified wafer completes forming a plurality of semiconductor devices that are identical in function, although at least one semiconductor device is different from the other semiconductor devices in a parameter setting.

In some embodiments, each semiconductor device includes an integrated circuit including a first circuit portion and a plurality of second circuit portions, the modified circuit member retaining the first circuit portion from electrical connection with a selected one of the plurality of second circuit portions.

In one aspect, the invention includes a method of using in manufacturing a plurality of electronic devices from a workpiece. The method generally includes assembling a group of records in a data file. Each record represents information that is uniquely associated with a corresponding electronic device that is manufactured from the workpiece. The method also includes controlling a deposition of a substance at selected locations on the workpiece based on the data file. At least one effect may be that the locations where the substance is applied may form a pattern that encodes the information. Provided the pattern is read by a suitable reading device or possibly by the naked eye or a lens or microscope or other visibility enhancement device, the information associated with the corresponding electronic device can be read.

In one embodiment, the selected locations are selected from predetermined locations that are suitable to form configurable elements that are the same in electronic devices of the same type. In one embodiment, when deposited on a selected location, the substance changes configuration of the configurable element at the selected location. In one embodiment, the substance, when deposited, differs from the surrounding surface.

In one embodiment, the method includes selecting a conductive substance and preparing the workpiece at the predetermined locations such that the substance, when deposited at the selected location, can make a conductive connection.

In some embodiments, the method further includes selecting an etchant as the substance. In one embodiment, the method further comprises preparing the workpiece at the predetermined locations such that the substance, when deposited at the selected location, forms a depression. In one embodiment, the etchant interrupts a conductive connection.

In one embodiment, the plurality of predetermined locations are arranged in a matrix. The method also includes configuring the configurable elements formed at the plurality of predetermined locations to encode the information associated with the corresponding electronic device.

In one embodiment, the method further includes separating the plurality of electronic devices from one another to obtain a plurality of dies.

In one embodiment, the method further comprises at least one of: providing a wafer as the workpiece to manufacture the electronic devices as semiconductor devices; providing a plastic tape to make the electronic devices as organic circuit devices based on an artificial wafer substrate provided by the plastic tape; providing a plastic board as the workpiece to manufacture the electronic devices based on printed circuit boards; and providing a graphene layer on the workpiece to fabricate the electronic devices as graphene-based electronic devices.

In one aspect, the invention includes a semiconductor device. The semiconductor device includes a die supporting at least one circuit element configured to provide functionality to the semiconductor device, and a machine-readable pattern including one or more recesses for encoding the information associated with the die. In one embodiment, the machine-readable pattern is formed on an upper metal layer. In one embodiment, the machine readable pattern is at least one of a binary code pattern, a bar code pattern, and a qr code pattern.

In one aspect, the invention includes an elementary particle detector. The elementary particle detector comprises a matrix of semiconductor detector dice. Each die supports a matrix of circuit elements configured to generate an output voltage signal when struck by an elementary particle. In addition, each die has a machine-readable pattern that encodes the information associated with each die.

In one aspect, the invention includes a method for semiconductor chip analysis. The method includes using a machine to detect a code pattern on the surface of a semiconductor device included in the semiconductor chip. The method also includes using a processor to parse the code pattern to extract information represented by the code pattern.

In an embodiment, the method further comprises using a radiation detector to detect radiation reflected from the semiconductor device. In one embodiment, the machine comprises a controllable radiation source. The method also includes controlling the controllable radiation source to radiate radiation to the semiconductor device. In one embodiment, the method further comprises selecting a wavelength of the radiation from a wavelength spectrum covering the visible light, ultraviolet radiation, and X-radiation to provide optimum contrast for a given surface material and / or texture pattern.

In one embodiment, the method further comprises at least one of: interpreting the code pattern representing binary coded information; interpreting the code pattern representing bar coded information; and interpreting the code pattern representing qr-coded information.

As other modifications and variations will be apparent to those skilled in the art that are varied to suit specific operating requirements and environments, it is to be understood that the invention is not limited to the example chosen for purposes of disclosure and covers all changes and modifications. which do not depart from the true spirit and scope of this invention. In particular, it is to be understood that in the manufacturing process of the semiconductor devices, particularly when the semiconductor devices are integrated circuits but are not limited to ICs, the methods according to the invention are performed at different processing stages of the wafer in various aspects described herein ("making connections" and " Breaking Connections ") may use either one or the other, or both, for example, circuit element structures at different locations and / or in different ones Configure layers of the semiconductor devices.

Persistently storing digital information in a chip can be achieved by changing the physical properties of a structure from one "state" to another, and one way to accomplish this is to use a laser pulse. There are a number of conventional ways to permanently change the electrical and physical properties of the semiconductor devices and other structures using laser pulses. To mention a common example, a normally low current path for current flow may be interrupted by converting it to a high impedance path (ideally by converting from a "short circuit" to an "open circuit"). In this way, by cutting or not cutting selected "paths" in a group of paths, it is possible to store a bit string whose values can be electrically read by a read circuit to perform a read.

As used herein, a logic state "0" (also referred to herein as logic "0" for short) corresponds to the physical condition of a "short circuit", thus representing a logic "0", and a logic state "1" (also referred to herein as logic "1" for short) corresponds to the physical condition of an "open circuit", thus representing a logical "1". It is to be understood that the representation of the logic "0" or "1" by a short circuit or an open circuit is a matter of agreement and / or choice of the skilled person, except other technical circumstances which are expressly mentioned require contradictory and thus determine the presentation in advance. In particular, a process technology used in manufacturing the semiconductor device may predetermine whether a conductive path is formed to represent a logical "0" or a logical "1". Other more general requirements may also be listed: in some implementations, the "conductive path" should be: low impedance (to essentially make a short circuit); easy to interrupt by using a laser pulse; as soon as it is "cut through" by the laser pulse; to be functionally reliable as an open circuit element, for example, to achieve a long data retention period of the "open circuit"; and to be reliable as a short-circuiting element when it is "not cut through", for example, to achieve a long data retention time of the "short circuit".

As a "lump" is used herein, it may be a droplet or a short line formed, for example, by depositing a small amount of a liquid on a surface or by providing a small amount of a paste on a surface becomes. In this context, "small" means that gravity is a force that can be neglected substantially in the context of the present techniques when compared to the surface tension and other inherent forces of the body of the lump.

As used herein, the term semiconductor device structure may refer to a semiconductor device in a finished wafer. The term also includes a portion of a semiconductor device that has been completed in a manufacturing process, although the manufacturing process has not been completed yet, this meant that the manufacturing of the wafer has not yet been completed. In other words, the semiconductor device structure may also be a semiconductor device in manufacturing, and thus does not necessarily have to be a completed semiconductor device.

As used herein, the word "exemplary" means that it serves as an example, case or representation. Any aspect or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or configurations. Instead, the use of the word is to be understood, by way of example, as representing concepts and methods in a concrete manner. For example, the term "techniques" may refer to one or more devices, devices, methods of manufacture, and / or computer readable instructions, as described herein in the context.

As used herein, the term "or" is to be understood in its meaning as an inclusive or not as an exclusive or. That is, "X implements A or B" is to be understood to mean any of the natural inclusive implementations except as otherwise stated or otherwise made obvious from the context. That is, if X uses A; X B inserts; or X uses both A and B, "X sets A or B" is satisfied in any of the above examples.

As used herein, the terms "a," "an," or "an" are generally to be understood to mean "one or more," unless otherwise specified or made clear from context, that they are focused on a unique shape.

Although the foregoing description has been described in conjunction with an exemplary embodiment, it is to be understood that the term "exemplary" is meant to be an example only, but not the best or optimal. Accordingly, the disclosure is to be understood to cover alternatives, changes, and equivalences that are included within the scope of the disclosure.

The implementations are described herein in terms of exemplary embodiments. It is to be understood, however, that individual aspects of the implementations may be claimed separately and that one or more features of the various embodiments described herein may be combined with each other except as expressly stated otherwise. In some examples, known features are omitted or simplified to clarify the description of the exemplary implementations.

The order in which the embodiments / implementations and methods / processes are described is not to be construed as a limitation and any number of the described implementations and processes may be combined.

As the terms "comprise," "include," "include," "include," "with," and similar terms or variants thereof are used herein, they are open-ended terms to be understood as inclusive. These terms mean the presence of the mentioned elements or features, but they do not exclude additional elements or features.

As the directional terminology such as "top", "bottom", "front", "rear", etc., is used here, it is described with respect to the orientation in the figure (s).

As used herein, the terms "first," "second," and the like will also be used to describe, and are not to be construed as limiting, any of several elements, ranges, portions, etc., unless expressly stated otherwise ,

While specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This disclosure is to be understood to cover all adaptations and variations of the specific embodiments discussed herein.

Claims (17)

A method of use in manufacturing semiconductor device chips, the method comprising: Providing a wafer comprising a plurality of semiconductor device structures; Testing a semiconductor device structure; and on the basis of a test result, providing a substance on a selected portion of the wafer to selectively configure a circuit element of the semiconductor device structure. A wafer comprising a plurality of similar semiconductor device structures, each having a plurality of circuit elements, wherein a passive circuit element provided at a selected location between a first pair of lands in a first semiconductor device structure is replaced by another passive circuit element attached to the first semiconductor device structure selected location between a second pair of contact lands in a second semiconductor device structure, characterized in that the passive circuit element in the first semiconductor device structure comprises a conductive material, while the other passive circuit element comprises no conductive material. The, comprising: a pair of dielectric lands electrically separating two conductive nodes associated with the pair of dielectric lands; and a conductive line establishing an electrical connection between the two conductive nodes associated with the dielectric contact land; wherein a surface of the conductive line has a convex cross section. The, comprising: a plurality of pairs of dielectric lands, each pair of dielectric lands electrically separating two conductive nodes associated with the pair of dielectric lands; and a conductive substance that is digitally distributed over the plurality of pairs of dielectric pads, and wherein the conductive substance, where present on a pair of dielectric lands, establishes an electrical connection between the two conductive nodes associated with the dielectric land. A mask for use in a wafer lithography comprising a pattern configured to project a metal structure onto the wafer, the pattern comprising a plurality of identical pattern portions, each of the identical pattern portions comprising a matrix of paired opposing contact lands each of the contact webs comprises a round tongue tip. A plant for use in manufacturing semiconductor devices, the plant comprising a printing unit configured to print a conductive substance on selected portions of a wafer. A method of use in manufacturing semiconductor device chips, comprising in this order: Processing a wafer to form a plurality of semiconductor device structures provided in at least a first structural layer on the wafer; Checking the wafer; Adding another structural layer to the wafer; and between the actions of inspecting the wafer and adding a further structural layer to the wafer, selectively depositing a substance at a selected location on a selected portion of the wafer comprising a semiconductor device structure. Method for use in manufacturing semiconductor device chips, the method comprising: Providing a wafer having a plurality of semiconductor device structures; Testing a semiconductor device structure; and on the basis of a test result, selectively changing a circuit element of the semiconductor device structure by providing a liquid on a selected portion of the wafer. A wafer comprising a plurality of similar semiconductor devices, each having a plurality of circuit elements, wherein a circuit element at a selected location in a first semiconductor device differs from another circuit element at the selected location in the other semiconductor device in that the circuit element in FIG First semiconductor device is an ohmic element and is formed as an etched recess, while the other circuit element is conductive. The, comprising: a variety of fuses that includes at least one open fuse wherein an interruption of the electrical connection of the at least one opened fuse is formed by a concave wet etching crater. A plant for use in manufacturing semiconductor devices, the plant comprising a printing unit configured to print an etching substance on selected portions of a wafer. Method for use in manufacturing semiconductor devices, comprising in this order: Processing a wafer to form a plurality of semiconductor device structures provided in at least a first structural layer on the wafer; Checking the wafer; Adding another structural layer to the wafer; and between the actions of inspecting the wafer and adding a further structural layer to the wafer, selectively depositing a substance at a selected location on a selected portion of the wafer comprising a semiconductor device structure. A method of use in manufacturing semiconductor devices, the method comprising: Testing a wafer; on the basis of a test result, selectively providing a substance on the wafer to obtain an altered wafer having at least one selected altered portion; and Add a structural layer to the modified wafer. A method of using in manufacturing a plurality of electronic devices from a workpiece, the method comprising: Assembling a group of records in a data file, each record representing information that is uniquely associated with a corresponding electronic device made from the workpiece, and Based on the data file, controlling a deposition of a substance at selected locations on the workpiece. Semiconductor device comprising a die supporting at least one circuit element configured to provide functionality to the semiconductor device, and a machine-readable pattern comprising one or more pits for encoding information associated with the die. An elementary particle detector, comprising: an array of semiconductor detector dies, each supporting a matrix of circuit elements configured to generate an output voltage signal when struck by an elementary particle, and each having a machine-readable pattern encoding the information, which are assigned to each die. A method of semiconductor chip analysis, the method comprising: - Using a machine to detect a code pattern on the surface of a semiconductor device, which is included in the semiconductor chip, and Use a processor to parse the code pattern to extract information represented by the code pattern.

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