DE102017100349B4 - Separation of semiconductor dies and resulting structures - Google Patents

Abstract

A method comprising:obtaining a wafer (200) comprising:a first integrated circuit die (100),a second integrated circuit die (100), anda scribe frame region (202) between the first integrated circuit die (100) and the second integrated circuit die (100), andforming a notch (206) in the scribe frame region (202), the notch (206) extending through a plurality of dielectric layers (120) into a semiconductor substrate (102), and the notch (206) having:a first width (W5) at an interface between the plurality of dielectric layers (120) and the semiconductor substrate (102), anda second width (W4) at a surface of the plurality of dielectric layers (120) opposite the semiconductor substrate (102), wherein a ratio of the second width (W4) to the first width (W5) is at least 0.6 and less than 1.0 amounts.

Description

STATE OF THE ART

The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electronic devices (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, the improvement in integration density has resulted from incremental reductions in the minimum feature size, allowing more components to be integrated into a given area. With the growing need to downsize electronic devices, a need for smaller and more inventive packaging techniques of semiconductor dies has emerged. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to provide high integration and component density. PoP technology generally enables semiconductor devices to be manufactured with improved functionality and a small footprint on a printed circuit board (PCB).

From the US 2007/0272668 A1 and the US 2005/0101108 A1 Methods are known in which semiconductor dies are separated by first forming a notch with a laser beam and then a sawing process takes place in the notch.

SUMMARY OF THE INVENTION

The present invention relates to a method according to claim 1, which comprises forming a notch in a scribe frame region of a wafer, a method according to claim 9, in which a notch is formed in a scribe frame region using a plurality of laser beams and a saw blade is used to saw through a portion exposed by the notch, and a corresponding apparatus according to claim 13. Preferred embodiments are given in the dependent claims.

BRIEF DESCRIPTION OF THE DRAWINGS

• 1A bis 1C zeigen verschiedene Ansichten eines Halbleiter-Die in einem Wafer gemäß einigen Ausführungsformen;
• 2 bis 5 zeigen Querschnittsansichten verschiedener Zwischenschritte einer Vereinzelung eines Halbleiter-Die gemäß einigen Ausführungsformen; und
• 6A und 6B zeigen Querschnittsansichten eines Halbleitervorrichtungs-Package gemäß einigen Ausführungsformen.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

• 1A to 1C show various views of a semiconductor die in a wafer according to some embodiments;
• 2 to 5 show cross-sectional views of various intermediate steps of a semiconductor die singulation according to some embodiments; and
• 6A and 6B show cross-sectional views of a semiconductor device package according to some embodiments.

DETAILED DESCRIPTION

The disclosure below provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For example, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity, and does not, in and of itself, dictate any relationship between the various embodiments and/or configurations discussed.

In addition, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or otherwise oriented) and the terms relating to spatial relativity used herein may be equally interpreted accordingly.

Various embodiments are described in a particular context, namely a semiconductor die in a chip-on-wafer-on-substrate (CoWoS) package. However, various embodiments may be applied to semiconductor die singulation in other package configurations.

1A shows a cross-sectional view of a die 100 according to some embodiments. The die 100 may be a semiconductor die and could be any type of integrated circuit, such as a processor, a logic circuit, a memory, an analog circuit, a digital circuit, a mixed signal, and the like. Although reference is made to a die throughout the description, portions or all of the processing of the die 100 may occur while the die 100 is a portion of a larger wafer 200 (see 1B) For example, the wafer 200 comprises a plurality of dies 100 (e.g., each of which has features as described with reference to 1A described), and a singulation process may be applied to separate the dies 100 along a scribe frame region 202 between adjacent dies 100, as described in more detail below.

The die 100 may include a substrate 102, active devices 104, and an interconnect structure 106 over the substrate. The substrate 102 may include, for example, doped or undoped bulk silicon or an active layer of a silicon on insulator (SOI) substrate. In general, an SOI substrate includes a layer of a semiconductor material, such as silicon, formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate 102 may comprise other elemental semiconductors such as germanium, a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used.

Active devices 104, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, and the like, may be formed on the top surface of the substrate 102. The interconnect structure 106 may be formed over the active devices 104 and the substrate 102. The interconnect structure 106 may include interlayer dielectric (ILD) and/or intermetal dielectric (IMD) layers containing conductive features 108 (e.g., conductive lines and vias) formed using a suitable process. The ILD and IMD layers may include low-k dielectric materials, for example, having k values lower than about 4.0, and extra-low-k dielectric (ELK) materials, for example, having k values lower than about 2.0, disposed between such conductive features. In some embodiments, the ILD and IMD layers may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymers, silicon carbon material, compounds thereof, compositions thereof, combinations thereof, or the like, formed using any suitable process such as spin coating, chemical vapor deposition (CVD), and plasma enhanced CVD (PECVD).

The conductive features 108 may be formed using a damascene process, such as a single damascene or a dual damascene process. The conductive features 108 are formed from a conductive material (e.g., including copper, aluminum, tungsten, combinations thereof, and the like), and the conductive features 108 may be lined with a diffusion barrier layer and/or an adhesion layer (not shown). The diffusion barrier layer may be formed from one or more layers of TaN, Ta, TiN, Ti, CoW, or the like. The conductive features 108 in the interconnect structure 106 electrically connect various active devices 104 to form functional circuits within the die 100. The functions provided by such circuits may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuits, or the like. One skilled in the art will appreciate that the foregoing examples are provided for illustrative purposes to further explain applications of the various embodiments, and are in no way intended to limit the various embodiments. Other circuits may be used as appropriate for a given application.

It should also be noted that one or more etch stop layers (not shown) may be disposed between adjacent ones of the ILD and IMD layers. In general, the etch stop layers provide a mechanism to inhibit an etch process in forming vias. clockings and/or contacts. The etch stop layers are formed from a dielectric material having a different etch selectivity relative to the adjacent layers, eg the underlying substrate 102 and the overlying interconnect structure 106. In one embodiment, the etch stop layers may be formed from SiN, SiCN, SiCO, CN, combinations thereof, or the like deposited using a CVD or a PECVD technique.

As further demonstrated by 1A , the interconnect structure 106 further includes one or more sealing rings 110 that may also extend through the ILD and IMD layers adjacent to the conductive features 108. The sealing rings 110 may provide protection for the features of the die 100 (e.g., the conductive features 108) from water, chemicals, residues, and/or contaminants that may be present during processing of the die 100. Each sealing ring 110 may be formed along a perimeter of the die 100 and may be a continuous structure formed to surround a functional circuit region 119 of the die 100 (e.g., the region of the die 100 having the active devices 104 and the conductive features 108 formed therein), as shown in the embodiment shown in FIG. 1C provided top view of the Die 100. In 1C a single sealing ring 110 is shown, although several sealing rings can be accommodated (see e.g. 1A) . In addition, the sealing ring 110 in 1C has a substantially rectangular shape, although in other embodiments the sealing ring 110 may have a different shape in a top plan view. As shown by 1B As shown, the dies 100 in the wafer 200 are separated by a scribe frame region 202 (which is arranged, for example, between the sealing rings 110 of adjacent dies 100).

With reference to 1A the sealing rings 110 may be formed from a conductive material. In one embodiment, the sealing rings 110 are formed by a same material, at the same time, and using a same process(es) as the conductive features 108. For example, the sealing rings 110 may include conductive line portions in different ILD and IMD layers, with conductive via portions connecting the conductive line portions between the ILD and IMD layers.

In various embodiments, the sealing rings 110 may be electrically isolated from the active devices 104 and the sealing rings 110 may not form functional circuits with the active devices 104. The sealing rings 110 may be spaced from a functional circuit region 119 of the die 100 by a minimum distance. By including a minimum distance between the sealing rings 110 and functional circuits, the risk of damage to the conductive features 108 during formation of the sealing ring 110 may be reduced. Although 1A Additionally, in other embodiments, the sealing ring 110 may extend into the substrate 102. In some embodiments, a bottom surface of the sealing ring 110 may be substantially level with or lower than bottom surfaces of the active device regions (e.g., source/drain regions 104') in the substrate 102.

The die 100 also includes pads 114, such as aluminum pads, to which external connections are made. The pads 114 may provide electrical connection to the active devices 104 via the conductive features 108. The pads 114 are located on sides of the die 100 that may be referred to as respective active sides. Passivation films 112 are disposed over the interconnect structure 106 and on portions of the pads 114. The passivation films 112 may comprise a single passivation layer or a multi-layer structure. In some embodiments, the passivation films 112 may comprise a similar material as the underlying ILD and IMD layers (e.g., a low-k dielectric). In other embodiments, the passivation films 112 may be formed from non-organic materials, such as silicon oxide, undoped silicate glass, silicon oxynitride, and the like. Other suitable passivation materials may also be used.

Openings may be patterned through the passivation films 112 to expose respective center portions of the pads 114. The pads 116 are formed in the openings through the passivation films 112 and may be referred to as under-bump mat alloys (UBMs) 116. In the illustrated embodiment, the pads 116 are formed through openings in the passivation films 112 to the pads 114. To form the pads 116, for example, a seed layer (not shown) is formed over the passivation films 112. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The Photoresist may be formed using spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pads 116 and optionally the portion of the seal rings 110 above the passivation films 112. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed using plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portions of the seed layer on which the conductive material was not formed are removed. The photoresist may be removed using a suitable ashing or ablation process, such as using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, such as using a suitable etching process such as a wet or dry etch. The remaining portions of the seed layer and the conductive material form the pads 116. The remaining portions of the seed layer may optionally also provide portions of the sealing rings 110 over the passivation films 112. In the embodiment where the pads 116 are formed differently, more photoresist and patterning steps may be used.

The conductive interconnects 118 are formed on the UBMs 116. The conductive interconnects 118 may be BGA interconnects, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using an electroless nickel-electroless palladium-immersion gold (ENEPIG) technique, or the like. The conductive interconnects 118 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive interconnects 118 are formed by initially forming a layer of solder using such techniques as evaporation, electroplating, printing, solder transfer, ball arranging, or the like. After a layer of solder is formed on the structure, reflow may be performed to form the material into the desired bump shapes. In another embodiment, conductive interconnects 118 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be free of solder and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of metal pillar interconnects 118. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed using a plating process.

2 shows a scribe frame region 202 of the wafer 200. The scribe frame region 202 is arranged between the sealing rings 110 of adjacent dies 100. Each of the dies 100 may have similar features as in 1A , 1B and 1C , wherein like reference numerals refer to like elements formed using like processes. For example, each die 100 includes a semiconductor substrate 102, dielectric layers 120 (e.g., including low-k dielectric layers of the interconnect structure 106, and passivation films 112, see 1A) and sealing rings 110. In some embodiments, a thickness T1 of the dielectric layers 120 may be approximately 10 μm. In other embodiments, the dielectric layers 120 may have a different dimension. Although a single scribe frame region 202 is shown, each die 100 may be surrounded on all sides (eg, four sides) by scribe frame regions 202 in a top plan view of the wafer 200 (not shown). A singulation process of the embodiment described below may be applied to all sides of each die 100 to completely separate the dies 100 from other features in the wafer 200.

3 to 5 disclose a singulation process used to separate the dies 100 from other features in the wafer 200 (e.g., other dies 100), according to some embodiments. The singulation process may include a laser ablation process used to form a notch through the dielectric layers 120 that partially extends into the semiconductor substrate 102. The laser ablation process may include multiple passes with a laser beam to provide a notch with an appropriate configuration. After the notch is formed, a mechanical sawing process may be applied across the notch to completely singulate the dies 100.

With reference to 3 a laser ablation process is applied to the wafer 200 in the scribe frame region 202. The laser ablation process may include applying a plurality of laser beams 204 (labeled 204A through 204I) to the dielectric layers 120 and the substrate 102. A position, power, number and/or type of each laser beam is controlled to achieve a desired profile of the resulting In one embodiment, at least nine laser beams (e.g., labeled 204A through 204I) are applied to provide a notch with an appropriate profile. It has been found that fewer manufacturing defects are present as a result of a subsequent mechanical sawing process (see 5 ) may occur when at least nine laser beams are applied to the wafer 200. In other embodiments, a different number of laser beams may be applied to the wafer 200, such as a greater number than nine or a lesser number than nine.

Laser beams 204A-204I may be applied to wafer 200 inward from an outer periphery of a subsequently formed notch. Each laser beam 204A-204I may extend through dielectric layer 120 and partially into substrate 102. Laser beams 204A-204I may not pass completely through substrate 102, and laser beams 204A-204I may stop at an intermediate point between a top and bottom surface of substrate 102. In an embodiment using an outside-in notch formation process, laser beam 204A is applied before laser beam 204B, laser beam 204B is applied before laser beam 204C; laser beam 204D is applied before laser beam 204E, laser beam 204E is applied before laser beam 204F, laser beam 204F is applied before laser beam 204G, laser beam 204G is applied before laser beam 204H, and laser beam 204H is applied before laser beam 204I. In other embodiments, laser beams may be applied to wafer 200 in a different order. For example, in another embodiment, laser beams 204A through 204I may be applied to wafer 200 outward from a center of a subsequently formed notch. In an embodiment using an inside-out notch forming process, laser beam 204I is applied before laser beam 204G or 204H, laser beams 204G and 204H are applied before laser beams 204E or 204F, laser beams 204E and 204F are applied before laser beams 204C or 204D, and laser beams 204C or 204D are applied before laser beams 204A or 204B. Additionally, each laser beam 204A through 204I may be applied at a power of about 0.1 watts (W) to about 6 W.

4 shows the resulting notch 206 formed using the method described with reference to 3 described laser ablation process. The notch 206 extends through the dielectric layers 120 and partially into the substrate 102. In various embodiments, the notch 206 does not extend completely through the substrate 102, and a bottom surface of the notch 206 exposes a material of the substrate 102. In some embodiments, the notch 206 extends into the wafer 200 to a depth T2 of about 13 μm or more. In other embodiments, the notch 206 may extend to a different depth into the wafer 200.

In addition, as a result of the laser ablation process, remodeling regions 208 may be formed on sidewalls of the dielectric material 120 and the substrate 102. The remodeling regions 208 may be formed as a result of a redeposition of material (e.g., the material of the dielectric material 120 and/or the substrate 102) that is irradiated with the laser beam 204 (see 3 ) is irradiated during formation of the notch 206, and sidewalls of the notch 206 may be defined by the deformation regions 208. Although the deformation regions 208 are illustrated as being symmetrical (e.g., having a same shape on opposite sidewalls of the notch 206), in some embodiments the deformation regions 208 may have different profiles on each sidewall of the notch 206. The deformation regions 208 may have a width W1 at a widest point of about 5 µm to about 15 µm. Additionally, a lateral distance W2 from a first sealing ring 110 to a first deformation region 208 may be about 10 µm or more, and a lateral distance W2 from a second sealing ring 110 to a second deformation region 208 may be about 10 µm or more. The first sealing ring 110/first deformation region 208 may be disposed on an opposite side of the notch 206 relative to the second sealing ring 110/second deformation region 208. The lateral distances W2 and W3 may be the same or different. In other embodiments, deformation regions 208 may have a different dimension or be disposed at a different distance from the sealing rings 110.

The notch 206 is formed with a specific profile and/or dimensions to reduce manufacturing defects resulting from singulation. For example, the notch 206 has a first width W4 between opposing deformation regions 208 at a top surface of the dielectric layers 120, and the notch 206 has a second width W5 between opposing deformation regions 208 at a bottom surface of the dielectric layers 120/top surface of the substrate 102. In various embodiments, a ratio the width W4 to the width W5 may be approximately at least 0.6. In addition, an angle θ between a bottom surface of the notch 206 and a sidewall of the notch 206 may be approximately 90° to approximately 135°. It has been found that by using a laser ablation process to form the notch 206 with this profile, peeling/cracking of the dielectric layers 120 during subsequent mechanical sawing processes (see e.g. 5 ). For example, by designing the notch 206 to be relatively wide at the bottom surface of the dielectric layers 120 and to have relatively vertical (or obtuse-angled sidewalls), impact on exposed areas of the dielectric layers 120 during subsequent mechanical sawing processes (e.g., using a saw blade) may be reduced or at least avoided. By reducing the impact area of the saw blade(s) in subsequent mechanical sawing processes, peeling and/or cracking of the dielectric layers 120 during these processes may be reduced. In addition, due to the increased overall size of the notch 206 and the angle θ, a process window for applying a saw blade may be increased without significant risk of impact on the dielectric layer 120. Therefore, manufacturing defects may be reduced and yield may be improved. For example, experiments using the process described above have shown a 25% improvement in semiconductor device yield.

5 shows a next step in the dicing process. As shown, a saw blade 210 is used in a mechanical sawing step to complete the dicing process. The saw blade 210 is aligned with the notch 206 formed by the laser ablation process described above. The saw blade 210 is used to saw completely through the remaining lower portion of the substrate 102. In the illustrated embodiment, the saw blade has a width W6. In some embodiments, the width W6 is less than the width W5 (see 4 ) of the notch 206 at a lower surface of the dielectric layers 120. In one embodiment, the width W6 may be, for example, about 10 µm to about 100 µm, although other values of the width W6 may also be used depending on the width W5. In other embodiments, the saw blade 210 may have a different thickness. Still further, in other embodiments, multiple saw blades (e.g., having the same or different thickness) and multiple mechanical sawing steps may be used to complete the dicing process.

As through 5 As shown, the saw blade 210 forms a sidewall 102A of the substrate 102. In one embodiment, a sidewall deformation region 208 may be spaced from the sidewall 102A by a lateral distance W7 at a top surface of the dielectric layers 120, and the sidewall of the deformation region 208 may be spaced from the sidewall 102A by a distance W8 at a bottom surface of the dielectric layers 120. In some embodiments, the distance W7 is about 10 μm or more, while the distance W8 is about 10 μm to about 20 μm. It has been found that fewer manufacturing defects (e.g., peeling/cracking of the dielectric layers 120) result from a singulation using the saw blade 210 when the widths W4/W5 of the notch 206 (see 4 ) and/or the distances W7/W8 are in the above ranges.

After the dies 100 are singulated using the singulation process of the embodiment, the dies 100 may be packaged with other device features in a device package. For example, 6A and 6B a device package 300 comprising singulated dies 100. In various embodiments, multiple dies 100 (e.g. singulated from a same wafer or from different wafers) may be singulated and packaged in a single device package 300. The dies 100 may be logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., DRAM (dynamic random access memory) die, SRAM (static random access memory) die, etc.), power management dies (e.g., PMIC (power management integrated circuit) die), radio frequency (RF) dies), sensor dies, MEMS (microelectromechanical system) dies), signal processing dies (e.g., a DSP (digital signal processing) die), front-end dies (e.g., AFE (analog front end) dies), the like, or a combination thereof. Additionally, in some embodiments, the dies 100 may have different sizes (e.g., different heights and/or surface areas), and in other embodiments, the dies 100 may have the same size (e.g., same heights and/or surface areas).

The dies 100 may be initially bonded to a die 302 using any suitable bonding technique (e.g., flip-chip bonding using the conductive connectors 118 of the dies 100) while the die 302 is a part of a larger wafer (not shown). In some embodiments, the die 302 is an interposer with no active devices and has conductive vias 306 extending through a substrate material (e.g., silicon, a polymer material with or without fillers). ler, combinations thereof, and the like). The conductive vias 306 provide electrical routing from one surface of the die 302 to which the dies 100 are bonded to an opposite surface of the die 302. For example, the conductive vias 306 provide electrical routing between the conductive connectors 118 and the conductive connectors 308 of the die 302. The conductive connectors 306 may be BGA connectors, solder balls, metal pillars, C4 bumps, microbumps, bumps formed using an ENEPIG technique, or the like. The conductive connectors 306 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive interconnects 306 are formed by initially forming a layer of solder using such commonly used methods as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a layer of solder is formed on the structure, reflow may be performed to shape the material into the desired bump shapes. In another embodiment, the conductive interconnects 306 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be free of solder and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the metal pillar interconnects 306. The metal covering layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed using a plating process.

Additionally, die 302 may optionally also include redistribution layers (not explicitly shown) having conductive features that provide electrical routing between various dies 100 and through die 302. In other embodiments, die 302 may have a different configuration. For example, die 302 may be a semiconductor device die having active devices, passive devices, functional circuits, combinations thereof, or the like disposed therein.

After the dies 100 are bonded to the die 302, an encapsulant 304 may be formed at least partially around the dies 100 and between the dies 100 and the die 302. The encapsulant 304 may comprise a mold compound, an epoxy, an underfill, or the like, and may be applied by compression molding, transfer molding, capillary force, or the like. The encapsulant 304 may be disposed around the conductive connectors 118 to provide structural support to the conductive connectors 118 in the package 300. Additionally, the encapsulant 304 may extend partially along sidewalls of the dies 100. In the illustrated embodiment, the dies 100 extend higher than the encapsulant 304. In other embodiments, the encapsulant 304 may extend higher than the dies 100 or may have a top surface that is substantially flush with a top surface of the dies 100.

Due to the singulation process used to separate the dies 100, other side walls of the dies may have a profile as shown by 6B shown. 6B shows an area 300A (see also 6A) of Package 300. As shown by the 6B As shown, the die 100 includes a first sidewall 100A and a second sidewall 100B in region 300A that are disposed on a same side of the die 100. A material of the first sidewall 100A may be the material of the substrate 102, while a material of the second sidewall 100B may be the material of the deformation region 208. A bottom surface 100C of the die 100 connects the first sidewall 100A to the second sidewall 100B. The first sidewall 100A is laterally spaced from the second sidewall 100B by a distance W8 at an interface between the dielectric layers 120 and the substrate 102, and the first sidewall 100A is laterally spaced from the second sidewall 100B by a distance W7 at an interface of the dielectric layers 120 opposite the substrate 102. In some embodiments, the distance W7 is about 10 μm or more, while the distance W8 is about 10 μm to about 20 μm. The encapsulant 304 extends along the second sidewall 100B and, in some embodiments, may further extend along at least a portion of the first sidewall 100A. In such embodiments, the encapsulant 304 may contact the bottom surface 100C. In other embodiments, the encapsulant 304 may have a different shape and/or size relative to surfaces of the die 100.

Referring again to 6A the die 302 may be singulated from other features in the wafer (not shown) after the encapsulant 304 is formed. In some embodiments, the singulation process may be substantially similar to the singulation process applied to the dies 100. In other embodiments, a different type of singulation process (e.g., with or without laser rays) can be applied to the isolated Die 302.

After the die 302 is singulated, the die 302 may be bonded to a package substrate 312. The package substrate 312 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenophosphide, gallium indium phosphide, combinations of these, and the like may be used. Additionally, the package substrate 312 may be an SOI substrate. Generally, the package substrate 312 includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate 312, in an alternative embodiment, is based on an insulating core, such as a glass fiber reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternatives for the core material include bismaleimide triazine resin (BT resin), or alternatively other circuit board materials or films. Build-up films, such as ABF or other laminates, may be used for the package substrate 312.

The package substrate 312 may include active and passive devices (not shown in 6A As one skilled in the art will appreciate, a wide variety of devices, such as transistors, capacitors, resistors, combinations of these, and the like, may be used to create the structural and functional design requirements for package 300. The devices may be formed using any suitable techniques.

The package substrate 312 may also include metallization layers and vias (not shown) and bond pads over the metallization layers and the vias. The first metallization layers may be formed over the active and passive devices and are configured to connect the various devices to form a functional circuit. The metallization layers may be formed from alternating layers of a dielectric (e.g., a low-k dielectric material) and a conductive material (e.g., copper) with vias connecting the layers of the conductive material, and may be formed using any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate 312 is substantially free of active and passive devices.

In some embodiments, the conductive interconnects 308 on the die 302 may be reflowed to attach the die 302 to the bond pads of the package substrate 312. The conductive interconnects 308 may have an epoxy flux (not shown) formed thereon before being reflowed with at least a portion of the epoxy portion of the epoxy flux that remains after the die 302 is attached to the package substrate 312. This remaining epoxy portion may act as an underfill to reduce stress and protect the interconnects resulting from the reflow of the conductive interconnects 308. In some embodiments, an underfill 310 may be formed between the die 302 and the package substrate 312 and the surrounding conductive interconnects 308. The underfill may be formed by a capillary flow process after the die 302 is attached, or it may be formed using a suitable deposition process before the die 302 is attached.

The conductive features in the package substrate 312 may electrically connect the die 302 and the dies 100 to the conductive connectors 314 disposed on an opposite side of the package substrate 312 relative to the die 302. In some embodiments, the conductive connectors 314 are C4 bumps, BGA balls, microbumps, or the like, and the conductive connectors 314 may be used to electrically connect the package 300 to other semiconductor features, such as another package, another package substrate, another interposer, a motherboard, or the like.

As described herein, a dicing process may be used to separate a semiconductor die from other features (e.g., other semiconductor dies) in a wafer. The dicing process may first include using a laser ablation process to form a notch in the wafer having a suitable profile. Parameters of the laser ablation process (e.g., number of applied laser beams, power, position, order of applied laser beams) may be controlled to provide a suitable notch. For example, the notch may extend through multiple dielectric layers into a semiconductor substrate. The notch may have certain widths on opposite lateral surfaces of the dielectric layers to provide a large process window for subsequent dicing processes. Subsequently, Finally, a mechanical sawing process can be applied to completely separate the die from the wafer. It has been found that by controlling the notch to have a profile as described above, manufacturing defects (e.g., delamination and/or cracking of the dielectric layers) during the mechanical sawing process can be reduced. Therefore, the reliability of the dicing process and the yield can be improved.

According to an embodiment, a method includes providing a wafer comprising a first integrated circuit die, a second integrated circuit die, and a scribe frame region between the first integrated circuit die and the second integrated circuit die. The method further includes using a laser ablation process to form a notch in the scribe frame region, and after forming the notch, using a mechanical sawing process to completely separate the first integrated circuit die from the second integrated circuit die. The notch extends through a plurality of dielectric layers into a semiconductor substrate. The notch includes a first width at an interface between the plurality of dielectric layers and the semiconductor substrate and a second width at a surface of the plurality of dielectric layers opposite the semiconductor substrate. A ratio of the second width to the first width is at least about 0.6.

According to an embodiment, a method includes singulating a semiconductor die from a wafer. Singulating the semiconductor die includes forming a notch in a scribe frame region adjacent to the semiconductor die using a plurality of laser beams. The notch extends through a plurality of dielectric layers and partially into a semiconductor substrate. Singulating the semiconductor die further includes aligning a saw blade with the notch and using the saw blade to saw through a lower portion of the semiconductor substrate exposed by the notch. The saw blade is narrower than the notch at an interface between the plurality of dielectric layers and the semiconductor substrate. The method further includes, after singulating the semiconductor die, bonding the semiconductor die to another die using a plurality of conductive connectors. After bonding the semiconductor die, the semiconductor die includes a first sidewall and a second sidewall below the first sidewall. The first sidewall is laterally spaced from the second sidewall.

According to an embodiment, a device package comprises a first semiconductor die. The first semiconductor die comprises: a semiconductor substrate, a plurality of dielectric layers having an interface with the semiconductor substrate, a first sidewall, and a second sidewall below the first sidewall and disposed on a same side of the first semiconductor die as the first sidewall. The first sidewall extends laterally beyond the second sidewall. The device package also comprises a second semiconductor die bonded to the first semiconductor die via a plurality of conductive connectors. The device package also comprises an underfill disposed around the plurality of conductive connectors. The underfill extends along the second sidewall of the first semiconductor die.

Claims (16)

A method comprising: obtaining a wafer (200) comprising: a first integrated circuit die (100), a second integrated circuit die (100), and a scribe frame region (202) between the first integrated circuit die (100) and the second integrated circuit die (100), and forming a notch (206) in the scribe frame region (202), the notch (206) extending through a plurality of dielectric layers (120) into a semiconductor substrate (102), and the notch (206) having: a first width (W5) at an interface between the plurality of dielectric layers (120) and the semiconductor substrate (102), and a second width (W4) at a surface of the plurality of dielectric layers (120) opposite the semiconductor substrate (102), wherein a ratio of the second width (W4) to the first width (W5) is at least 0.6 and is less than 1.0. Procedure according to Claim 1 , wherein an angle (θ) between a lower surface of the notch (206) and a side wall of the notch (206) is 90° to 1350. Procedure according to Claim 1 or 2 further comprising: after forming the notch (206), using a mechanical sawing process to completely separate the first integrated circuit die (100) from the second integrated circuit die (100). Procedure according to Claim 3 , wherein the mechanical sawing process comprises using a saw blade (210) having a third width (W6), wherein the third width (W6) is smaller than the first width (W5). The method of any preceding claim, wherein forming the notch (206) in the scribe frame region (202) comprises a laser ablation process. Procedure according to Claim 5 wherein the laser ablation process further forms a deformation region (208) on a sidewall of the plurality of dielectric layers (120) and a sidewall of the semiconductor substrate (102). Procedure according to Claim 5 or 6 , wherein the laser ablation process comprises: applying a first laser beam at a first position in the scribe frame region (202), applying a second laser beam at a second position in the scribe frame region (202) after applying the first laser beam, and applying a third laser beam at a third position in the scribe frame region (202) after applying the second laser beam, wherein the second position is between the first position and the third position. Procedure according to Claim 5 or 6 , wherein the laser ablation process comprises: applying a first laser beam at a first position in the scribe frame region (202), applying a second laser beam at a second position in the scribe frame region (202) after applying the first laser beam, and applying a third laser beam at a third position in the scribe frame region (202) after applying the second laser beam, the third position being between the first position and the second position. A method comprising: singling a semiconductor die (100) from a wafer (200), wherein singulating the semiconductor die (100) comprises: forming a notch (206) in a scribe frame region (202) adjacent to the semiconductor die (100) using a plurality of laser beams (204), the notch (206) extending through a plurality of dielectric layers (120) and partially into a semiconductor substrate (102), forming a remodeling region (208) on sidewalls of the plurality of dielectric layers (120) and the semiconductor substrate (102) using the plurality of laser beams (204), the remodeling region (208) comprising a redeposited material irradiated by the plurality of laser beams (204); Aligning a saw blade (210) with the notch (206), the saw blade (210) being narrower than the notch (206) at an interface between the plurality of dielectric layers (120) and the semiconductor substrate (102), and using the saw blade (210) to saw through a lower portion of the semiconductor substrate (102) exposed by the notch (206); wherein the saw blade forms a side wall (100A; 102A) of the semiconductor substrate after sawing through, and wherein the side wall (100A; 120A) of the semiconductor substrate (102) is laterally spaced from a side wall (100B) of the deformation region (208) by a first distance (W8) at the interface between the plurality of dielectric layers (120) and the semiconductor substrate (102), wherein the side wall (100A; 102A) of the semiconductor substrate (102) is laterally spaced from the side wall (100B) of the deformation region (208) by a second distance (W7) at a surface of the plurality of dielectric layers (120) opposite the semiconductor substrate (102), wherein the first distance (W8) is between 10 µm and 20 µm, and wherein the second distance (W7) is at least 10 µm. Procedure according to Claim 9 further comprising: forming an encapsulant (304) around the plurality of conductive connectors (118), the encapsulant (304) extending along the sidewall (100B) of the forming region (208). Method according to one of the preceding Claims 9 until 10 , wherein the notch (206) has a first width (W5) at the interface between the plurality of dielectric layers (120) and the semiconductor substrate (102), wherein the notch (206) has a second width (W4) at a surface of the plurality of dielectric layers (120) opposite the semiconductor substrate (102), and wherein a ratio of the first width (W5) to the second width (W4) is at least 0.6. Method according to one of the preceding Claims 9 until 11 , wherein the semiconductor die (100) has a sealing ring (110) surrounding a functional circuit region (119) of the semiconductor die (100), and wherein the sealing ring (110) is arranged between the scribe frame region (202) and the functional circuit region (119), and wherein the sealing ring (110) extends over an upper surface of the plurality of dielectric layers (120) during singulation of the semiconductor die (100). A device comprising: a first semiconductor die, the first semiconductor die comprising: a semiconductor substrate (102), a plurality of dielectric layers (120) defining an interface with the semiconductor substrate (102) on have a first sidewall (100A), and a second sidewall (100B) below the first sidewall (100A) and which is arranged on a same side of the first semiconductor die (100) as the first sidewall (100A), the first sidewall (100A) being laterally spaced from the second sidewall (100B), and an underfill (304) extending along the second sidewall (100B) of the first semiconductor die (100); wherein a material of the first sidewall (100A) is a material of the semiconductor substrate (102), wherein a material of the second sidewall (100B) is a material of a deformation region (208), and wherein the deformation region (208) comprises a material of the plurality of dielectric layers (120); wherein the first semiconductor die (100) further comprises a bottom surface (100C) connecting the first sidewall (100A) to the second sidewall (100B), wherein a material of the bottom surface (100C) is the material of the semiconductor substrate (102); and wherein the underfill (304) contacts the bottom surface (100C). Device according to Claim 13 further comprising a second semiconductor die (302) bonded to the first semiconductor die (100) through a plurality of conductive connectors (118), wherein the underfill (304) is disposed around the plurality of conductive connectors (118). Device according to Claim 13 or 14 , wherein the first sidewall (100A) is laterally spaced from the second sidewall (100B) by a first distance (W8) at the interface between the plurality of dielectric layers (120) and the semiconductor substrate (102), wherein the first sidewall (100A) is laterally spaced from the second sidewall (100B) by a second distance (W7) at a surface of the plurality of dielectric layers (120) opposite the semiconductor substrate (102), wherein the first distance (W8) is between 10 µm and 20 µm, and wherein the second distance (W7) is at least 10 µm. Device according to one of the preceding Claims 13 until 15 , wherein an angle (Θ) between the second side wall (100B) and the lower surface is 90° to 1300.

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