DE102017012256B3 - A cavity structure device and method of manufacturing the same - Google Patents

Abstract

The present disclosure relates to a device (10) having a substrate arrangement (13) with a first circuit arrangement (11), which heats up during operation, and a second circuit arrangement (12) which is integrated in a substrate material of the substrate arrangement (13). Furthermore, the device (10) has a cavity structure (14) which is arranged between the first and the second circuit arrangement (11, 12) and is formed in the substrate material and has a lower pressure than ambient atmospheric pressure. The present disclosure also relates to a method for producing such a device (10).

Description

The present disclosure relates to an apparatus having a cavity structure and a method of manufacturing the same, and more particularly to a structure and method for an integrated IR emitter, filter and ASIC with reduced power consumption and reduced volume.

With integrated circuits, such as MEMS (Micro-Electro-Mechanical-Systems), the size and height as well as the power loss play a major role, especially if the chip is to be implemented in mobile devices such as smartphones. In addition, the costs of MEMS solutions are important to consider.

In the present disclosure, for example, an integrated circuit arrangement and a circuit arrangement that heats up during operation are to be implemented in a common package, specifically with the smallest possible size or height and low cost, so that this package can be used in a mobile device, for example.

Before the concepts of the present disclosure are discussed in more detail, some previous solutions are first briefly presented.

In the US 2013/0 140 958 A1 describes devices with piezoelectric material structures integrated into substrates. Fabrication techniques for forming such devices are also described. Manufacturing may include bonding a wafer made of piezoelectric material to a substrate made of a different material. A structure such as a resonator can then be formed from the wafer of piezoelectric material.

In the US 2015/0 158 720 A1 describes a microelectromechanical system (MEMS) structure with an integrated heating device. The MEMS structure with integrated heating device comprises a first substrate with cavities, which is connected to a second substrate and thus forms a plurality of sealed enclosures which can be distinguished into at least two types of enclosure. Each of the plurality of sealed enclosures is defined by the first substrate, the second substrate, and a gasket material, the first type of enclosure further comprising at least one getter element for reducing cavity pressure in the first enclosure type and an outgassing element for increasing cavity pressure in the first enclosure type upon activation . The first type of enclosure further comprises at least one heating device, which is integrated into the first substrate next to the getter element or the outgassing element, in order to adjust the temperature of the getter element or the outgassing element, whereby heating of the getter element or the outgassing element is provided.

In the US 8 575 578 B1 describes a chip-scale infrared emitter package comprising an emitter chip and a housing. The emitter chip includes: a base with a central cavity; a membrane having a peripheral end, the peripheral end being isolated from a periphery of the central cavity by a loop-shaped gap; an electrical resistance formed on the diaphragm; at least one narrow support beam extending from the peripheral end of the membrane through the looped gap to the base; and a reflective material coated on the membrane. The housing comprises a can housing and a transparent window panel. The window panel abuts the can body to define an enclosed vacuum chamber. The emitter chip is mounted in the enclosed vacuum chamber. The enclosed vacuum chamber has a pressure of less than 0.01 torr.

The US 2011/0 209 815 A1 describes a movable device of acceleration sensors and a vibrating device of a gyroscope, which are formed on the same sensor wafer and are spaced from one another by a wall. A cover wafer with corresponding gaps for the movable mechanical components of the acceleration sensors and the gyroscope is provided for the wafer, and an adsorber, which is divided into several sections and is arranged in the gap for the gyroscope. After the sensor wafer and the lid wafer have been connected to each other at an inactivation temperature of the adsorber and in an atmospheric pressure environment of rare gas and activated gas, the adsorber sections are sequentially activated to adsorb the activated gas to adjust the pressure inside the gyroscope, whereby a combined sensor wafer is produced.

The US 2012/0 228 733 A1 describes a micro MEMS getter device for controlling an ambient pressure within a hermetic package which encloses various types of MEMS, photonic or optoelectronic devices. The micro getter device revolves around a platform which is suspended at a height above a substrate and which is supported by support legs with low thermal conductivity. Layers are deposited on the platform, such layers including a properly structured resistor element, a heat spreading layer and finally a thin film getter material. When an electric current flows through it, it heats up Resistance element the thin film getter material until it reaches its activation temperature. The getter material then absorbs the gas species that might be present in the hermetic package.

The US 2013/0 082 376 A1 describes a microelectronic device structure that includes improved thermal dissipation capability. The structure includes a three-dimensional (3D) integrated chip assembly that is flip-chip bonded to a substrate. The chip arrangement comprises a device substrate with an active device arranged thereon. A cover layer is physically bonded to the device substrate to at least partially define a hermetic seal around the active device. The microelectronic device structure provides multiple heat dissipation paths to dissipate the heat generated therein.

However, previously known solutions are too large. In addition, they have a very high power loss and thus a large amount of heat dissipation. They are therefore not suitable for use in mobile devices.

It would therefore be desirable to provide a solution for minimizing the size of a package while at the same time reducing costs and at the same time reducing the power dissipation in the application.

One aspect of the present disclosure relates to a device with a substrate arrangement with a first circuit arrangement which heats up during operation and a second circuit arrangement which is integrated in a substrate material of the substrate arrangement and a cavity structure which is arranged between the first and the second circuit arrangement and which is in the substrate material is formed, and has a pressure lower than an ambient atmospheric pressure.

A further aspect of the present disclosure relates to a method in which a substrate arrangement is provided with a first circuit arrangement, which heats up during operation, and a second circuit arrangement which is integrated in a substrate material of the substrate arrangement. In addition, according to this method, a cavity structure arranged between the first and the second circuit arrangement is formed in the substrate material, the cavity structure having a pressure that is lower than an ambient atmospheric pressure.

• 1 eine seitliche Schnittansicht eines Ausführungsbeispiels einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 2A eine seitliche Schnittansicht eines weiteren Ausführungsbeispiels einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 2B eine seitliche Schnittansicht eines weiteren Ausführungsbeispiels einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 2C eine seitliche Schnittansicht eines weiteren Ausführungsbeispiels einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 2D eine Draufsicht auf ein Ausführungsbeispiel einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3A einen ersten Schritt eines Ausführungsbeispiels eines Verfahrens zum Herstellen einer Vorrichtung gemäß dieser Offenbarung,
• 3B einen zweiten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3C einen dritten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3D einen vierten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3E einen fünften Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3F einen sechsten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3G einen siebten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3H einen achten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 31 einen neunten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3J einen zehnten Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3K einen elften Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 3L einen zwölften Schritt dieses Verfahrens zum Herstellen einer Vorrichtung gemäß der vorliegenden Offenbarung,
• 4 ein schematisches Blockdiagramm eines Ausführungsbeispiels für ein Verfahren gemäß der vorliegenden Offenbarung, und
• 5 ein schematisches Blockdiagramm eines weiteren Ausführungsbeispiels für ein Verfahren gemäß der vorliegenden Offenbarung.

Exemplary embodiments of the present disclosure are shown in the drawing and are explained below. Show it:

• 1 a side sectional view of an embodiment of a device according to the present disclosure,
• 2A a side sectional view of a further embodiment of a device according to the present disclosure,
• 2 B a side sectional view of a further embodiment of a device according to the present disclosure,
• 2C a side sectional view of a further embodiment of a device according to the present disclosure,
• 2D a plan view of an embodiment of a device according to the present disclosure,
• 3A a first step of an embodiment of a method for producing a device according to this disclosure,
• 3B a second step of this method for manufacturing a device according to the present disclosure,
• 3C a third step of this method for manufacturing a device according to the present disclosure,
• 3D a fourth step of this method for manufacturing a device according to the present disclosure,
• 3E a fifth step of this method for manufacturing a device according to the present disclosure,
• 3F a sixth step of this method for manufacturing a device according to the present disclosure,
• 3G a seventh step of this method for manufacturing a device according to the present disclosure,
• 3H an eighth step of this method for manufacturing a device according to the present disclosure,
• 31 a ninth step of this method for manufacturing a device according to the present disclosure,
• 3Y a tenth step of this method for manufacturing a device according to the present disclosure,
• 3K an eleventh step of this method for manufacturing a device according to the present disclosure,
• 3L a twelfth step of this method for manufacturing a device according to the present disclosure,
• 4th a schematic block diagram of an embodiment of a method according to the present disclosure, and
• 5 a schematic block diagram of a further exemplary embodiment of a method according to the present disclosure.

Some exemplary embodiments are described in more detail below with reference to the figures, elements with the same or similar function being provided with the same reference symbols.

1 shows an apparatus 10 according to an embodiment. The device 10 has, inter alia, a substrate arrangement 13th on. The substrate arrangement 13th may have a single substrate, multiple substrates, or one or more sub-substrate arrangements.

The substrate arrangement 13th has a first circuit arrangement which heats up during operation 11 and a second circuit arrangement 12th on. The second circuit arrangement 12th is in a substrate material of the substrate arrangement 13th integrated. This can be an integrated circuit, or IC for short. The second circuit arrangement 12th can for example be an ASIC (Application Specific Integrated Circuit).

The first circuit arrangement 11 can also be an IC. But it is also conceivable that the first circuit arrangement 11 is a non-integrated circuit arrangement, which by means of known methods, for example in SMD technology (English. Surface Mounted Device) or by means of structuring methods, in, on or on the substrate arrangement 13th is attached or structured. The first circuit arrangement 11 can for example be a MEMS module (Micro Electro Mechanical System), for example a MEMS heating element or a MEMS microphone.

The device 10 also has a cavity structure 14th in the substrate material of the substrate assembly 13th is trained. This cavity structure 14th is between the first and the second circuit arrangement 11 , 12th arranged. The cavity structure 14th has a lower pressure compared to an ambient atmospheric pressure. The ambient atmospheric pressure does not have to be the air pressure, but here it is generally the pressure of the device 10 surrounding medium. The ambient atmospheric pressure can also be referred to as the hydrostatic pressure of the respective medium. This can vary depending on the position and height. For example, the standard air pressure at sea level is around 1013.25 hPa, i.e. around 1 bar.

For example, in the cavity structure 14th a vacuum prevail, at least as far as a vacuum can be produced within the scope of what is technically feasible. In reality, this will usually not be an absolute or one hundred percent vacuum. The term “vacuum” is therefore used for the present disclosure as the definition common in technology, namely that this is an almost completely evacuated space.

According to an embodiment, the pressure in the cavity structure can be less than 10% or less than 1% of the ambient atmospheric pressure. In the cavity structure 14th So there is a negative pressure compared to the ambient atmospheric pressure. For example, with the above-mentioned standard air pressure at sea level, the negative pressure is in the cavity structure 14th less than about 101.33 hPa, that is to say about 0.1 bar, or less than about 10.13 hPa, that is about 0.01 bar.

The pressure in the cavity structure decreases 14th below 0.3 bar or 300 mbar and more and more molecules from the cavity structure 14th removed, one obtains a rough vacuum, fine vacuum, high vacuum and finally ultra-high vacuum (like in space). In this technical sense, a negative pressure with the low pressures specified in the present disclosure can be referred to with the generic term vacuum.

The 2A , 2 B , 2C and 2D show further examples of a device 10 according to the present disclosure and illustrate conceivable relative positions of the first circuit arrangement 11 , the second circuit arrangement 12th and the cavity structure 14th relative to each other.

For example shows 2A an embodiment according to which the cavity structure 14th between the two circuit arrangements 11 , 12th in a lateral direction X ₁ extends and at least the first circuit arrangement 11 or the second circuit arrangement 12th completely within a projection P of the cavity structure 14th perpendicular to this lateral extension direction X ₁ is arranged.

This projection P is intended with reference to 2D are explained in more detail. This is a top view of the device 10 . It is the lateral dimensions of the substrate arrangement 13th , the first circuit arrangement 11 , the second circuit arrangement 12th and the cavity structure 14th to see.

As mentioned at the outset, the cavity structure extends 14th in a lateral extension direction X ₁ . As in 2D is recognizable, can become the cavity structure 14th also extend in a second lateral extension direction Y ₁ which can be seen here. In the 2D The top view shown thus shows the projection P of the cavity structure 14th perpendicular to the lateral extension directions X ₁ , Y ₁ .

As can also be seen, the first circuit arrangement 11 and the second circuit arrangement 12th completely within this projection P of the cavity structure 14th lie.

In 1 for example, there is only the second circuit arrangement 12th completely within the projection P of the cavity structure 14th and the first circuit arrangement 11 lies only in sections within the projection P of the cavity structure 14th . But it is also conceivable the other way around.

In 2 B can both the first and the second circuit arrangement 11 , 12th in sections within the projection P of the cavity structure 14th lie.

2C shows an embodiment with two cavity structures 14a , 14b , wherein both the first and the second circuit arrangement 11 , 12th each section within the projection P _a , P _b of at least one of the two cavity structures 14a , 14b can lie. The same applies, of course, to the areas of overlap if only one of the two cavity structures shown 14a , 14b would exist.

The 3A to 3L show individual process steps that can be carried out in the sequence shown or in a sequence deviating therefrom in order to make an above-mentioned device 10 to obtain. One or more of the in the 3A to 3K The illustrated process steps can be optional.

In 3A becomes a first substrate 31 provided. The substrate 31 can be a wafer substrate, which is separated into individual chips after processing has taken place. In the case of the substrate or wafer substrate 31 it can be a silicon substrate, for example.

On the in 3A pictured overhead or first surface 30A of the wafer substrate 31 becomes a first layer 32 , for example a passivation and / or etch stop layer, for example an oxide layer 32 , deposited. On the oxide layer 32 becomes another layer 33 deposited, which is designed to distribute heat or thermal radiation. On this shift 33 it can be, for example, a polysilicon layer.

On the two layers 32 , 33 becomes another layer 34 deposited. This can be a nitride layer. The nitride layer 34 can be designed to form an oscillatable membrane, as will be described in more detail later.

As in 3B can then be a heating element 35 be structured. The heating element 35 can have metal, preferably with a high coefficient of thermal conductivity, such as platinum. The heating element 35 can be on the first side or surface 30A of the wafer substrate 31 along, for example meandering, extend.

The heating element 35 can with another layer 36 , for example another nitride layer 36 to be covered. In addition, a further passivation and / or etch stop layer can be used 37 , for example another oxide layer 37 , on the structured wafer substrate 31 to be deposited.

As in 3C As shown, an oxide removal process can then be used to remove the oxide layers 32 , 37 at least in the area of the heating elements 35 and the portions of the nitride and polysilicon layers disposed therebetween 33 , 34 to remove. Common dry or wet chemical etching processes can be used for this.

The first circuit arrangement that heats up during operation 11 has at least the aforementioned heating elements 35 on. The heating elements 35 can, as will be described in more detail later, be electrically contacted so that the heating elements 35 heat up as a result. The resulting heat can be given off, for example, in the form of infrared radiation (IR radiation).

The one from the first circuit arrangement 11 or the heating elements 35 Heat generated can be applied to at least one of the heating elements 35 thermally coupled layers 33 , 34 be transmitted.

The polysilicon layer 33 be designed, for example, as a heat spreader layer. Thus, this heat dissipating layer 33 also as a heat distribution element 33 are designated. This heat distribution element 33 is designed to be used by the first circuit arrangement 11 generated heat approximately evenly over the entire surface of the heat distribution device 33 to distribute.

The heating elements 35 can be used together with the heat distribution element 33 form an IR emitter. Thus, the first circuit arrangement 11 an IR emitter 33 , 35 on.

The one above the heat distribution element 33 arranged nitride layer 34 can be designed as a membrane that reacts to air vibrations and can be used, for example, as a microphone membrane.

With the optional steps described so far, one can therefore create a substrate arrangement 31 with a first circuit arrangement that heats up during operation 11 receive. This in 3C depicted substrate arrangement 31 can also be referred to as an emitter wafer.

In 3D becomes a second substrate 38 or a second wafer substrate 38 , for example a silicon wafer substrate 38 , provided. On the processed first wafer substrate 31 facing side can be the second wafer substrate 38 a coating 39 which is designed to filter light of a certain wavelength. For example, this can be a layer 39 act that allows light in the infrared wavelength range (IR) to pass.

On the IR filter layer 39 can be another coating 40 be arranged. This can be, for example, a SOG layer (Spin On Glass), the surface of the second wafer substrate 38 to planarize.

As in 3E can then be seen, both wafer substrates 31 , 38 are bonded together. The oxide layer is used for this 37 of the first wafer substrate 31 with the SOG layer 40 of the second wafer substrate 38 connected This forms in an area between the heating elements 35 a cavity structure 41 out.

For bonding the two wafer substrates 31 , 38 A vacuum bonding process can be used, so that in the cavity structure 41 forms a vacuum.

One of two substrates is thus obtained 31 , 38 Existing substrate arrangement with a first circuit arrangement which heats up during operation 11 .

As in 3F shown, the first wafer substrate 31 optionally to a desired strength or thickness D ₁ , for example, 50 µm or less, can be thinned out. Here the second side 30B or the underside of the wafer substrate 31 , for example by polishing, grinding, etc., be thinned out.

As in 3G shown can be based on the first circuit arrangement 11 facing away from the bottom 30B of the first wafer substrate 31 a cavity 42 in the first wafer substrate 31 be formed. This cavity 42 can be formed, for example, by means of common structuring processes.

In the cavity 42 can optionally be a reflection arrangement 43 for reflecting one of the first circuit arrangement 11 given thermal radiation are provided. This reflection arrangement 43 can be at the bottom of the cavity 42 , ie on one of the first circuit arrangement 11 facing surface area of the cavity 42 , to be ordered. The reflection arrangement 43 can be used as a layer, for example as a metal layer, in the cavity 42 separated and structured accordingly.

It is conceivable that the reflection arrangement 43 has approximately the same lateral dimensions as the first circuit arrangement 11 and / or the second circuit arrangement 12th . In addition, the reflection arrangement 43 completely within a projection of the cavity 42 or completely within a projection of the first and / or second circuit arrangement 11 , 12th perpendicular to (see 2D ) the lateral extension direction of the cavity 42 or circuit arrangements 11 , 12th be arranged.

As in 3H is shown, a third substrate or wafer substrate 44 , e.g. a silicon wafer substrate 44 , to be provided. In this third wafer substrate 44 can have a second circuit arrangement 12th be integrated. In the example shown here, the second circuit arrangement can be 12th be an integrated ASIC (Application Specific Integrated Circuit). This ASIC 12th can be at the rear on the second side or underside 30B of the first wafer substrate 31 to be ordered. The ASIC 12th can therefore also be referred to as a flipped ASIC.

That the second circuit arrangement 12th comprising third wafer substrate 44 can therefore on one of the first circuit arrangement 11 opposite side 30B of the first wafer substrate 31 be arranged or bonded. The ASIC 12th itself can be on the bond side or on the first wafer substrate 31 opposite side 30C of the third wafer substrate 44 be integrated or structured.

On this same page 30C of the third wafer substrate 44 can optionally also have electrical connection contact surfaces 45 , e.g. bond pads 45 , for making electrical contact with the ASICS 12th be provided. The entire device 10 can thus be mounted later on, for example, a PCB or the like using flip-chip mounting technology.

The result of bonding the first wafer substrate 31 with the third wafer substrate 44 is in 31 pictured.

In 31 it can be seen that by bonding the first wafer substrate 31 with the third wafer substrate 44 a closed cavity structure 14th is trained. The first wafer substrate 31 and the third wafer substrate 44 can be bonded together using a vacuum bonding process so that in the cavity structure 14th there is a vacuum within the meaning of the present disclosure.

With the steps described so far, some of which are optional, you can create a device 10 with a substrate arrangement 13th obtained, this substrate arrangement 13th a first circuit arrangement which heats up during operation 11 and a second circuit arrangement 12th in a substrate material of the substrate assembly 13th is integrated, has.

The substrate arrangement 13th In this exemplary embodiment, has at least the emitter wafer, ie the first wafer substrate described above 31 , and the ASIC wafer, ie the third wafer substrate described above 44 on. The entire device 10 can be optional, as here in 31 is shown next to this substrate arrangement 13th also a filter substrate, ie the previously described second wafer substrate 38 , exhibit.

In the 31 depicted substrate arrangement 13th In this exemplary embodiment, has two partial substrate arrangements stacked one on top of the other S ₁ , S ₂ on. The first sub-substrate arrangement S ₁ is in this embodiment by the first wafer substrate described above 31 represents. The first sub-substrate arrangement S ₁ has the first circuit arrangement 11 on. The second sub-substrate arrangement S ₂ is in this embodiment by the ASIC 12th comprising third wafer substrate 44 represents.

The device 10 has one between the first and second circuitry 11 , 12th arranged cavity structure 14th in the substrate material of the substrate assembly 13th is formed and has a lower pressure compared to an ambient atmospheric pressure.

As mentioned earlier, the void structure is 14th as a closed recess in at least one of the two partial substrate arrangements S ₁ , S ₂ educated. In the method described above, this recess was 14th through those in the first wafer substrate 31 formed cavity 42 educated. But it is just as easy to imagine that such a cavity 42 at the corresponding location in the third wafer substrate 44 , or in both the first and third wafer substrates 31 , 44 is trained.

As before with reference to 3C has been described, the first circuit arrangement 11 one or more heating elements 35 exhibit. The layer 33 can be thermal with the heating element 35 be coupled and serve as a heat-dissipating or heat-radiating layer, which together with the heating elements 35 can form an IR emitter.

The one from the first circuit arrangement 11 Radiated heat can thus be radiated, for example, in the form of electromagnetic radiation, and in particular in the form of infrared radiation. The one from the first circuit arrangement 11 emitted electromagnetic radiation has a main emission direction 47 on. The main direction of radiation 47 can, as shown, in the direction of the second wafer substrate 38 be directed, wherein the radiated heat radiation through the second wafer substrate 38 can be decoupled through into the environment. In this main direction of radiation 47 a major part, ie over 50%, of the radiated thermal radiation can be radiated.

The one from the first circuit arrangement 11 emitted electromagnetic radiation can also have a secondary emission direction 48 exhibit. This secondary emission direction 48 is from the main radiation direction 47 differently. In this exemplary embodiment, the secondary emission direction is 48 towards the cavity structure 14th , and thus the main direction of radiation 47 opposite, directed.

The ones in the secondary emission direction 48 emitted electromagnetic radiation can be at the reflection arrangement described above 43 in the main direction of radiation 47 be reflected back.

As before with reference to 3D has been described, the device 10 an optical filter 39 on. In the exemplary embodiment described here, this can be the layer described at the beginning 39 act, which can be formed, for example, as an IR filter layer.

The optical filter 39 can be in the main direction of radiation 47 after the first circuit arrangement 11 be arranged. In addition, between the first circuit arrangement 11 and the optical filter 39 the, previously referring to 3E mentioned, second cavity structure 41 be trained. This second cavity structure 41 can have a pressure which is lower than that of ambient atmospheric pressure.

According to one exemplary embodiment, that is in the second cavity structure 41 prevailing pressure less than 10% or less than 1% of the ambient atmospheric pressure. The second Cavity structure 41 can have a vacuum within the meaning of the present disclosure.

The optical filter 39 can, according to conceivable embodiments, monolithically with the second wafer substrate 38 or with the third sub-substrate arrangement S ₃ be trained. As a reminder, the third sub-substrate arrangement S ₃ can be the second wafer substrate 38 and optionally further substrates (not shown here for the sake of simplicity).

According to the in 31 The illustrated embodiment can use the optical filter 39 on the third sub-substrate arrangement S ₃ be arranged, this third sub-substrate arrangement S ₃ with which the first and the second sub-substrate arrangements S ₁ , S ₂ having substrate arrangement 13th can be connected.

The third sub-substrate arrangement S ₃ can thus also be referred to as a filter wafer.

As in 31 is further shown, the substrate arrangement 13th at least one electrical connection 51 for contacting the first circuit arrangement 11 and at least one electrical connection 52 for contacting the second circuit arrangement 12th exhibit.

Contact surfaces 53 the electrical connections 51 , 52 can on one the second circuit arrangement 12th having portion of the substrate arrangement be arranged. In the present exemplary embodiment, the contact areas are 53 the electrical connections 51 , 52 at the ASIC 12th having second partial substrate arrangement S ₂ arranged. As a reminder, the second sub-substrate assembly S ₂ can be the third wafer substrate 44 and optionally further substrates (not shown here for the sake of simplicity).

The contact areas 53 are at the in 31 shown step of a passivation layer 49 , for example an oxide layer, covered.

The 3Y shows another possible process step. Here is a passivation layer 50 , for example a nitride layer, on top of the oxide layer 49 deposited and the contact surfaces 53 the electrical connections 51 , 52 for the first and the second circuit arrangement 11 , 12th were exposed, for example by means of plasma etching or using other suitable methods.

The electrical connection 51 the first circuit arrangement 11 is an example here in a TSV through-hole plating 55 (Eng. Through Silicon Via) formed, which extends through the substrate arrangement 13th extends therethrough.

Such a TSV through-hole plating can be used for this purpose 55 from that of the cavity structure 14th facing away from the rear 30C the second sub-substrate arrangement S ₂ starting in the direction of the first circuit arrangement 11 are etched, up to the oxide layer acting here as an etch stop 32 . Then the TSV via 55 processed in the form of an oxide spacer, and the TSV via 55 can be filled with a barrier layer and with a thermally and / or electrically conductive material. For filling the TSV through-hole plating 55 For example, copper can be used.

According to conceivable exemplary embodiments, the device can 10 a multiplicity (not explicitly shown here) laterally around the cavity structure 14th arranged around, filled with a thermally and / or electrically conductive material, TSV vias 55 exhibit.

The multiple TSV vias 55 a distance D ₁ to the cavity structure 14th that is less than a distance D ₂ to a lateral or lateral outside of the substrate arrangement. The TSV vias 55 can thus be as close as possible to the cavity structure 14th be arranged.

The process steps described above can be carried out on a single chip or, to save costs, at the wafer level. In the latter case, a wafer stack with a large number of the devices described above is at the end 10 in front.

This wafer stack can, as in 3K is shown to be isolated. You get a large number of individual packages 10 or individual devices 10 according to an embodiment.

Optionally, before separating the packages 10 a so-called RDL (Redistribution Layer) can be implemented to control the TSV through-hole plating 55 with the last metal of the ASIC 12th to contact.

In 3L is an isolated package 10 or an isolated device 10 pictured on a substrate 61 is arranged. This substrate 61 can for example be a printed circuit board PCB or a laminate of known type. The device 10 can be attached in so-called bump technology, using micropillar technology or using RDLs in an eWLB (embedded wafer level ball grid array). So-called bumps or pillars can be used for this 62 be used.

As described above, the device 10 multiple sub-substrate arrangements S ₁ , S ₂ , S ₃ have, which in turn have one or more individual substrates 31 , 38 , 44 can have. The first sub-substrate arrangement S ₁ can be a thickness W ₁ have, which is about 50 microns. The second sub-substrate arrangement S ₂ can be a thickness W ₂ have, which is about 65 µm. The third sub-substrate arrangement S ₂ a thick one W ₃ have, which is about 35 µm. The first and second substrates 31 , 44 can put together a thickness W ₄ of about 110 µm.

4th In summary, FIG. 8 shows a block diagram of an exemplary embodiment of a method according to the present disclosure.

In block 401 becomes a substrate assembly 13th with a first circuit arrangement that heats up during operation 11 and a second circuit arrangement 12th in a substrate material of the substrate assembly 13th is integrated, provided.

In block 402 becomes one between the first and second circuitry 11 , 12th arranged cavity structure 14th formed in the substrate material, the cavity structure 14th has a lower pressure compared to an ambient atmospheric pressure.

5 In summary, FIG. 8 shows a block diagram of a further exemplary embodiment of a method according to the present disclosure.

In block 501 becomes a first wafer substrate 31 with a first page 30A and an opposite second side 30B provided, being on the first page 30A a heat distribution layer 33 is arranged.

In block 502 becomes a heating element 35 on the heat distribution layer 33 structured.

In block 503 becomes a cavity 42 in the second page 30B of the first wafer substrate 31 etched and a heat reflective layer 43 becomes at the bottom of the cavity 42 arranged.

In block 504 becomes a second wafer substrate 44 with an integrated circuit 12th provided.

In block 505 become the first and second wafer substrates 31 , 44 bonded, the cavity 42 a closed cavity 14th forms that between the integrated circuit 12th and the heat distribution layer 33 is arranged and has a lower pressure than the ambient atmospheric pressure.

After the structural features have been described, the mode of operation shall be described with reference to FIG 3L to be discribed.

The device disclosed here 10 can for example be used as a photoacoustic sensor. The first circuit arrangement 11 can be a heating element 35 for radiating thermal radiation. The second circuit arrangement 12th can use an ASIC to control the heating element 35 be.

The heating element 35 can generate temperatures of 300 ° C to 800 ° C during operation. The underlying ASIC 12th should only heat up by a few 10 ° C. For example, the ASIC should not heat up to more than 65 ° C. The distance between the heating element 35 and the ASIC 12th inside the device 10 however is only a few micrometers. So you face the challenge of the ASIC 12th from the heating element 35 as far as possible to be thermally decoupled.

This is done in the device 10 among other things through the cavity structure 14th accomplished, being in the cavity structure 14th a negative pressure, and in particular a vacuum, is located. Because the vacuum between the heating element 35 and the ASIC 12th those from the heating element 35 poorly conducts given heat, little heat loss is generated here. That is, within the cavity structure 14th very little of the radiated heat is conducted into surrounding structures. Thermal radiation is the dominant effect here compared to thermal conduction.

One in the cavity structure 14th optionally available reflection arrangement 43 the heat radiation can also come from the ASIC 12th keep away. The reflection arrangement 43 is for this between the ASIC 12th and the heating element 35 arranged. In more general terms, the reflection arrangement is 43 between the first circuit arrangement 11 and the second circuit arrangement 12th arranged.

The heating element 35 and the one with the heating element 35 thermally coupled heat radiating layer 33 can together make a heat distribution element 33 , 35 form. The heat distribution element can be an IR emitter, for example. The IR emitter 33 , 35 can in at least one of at least two directions, ie in the direction of the cavity structure 14th and in the direction of the IR filter 39 , radiate.

The IR emitter 33 , 35 can be in a second cavity structure 41 are located in which there is also negative pressure or a vacuum. This vacuum also serves the purpose described above, with heat radiation dominating over heat conduction. Thus the IR emitter shines 33 , 35 just as well as without a vacuum. However, the thermal radiation can spread almost unhindered in the vacuum. The vacuum thus avoids unwanted heating of the surrounding structures.

The result is that with one device 10 According to the present disclosure, a desired photoacoustic effect clearly dominates over an undesired thermoacoustic effect.

Also the TSV vias filled with thermally conductive material 55 serve to improve the protection of the ASIC 12th from excessive heating. Heat, for example, via the cavity structure 14th to the emitter substrate 31 and / or to the ASIC substrate 44 is released, can by means of the thermally conductive filling in the TSV vias 55 recorded and discharged, for example, to a PCB or the like.

The more TSV vias 55 are present, and the closer they are to the cavity structure 14th are arranged, the more heat can be dissipated here.

The idea of this disclosure is to be summarized again in other words below.

With integrated circuits, such as MEMS (Micro-Electro-Mechanical-Systems), the size and height as well as the power loss play a major role, especially if the chip is to be implemented in mobile devices such as smartphones. In addition, the costs of MEMS solutions are important to consider.

For example, in an example of the present disclosure, an IR emitter and an IR filter are intended to be in a single package 10 can be implemented with an additional ASIC 12th and a microphone MEMS chip 11 with the smallest possible size or height and cost.

However, known solutions for this are too large and therefore not suitable for use in mobile devices.

The present disclosure offers a solution for minimizing the complete IR emitter / filter / ASIC system while at the same time reducing costs. In addition, the power loss in the application is reduced at the same time.

In existing concepts, the IR emitter, the filter and the ASIC are designed as separate components that have to be housed individually in a common housing. In some special solutions, the filter is arranged directly on the emitter, which is typically done chip-on-chip.

Existing solutions for a photoacoustic gas sensor, for example, provide for the IR chip to be designed with a thin heating membrane, a cavity in the silicon substrate and, optionally, a ventilation hole. In order to avoid excessive heating of the filter chip, a standoff layer made of SU8 (polymer) is arranged between the two chips, which is done chip by chip at chip level.

With this implementation, however, the height of the entire arrangement of emitter and filter becomes very large and can even become too large and / or emit too much heat and power to be used in mobile applications. In all of these known applications, however, the ASIC is arranged separately below the emitter.

An exemplary embodiment of the present disclosure, however, provides the device 10 and to carry out the method at the wafer level and to use wafer-to-wafer bonding processes in order to save both the size and the associated costs. The emitter 33 , 35 , the filter 39 and the ASIC 12th can be stacked on top of each other at wafer level and as a complete chip stack 10 are manufactured.

Specifically, embodiments can provide that a cavity 14th including a heating membrane 33 , 34 and a filter 39 processed by means of a hermetic sealing-bonding process. The bonding can be carried out in a vacuum, so that the heating element 33 , 34 , 35 and the filter 39 stand under vacuum.

At a later point in this process, this wafer stack formed in this way can be hermetically sealed with the ASIC wafer 44 be bonded under vacuum, using a vacuum cavity 14th in the emitter wafer 31 is included.

Because of the vacuum in this cavity 14th between the filter 39 and the emitter 33 , 34 , 35 the power loss can be reduced considerably, as the heat conduction in the vacuum is reduced and heat radiation instead becomes the only dominant effect.

Due to the vacuum between the emitter wafer 31 and the ASIC wafer 44 can cause the ASIC to heat up 12th through the emitter 33 , 34 , 35 be reduced. An electrical connection to the emitter 33 , 34 , 35 with the ASIC 12th can for example by means of a Through-Silicon-Via (TSV) 55 will be realized.

In this example the ASIC chip should be 44 and the emitter chip 31 be roughly the same size.

Individual steps of a possible exemplary embodiment for a method according to the present disclosure are to be briefly and concisely again below with reference to 3A to 3L , can be summarized.

In 3A becomes a silicon substrate wafer 31 with an oxide layer 32 and a polysilicon heat spreader layer 33 preprocessed. On top is a nitride layer 34 deposited.

In 3B becomes a metallic heating element 35 (e.g. platinum) structured and using nitride 36 and oxide 37 covered.

In 3C an oxide-releasing etching is carried out in the area of the heat spreader 33 , 34 and the heating element 35 .

In 3D becomes an additional wafer 38 with an IR filter layer 39 and a spin-on-glass layer 40 prepared.

In 3E become both wafers 31 , 38 hermetically bonded under vacuum.

In 3F becomes the emitter wafer 31 thinned to the nominal thickness, typically about 50 µm.

In 3G will be in the back of the emitter wafer 31 a cavity 42 etched and a reflective metal shield 43 will be in this cavity 42 separated and shaved.

In 3H becomes the ASIC wafer 44 with bond pads 45 Mistake.

In 31 become the emitter / filter wafer 31 , 38 and the ASIC wafer 44 hermetically bonded under vacuum. It then becomes an oxide 49 deposited and a TSV 55 is formed (e.g. by means of TSV etching with an etch stop on the oxide 32 on the emitter wafer 31 ). An oxide spacer is formed and the TSV 55 is filled with a barrier and copper, and the copper is attached to the back of the wafer 44 structured.

In 3Y becomes a passivation nitride layer 50 deposited and the bond pads 52 are exposed by means of plasma etching.

In 3K becomes the wafer stack 10 occasionally (dicing). Optionally, a so-called redistribution layer (RDL) can be implemented before the separation in order to protect the TSV 55 with the last metal layer of the ASIC 12th to connect (which saves space).

In 3L becomes the chip 10 placed on a laminate / PCB / eWLB etc., e.g. using bump technology, micropillars 62 or RDL in eWLB (embedded Wafer Level Ball Grid Array).

An optionally conceivable solution could provide the filter 39 monolithically in, on or on the emitter wafer 31 to integrate, and the emitter wafer 31 and the ASIC wafer 44 to bond under vacuum as described. Accordingly, a feature of this disclosure is the emitter wafer 31 and the ASIC wafer 44 stack at wafer level and draw a vacuum between the two stacked wafers / chips.

• • Strahlung im Vakuum reduziert Wärmeleitung
• • ein Aufheizen des ASICs 12 durch den Emitter 33, 34, 35 wird reduziert aufgrund des Vakuums zwischen den beiden Wafern (Emitter-Wafer 31 und ASIC-Wafer 44)
• • Reduzierung des gesamten Systemvolumens bezüglich Höhe und Fläche
• • Integration von Filter 39, Heizsystem 33, 34, 35 und ASIC 12 auf Wafer-Level reduziert Kosten
• • der Chipstapel 10 kann mittels Microbumps 62 und Micropillars auf einem PCB oder ähnlichem Substrat 61 unterhalb von weiteren Chips, wie z.B. einem MEMS-Mikrofon, angeordnet werden
• • mit wärmeleitfähigem Material (z.B. Kupfer) gefüllte TSVs 55 können vom Emitter 33, 34, 35 abgegebene Wärme an dem ASIC 12 vorbei und z.B. in das PCB 61 oder ein ähnliches Substrat ableiten.

In summary, the device and the method according to the present disclosure offer the following advantages:

• • Radiation in a vacuum reduces heat conduction
• • a heating up of the ASIC 12th through the emitter 33 , 34 , 35 is reduced due to the vacuum between the two wafers (emitter wafer 31 and ASIC wafers 44 )
• • Reduction of the total system volume in terms of height and area
• • Integration of filters 39 , Heating system 33 , 34 , 35 and ASIC 12th reduces costs at wafer level
• • the stack of chips 10 can by means of microbumps 62 and micropillars on a PCB or similar substrate 61 be arranged below other chips, such as a MEMS microphone
• • TSVs filled with thermally conductive material (eg copper) 55 can from the emitter 33 , 34 , 35 dissipated heat at the ASIC 12th over and e.g. in the PCB 61 or derive a similar substrate.

1. 1. Vorrichtung (10) mit einer Substratanordnung mit einer ersten, sich im Betrieb erwärmenden Schaltungsanordnung (11) und einer zweiten Schaltungsanordnung (12), die in einem Substratmaterial der Substratanordnung integriert ist, und einer zwischen der ersten und der zweiten Schaltungsanordnung (11, 12) angeordneten Hohlraumstruktur (14), die in dem Substratmaterial ausgebildet ist, und einen gegenüber einem Umgebungsatmosphärendruck geringeren Druck aufweist.
2. 2. Vorrichtung (10) nach Aspekt 1, wobei der Druck in der Hohlraumstruktur (14) weniger als 10% oder weniger als 1% des Umgebungsatmosphärendrucks beträgt.
3. 3. Vorrichtung (10) nach Aspekt 1, wobei sich die Hohlraumstruktur (14) zwischen den beiden Schaltungsanordnungen (11, 12) in einer lateralen Richtung (X₁ , Y₁) erstreckt und zumindest die erste Schaltungsanordnung (11) oder die zweite Schaltungsanordnung (12) vollständig innerhalb einer Projektion der Hohlraumstruktur (14) senkrecht zu dieser lateralen Erstreckungsrichtung (X_1, Y₁) angeordnet ist.
4. 4. Vorrichtung (10) nach Aspekt 1, wobei die Substratanordnung zwei übereinander gestapelte Teilsubstratanordnungen (S₁ , S₂ ) aufweist, wobei eine erste Teilsubstratanordnung (S₁ ) die erste Schaltungsanordnung (11) und eine zweite Teilsubstratanordnung (S₂ ) die zweite Schaltungsanordnung (12) aufweist, und die Hohlraumstruktur (14) als eine verschlossene Ausnehmung in zumindest einer der beiden Teilsubstratanordnungen (S₁ , S₂ ) ausgebildet ist.
5. 5. Vorrichtung (10) nach Aspekt 1, wobei die Vorrichtung (10) ein mit der ersten Schaltungsanordnung (11) gekoppeltes Wärmeverteilelement (33) aufweist, das ausgebildet ist, um die von der ersten Schaltungsanordnung (11) erzeugte Wärme etwa gleichmäßig über die gesamte Oberfläche des Wärmeverteilelements (33) zu verteilen.
6. 6. Vorrichtung (10) nach Aspekt 1, wobei die erste Schaltungsanordnung (11) einen IR-Emitter (33, 35) aufweist.
7. 7. Vorrichtung (10) nach Aspekt 1, wobei die Vorrichtung (10) eine Reflektionsanordnung (43) zum Reflektieren einer von der ersten Schaltungsanordnung (11) abgegebenen Wärmestrahlung aufweist, wobei die Reflektionsanordnung (43) innerhalb der Hohlraumstruktur (14) an einem der ersten Schaltungsanordnung (11) zugewandten Oberflächenbereich der Hohlraumstruktur (14) angeordnet ist.
8. 8. Vorrichtung (10) nach Aspekt 1, wobei die Vorrichtung (10) ein optisches Filter (39) aufweist, das ausgebildet ist, um eine von der ersten Schaltungsanordnung (11) ausgestrahlte elektromagnetische Strahlung zu filtern, wobei das optische Filter (39) in einer Hauptabstrahlrichtung (47) der elektromagnetischen Strahlung nach der ersten Schaltungsanordnung (11) angeordnet ist, und wobei zwischen der ersten Schaltungsanordnung (11) und dem Filter (39) eine zweite Hohlraumstruktur (41) ausgebildet ist, die einen gegenüber einem Umgebungsatmosphärendruck geringeren Druck aufweist.
9. 9. Vorrichtung (10) nach Aspekt 8, wobei der Druck in der zweiten Hohlraumstruktur (41) weniger als 10% oder weniger als 1% des Umgebungsatmosphärendrucks beträgt.
10. 10. Vorrichtung (10) nach Aspekt 8, wobei das optische Filter (39) monolithisch mit der Substratanordnung ausgebildet ist.
11. 11. Vorrichtung (10) nach Aspekt 8, wobei das optische Filter (39) an einer dritten Teilsubstratanordnung (S₃ ) angeordnet ist, und diese dritte Teilsubstratanordnung (S₃ ) mit der Substratanordnung verbunden ist.
12. 12. Vorrichtung (10) Aspekt 1, wobei die Substratanordnung zumindest einen elektrischen Anschluss (51) zum Kontaktieren der ersten Schaltungsanordnung (11) und zumindest einen elektrischen Anschluss (52) zum Kontaktieren der zweiten Schaltungsanordnung (12) aufweist, wobei Kontaktflächen (53) der elektrischen Anschlüsse (51, 52) an einem die zweite Schaltungsanordnung (12) aufweisenden Abschnitt der Substratanordnung angeordnet sind.
13. 13. Vorrichtung (10) nach Aspekt 12, wobei durch die Substratanordnung hindurch eine Durchkontaktierung (55) ausgebildet ist, die eine Kontaktfläche (53) des zumindest einen elektrischen Anschluss (51) zum Kontaktieren der ersten Schaltungsanordnung (11) elektrisch leitend mit der ersten integrierten Schaltungsanordnung (11) verbindet, wobei diese Durchkontaktierung (55) mit einem thermisch und elektrisch leitfähigen Material gefüllt ist.
14. 14. Vorrichtung (10) nach Aspekt 13, wobei die Vorrichtung (10) eine Vielzahl von lateral um die Hohlraumstruktur (14) herum angeordneten, mit einem thermisch und elektrisch leitfähigen Material gefüllten, Durchkontaktierungen (55) aufweist.
15. 15. Vorrichtung (10) nach Aspekt 13, wobei ein Abstand (D₁ ) zwischen der Durchkontaktierung (55) und der Hohlraumstruktur (14) geringer ist als ein Abstand (D₂ ) zwischen der Durchkontaktierung (55) und einer Außenseite der Substratanordnung.
16. 16. Waferstack mit einer Vielzahl an Vorrichtungen (10) gemäß Aspekt 1.
17. 17. Verfahren mit den folgenden Schritten:
    • Bereitstellen einer Substratanordnung mit einer ersten, sich im Betrieb erwärmenden Schaltungsanordnung (11) und einer zweiten Schaltungsanordnung (12), die in einem Substratmaterial der Substratanordnung integriert ist, und
    • Ausbilden einer zwischen der ersten und der zweiten Schaltungsanordnung (11, 12) angeordneten Hohlraumstruktur (14) in dem Substratmaterial, wobei die Hohlraumstruktur (14) einen gegenüber einem Umgebungsatmosphärendruck geringeren Druck aufweist.
18. 18. Verfahren nach Aspekt 17, wobei der Schritt des Ausbildens der Hohlraumstruktur (14) beinhaltet, dass der Druck in der Hohlraumstruktur (14) weniger als 10% oder weniger als 1% des Umgebungsatmosphärendrucks beträgt.
19. 19. Verfahren nach Aspekt 17, wobei der Schritt des Bereitstellens der Substratanordnung beinhaltet, dass zwei Teilsubstratanordnungen (S₁ , S₂ ) übereinander gestapelt werden, wobei eine erste Teilsubstratanordnung (S₁ ) die erste Schaltungsanordnung (11) aufweist und eine zweite Teilsubstratanordnung (S₂ ) die zweite Schaltungsanordnung (12) aufweist, und wobei der Schritt des Ausbildens der Hohlraumstruktur (14) beinhaltet, dass die Hohlraumstruktur (14) als eine verschlossene Ausnehmung (42) in zumindest einer der beiden Teilsubstratanordnungen (S₁ , S₂ ) ausgebildet wird.
20. 20. Verfahren nach Aspekt 19, wobei die erste Teilsubstratanordnung (S₁ ) und die zweite Teilsubstratanordnung (S₂ ) unter Anwendung eines Vakuum-BondVerfahrens miteinander verbunden werden.
21. 21. Verfahren nach Aspekt 17, wobei eine Reflektionsanordnung (43) zum Reflektieren einer von der ersten Schaltungsanordnung (11) abgegebenen Wärmestrahlung bereitgestellt wird, wobei die Reflektionsanordnung (43) innerhalb der Hohlraumstruktur (14) an einem der ersten Schaltungsanordnung (11) zugewandten Oberflächenbereich der Hohlraumstruktur (14) angeordnet wird.
22. 22. Verfahren nach Aspekt 17, aufweisend ein Bereitstellen eines optischen Filters (39), das ausgebildet ist, um eine von der ersten Schaltungsanordnung (11) ausgestrahlte elektromagnetische Strahlung zu filtern, wobei das optische Filter (39) in einer Hauptabstrahlrichtung (47) der elektromagnetischen Strahlung nach der ersten Schaltungsanordnung (11) angeordnet wird, und Ausbilden einer zweiten Hohlraumstruktur (41) zwischen der ersten Schaltungsanordnung (11) und dem Filter (39), wobei die zweite Hohlraumstruktur (41) einen gegenüber dem Umgebungsatmosphärendruck geringeren Druck aufweist.
23. 23. Verfahren nach Aspekt 22, wobei der Schritt des Ausbildens der zweiten Hohlraumstruktur (41) beinhaltet, dass der Druck in der zweiten Hohlraumstruktur (41) weniger als 10% oder weniger als 1% des Umgebungsatmosphärendrucks beträgt.
24. 24. Verfahren nach Aspekt 22, wobei das optische Filter (39) monolithisch mit der Substratanordnung ausgebildet wird.
25. 25. Verfahren nach Aspekt 22, wobei das optische Filter (39) an einer dritten Teilsubstratanordnung (S₃ ) angeordnet wird, und diese dritte Teilsubstratanordnung (S₃ ) mit der Substratanordnung verbunden wird.
26. 26. Verfahren nach Aspekt 17, aufweisend ein Bereitstellen von zumindest einem elektrischen Anschluss (51) zum Kontaktieren der ersten Schaltungsanordnung (11) und zumindest einem elektrischen Anschluss (52) zum Kontaktieren der zweiten Schaltungsanordnung (12), wobei Kontaktflächen (53) der elektrischen Anschlüsse (51, 52) an einem die zweite Schaltungsanordnung (12) aufweisenden Abschnitt der Substratanordnung angeordnet werden.
27. 27. Verfahren nach Aspekt 26, aufweisend ein Ausbilden von zumindest einer sich durch die Substratanordnung hindurch erstreckenden Durchkontaktierung (55), die eine Kontaktfläche (53) des zumindest einen elektrischen Anschlusses (51) zum Kontaktieren der ersten Schaltungsanordnung (11) elektrisch leitend mit der ersten Schaltungsanordnung (11) verbindet, und Füllen dieser Durchkontaktierung (55) mit einem elektrisch und thermisch leitfähigen Material.
28. 28. Verfahren nach Aspekt 27, ferner aufweisend ein Ausbilden einer Vielzahl von lateral um die Hohlraumstruktur (14) herum angeordneten, mit elektrisch und thermisch leitfähigem Material gefüllten, Durchkontaktierungen (55).
29. 29. Verfahren nach Aspekt 27, wobei der Schritt des Ausbildens von zumindest einer Durchkontaktierung (55) beinhaltet, dass die zumindest eine Durchkontaktierung (55) derart gegenüber dem Hohlraum (14) angeordnet wird, dass ein Abstand (D₁ ) zwischen der Durchkontaktierung (55) und der Hohlraumstruktur (14) geringer ist als ein Abstand (D₂ ) zwischen der Durchkontaktierung (55) und einer Außenseite der Substratanordnung.
30. 30. Verfahren mit den folgenden Schritten:
    • Bereitstellen eines ersten Wafersubstrats (31) mit einer ersten Seite (30A) und einer gegenüberliegenden zweiten Seite (30B), wobei auf der ersten Seite (30A) eine Wärmeverteilschicht (33) angeordnet ist,
    • Strukturieren eines Heizelements (35) auf der Wärmeverteilschicht (33),
    • Ätzen einer Kavität (14) in die zweite Seite (30B) des ersten Wafersubstrats (31) und Anordnen einer Wärmereflektionsschicht (43) am Grund der Kavität (14),
    • Bereitstellen eines zweiten Wafersubstrats (44) mit einer integrierten Schaltung (12), und
    • Bonden des ersten und des zweiten Wafersubstrats (31, 44), wobei die Kavität (14) einen geschlossenen Hohlraum bildet, der zwischen der integrierten Schaltung (12) und der Wärmeverteilschicht (33) angeordnet ist und einen gegenüber dem Umgebungsatmosphärendruck geringeren Druck aufweist.

The present disclosure may include the following aspects:

1. 1. Device ( 10 ) with a substrate arrangement with a first circuit arrangement which heats up during operation ( 11 ) and a second circuit arrangement ( 12th ), which is integrated in a substrate material of the substrate arrangement, and one between the first and the second circuit arrangement ( 11 , 12th ) arranged cavity structure ( 14th ), which is formed in the substrate material, and has a lower pressure compared to an ambient atmospheric pressure.
2. 2nd device ( 10 ) by aspect 1 , where the pressure in the cavity structure ( 14th ) is less than 10% or less than 1% of ambient atmospheric pressure.
3. 3rd device ( 10 ) by aspect 1 , where the cavity structure ( 14th ) between the two circuit arrangements ( 11 , 12th ) in a lateral direction ( X ₁ , Y ₁ ) and at least the first circuit arrangement ( 11 ) or the second circuit arrangement ( 12th ) completely within a projection of the cavity structure ( 14th ) perpendicular to this lateral extension direction ( X _1, Y ₁ ) is arranged.
4. 4. Device ( 10 ) by aspect 1 , wherein the substrate arrangement is two sub-substrate arrangements stacked one on top of the other ( S ₁ , S ₂ ), wherein a first sub-substrate arrangement ( S ₁ ) the first circuit arrangement ( 11 ) and a second sub-substrate arrangement ( S ₂ ) the second circuit arrangement ( 12th ), and the cavity structure ( 14th ) as a closed recess in at least one of the two partial substrate arrangements ( S ₁ , S ₂ ) is trained.
5. 5th device ( 10 ) by aspect 1 , where the device ( 10 ) one with the first circuit arrangement ( 11 ) coupled heat distribution element ( 33 ), which is designed to be used by the first circuit arrangement ( 11 ) generated heat approximately evenly over the entire surface of the heat distribution element ( 33 ) to distribute.
6. 6. Device ( 10 ) by aspect 1 , where the first circuit arrangement ( 11 ) an IR emitter ( 33 , 35 ) having.
7. 7. Device ( 10 ) by aspect 1 , where the device ( 10 ) a reflection arrangement ( 43 ) to reflect one of the first circuit arrangement ( 11 ) emitted heat radiation, wherein the reflection arrangement ( 43 ) within the cavity structure ( 14th ) on one of the first circuit arrangement ( 11 ) facing surface area of the cavity structure ( 14th ) is arranged.
8. 8. Device ( 10 ) by aspect 1 , where the device ( 10 ) an optical filter ( 39 ), which is designed to provide one of the first circuit arrangement ( 11 ) to filter emitted electromagnetic radiation, whereby the optical filter ( 39 ) in a main radiation direction ( 47 ) the electromagnetic radiation after the first circuit arrangement ( 11 ) is arranged, and wherein between the first circuit arrangement ( 11 ) and the filter ( 39 ) a second cavity structure ( 41 ) is formed, which has a lower pressure compared to an ambient atmospheric pressure.
9. 9. Device ( 10 ) by aspect 8th , where the pressure in the second cavity structure ( 41 ) is less than 10% or less than 1% of ambient atmospheric pressure.
10. 10. Device ( 10 ) by aspect 8th , where the optical filter ( 39 ) is formed monolithically with the substrate arrangement.
11. 11. Device ( 10 ) by aspect 8th , where the optical filter ( 39 ) on a third sub-substrate arrangement ( S ₃ ) is arranged, and this third sub-substrate arrangement ( S ₃ ) is connected to the substrate arrangement.
12. 12. Device ( 10 ) Aspect 1 , wherein the substrate arrangement has at least one electrical connection ( 51 ) for contacting the first circuit arrangement ( 11 ) and at least one electrical connection ( 52 ) for contacting the second circuit arrangement ( 12th ), where contact surfaces ( 53 ) the electrical connections ( 51 , 52 ) on one the second circuit arrangement ( 12th ) having section of the substrate arrangement are arranged.
13. 13. Device ( 10 ) by aspect 12th , whereby a through-hole ( 55 ) is formed, which has a contact surface ( 53 ) of at least one electrical connection ( 51 ) for contacting the first circuit arrangement ( 11 ) electrically conductive with the first integrated circuit arrangement ( 11 ) connects, whereby this via ( 55 ) is filled with a thermally and electrically conductive material.
14. 14. Device ( 10 ) by aspect 13th , where the device ( 10 ) a multitude of laterally around the cavity structure ( 14th ) arranged around, filled with a thermally and electrically conductive material, vias ( 55 ) having.
15. 15. Device ( 10 ) by aspect 13th , where a distance ( D ₁ ) between the via ( 55 ) and the cavity structure ( 14th ) is less than a distance ( D ₂ ) between the via ( 55 ) and an outside of the substrate arrangement.
16. 16. Wafer stack with a variety of devices ( 10 ) according to aspect 1 .
17. 17. Procedure with the following steps:
    • Providing a substrate arrangement with a first circuit arrangement which heats up during operation ( 11 ) and a second circuit arrangement ( 12th ), which is integrated in a substrate material of the substrate arrangement, and
    • Forming a between the first and the second circuit arrangement ( 11 , 12th ) arranged cavity structure ( 14th ) in the substrate material, the cavity structure ( 14th ) has a lower pressure compared to an ambient atmospheric pressure.
18. 18. Procedure by aspect 17th , wherein the step of forming the cavity structure ( 14th ) implies that the pressure in the cavity structure ( 14th ) is less than 10% or less than 1% of ambient atmospheric pressure.
19. 19. Procedure by aspect 17th , wherein the step of providing the substrate arrangement includes that two sub-substrate arrangements ( S ₁ , S ₂ ) are stacked on top of each other, with a first partial substrate arrangement ( S ₁ ) the first circuit arrangement ( 11 ) and a second sub-substrate arrangement ( S ₂ ) the second circuit arrangement ( 12th ), and wherein the step of forming the cavity structure ( 14th ) implies that the cavity structure ( 14th ) as a closed recess ( 42 ) in at least one of the two partial substrate arrangements ( S ₁ , S ₂ ) is trained.
20. 20. Procedure by aspect 19th , wherein the first sub-substrate arrangement ( S ₁ ) and the second sub-substrate arrangement ( S ₂ ) are connected to one another using a vacuum bonding process.
21. 21. Procedure by aspect 17th , where a reflection arrangement ( 43 ) to reflect one of the first circuit arrangement ( 11 ) emitted heat radiation is provided, wherein the reflection arrangement ( 43 ) within the cavity structure ( 14th ) on one of the first circuit arrangement ( 11 ) facing surface area of the cavity structure ( 14th ) is arranged.
22. 22. Procedure by Aspect 17th , comprising providing an optical filter ( 39 ), which is designed to provide one of the first circuit arrangement ( 11 ) to filter emitted electromagnetic radiation, whereby the optical filter ( 39 ) in a main radiation direction ( 47 ) the electromagnetic radiation after the first circuit arrangement ( 11 ) is arranged, and forming a second cavity structure ( 41 ) between the first circuit arrangement ( 11 ) and the filter ( 39 ), where the second cavity structure ( 41 ) has a lower pressure than the ambient atmospheric pressure.
23. 23. Procedure by aspect 22nd , wherein the step of forming the second cavity structure ( 41 ) implies that the pressure in the second cavity structure ( 41 ) is less than 10% or less than 1% of ambient atmospheric pressure.
24. 24. Procedure by aspect 22nd , where the optical filter ( 39 ) is formed monolithically with the substrate arrangement.
25. 25. Procedure by aspect 22nd , where the optical filter ( 39 ) on a third sub-substrate arrangement ( S ₃ ) is arranged, and this third sub-substrate arrangement ( S ₃ ) is connected to the substrate arrangement.
26. 26. Procedure by Aspect 17th , having a provision of at least one electrical connection ( 51 ) for contacting the first circuit arrangement ( 11 ) and at least one electrical connection ( 52 ) for contacting the second circuit arrangement ( 12th ), where contact areas ( 53 ) the electrical connections ( 51 , 52 ) on one the second circuit arrangement ( 12th ) having portion of the substrate arrangement are arranged.
27. 27. Procedure by aspect 26th , comprising the formation of at least one via extending through the substrate arrangement ( 55 ) that have a contact surface ( 53 ) of the at least one electrical connection ( 51 ) for contacting the first circuit arrangement ( 11 ) electrically conductive with the first circuit arrangement ( 11 ) connects, and filling this via ( 55 ) with an electrically and thermally conductive material.
28. 28. Procedure by aspect 27 , further comprising forming a plurality of laterally around the cavity structure ( 14th ) arranged around, filled with electrically and thermally conductive material, vias ( 55 ).
29. 29. Procedure by Aspect 27 , wherein the step of forming at least one via ( 55 ) includes that the at least one via ( 55 ) so opposite to the cavity ( 14th ) is arranged that a distance ( D ₁ ) between the via ( 55 ) and the cavity structure ( 14th ) is less than a distance ( D ₂ ) between the via ( 55 ) and an outside of the substrate arrangement.
30. 30. Procedure with the following steps:
    • Providing a first wafer substrate ( 31 ) with a first page ( 30A) and an opposite second side ( 30B) , where on the first page ( 30A) a heat distribution layer ( 33 ) is arranged,
    • Structuring a heating element ( 35 ) on the heat distribution layer ( 33 ),
    • Etching a cavity ( 14th ) in the second page ( 30B) of the first wafer substrate ( 31 ) and arranging a heat reflective layer ( 43 ) at the bottom of the cavity ( 14th ),
    • Providing a second wafer substrate ( 44 ) with an integrated circuit ( 12th ), and
    • Bonding the first and second wafer substrates ( 31 , 44 ), where the cavity ( 14th ) forms a closed cavity between the integrated circuit ( 12th ) and the heat distribution layer ( 33 ) is arranged and has a lower pressure compared to the ambient atmospheric pressure.

Although some aspects have been described in connection with a device, it goes without saying that these aspects also represent a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Analogously, aspects that have been described in connection with or as a method step also represent a description of a corresponding block or details or features of a corresponding device. Some or all of the method steps can be carried out by a hardware device (or using a hardware device). Apparatus), such as a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some or more of the most important process steps can be performed by such an apparatus.

Depending on specific implementation requirements, exemplary embodiments of the invention can be implemented in hardware or in software or at least partially in hardware or at least partially in software. The implementation can be carried out using a digital storage medium, for example a floppy disk, a DVD, a BluRay disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or any other magnetic or optical memory Memory are carried out on the electronically readable control signals are stored, which can interact with a programmable computer system or cooperate in such a way that the respective method is carried out. Therefore, the digital storage medium can be computer readable.

Some exemplary embodiments according to the invention thus include a data carrier which has electronically readable control signals which are capable of interacting with a programmable computer system in such a way that one of the methods described herein is carried out.

In general, exemplary embodiments of the present invention can be implemented as a computer program product with a program code, the program code being effective to carry out one of the methods when the computer program product runs on a computer.

The program code can, for example, also be stored on a machine-readable carrier.

Other exemplary embodiments include the computer program for performing one of the methods described herein, the computer program being stored on a machine-readable carrier. In other words, an exemplary embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer.

A further exemplary embodiment of the method according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the methods described herein is recorded. The data carrier or the digital storage medium or the computer-readable medium are typically tangible and / or non-transitory.

A further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents or represents the computer program for performing one of the methods described herein. The data stream or the sequence of signals can, for example, be configured to be transferred via a data communication connection, for example via the Internet.

Another exemplary embodiment comprises a processing device, for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.

Another exemplary embodiment comprises a computer on which the computer program for performing one of the methods described herein is installed.

Another exemplary embodiment according to the invention comprises a device or a system which is designed to transmit a computer program for performing at least one of the methods described herein to a receiver. The transmission can take place electronically or optically, for example. The receiver can be, for example, a computer, a mobile device, a storage device or a similar device. The device or the system can, for example, comprise a file server for transmitting the computer program to the recipient.

In some exemplary embodiments, a programmable logic component (for example a field-programmable gate array, an FPGA) can be used to carry out some or all of the functionalities of the methods described herein. In some exemplary embodiments, a field-programmable gate array can interact with a microprocessor in order to carry out one of the methods described herein. In general, in some exemplary embodiments, the methods are performed by any hardware device. This can be hardware that can be used universally, such as a computer processor (CPU), or hardware specific to the method, such as an ASIC, for example.

The embodiments described above are merely illustrative of the principles of the present invention. It is to be understood that modifications and variations of the arrangements and details described herein will be apparent to other skilled persons. It is therefore intended that the invention be limited only by the scope of protection of the following patent claims and not by the specific details presented herein with reference to the description and explanation of the exemplary embodiments.

Claims (28)

Device (10) having a substrate arrangement (13) with a first circuit arrangement (11) which heats up during operation, the first circuit arrangement (11) having at least one heating element (35) and a heat distribution element (33) coupled to the heating element (35) ; wherein the coupled heat distribution element (33) is designed to distribute the heat generated by the first circuit arrangement (11) approximately evenly over the entire surface of the heat distribution element (33); wherein the heat distribution element (33) and the heating element (35) together form an IR emitter for a photoacoustic sensor; a second circuit arrangement (12) which is integrated in a substrate material of the substrate arrangement (13), the second circuit arrangement (12) being designed to control the heating element (35); a cavity structure (14) which is arranged between the first and the second circuit arrangement (11, 12) and is formed in the substrate material and has a lower pressure than an ambient atmospheric pressure; wherein the cavity structure (14) is designed to thermally decouple the second circuit arrangement (12) from the heating element (35); and wherein the cavity structure (14) extends between the two circuit arrangements (11, 12) in a first and a second lateral direction (X _1, Y ₁ ), and wherein both the first circuit arrangement (11) and the second circuit arrangement (12 ) are arranged at least in sections within a projection of the cavity structure (14) perpendicular to the lateral extension directions (X _1, Y ₁ ). Device (10) according to Claim 1 , wherein the first circuit arrangement (11) and the second circuit arrangement (12) are arranged completely within the projection of the cavity structure (14) perpendicular to the lateral extension directions (X ₁ , Y ₁ ). Device (10) according to one of the preceding claims, wherein the device (10) has a reflection arrangement (43) for reflecting a thermal radiation emitted by the first circuit arrangement (11), the reflection arrangement (43) inside the cavity structure (14) at one of the First circuit arrangement (11) facing surface area of the cavity structure (14) is arranged. Device (10) according to one of the preceding claims, wherein the pressure in the cavity structure (14) is less than 10% or less than 1% of the ambient atmospheric pressure. Device (10) according to one of the preceding claims, wherein the substrate arrangement has two sub-substrate arrangements (S ₁ , S ₂ ) stacked one above the other, a first sub-substrate arrangement (S ₁ ) the first circuit arrangement (11) and a second sub-substrate arrangement (S ₂ ) the second Has circuit arrangement (12), and the cavity structure (14) is designed as a closed recess in at least one of the two partial substrate arrangements (S ₁ , S ₂ ). Device (10) according to one of the preceding claims, wherein the device (10) has an optical filter (39) which is designed to filter electromagnetic radiation emitted by the first circuit arrangement (11), the optical filter (39) is arranged in a main emission direction (47) of the electromagnetic radiation after the first circuit arrangement (11), and wherein a second cavity structure (41) is formed between the first circuit arrangement (11) and the filter (39), which has a lower pressure compared to an ambient atmospheric pressure having. Device (10) according to Claim 6 wherein the pressure in the second cavity structure (41) is less than 10% or less than 1% of the ambient atmospheric pressure. Device (10) according to Claim 6 or 7th wherein the optical filter (39) is monolithically formed with the substrate arrangement. Device (10) according to one of the Claims 6 to 8th , wherein the optical filter (39) is arranged on a third sub-substrate arrangement (S ₃ ), and this third sub- _{substrate arrangement (S 3} ) is connected to the substrate arrangement. Device (10) according to one of the preceding claims, wherein the heat radiation emitted by the first circuit arrangement (11) has a main radiation direction (47) and a secondary radiation direction (48); wherein a major portion of the radiated thermal radiation is radiated in this main radiation direction (47); and wherein the secondary emission direction (48) is directed in the direction of the cavity structure (14) and thus opposite to the main emission direction (47) of the first circuit arrangement (11). Device (10) according to one of the preceding claims, wherein the substrate arrangement has at least one electrical connection (51) for contacting the first circuit arrangement (11) and at least one electrical connection (52) for contacting the second circuit arrangement (12), wherein contact surfaces (53 ) the electrical connections (51, 52) are arranged on a section of the substrate arrangement having the second circuit arrangement (12). Device (10) according to Claim 11 , wherein a through-contact (55) is formed through the substrate arrangement, which connects a contact surface (53) of the at least one electrical connection (51) for contacting the first circuit arrangement (11) with the first integrated circuit arrangement (11) in an electrically conductive manner, this being Via (55) is filled with a thermally and electrically conductive material. Device (10) according to Claim 12 wherein the device (10) has a multiplicity of vias (55) which are arranged laterally around the cavity structure (14) and filled with a thermally and electrically conductive material. Device (10) according to Claim 12 or 13th , wherein a distance (D ₁ ) between the via (55) and the cavity structure (14) is less than a distance (D ₂ ) between the via (55) and an outside of the substrate arrangement. Wafer stack with a plurality of devices (10) according to one of the preceding claims. Method comprising the following steps: providing a substrate arrangement with a first circuit arrangement (11) which heats up during operation, the first circuit arrangement having at least one heating element (35) and a heat distribution element (33) coupled to the heating element; wherein the coupled heat distribution element (33) is designed to distribute the heat generated by the first circuit arrangement (11) approximately evenly over the entire surface of the heat distribution element (33); wherein the heat distribution element (33) and the heating element (35) together form an IR emitter for a photoacoustic sensor; Providing a second circuit arrangement (12) which is integrated in a substrate material of the substrate arrangement, the second circuit arrangement being designed to control the heating element (35); Forming a cavity structure (14) arranged between the first and the second circuit arrangement (11, 12) in the substrate material, the cavity structure (14) having a pressure which is lower than that of an ambient atmospheric pressure; wherein the cavity structure (14) is designed to thermally decouple the second circuit arrangement (12) from the heating element (35); and wherein the cavity structure (14) extends between the two circuit arrangements (11, 12) in a first and second lateral direction (X _1, Y ₁ ), and wherein both the first circuit arrangement (11) and the second circuit arrangement (12) are arranged at least in sections within a projection of the cavity structure (14) perpendicular to the lateral extension directions (X ₁ , Y ₁ ). Procedure according to Claim 16 the method further comprising: providing a reflection arrangement (43) for reflecting heat radiation emitted by the first circuit arrangement (11), and arranging the reflection arrangement (43) within the cavity structure (14) on a surface region of the cavity structure facing the first circuit arrangement (11) (14). Procedure according to Claim 16 or Claim 17 wherein the step of forming the cavity structure (14) includes the pressure in the cavity structure (14) being less than 10% or less than 1% of the ambient atmospheric pressure. Method according to one of the Claims 16 to 18th , wherein the step of providing the substrate arrangement includes that two sub-substrate arrangements (S ₁ , S ₂ ) are stacked one on top of the other, a first sub-substrate arrangement (S ₁ ) having the first circuit arrangement (11) and a second sub-substrate arrangement (S ₂ ) having the second circuit arrangement (12), and wherein the step of forming the cavity structure (14) includes that the cavity structure (14) is formed as a closed recess (42) in at least one of the two partial substrate arrangements (S ₁ , S ₂ ). Procedure according to Claim 19 , wherein the first sub-substrate arrangement (S ₁ ) and the second sub-substrate arrangement (S ₂ ) are connected to one another using a vacuum bonding method. Method according to one of the Claims 16 to 20th , comprising providing an optical filter (39) which is designed to filter electromagnetic radiation emitted by the first circuit arrangement (11), the optical filter (39) in a main emission direction (47) of the electromagnetic radiation after the first circuit arrangement (11) is arranged, and forming a second cavity structure (41) between the first circuit arrangement (11) and the filter (39), the second cavity structure (41) having a lower pressure than the ambient atmospheric pressure. Procedure according to Claim 21 wherein the step of forming the second cavity structure (41) includes the pressure in the second cavity structure (41) being less than 10% or less than 1% of the ambient atmospheric pressure. Procedure according to Claim 21 or 22nd wherein the optical filter (39) is monolithically formed with the substrate assembly. Method according to one of the Claims 21 to 23 , wherein the optical filter (39) is arranged on a third sub-substrate arrangement (S ₃ ), and this third sub- _{substrate arrangement (S 3} ) is connected to the substrate arrangement. Method according to one of the Claims 16 to 24 , comprising providing at least one electrical connection (51) for contacting the first circuit arrangement (11) and at least one electrical connection (52) for contacting the second circuit arrangement (12), wherein contact surfaces (53) of the electrical connections (51, 52) be arranged on a section of the substrate arrangement having the second circuit arrangement (12). Procedure according to Claim 25 , comprising the formation of at least one through-contact (55) extending through the substrate arrangement, which connects a contact surface (53) of the at least one electrical connection (51) for contacting the first circuit arrangement (11) with the first circuit arrangement (11) in an electrically conductive manner , and filling this via (55) with an electrically and thermally conductive material. Procedure according to Claim 26 , further comprising forming a multiplicity of vias (55) arranged laterally around the cavity structure (14) and filled with electrically and thermally conductive material. Procedure according to Claim 26 or 27 , wherein the step of forming at least one via (55) includes that the at least one via (55) is arranged opposite the cavity (14) in such a way that a distance (D ₁ ) between the via (55) and the cavity structure ( 14) is less than a distance (D ₂ ) between the via (55) and an outside of the substrate arrangement.

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