DE102016118921A1 - Improved ESD device - Google Patents
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Abstract
Eine integrierte Schaltungsvorrichtung umfasst mindestens zwei auf ein Substrat epitaxisch aufgewachsene aktive Bereiche, wobei die aktiven Bereiche zwischen einer ersten Gatevorrichtung und einer zweiten Gatevorrichtung liegen. Die integrierte Schaltungsvorrichtung umfasst mindestens ein Dummygate zwischen den zwei epitaxisch aufgewachsenen aktiven Bereichen und zwischen der ersten Gatevorrichtung und der zweiten Gatevorrichtung, wobei jeder aktive Bereich im Wesentlichen eine gleichmäßige Länge aufweist. Die erste Gatevorrichtung und die zweite Gatevorrichtung sind über einer ersten Mulde ausgebildet, die einen ersten Leitfähigkeitstyp aufweist, und das Dummygate ist über einer zweiten Mulde ausgebildet, die einen zweiten Leitfähigkeitstyp aufweist.An integrated circuit device comprises at least two active regions epitaxially grown on a substrate, the active regions lying between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, each active region having a substantially uniform length. The first gate device and the second gate device are formed over a first well having a first conductivity type, and the dummy gate is formed over a second well having a second conductivity type.
Description
PRIORITÄTSINFORMATIONPRIORITY INFORMATION
Diese Anmeldung ist eine continuation-in-part der US Anmeldung N. 13/932,521, die am 1. Juli 2013 mit dem Titel „Epitaxial Growth Between Gates” eingereicht wurde und die die Priorität der US vorläufigen Anmeldung N. 61/779,842, die am 13. März 2013 eingereicht wurde, beansprucht, deren Offenbarung hierin durch Bezugnahme aufgenommen ist.This application is a continuation-in-part of US Application No. 13 / 932,521, filed July 1, 2013, entitled "Epitaxial Growth Between Gates" and which is the priority of US Provisional Application No. 61 / 779,842, the on Mar. 13, 2013, the disclosure of which is incorporated herein by reference.
HINTERGRUNDBACKGROUND
Elektronische Geräte, die integrierte Schaltungen verwenden, sind anfällig für elektrostatische Entladungen (ESD). Elektrostatische Entladungen können von einem Menschen verursacht werden, der das Gerät hält, oder von anderen Ursachen. Eine elektrostatische Entladung kann eine große Menge an elektrischem Strom durch Schaltungen fließen lassen, die für derart hohe Ströme empfindlich sind, sodass die Schaltungen beschädigt werden. Um die Anfälligkeit für ESD-Schäden zu reduzieren, umfassen integrierte Schaltungen typischerweise eine ESD-Vorrichtung, die ESD von empfindlichen Schaltungen wegleiten.Electronic devices using integrated circuits are prone to electrostatic discharge (ESD). Electrostatic discharges can be caused by a person holding the device or by other causes. An electrostatic discharge can allow a large amount of electrical current to flow through circuits that are sensitive to such high currents that damage the circuits. To reduce the susceptibility to ESD damage, integrated circuits typically include an ESD device that redirects ESD away from sensitive circuits.
Eine Art von ESD-Vorrichtung umfasst mehrere aktive Bereiche, wie Source- oder Drain-Bereiche, zwischen einer länglichen Gatevorrichtung. Die Gatevorrichtung wird für das Gate eines Transistors verwendet. Der Transistor wirkt als Schalter, der öffnet, wenn ein hoher elektrischer Strom wie eine ESD detektiert wird. Der offene Schalter lässt die ESD durch, um zu vermeiden, dass sie Fluss durch die empfindlichen Schaltungen fließt.One type of ESD device includes a plurality of active regions, such as source or drain regions, between an elongate gate device. The gate device is used for the gate of a transistor. The transistor acts as a switch that opens when a high electrical current such as an ESD is detected. The open switch passes the ESD to prevent it from flowing through the sensitive circuits.
Ein Problem, dass mit der Ausbildung einer ESD-Vorrichtung zusammenhängt, wird durch Silizide verursacht. Bei der Ausbildung von Transistorvorrichtungen werden Silizide typischerweise in Halbleiter-Metall-Übergängen verwendet, um einen effizienten Übergang zu ermöglichen. Dies liegt daran, dass Silizide elektrischen Strom relativ gut leiten. Es ist jedoch wünschenswert, dass Silizide nicht unmittelbar neben dem Gate über den Source- oder Drain-Bereichen ausgebildet werden. Sollten Silizidschichten dort gebildet werden, könnte ein durch die Source- und Drain-Bereiche fließender Strom, sich durch das Silizid ausbreiten, was Schäden verursachen könnte, da die sich aus den hohen ESD-Strömen ergebende Stromdichte das Silizid und das umgebende Material abbrennen könnte.A problem associated with the formation of an ESD device is caused by silicides. In the formation of transistor devices, silicides are typically used in semiconductor-metal junctions to allow for efficient junction. This is because silicides conduct electricity relatively well. However, it is desirable that silicides not be formed immediately adjacent the gate over the source or drain regions. Should silicide layers be formed there, current flowing through the source and drain regions could propagate through the silicide, which could cause damage, since the current density resulting from the high ESD currents could burn off the silicide and surrounding material.
Ein weiteres Problem, das mit der Bildung von ESD-Vorrichtungen zusammenhängt, entsteht, wenn die Source/Drain-Bereiche durch einen epitaxischen Wachstumsprozess ausgebildet werden. Ein epitaxischer Wachstumsprozess umfasst das Aufwachsen eines Halbleiterkristalls auf einen existierenden Kristall. Wenn Source- oder Drain-Bereiche auf diese Art und Weise ausgebildet werden, kann die Länge der Bereiche die Gleichmäßigkeit der epitaxialen Strukturen beeinflussen. Wenn eine Struktur in Bezug auf andere nahe gelegenen Strukturen zu lang ist, kann sich eine Reihe von ungleichmäßigen epitaxialen Strukturen bilden. Dies wird als „Loading-Effekt” bezeichnet. Daher ist es gewünscht, ESD-Vorrichtungen oder andere Vorrichtungen herzustellen, die epitaxial aktive Bereiche zwischen Gates verwenden, ohne zu viel nachteiligen Loading-Effekt.Another problem associated with the formation of ESD devices arises when the source / drain regions are formed by an epitaxial growth process. An epitaxial growth process involves growing a semiconductor crystal onto an existing crystal. If source or drain regions are formed in this manner, the length of the regions can affect the uniformity of the epitaxial structures. If one structure is too long with respect to other nearby structures, a series of uneven epitaxial structures may form. This is called a "loading effect". Therefore, it is desired to fabricate ESD devices or other devices that utilize epitaxially active regions between gates without too much adverse loading effect.
KURZE BESCHREIBUNG DER ZEICHNUNGENBRIEF DESCRIPTION OF THE DRAWINGS
Aspekte der vorliegenden Offenbarung werden am besten aus der folgenden detaillierten Beschreibung verstanden, wenn sie mit den beigefügten Figuren gelesen wird. Man beachte, dass in Übereinstimmung mit dem üblichen Vorgehen in der Branche verschiedene Einrichtungen nicht maßstabsgetreu gezeigt sind. Tatsächlich können die Abmessungen der verschiedenen Einrichtungen zur Klarheit der Beschreibung beliebig vergrößert oder verkleinert werden.Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that various devices are not shown to scale in accordance with standard industry practice. In fact, the dimensions of the various devices can be arbitrarily increased or decreased for clarity of description.
DETAILLIERTE BESCHREIBUNGDETAILED DESCRIPTION
Es ist zu verstehen, dass die folgende Offenbarung viele verschiedene Ausführungsformen oder Beispiele vorsieht, um verschiedene Merkmale der Offenbarung zu implementieren. Spezifische Beispiele von Komponenten und Anordnungen sind unten beschrieben, um die vorliegende Offenbarung zu vereinfachen. Diese sind natürlich nur Beispiele und sollen nicht einschränkend wirken. Des Weiteren kann das Ausführen eines ersten Prozesses vor einem zweiten Prozess in der folgenden Beschreibung beispielsweise Ausführungsformen umfassen, in denen der zweite Prozess unmittelbar nach dem ersten Prozess ausgeführt wird, und kann auch Ausführungsformen umfassen, in denen zusätzliche Prozesse zwischen dem ersten Prozess und dem zweiten Prozess ausgeführt werden können. Unterschiedliche Merkmale können der Einfachheit und der Klarheit halber unter Verwendung verschiedener Maßstäbe dargestellt werden. Ferner kann das Ausbilden einer ersten Einrichtung über oder auf einer zweiten Einrichtung in der folgenden Beschreibung kann beispielsweise Ausführungsformen umfassen, in denen die erste und die zweite Einrichtung in direktem Kontakt ausgebildet sind, und kann auch Ausführungsformen umfassen, in denen zusätzliche Einrichtungen zwischen der ersten Einrichtung und der zweiten Einrichtung ausgebildet sein können, so dass die erste und die zweite Einrichtung nicht in direktem Kontakt sein müssen.It is to be understood that the following disclosure provides many different embodiments or examples to implement various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course these are just examples and should not be limiting. Further, performing a first process prior to a second process in the following description may include, for example, embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes between the first process and the second process Process can be performed. Different features may be presented for simplicity and clarity using various scales. Further, forming a first device over or on a second device in the following description may, for example, include embodiments in which the first and second devices are formed in direct contact, and may also include embodiments in which additional devices are interposed between the first device and the second device may be configured so that the first and second devices need not be in direct contact.
Weiter können räumlich relative Begriffe, wie „unten”, „unter”, „unterer”, „über”, „oberer” und derartige, hier zur Einfachheit der Beschreibung verwendet werden, um die Beziehung eines Elements oder einer Einrichtung mit einem oder mehreren anderen Elementen oder Einrichtungen zu beschreiben, wie sie in den Figuren gezeigt sind. Die räumlich relativen Begriffe sollen verschiedene Orientierungen der Vorrichtung, die verwendet oder betrieben wird, zusätzlich zu der in den Figuren gezeigten Orientierung umfassen. Zum Beispiel wenn eine in den Figuren dargestellte Vorrichtung umgedreht wird, sind Elemente, die laut der Beschreibung „unterhalb von” oder „unter” anderen Elementen oder Einrichtungen sind, dann „über” den anderen Elementen oder Einrichtungen. Der exemplarische Begriff „unter” bezieht sich daher sowohl auf eine Orientierung „unter” als auch „über”. Die Vorrichtung kann anders orientiert sein (um 90 Grad gedreht oder in einer anderen Orientierung), und die räumlich relativen Begriffe, die hier verwendet werden, können ebenfalls demgemäß interpretiert werden.Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one element or device to one or more others Describe elements or devices as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientation shown in the figures. For example, when a device shown in the figures is turned over, elements that are described as being "below" or "below" other elements or devices are then "above" the other elements or devices. The exemplary term "under" therefore refers both to an orientation "below" and "above". The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.
Gemäß dem vorliegenden Beispiel können die aktiven Bereiche
Die aktiven Bereiche
Die Gatestrukturen
In manchen Beispielfällen können die Gatevorrichtungen
Das Dummygate
Die Klammern
Die Lücken
Wie oben erwähnt können Kontaktierungen
Durchkontaktierungen (Vias) werden dann in die dielektrischen Zwischenschicht
Ähnliche Verfahren können verwendet werden, um die Gatevorrichtungen
Die STI-Strukturen
Die Dummygates sind mit einem solchen Abstand angeordnet, dass die aktiven Bereiche zwischen einer jeden Gate-Struktur
Die Anzahl der Dummygates und somit die Größe des Epitaxie-Fensters kann so ausgewählt werden, dass der Loading-Effekt unter einen Schwellenwert reduziert wird. Dieser Schwellenwert kann während der Entwurfsphase vorbestimmt werden oder während der Herstellungsphase bestimmt werden. Die Epitaxie-Fenster zwischen Gates sind von der folgenden Gleichung definiert:
Wd das reduzierte Epitaxie-Fenster
W das ursprüngliche Fenster
n die Anzahl der Dummygates ist; und
L die Breite der Dummygates ist.The number of dummy gates and thus the size of the epitaxy window can be selected to reduce the loading effect below a threshold. This threshold may be predetermined during the design phase or determined during the manufacturing phase. The epitaxy windows between gates are defined by the following equation:
Wd the reduced
W the
n is the number of dummy gates; and
L is the width of the dummy gates.
Das Epitaxie-Fenster
In diesem Beispiel liegt lediglich eine einzige Kontaktierung
Obwohl ein Finnenstruktur-Transistor gezeigt ist, kann das hierin Beschriebene ebenfalls mit einer konventionellen CMOS-Architektur (Complementary Metal Oxide Semiconductor) verwendet werden. Zum Beispiel kann ein konventioneller aktiver Bereich zwischen Gates und Dummygate aufgewachsen werden, anstatt mehrerer zwischen den Gates aufgewachsenen aktiven Finnenbereiche.Although a fin structure transistor is shown, what has been described herein can also be used with a conventional CMOS architecture (Complementary Metal Oxide Semiconductor). For example, a conventional active area may be grown between gates and dummy gate rather than multiple active fin areas grown between the gates.
Das Vorhandensein gleichmäßigerer aktiver Bereiche zwischen den Gates kann einen Replacement-Gate-Prozess besserer Qualität ermöglichen. In manchen Fällen sind tatsächliche Gates aus einem Polysilizium-Material, und werden dann durch ein metallisches Material ersetzt. Dieser Prozess umfasst das Bilden von Seiten-Abstandshaltern an den Seiten des Polysilizium-Gates, das Entfernen des Polysiliziums, und dann das Ersetzen der verbleibenden Lücke durch ein metallisches Material.Having more even active areas between the gates can enable a better quality replacement gate process. In some cases, actual gates are made of a polysilicon material and are then replaced by a metallic material. This process involves forming side spacers on the sides of the polysilicon gate, removing the polysilicon, and then replacing the remaining gap with a metallic material.
Die Dummygates
In manchen Beispielen kann die n-Mulde
In manchen Beispielen kann die Grenzfläche
Gemäß einem Beispiel umfasst eine integrierte Schaltungsvorrichtung mindestens zwei auf ein Substrat epitaxisch aufgewachsene aktive Bereiche, wobei die aktiven Bereiche zwischen einer ersten Gatevorrichtung und einer zweiten Gatevorrichtung liegen. Die integrierte Schaltungsvorrichtung umfasst mindestens ein Dummygate zwischen den zwei epitaxisch aufgewachsenen aktiven Bereichen und zwischen der ersten Gatevorrichtung und der zweiten Gatevorrichtung, wobei jeder aktive Bereich im Wesentlichen die gleiche Länge aufweist. Die erste Gatevorrichtung und die zweite Gatevorrichtung sind über einer ersten Mulde ausgebildet, die einen ersten Leitfähigkeitstyp aufweist, und das Dummygate ist über einer zweiten Mulde ausgebildet, die einen zweiten Leitfähigkeitstyp aufweist.According to one example, an integrated circuit device comprises at least two active regions epitaxially grown on a substrate, the active regions lying between a first gate device and a second gate device. The integrated circuit device comprises at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, each active region having substantially the same length. The first gate device and the second gate device are formed over a first well having a first conductivity type, and the dummy gate is formed over a second well having a second conductivity type.
Gemäß einem Beispiel umfasst ein Verfahren zur Bildung einer Elektrostatischen-Entladungs-Vorrichtung (ESD) das Bilden einer ersten Mulde auf einem Substrat, die einen ersten Leitfähigkeitstyp aufweist, das Bilden einer zweiten Mulde innerhalb der ersten Mulde, wobei die zweite Mulde einen zweiten Leitfähigkeitstyp aufweist, das Bilden einer ersten Gatevorrichtung und einer zweiten Gatevorrichtung über der ersten Mulde, das Bilden einer Vielzahl von aktiven Bereichen zwischen der ersten Gatevorrichtung und der zweiten Gatevorrichtung, wobei jeder der aktiven Bereiche im Wesentlichen die gleiche Länge aufweist, und das Bilden eines Dummygates innerhalb einer Lücke zwischen den aktiven Bereichen, wobei das Dummygate über der zweiten Mulde gebildet wird.In one example, a method of forming an electrostatic discharge device (ESD) includes forming a first well on a substrate having a first conductivity type, forming a second well within the first well, the second well having a second conductivity type , forming a first gate device and a second gate device over the first well, forming a plurality of active regions between the first gate device and the second gate device, each of the active regions having substantially the same length, and forming a dummy gate within one Gap between the active regions, where the dummy gate is formed over the second well.
Gemäß einem Beispiel umfasst eine integrierte Schaltungsvorrichtung mindestens zwei auf ein Substrat epitaxisch aufgewachsene aktive Bereiche, wobei die aktiven Bereiche zwischen einer ersten Gatevorrichtung und einer zweiten Gatevorrichtung liegen. Die integrierte Schaltungsvorrichtung umfasst ferner mindestens ein Dummygate zwischen den zwei epitaxisch aufgewachsenen aktiven Bereichen und zwischen der ersten Gatevorrichtung und der zweiten Gatevorrichtung, wobei jeder aktive Bereich im Wesentlichen die gleiche Länge aufweist. Die erste Gatevorrichtung und die zweite Gatevorrichtung sind über einer ersten Mulde ausgebildet, die einen ersten Leitfähigkeitstyp aufweist, und das Dummygate ist über einer Lücke zwischen einer zweiten Mulde und einer dritten Mulde ausgebildet, wobei die zweite Mulde und die dritte Mulde einen zweiten Leitfähigkeitstyp aufweisen.According to one example, an integrated circuit device comprises at least two active regions epitaxially grown on a substrate, the active regions lying between a first gate device and a second gate device. The integrated circuit device further comprises at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, each active region having substantially the same length. The first gate device and the second gate device are formed over a first well having a first conductivity type, and the dummy gate is formed over a gap between a second well and a third well, the second well and the third well having a second conductivity type.
Es sollte verstanden werden, dass mehrere unterschiedliche Kombinationen der oben aufgeführten Ausführungsformen und Schritte in unterschiedlichen Reihenfolgen oder parallel verwendet werden können, und dass kein einzelner Schritt kritisch oder unabdingbar ist. Zudem sollte erkannt werden, dass obwohl der Begriff „Elektrode” hierin verwendet wird, der Begriff das Konzept einer „Elektrodenkontaktierung” umfasst. Ferner können Merkmale, die oben in Bezug auf manche Ausführungsformen dargestellt und aufgeführt sind, mit Merkmalen kombiniert werden, die in Bezug auf andere Ausführungsformen dargestellt und aufgeführt sind. Demnach sollte verstanden werden, dass alle solche Abweichungen zum Umfang dieser Erfindung gehören.It should be understood that several different combinations of the above-listed embodiments and steps may be used in different orders or in parallel, and that no single step is critical or essential. In addition, it should be appreciated that although the term "electrode" is used herein, the term includes the concept of "electrode contacting". Further, features illustrated and listed above with respect to some embodiments may be combined with features illustrated and listed with respect to other embodiments. Thus, it should be understood that all such variations are within the scope of this invention.
Im Vorhergehenden sind Merkmale mehrerer Ausführungsforme hervorgehoben worden. Einem Fachmann sollte ersichtlich sein, dass die vorliegende Offenbarung als Ausgangspunkt verwendet werden kann, um andere Verfahren oder Strukturen zu entwerfen, oder zu modifizieren, um die gleiche Funktion zu erfüllen, und/oder um die gleichen Vorteile zu erreichen als die hierin beschriebenen Ausführungsformen. Einem Fachmann sollte ebenfalls ersichtlich sein, dass solche äquivalente Konstrukte von dem Geist und dem Umfang der vorliegenden Offenbarung nicht abweichen, und dass Änderungen, Ersetzungen und Umänderungen gemacht werden können, ohne von dem Geist und dem Umfang der vorliegenden Offenbarung abzuweichen.In the foregoing, features of several embodiments have been emphasized. One skilled in the art should appreciate that the present disclosure may be used as a starting point to design or modify other methods or structures to achieve the same function and / or to achieve the same advantages as the embodiments described herein. It should also be apparent to those skilled in the art that such equivalent constructs are not to depart from the spirit and scope of the present disclosure, and changes, substitutions and alterations can be made without departing from the spirit and scope of the present disclosure.
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