DE102016117588A1 - Processor arrangement and method for operating a processor arrangement - Google Patents

Abstract

According to various embodiments, a processor arrangement (100) may include: a set of logic circuits (402); at least one register (404) assigned to the set of logic circuits (402); a display panel (302) configured to control the communication between the set of logic circuits (402) and the at least one register (404), and further configured for each logic circuit of the set of logic circuits (402) Evaluate number of instruction cycles to be executed, thereby forming a set of instruction cycle values, an evaluation circuit (302, 506) configured to determine a lowest value of the set of instruction cycle values, and further configured to generate a power reduction request signal, if the lowest value is greater than or equal to a predefined command cycle value; at least one peripheral circuit (104) and a power circuit (510) coupled to the at least one peripheral circuit (104); wherein the power circuit (510) is configured to control a power state of the at least one peripheral circuit (104) based on the power reduction request signal provided by the evaluation circuit.

Description

Technical area

Various embodiments generally relate to a processor arrangement and method for operating a processor arrangement.

background

In general, various electronic devices may include a processor, e.g. A microprocessor, a controller, a microcontroller, a logic chip, and the like. It may be desirable for an electronic device, e.g. For example, a processor can consume as little power as possible or can use the power as efficiently as possible. Therefore, z. For example, processor performance management techniques can be used to balance power and energy consumption. Conventionally, power management may involve changing the operating state of a processor to one or more operating states in which the power consumption of the processor is reduced (such state may also be referred to as power saving state) if the processing load assigned to the processor enables the operating state to be changed. Conventionally, a processor under high processing load can not be influenced by the power management so as not to decrease the performance of the processor, so that fast processing can be maintained. The power consumption and also the heat generated by a conventional processor can only be reduced if the processor is not in use or is not working at full capacity.

Brief description of the drawings

In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale, with emphasis instead being generally placed upon explanation of the principles of the invention. In the following description, various embodiments of the invention will be described with reference to the following drawings, in which:

1A and 1B each show a schematic view of a processor or processor arrangement according to various embodiments;

2 a schematic view of a central processing unit of a processor according to various embodiments;

3A to 3E each show a schematic view of a display panel for executing out-of-order instructions according to various embodiments;

4 to 6 each show a schematic view of a processor or processor arrangement according to various embodiments;

7 and 8th each show a schematic flow diagram of a method of operating a processor or processor arrangement according to various embodiments;

9A and 9B each show a schematic view of a display panel according to various embodiments;

10A and 10B each show a schematic view of a power adapter and a processor or processor arrangement according to various embodiments; and

11 12 shows a schematic diagram of the power consumption of the processor according to various embodiments with a conventional processor.

description

The following detailed description refers to the accompanying drawings which, for purposes of explanation, show specific details and embodiments in which the invention may be practiced.

The following detailed description refers to the accompanying drawings which, for purposes of explanation, show specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. Various embodiments will be described in conjunction with methods, and various embodiments will be described in connection with apparatus. Of course, however, embodiments described in connection with methods may equally apply to the devices, and vice versa.

The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, ie, one, two, three, four, and so on. The term "a plurality" may be understood to include any integer greater than or equal to two, that is, two, three, four, five, and so on.

The term "coupled" is used herein to mean electrically connected (eg, configured to communicate with each other), which may include a direct connection or an indirect connection, where an indirect connection may include only additional structures in the current path, which do not affect the essential function of the described circuit or device.

A "circuit" as used herein is understood to be any type of implementation entity that may include specialized hardware or a processor executing software. A circuit may thus be an analog circuit, a digital circuit, a mixed signal circuit. A circuit may thus comprise a logic circuit, a processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a user programmable logic array (FPGA), an integrated circuit, an application specific integrated circuit (ASIC), etc or any combination thereof, or be part of it. Any other type of implementation of the respective functions, which will be described in more detail below, may also be understood as a "circuit". Of course, any two (or more) of the circuits detailed herein may be implemented as a single circuit having substantially equivalent functionality, and, conversely, any single circuit detailed herein may be implemented as two (or more) separate circuits having substantially equivalent functionality. In addition, references to a "circuit" may refer to two or more circuits that together form a single circuit. The term "circuitry" may refer to a single circuit, a collection of circuits, and / or an electronic device consisting of one or more circuits.

As used herein, "memory" may be understood as a non-transitory computer-readable medium in which data or information for retrieval may be stored. References to a "memory" contained herein may thus be understood to refer to volatile or nonvolatile memory, including random access memory (RAM), read only memory (ROM), flash memory, semiconductor memory, magnetic tape, hard disk drive, optical drive etc. or any combination thereof. It can also be seen that registers, shift registers, processor registers, data buffers, etc. are also included here by the term memory. It will be appreciated that a single component, referred to as a "memory" or "a memory," may consist of more than one different type of memory, and thus may refer to a common component with one or more types of memory , It will be readily understood that any single memory component may be separated into a plurality of shared memory components, and vice versa. Although a memory may be illustrated as being separate from one or more other components (as in the drawings, for example), it is further understood that the memory may be incorporated into another component, such as memory. B. may be integrated on a common integrated chip.

A processor can accommodate many different levels of static or power dissipation management. Conventionally, these techniques are used when a CPU and / or a bus master of the processor become inactive. In these cases, one or more power domains may be turned off or one or more power domain supplies may be reduced. Various embodiments are based on static loss management or power management in the case where the CPU of the processor is active. In other words, it has been recognized that power can be saved in peripherals of a busy CPU since in that case the CPU can not access the peripherals.

According to various embodiments, a method and system for reducing switching power consumption is provided by utilizing display panel data from dynamically-scheduled processors. A processor arrangement can be created, for example. The processor assembly may include at least one processor configured to communicate with at least one peripheral device, an evaluation circuit configured to evaluate processing load data representing a processing load of at least one processor, and a controller configured thereto is to generate a power reduction request signal for at least one peripheral device based on the evaluated processing load data to reduce power consumption of at least one peripheral device when the processing load of the at least one processor is greater than a predefined processing load value.

In another example, a processor arrangement may be provided. The processor assembly comprises: at least one processing unit, at least one peripheral unit coupled to the at least one processing unit, an evaluation circuit configured to evaluate processing load data representing a processing load of the processing unit, and a control circuit configured to to change an operating state of the at least one peripheral unit into a power saving state (ie, a reduced power consumption state) on the basis of the evaluated processing load data when the processing load of the at least one processing unit is greater than a predefined processing load value.

In another example, a processor may include a plurality of processing units (PU), at least one register assigned to the plurality of processing units, and a display panel configured to evaluate processing load data for each of the plurality of processing units. The display panel is further configured to generate a power reduction request signal for a peripheral circuit based on the evaluated processing load data.

In another example, a processor or processor arrangement may include at least one functional unit circuit, at least one data register assigned to the at least one functional unit circuit, a display panel configured to control communication between the at least one functional unit and the at least one data register Processing load of the at least one functional unit, an evaluation circuit configured to evaluate processing load data for the at least one functional unit and generate a power reduction request signal based on the evaluated processing load data, a peripheral unit, and a power adapter coupled to the peripheral unit is, include. The power adapter is configured to control a power state (i.e., changing an operating state) of the peripheral unit based on the power reduction request signal supplied from the evaluation circuit.

In another example, a processor array having a set of logic circuits, at least one register associated with the set of logic circuits, a display panel configured to evaluate, for each logic circuit of the set of logic circuits, a corresponding number of instruction cycles to be executed A set of instruction cycle values, an evaluation circuit configured to determine a lowest value of the set of instruction cycle values, and further configured to generate a power reduction request signal when the lowest value is greater than or equal to a predefined instruction cycle value , On the basis of the power reduction request signal, an operating state of the at least one peripheral circuit may be changed to reduce the power consumption of the at least one peripheral circuit. Therefore, a power circuit may be coupled to the at least one peripheral circuit. The power circuit may be configured to receive the power reduction request signal and to control the power consumption of the at least one peripheral circuit based on the received power reduction request signal provided by the evaluation circuit.

According to various embodiments, a processor arrangement may configure a set of logic circuits, at least one register assigned to the set of logic circuits, a display panel configured to control the communication between the set of logic circuits and the at least one register, and further configured thereto is to evaluate, for each logic circuit of the set of logic circuits, a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values, an evaluation circuit configured to determine a lowest value of the set of instruction cycle values, and further configured to Generating a power reduction request signal when the lowest value is greater than or equal to a predefined command cycle value, at least one peripheral circuit, and a power circuit coupled to the at least one peripheral circuit, wherein the power circuit is configured to reduce power consumption (e.g. By changing the operating state) of the at least one peripheral circuit based on the power reduction request signal supplied from the evaluation circuit. According to various embodiments, the set of logic circuits may include any circuit that embodies a so-called functional unit (FU).

1A and 1B each represent a processor or a processor arrangement 100 (also referred to as a chip, processing chip, microprocessor, and the like) according to various embodiments. The processor arrangement 100 can one or more central processing units (CPUs) 102 and one or more peripheral devices (also referred to as peripheral circuits) 104 include. The one or more central units 102 and the one or more peripherals 104 can be coupled together, for. B. via a communication circuit 106 , According to various embodiments, the processor arrangement 100 may be embodied as a single chip (eg, as a system on a chip, SoC), or alternatively, the processor arrangement 100 at least one processor with the one or more central processing units 102 (eg, embodied as a single chip) comprising one or more peripheral devices 104 , z. B. via a communication circuit 106 (as the connection structure 106 can be implemented) are coupled. The masters (ie the one or more central units 102 ) can be used with slaves (ie the one or more peripherals 104 ) via the connection structure 106 connected to a (eg, hierarchical) bus, a crossbar, an on-chip network, or any other suitable interconnect structure 106 , z. A programmable power bus, or may be.

As in 1A and 1B shown, the processor arrangement 100 as described here, at least one CPU 102 include. The CPU 102 may include or may be embodied as one or more logic circuits. The one or more logic circuits, the z. For example, defining a set of logic circuits may be configured to perform, for example, computational and / or logical operations. The set of logic circuits may be further configured to perform control and / or input / output (I / O) operations.

According to various embodiments, the processor arrangement 100 furthermore several central units 102 (also referred to as cores), z. B. two to eight cores or even more than eight cores. In general, these processors or processor arrangements may be referred to as multi-core chips or multi-core processors. According to various embodiments, a central processing unit 102 may be operated on the basis of instructions, ie may be configured to execute instructions by performing basic computational, logical, control and input / output (I / O) operations specified by the instructions. The at least one central unit 102 may generally comprise at least one processing unit (PU) and at least one control unit (CU). The processing unit may comprise a processing unit circuit or may be embodied as a processing unit circuit. The control unit (CU) may comprise a control unit circuit or may be embodied as a control unit circuit. A processing unit may be configured as an arithmetic logic unit (ALU) to perform basic computational and / or logical operations. The arithmetic unit may comprise an arithmetic-logic circuit or may be embodied as an arithmetic-logic circuit. The at least one central unit 102 may further comprise one or more floating point units (FPU) and / or one or more graphics processing units (GPU). A floating-point unit or graphics processing unit may comprise a plurality of arithmetic units.

The at least one central unit 102 may be configured with CPU-external components 104 (also as peripheral devices 104 or peripheral circuits 104 designated), such as. B. memory components 104 , I / O components 104 , a timing management circuit 104 (also called clock management unit, CMU) to communicate. The at least one central unit 102 and / or processor arrangement 100 may include one or more registers configured to provide operands to the respective processing unit (eg, the ALU) and store the results of processing unit operations. The control unit (CU) may be configured to fetch instructions from a memory and execute the fetched instructions by directing the coordinated operations of the processing unit, the registers, and other components.

2 represents the central unit 102 with multiple functional units (FU). Illustratively, the processing unit of a processor or a processor arrangement 100 comprise several functional units, for. At least one integer functional unit and one or more floating-point functional units, e.g. B. an integer unit 202i , a floating-point unit 202f , a multiplier unit 202m and a dividing unit 202d , The functional units 202i . 202f . 202m . 202d may include a functional unit circuit or may be embodied as a functional unit circuit.

The operation of a central processing unit 102 can be based on an execution of a sequence of commands (in other words, execute a program) in a memory 204 are stored. In general, a central processing unit 102 various instruction cycles based on different instruction sets (eg, reduced instruction set computer (RISC) or complex instruction set computer (CISC)). The central unit 102 however, can generally be based on a command fetch cycle 206 , Command decoding 208 and instruction execution by the functional units 202i . 202f . 202m . 202d operate. Such as in 2 As shown, the instructions may be fetched, decoded, and executed in a sequential order, which is therefore referred to as output in order and execution in order.

A register 210 can be used to store commands after fetching and / or decoding. The registry 210 may be or include a command register (IR). During decoding, the instruction present in the instruction register is interpreted by the decoder. The registry 210 may further comprise one or more data registers. A save command may be reading data from the store 204 or writing data to memory 204 include. Data coming from the store 204 can be stored in the one or more data registers.

The control unit of the central processing unit may be configured to display the decoded information as a sequence of control signals to the relevant functional units 202i . 202f . 202m . 202d to perform the actions requested by the command, such as B. reading values from the registers, directing them to the functional units 202i . 202f . 202m . 202d to perform mathematical or logical functions on them, and writing 212 of the result in the register 210 back. If the functional units 202i . 202f . 202m . 202d involved, a condition signal may be sent back to the control unit. The result generated by the operation may be in memory 204 get saved 214 , A program counter may be used to define the particular memory address from which the next instruction will be fetched.

The central unit 102 There may further comprise a memory address register, a memory data register, a command register, a controller configured to decode the program instruction, select a data source register and / or a special arithmetic operation, and coordinate the instruction cycles. The functional units 202i . 202f . 202m . 202d (including one or more arithmetic units) may be configured to perform the desired mathematical and logical operations.

According to various embodiments, the at least one central unit 102 be configured to perform out-of-order execution (also referred to as dynamic execution or dynamic scheduling) to make more efficient use of instruction cycles, e.g. By avoiding idle command cycles. Using the concept of out of order execution, the processor arrangement 100 Execute commands in a time-efficient order, eg. Rather, on the basis of the availability of input data rather than their original order in the program. Execution of out-of-order instructions can lead to conflicts if the instructions are not independent or if a sequence requires the instructions to be executed one after the other. Therefore, a so-called scoreboard may be provided to check data dependencies of each instruction and to control the release and distribution of new instructions to avoid conflicts with previously issued and / or incomplete instructions, as shown schematically in FIG 3A to 3E shown.

The scoreboard 302 can be configured to avoid hazards by tracking data dependencies, as in 3A shown. The scoreboard 302 can be data about the functional units 304a . 304s . 304m while considering data dependencies. The scoreboard 302 can control and check the reading of operands, execution and writeback. As a result, commands that are fetched later could be executed earlier than their predecessors. The scoreboard 302 can be configured to communicate 303 between the functional units 304a . 304s . 304m (ie the set of logic circuits that comprise the functional units 304a . 304s . 304m provide) and the at least one register 306 (eg, the data register) (e.g., instructing operations and checking operations).

3B Represents a centralized scoreboard 302 in a schematic view according to various embodiments. The centralized scoreboard 302 may be configured to audit and / or monitor data dependencies and to manage data hazards and / or structural hazards. The scoreboard 302 may be configured to be an execution state of commands 312 to check and / or monitor the readiness of the functional units 314 , Data dependencies among them and the amount of time 314t in clock cycles that a functional unit assigned to a command is likely to be busy checking and / or monitoring. In the in 3B In the example shown, the functional units Mult1 and Add are shown busy for a further nine cycles or one cycle. Furthermore, the scoreboard 302 be configured to a register result state 316 to be checked and / or monitored.

Explaining, the scoreboard 302 for each logic circuit of the set of logic circuits (ie, for each FU of the set of FUs), a corresponding number (e.g., 9 Mult1, 1 for Add, 0 for Integer, 0 for Mult2, and 0 for Division) of evaluating instruction cycles to be executed, thereby forming a set of instruction cycle values (eg, 0, 9, 0, 1, 0 assigned to the function units integer, Mult1, Mult2, Add, Division).

In the in 3B In this case, some of the functional units are not busy, ie have instruction cycles to execute zero, so that in this case the power reduction request signal can not be generated according to various embodiments. However, if all functional units were busy, ie, one or more instruction cycles to be executed, the power reduction request signal is generated according to various embodiments.

3C represents a distributed display panel, which works on the basis of the so-called Tomasulo algorithm. Based on the originally developed Tomasulo algorithm, as exemplified in 3D In a schematic view, there may be several possible variants of this algorithm. The basic principle of the Tomasulo algorithm may be the use of reservation stations, whereby the instructions are distributed. Therefore, register renaming in hardware may be performed via a reservation station for each of the functional units. An operation bus (also referred to as a common data bus) can be used to distribute the data. The common data bus connects the reservation stations with their assigned functional units to provide data to each of the reservation stations. This decentralized scoreboard is used to improve the parallel execution of commands.

3E represents a distributed (also called decentralized) scoreboard 302 z. Using reservation stations 324 in a schematic view according to various embodiments. The distributed display panel 302 , as in 3C to 3E may be configured to check and / or monitor data dependencies and data and structural hazards by distributing data (eg, instructions) to the respective reservation stations 324 to be assigned to the functional units assigned. The scoreboard 302 can be configured to specify the execution state of commands 312 , the condition of the reservation stations 324 , Data dependencies among them and the amount of time 324t in clock cycles that a functional unit assigned to the respective reservation station is likely to be busy testing and / or monitoring. In the in 3E In the example shown, the functional units Mult1 and Add are shown busy for a further nine cycles or one cycle. Furthermore, the scoreboard 302 be configured to the register result state 316 to pursue. Furthermore, the scoreboard 302 be configured to check and / or monitor load instructions (also referred to as read instructions). Furthermore, the scoreboard 302 be configured to test and / or monitor memory commands (also referred to as write commands). According to various embodiments, load instructions and / or store instructions may be memory access 326 According to various embodiments, the power reduction signal may not be generated when a memory access 326 is executed or must be executed in the next cycle.

Explaining, the scoreboard 302 for each logic circuit of the set of logic circuits (ie, for each functional unit of the set of functional units) a corresponding number (e.g., 9 for Mult1, 1 for Add, 0 for integer, 0 for Mult2, and 0 for division) of evaluating instruction cycles to be executed, thereby forming a set of instruction cycle values (eg, 0, 9, 0, 1, 0 assigned to the function units integer, Mult1, Mult2, Add, Division).

In the in 3E In the example illustrated, some of the functional units are not busy, ie, have instruction cycles to execute zero, so that in this case the power reduction request signal may not be generated according to various embodiments. However, if all functional units were busy, ie, one or more instruction cycles to be executed, the power reduction request signal is generated according to various embodiments. For example, all functional units would be busy if all reservation stations assigned to the functional units were filled with at least one command.

Regardless of whether the display panel is implemented in a centralized or distributed fashion, it is possible to maintain information about the amount of time that the functional units (centralized) or their reservation stations (distributed) are likely to be busy. Therefore, according to various embodiments, these are the information used to reduce power consumption.

By way of example, when all functional units are busy while guaranteeing that all functional units consume a minimum number of clock cycles, power consumption of peripheral devices (eg, a flash memory) can be reduced because it is likely that no peripheral device is being accessed.

Furthermore, the memory access can be viewed in such a way that the power consumption of a peripheral device can only be reduced if the memory is not accessed 326 , z. If there are no load or store instructions.

In the in 3E As shown, both reservation stations are busy and need one cycle and nine cycles to complete the execution of a command assigned to their functional units. Currently, there is no instruction fetch because all reservation stations are busy. There is no datastore access because the pipeline contains no load / store instructions. In this case, the peripherals 104 into a power saving state (also referred to as a reduced power state). This is achieved, for example, by generating a power reduction signal. According to various embodiments, a circuit (eg, a power circuit) may control the operating state of the peripherals 104 each change and the peripherals 104 in the reduced power state when the power reduction signal is received and put into a non-reduced power state (also referred to as a default state) when no power reduction signal is received.

4 represents a processor or a processor arrangement 100 in a schematic view configured in the same manner or in a similar manner as previously described, according to various embodiments. The processor arrangement 100 can be a central processing unit with a set of functional units 402 (also referred to as a set of logic circuits). The processor arrangement 100 Can at least one register 404 (eg, at least one data register) corresponding to the set of functional units 402 is assigned. The processor 100 can be a (centralized or distributed) scoreboard 302 which is configured to communicate 403 between the set of functional units 402 and the at least one register 404 to control, cf. 3B or 3D , According to various embodiments, the display panel 302 further configured to, for each functional unit of the set of functional units 402 a corresponding number of instruction cycles to be executed 314t . 324t (see. 3B or 3D ), thereby forming a set of instruction cycle values. The scoreboard 302 (eg, an evaluation circuit embedded in the display panel or coupled to the display panel) may be further configured to determine a lowest value of the set of command cycle values, and further a power reduction request signal 407 when the lowest value is greater than or equal to a predetermined instruction cycle value. The predefined instruction cycle value may be at least the value 1, such that when each functional unit of the processor 100 is busy and guaranteed to be busy for another cycle, the power reduction request signal 407 can be generated. However, the predefined instruction cycle value may be greater than 1, e.g. B. 5 or greater than 5, z. B. 10 or greater than 10, z. B. 20 or greater than 20 be.

In the case that the predefined instruction cycle value is exactly 1 and all functional units of the processor arrangement 100 for one cycle are illustratively the lowest value of the set of instruction cycle values 1, therefore equal to the predefined instruction cycle value, so that a power reduction request signal 407 is produced. In the case that the predefined command cycle value is exactly 1 and all functional units of the processor arrangement 100 are busy for two cycles, the lowest value of the set of instruction cycle values is 2 and therefore greater than the predefined instruction cycle value, so that a power reduction request signal 407 is produced. In the case that the predefined command cycle value is 1 and at least one functional unit of the processor arrangement 100 is not busy (ie has zero cycles to execute) and the other functional units of the processor array 100 are busy for one cycle or more than one cycle, the lowest value of the set of instruction cycle values is 0 and therefore less than the predefined instruction cycle value, so that the power reduction request signal 407 is not generated. If the predefined instruction cycle value is 5 and only one functional unit of the processor arrangement 100 is busy for less than 5 cycles, the lowest value of the set of instruction cycle values is less than 5 and therefore less than the predefined instruction cycle value, such that the power reduction request signal 407 is not generated. In this way, the predefined instruction cycle value defines the minimum number of cycles to be performed by a functional unit to be considered busy. If all functional units of the processor arrangement 100 are busy, the power reduction request signal 407 generated (ie the power consumption of the peripherals 104 can be reduced).

According to various embodiments, the processor arrangement 100 at least one peripheral circuit 104 and a power circuit connected to the at least one peripheral circuit 104 coupled. The power circuit may be configured to have a power state (eg, changing an operating state) of the at least one peripheral circuit 104 based on the power reduction request signal 407 that through the scoreboard 302 is supplied (for example, by an evaluation circuit embedded in the display panel circuit or an evaluation circuit coupled to the display panel circuit). According to various embodiments, the control of the power state of a peripheral device 104 reducing the power consumption of the peripheral device 104 by changing the operating state of the peripheral device 104 from a default state to a power saving state.

5 shows a schematic view of a processor arrangement 100 configured in the same or a similar manner as previously described, according to various embodiments. The processor arrangement 100 can be a set of logic circuits 402 include. The set of logic circuits 402 may represent a set of functional units, e.g. Adding, subtracting, multiplying, dividing and the like as described herein. The processor arrangement 100 Can at least one register 404 (eg, at least one data register) corresponding to the set of logic circuits 402 is assigned. The processor arrangement 100 can a scoreboard 302 which is configured to communicate 403 between the set of logic circuits 402 and the at least one register 404 to control, cf. 3B or 3D , and further configured for each logic circuit of the set of logic circuits 402 evaluate a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values. The processor arrangement 100 can be an evaluation circuit 506 configured to determine a lowest value of the set of instruction cycle values 505 , and further configured to receive a power reduction request signal 407 when the lowest value is greater than or equal to a predefined command cycle value. To find the lowest value of the set of instruction cycle values 505 , can the evaluation circuit 506 and the scoreboard 302 be configured to communicate with each other. The scoreboard 302 For example, the number of instruction cycles to be executed for each of the logic circuits 402 provide. On the basis of this, the evaluation circuit 506 be configured to determine if at least one of the logic circuits 402 has a number of instruction cycles to execute that is less than the predefined number of instruction cycles. The processor arrangement 100 can be at least one peripheral circuit 104 and a power circuit 510 include, with the at least one peripheral circuit 104 is coupled. The power circuit 510 may be configured to a power state of the at least one peripheral circuit 104 based on the power reduction request signal 407 that from the evaluation circuit 506 is delivered to control 509 ,

According to various embodiments, the evaluation circuit 506 as part of the scoreboard 302 be embodied or may be a separate circuit that works with the scoreboard 302 is paired and configured with the scoreboard 302 to communicate (eg to receive at least data from it).

6 shows a schematic view of a processor arrangement 100 configured in the same or a similar manner as previously described, according to various embodiments. The processor arrangement 100 may include: a plurality of logic circuits 402 which is controlled by a control circuit 602 to be controlled 603 , an evaluation circuit 606 configured for each logic circuit of the plurality of logic circuits 402 evaluate 605 whether the logic circuit is in a busy state or a non-busy state, according to a criterion representing a number of commands to be performed by the logic circuit, and a power saving circuit 610 , which is configured to reduce the power consumption of a peripheral circuit 104 according to an energy saving scheme 607 to control 609 , According to various embodiments, the power-saving scheme may be 607 a first mode (eg, a working mode) in which at least one logic circuit of the plurality of logic circuits 402 is in the non-busy state and / or in which the peripheral circuit 104 with the control circuit 602 communicates 611 , and a second mode (eg, a power saving mode) in which each logic circuit of the plurality of logic circuits 402 is in the employed state include. The peripheral circuit 104 is configured to consume less energy in the second mode than in the first mode. The energy saving scheme 607 can, as before with respect to the generation of the power reduction signal 407 described, be embodied.

According to various embodiments, the set of logic circuits 402 at least one logic circuit of the following group of logic circuits comprises: an integer unit circuit, a floating point unit circuit, a multiplier unit circuit, and a divide-by-count circuit. Illustratively, the set of logic circuits comprises 402 the functional units (FUs) of the central processing unit or of the processor, as previously described.

According to various embodiments, the at least one peripheral circuit 104 For example, a memory circuit, an input / output circuit, a wireless communication circuit, a wire-based communication circuit, and / or an embedded voltage regulator, and the like may be included.

According to various embodiments, a power saving mode of a peripheral circuit or a power reduced state of a peripheral circuit may be reduced Clock frequency, a reduced operating voltage, an off state and the like include. Therefore, decreasing the power state of each peripheral circuit may include decreasing a clock frequency, decreasing an operating voltage, or turning off the state of the respective peripheral circuit.

According to various embodiments, the control circuit 602 a scoreboard may or may be part of a scoreboard. Alternatively, the control circuit 602 include any other suitable circuit. Furthermore, the evaluation circuit 606 a part of the control circuit 602 or may be a separate circuit connected to the control circuit 602 is coupled. The evaluation circuit 606 may include a scoreboard or may be part of a scoreboard. Alternatively, the evaluation circuit 606 include any other suitable circuit.

7 FIG. 3 illustrates a schematic flowchart of a method. FIG 700 for operating a processor arrangement, e.g. B. the here with reference to 4 and 5 described processor arrangement 100 , The method 700 may include: at 710 operating a set of logic circuits 402 based on execution of instructions out of order 720 evaluating for each logic circuit of the set of logic circuits 402 a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values 730 evaluating a lowest value of the set of instruction cycle values 740 Generating a power reduction request signal 407 when the lowest value is greater than or equal to a predefined command cycle value, and at 750 controlling a power state of at least one peripheral circuit 104 based on the power reduction request signal 407 ,

8th FIG. 3 illustrates a schematic flowchart of a method. FIG 800 for operating a processor arrangement, e.g. B. the here with reference to 6 described processor arrangement 100 , The method 800 may include: at 810 the evaluation for each logic circuit of several logic circuits 402 whether the logic circuit is in a busy state or idle state, according to a criterion representing a number of instructions to be executed by the logic circuit, and at 820 controlling a power consumption of a peripheral circuit 104 According to an energy-saving scheme, the energy-saving scheme comprises: a first mode (eg, a working mode) in which at least one logic circuit of the plurality of logic circuits 402 is in the idle state or in which the peripheral circuit 104 with at least one of the logic circuits 402 communicates (eg via the control circuit 602 ), and a second mode (eg, a power saving mode) in which each logic circuit of the plurality of logic circuits 402 is in a busy state. The peripheral circuit 104 consumes less energy in the second mode than in the first mode.

9A and 9B set the operating scheme of the scoreboard 302 according to various embodiments.

As with respect to 4 described, the scoreboard can 302 be configured to make a request 407 for low power to produce when all functional units 402 (eg all logic circuits) are busy. To determine if all functional units 402 are busy, the number of cycles to be performed can be compared to a predefined number of cycles.

According to various embodiments, the instruction set architecture (ISA) of the processor or processor assembly 100 be extended to support performance management as described herein. Therefore, a power management register 922 be provided. The performance management register 922 can, for example, two bit fields 922E . 922c exhibit. As an alternative, however, only one of the two bit fields can 922E . 922c be provided. A first bit field 922c (labeled "cycles") may be programmed by an application and may serve as a comparator reference, ie, as a predefined number of cycles or as a predefined command cycle value. A second bit field 922E (labeled "EN") may be used to enable or disable the performance management described herein. Only if the second bit field 922E is set to a release value and only if all functional units 402 are employed, ie each of the functional units 402 has a number of cycles to be executed that is greater than the predefined number of cycles in the first bit field 922c can therefore be the requirement 407 be generated for low power.

As in 9B shown, the scoreboard 302 (or analogously the evaluation circuit 506 . 606 ) a MIN logic 932 include, for. B. is configured to determine a minimum value of the input values and to output this minimum value. The MIN logic 932 may be configured to determine which of the functional units / reservation stations has the least execution time represented by the respective cycle count for each of the functional units / reservation stations. The scoreboard 302 may also have a COMP logic 934 configured to be the result of the MIN logic 932 (ie the minimum number of cycles to be performed by one of the drives) with the reference 922c (ie the predefined number of cycles) programmed by the application.

Based on the result of the COMP logic 934 may be the power reduction request signal 407 be generated, that is, only if the minimum value of the MIN logic 932 is greater than that of the bit field 922c provided reference.

According to various embodiments, the display panel 302 an AND logic 936 include, in addition to the result of the COMP logic 934 the second bit field 922E so that the power reduction request signal 407 can only be generated when the power management is released. The AND logic 936 may also be configured to view a busy state of all functional units / reservation stations, ie, if not already in the construction of the MIN logic 932 and the COMP logic 934 is included, so that the power reduction request signal 407 can only be generated if all functional units / reservation stations are busy. The busy state of all functional units / reservation stations can be determined by another AND logic 938 which includes the busy state of each of the functional units / reservation stations as input.

According to various embodiments, the display panel 302 be configured to output the MIN logic 932 (called cycle count or minimum value) z. B. to a power adapter (see. 10A and 10B ) to deliver. The logic described above can operate on the usual bitwise 0/1 principle (false / true principle).

10A represents the operating principle of a power adapter 510 (Also called power circuit) and 10B represents the operating principle of the power adapter 510 in combination with the processor arrangement 100 and the peripherals 104 according to various embodiments.

The power adapter 510 can be a multiplexer 1050 or any other suitable circuit. The multiplexer 1050 can be configured to have an output signal 1051 to the peripherals 104 to deliver. The output signal 1051 can be from a group of signals 1061 . 1062 . 1063 be selected according to various embodiments. Illustratively, various actions for the peripherals, e.g. B. Action-1 ( 1061 ), Action-2 ( 1062 ) or a default treatment ( 1063 ) 104 through the power adapter 510 based on the input data to the power adapter 510 from the scoreboard 302 (or analogous to the evaluation circuit 506 . 606 ) are controlled.

The power adapter 510 may be an encoder circuit 1070 include, the bit fields C1, C2 to zero or one, which z. Represents false or true based on the cycle count as input. As previously described, the cycle count (also referred to as the lowest value of the set of instruction cycle values) may be determined by the display panel 302 be provided as an output. For example, if the cycle count is less than a cycle reference count, the encoder may set bit fields C1, C2 to (1,0). Further, the bit fields C1, C2 may be set to (0,1) if, for example, the cycle count is greater than or equal to the cycle reference count. The power adapter 510 may further comprise a release bit field (EN).

The power adapter 510 can be an AND logic circuit 1080 include, the AND logic circuit 1080 may be configured to have a placement action signal 1081 as output to one or the inputs of the multiplexer 1050 to deliver when the AND logic circuit 1080 the request 407 for low power from the scoreboard 302 and when the ENABLE enable field is set to enable (that is, when the operation of the power adapter 510 is released). If the enable bit field EN is not set to enable (for example, to zero), the operation of the power adapter may occur 510 be locked and the power adapter 510 is configured to the default action 1063 over the multiplexer 1050 issue. If no requirement 407 for low power from the AND logic circuit 1080 is the power adapter 510 also configured to the default treatment 1063 over the multiplexer 1050 issue.

As an example, the multiplexer 1050 be configured to the first action-1 ( 1061 ) if the bit fields C1, C2 were set to (1,0) and if the AND logic circuit 1080 the placement action signal 1081 supplies. Furthermore, the multiplexer 1050 be configured to the second action-2 ( 1062 ) if the bit fields C1, C2 were set to (0,1) and if the AND logic circuit 1080 the placement action signal 1081 supplies. In a similar way, the multiplexer 1050 be configured in any other suitable manner, including, for example, one or more bit fields to trigger one or more actions.

Illustrating may be the power adapter 510 be configured to different action signals 1061 . 1062 to the peripherals 104 on the Base of the encoded cycle count, and only if the AND logic circuit 1080 the placement action signal 1081 delivers, spend. Otherwise, the default signal 1063 to the peripherals 104 output.

As in 10B shown, the peripherals 104 , z. A modem, an embedded voltage regulator (EVR), a flash memory, etc., with the power adapter 510 via a programmable power bus 1008 be coupled. Examples of the different action signals 1061 . 1062 The following may be the case: for a flash memory, a signal "Enter sleep mode" or a signal "Entering the start mode", for an EVR a signal "Reduce output by 5 mV" or an "Output switch off" - signal, for a modem, a signal "reduce sampling frequency" or a "shutdown" signal and the like.

As an example, if the value of the cycle count is high, e.g. Defined by a reference value (eg, 100 or any other suitable number), the power save mode would be long enough to reduce the power consumption of the peripheral device to a lower value compared to the case when the value of the cycle count is low and the power saving mode would be short.

If the value of the cycle count is greater than a corresponding cycle reference count, power consumption of the peripherals may be reduced to a first reduced power state, and if the cycle count value is less than the cycle reference count, power consumption of the peripheral devices may be reduced to a second state Performance be reduced. The power consumption of the peripheral devices in the first state with reduced power may be lower than in the second state with reduced power. If the value of the cycle count is higher than a corresponding cycle reference count, the power consumption of the peripherals may be reduced to a first power consumption value, and if the value of the cycle count is less than the cycle reference count, the power consumption of the peripherals may be reduced to a second power consumption value. The first power consumption value may be lower than the second power consumption value.

11 FIG. 12 illustrates decreasing the average electrical current using the power saving method described herein according to various embodiments. Conventional power-saving circuits common to conventional processors 1100 can only reduce power consumption when a CPU is idle 1100a , An additional power saving 1102 According to various embodiments, by reducing the power consumption of the peripherals, it is possible to achieve when a central processing unit is busy, ie, fully engaged, as described herein. The computing power can not, according to various embodiments, by the additional power saving 1102 be influenced because the power consumption of the peripheral devices is only reduced when the central processing unit is fully busy and therefore does not access the peripherals anyway.

As in 11 shown, can not change the background current 1104 in comparison to conventional power saving schemes 1100 consist. The mean current 1106a by the processor or processor assembly 100 that is described here according to various embodiments is consumed, but may be compared to the average current 1106c that of a conventional processor 1100 is consumed 1106r ,

According to various embodiments, a processor may include: a set of functional units (eg, embodied by a set of functional unit circuits), at least a register assigned to the set of functional units, a display panel configured to control the communication between the set of functional units and the at least one register, and further configured to have a corresponding number for each functional unit of the set of functional units of instruction cycles to be executed, thereby forming a set of instruction cycle values, an evaluation circuit configured to determine a lowest value of the set of instruction cycle values, and further configured to generate a power reduction request signal if the lowest value is greater than or equal to a predefined command cycle value. According to various embodiments, a processor arrangement 100 a processor and at least one peripheral circuit and a power circuit coupled to the at least one peripheral circuit, the power circuit configured to provide a power state of the at least one peripheral circuit based on the power reduction request signal provided by the evaluation circuit is going to control. According to various embodiments, when the peripheral circuit is part of the processor, the processor arrangement may be 100 as processor, z. As a microchip or microcontroller, are considered.

According to various embodiments, a processor arrangement may include: a set of functional units, at least one register assigned to the set of functional units, a display panel configured to control the communication between the set of functional units and the at least one register, and and configured to evaluate, for each functional unit of the set of functional units, a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values, an evaluation circuit configured to determine a lowest value of the set of instruction cycle values, and further configured thereto is to generate a power reduction request signal when the lowest value is greater than or equal to a predefined command cycle value, and at least one peripheral circuit and a power circuit connected to the at least one peripheral circuit is coupled. The power circuit is configured to control a power state of the at least one peripheral circuit based on the power reduction request signal supplied from the evaluation circuit. The set of functional units may include one or more computing circuits and / or one or more logic circuits configured to perform computational and / or logical operations. Arithmetic operations may include, for example, adding, subtracting, incrementing, decrementing, passing through, and the like. Logical operations may include, for example: AND, OR, XOR, and the like. The set of functional units may also include a floating point unit (eg, embodied by one or more floating point unit circuits). The set of functional units may also include other types of functional units (eg, a graphics processing unit or sound processing unit), depending on the field of application of the processor 100 include. However, in some cases, the type of functional unit may not be relevant to the power management scheme described herein as long as it is guaranteed that each of the functional units is busy and has no access to the peripheral devices if the peripheral devices are set to a degraded state.

Example 1 is a processor arrangement comprising: a set of logic circuits; at least one register assigned to the set of logic circuits; a display panel configured to control the communication between the set of logic circuits and the at least one register, and further configured to evaluate, for each logic circuit of the set of logic circuits, a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values an evaluation circuit configured to determine a lowest value of the set of command cycle values and further configured to generate a power reduction request signal when the lowest value is greater than or equal to a predefined command cycle value; at least one peripheral circuit and a power circuit coupled to the at least one peripheral circuit; wherein the power circuit is configured to control a power state of the at least one peripheral circuit based on the power reduction request signal supplied from the evaluation circuit.

In Example 2, the processor arrangement of Example 1 may optionally include the set of logic circuits including at least one logic circuit of the following group of logic circuits: an integer unit circuit, a floating point unit circuit, a multiplier unit circuit, and a divide-by-count circuit.

In Example 3, the processor arrangement of Example 1 or 2 may optionally include the at least one peripheral circuit comprising at least one peripheral circuit of the following group of peripheral circuits: a memory circuit, an input / output circuit, a driver circuit, a communication circuit. The communication circuit may be a wireless communication circuit or a wire-based communication circuit. The driver circuit may be a (eg embedded) voltage regulator.

In Example 4, the processor arrangement of any one of Examples 1 to 3 may optionally include the evaluation circuit further configured to determine a busy state for each logic circuit of the set of logic circuits and generate the power reduction request signal if each logic circuit of the set of Logic circuits is busy.

In Example 5, the processor arrangement of any one of Examples 1 to 4 may optionally include the evaluation circuit configured to determine a memory access state for each logic circuit of the set of logic circuits and to generate the power reduction request signal only if each logic circuit of the set of Logic circuits are not instructed to access the memory.

In Example 6, the processor arrangement of any one of Examples 1 to 5 may optionally further include: a programmable register having a bit field representing the predefined command cycle value.

Optionally, in Example 7, the processor arrangement of any one of Examples 1 to 6 may further include: a programmable register having a enable bit field representing a power-saving state and a non-power-saving state, wherein the evaluation circuit is further configured to only generate the power-down request signal when the bit field represents the power-saving state.

In Example 8, the processor arrangement of any of Examples 1 through 7 may optionally include the power circuit further comprising a programmable power bus connecting the power circuit to the at least one peripheral circuit.

In Example 9, the processor arrangement of any of Examples 1 through 8 may optionally include the power circuit configured to generate one or more power state action signals to one or more corresponding power states of the at least one peripheral circuit based on the respective generated power reduction state action signal to control.

In Example 10, the processor arrangement of Example 9 may optionally include the evaluation circuit further configured to provide the lowest value of the set of instruction cycle values to the power circuit.

In Example 11, the processor arrangement of Example 10 may optionally include the power circuit further configured to generate the respective power reduction state action signal based on the lowest value of the set of command cycle values provided by the evaluation circuit.

In another example, the power circuit is configured to generate a first power reduction state action signal or a second power reduction state action signal to control a first power state or a second power state of the at least one peripheral circuit based on the respective generated power reduction state action signal. The evaluation circuit is further configured to provide the lowest value of the set of instruction cycle values to the power circuit. And the power circuit is further configured to generate the first power reduction state action signal or the second power reduction state action signal based on the lowest value of the set of command cycle values provided by the evaluation circuit.

In Example 12, the processor arrangement of Example 10 or 11 optionally may include the power circuit further configured to generate a bias power state action signal to control a Vorgabeleistungszustand the at least one peripheral circuit when no power reduction power request signal is supplied by the evaluation circuit ,

In Example 13, the processor arrangement of any one of Examples 1 to 12 may optionally include the processor arrangement configured as a processor arrangement having out-of-order execution with a set of instruction buffers, each instruction buffer of the set of instruction buffers associated with a respective logic circuit of the set of logic circuits , The command buffer may be, for example, a reservation station, such as with reference to FIG 3D described.

In Example 14, the processor arrangement of Example 13 may optionally include the evaluation circuit further configured to evaluate, for each instruction buffer of the set of instruction buffers, a corresponding number of instruction cycles to be executed by the respective logic circuit.

Example 15 is a processor arrangement comprising: a plurality of logic circuits controlled by a control circuit; an evaluation circuit configured to evaluate, for each logic circuit of the plurality of logic circuits, whether the logic circuit is in a busy state or an idle state, according to a criterion representing a number of instructions to be performed by the logic circuit; and a power saving circuit configured to control the power consumption of a peripheral circuit according to a power conservation scheme, the power saving scheme comprising: a first mode (eg, working mode) in which at least one logic circuit of the plurality of logic circuits is in the idle state or in which the peripheral circuit communicates with the control circuit; and at least one second mode (eg, a power save mode) in which each logic circuit of the plurality of logic circuits is in the busy state, wherein the peripheral circuit is configured to consume less power in the at least one second mode than in the first mode.

In Example 16, the processor arrangement of Example 15 may optionally include the peripheral circuitry not communicating with the control circuitry in the at least one second mode.

In Example 17, the processor arrangement of Example 15 or 16 may optionally include each of the plurality of logic circuits being a functional unit circuit. The functional unit circuit may be an arithmetic logic circuit.

In Example 18, the processor arrangement of any one of Examples 15 to 17 may optionally include the at least one peripheral circuit including at least one peripheral circuit of the following group of peripheral circuits: a memory circuit, an input / output circuit, a driver circuit, a communication circuit. The communication circuit may be a wireless communication circuit or a wire-based communication circuit. The driver circuit may be a (eg embedded) voltage regulator.

Example 19 is a method of operating a processor array, the method comprising: operating a set of logic circuits based on executing out-of-order instructions; Evaluating, for each logic circuit of the set of logic circuits, a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values; Evaluating a lowest value of the set of instruction cycle values; Generating a power reduction request signal if the lowest value is greater than or equal to a predefined command cycle value; and controlling a power state of at least one peripheral circuit based on the power reduction request signal.

Example 20 is a method comprising: evaluating, for each logic circuit of a plurality of logic circuits, whether the logic circuit is in a busy state or an idle state, according to a criterion representing a number of instructions to be performed by the logic circuit; and controlling a power consumption of a peripheral circuit according to an energy-saving scheme, the power-saving scheme comprising: a first mode (eg, work mode) in which at least one logic circuit of the plurality of logic circuits is in the non-busy state or in which the peripheral circuit is connected to the one Logic circuit communicates; and at least one second mode (eg, at least one power save mode) in which each logic circuit of the plurality of logic circuits is in the busy state. The peripheral circuitry consumes less energy in the at least one second mode than in the first mode.

Although the invention has been particularly shown and described with respect to particular embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims Claims defined to depart. The scope of the invention is, therefore, indicated by the appended claims and it is therefore intended to embrace all changes which fall within the meaning and range of equivalency of the claims.

Claims (17)

Processor arrangement ( 100 ), comprising: a set of logic circuits ( 402 ); at least one register ( 404 ), which corresponds to the set of logic circuits ( 402 ) is assigned; a scoreboard ( 302 ), which is configured to control the communication between the set of logic circuits ( 402 ) and the at least one register ( 404 ), and is further configured for each logic circuit of the set of logic circuits ( 402 ) evaluate a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values, an evaluation circuit ( 302 . 506 ) configured to determine a lowest value of the set of command cycle values and further configured to generate a power reduction request signal when the lowest value is greater than or equal to a predefined command cycle value; at least one peripheral circuit ( 104 ) and a power circuit ( 510 ) connected to the at least one peripheral circuit ( 104 ) is coupled; the power circuit ( 510 ) is configured to indicate a power state of the at least one peripheral circuit ( 104 ) on the basis of the power reduction request signal supplied from the evaluation circuit. A processor arrangement according to claim 1, wherein the set of logic circuits ( 402 ) comprises at least one logic circuit of the following group of logic circuits: an integer unit circuit, a floating point unit circuit, a multiplier unit circuit, and a divide-by-count circuit. Processor arrangement according to claim 1 or 2, wherein the at least one peripheral circuit ( 104 ) comprises at least one peripheral circuit of the following group of peripheral circuits: a memory circuit, an input / output circuit, a driver circuit, a communication circuit. Processor arrangement according to one of Claims 1 to 3, the evaluation circuit ( 302 . 506 ) is further configured to determine a busy state for each logic circuit of the set of logic circuits and to generate the power reduction request signal only when each logic circuit of the set of logic circuits is busy. Processor arrangement according to one of Claims 1 to 4, the evaluation circuit ( 302 . 506 ) is further configured to determine a memory access state for each logic circuit of the set of logic circuits and to generate the power reduction request signal only if each logic circuit of the set of logic circuits is not instructed to access the memory. The processor arrangement of one of claims 1 to 5, further comprising: a programmable register having a bit field representing the predefined instruction cycle value. The processor arrangement of claim 1, further comprising: a programmable register having a enable bit field representing a power saving state and a non-power saving state, wherein the evaluating circuit is further configured to generate the power reducing request signal only when the bit field represents the power saving state. Processor arrangement according to one of claims 1 to 7, wherein the power circuit ( 510 ) further comprises a programmable power bus connecting the power circuit to the at least one peripheral circuit. Processor arrangement according to claim 8, wherein the power circuit ( 510 ) is configured to generate one or more power state action signals to control one or more respective power states of the at least one peripheral circuit based on the respective generated power state action signal. Processor arrangement according to claim 9, wherein the evaluation circuit ( 302 . 506 ) is further configured to provide the lowest value of the set of command cycle values to the power circuit, and wherein the power circuit ( 510 ) is further configured to generate the respective power reduction state action signal based on the lowest value of the set of command cycle values provided by the evaluation circuit. Processor arrangement according to claims 9 or 10, wherein the power circuit ( 510 ) is further configured to generate a Vorgabeleistungsstats action signal to control a Vorgabeleistungszustand the at least one peripheral circuit when no power reduction power request signal is supplied by the evaluation circuit. Processor arrangement according to one of claims 1 to 11, wherein the processor arrangement ( 100 ) is configured as a processor arrangement having out-of-order execution with a set of instruction buffers, each instruction buffer of the set of instruction buffers being assigned to a respective logic circuit of the set of logic circuits. Processor arrangement according to claim 12, wherein the evaluation circuit ( 302 . 506 ) is further configured to evaluate, for each instruction buffer of the set of instruction buffers, a corresponding number of instruction cycles to be executed by the respective logic circuit. Processor arrangement ( 100 ), comprising: a plurality of logic circuits ( 402 ), which are controlled by a control circuit ( 302 ) to be controlled; an evaluation circuit ( 506 ) configured for each logic circuit of the plurality of logic circuits ( 402 ) to evaluate whether the logic circuit is in a busy state or a non-busy state according to a criterion representing a number of commands to be performed by the logic circuit; and a power saving circuit ( 606 ) configured to reduce the power consumption of a peripheral circuit ( 104 ) according to an energy-saving scheme ( 407 ), the power management scheme comprising: a first mode in which at least one logic circuit of the plurality of logic circuits ( 402 ) is in the idle state or in which the peripheral circuit communicates with the control circuit; and at least one second mode in which each logic circuit of the plurality of logic circuits ( 402 ) is in the busy state, the peripheral circuit ( 104 ) is configured to consume less energy in the at least one second mode than in the first mode. Processor arrangement according to claim 14, wherein the peripheral circuit ( 104 ) in the at least one second mode not with the control circuit ( 302 ) communicates. A method of operating a processor array, the method comprising: operating a set of logic circuits based on executing out-of-order instructions; Evaluating, for each logic circuit of the set of logic circuits, a corresponding number of instruction cycles to be executed, thereby forming a set of instruction cycle values; Evaluating a lowest value of the set of instruction cycle values; Generating a power reduction request signal if the lowest value is greater than or equal to a predefined command cycle value; and controlling a power state of at least one peripheral circuit based on the power reduction request signal. A method comprising: Evaluating, for each logic circuit of a plurality of logic circuits, whether the logic circuit is in a busy state or an idle state, according to a criterion representing a number of instructions to be performed by the logic circuit; and Controlling a power consumption of a peripheral circuit according to an energy-saving scheme, the power-saving scheme comprising: a first mode in which at least one logic circuit of the plurality of logic circuits is in the idle state or in which the peripheral circuit communicates with the logic circuit; and at least one second mode in which each logic circuit of the plurality of logic circuits is in the busy state, wherein the peripheral circuit consumes less energy in the at least one second mode than in the first mode.

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