DE102016116722A1 - Finfets and methods for forming finfets - Google Patents

Abstract

One embodiment is a structure having a first fin over a substrate, a second fin above the substrate, the second fin adjacent to the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region is located between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, wherein the gate structure defines channel regions in the first fin and the second fin, a gate sealing spacer Side walls of the gate structure, wherein a first portion of the gate-sealing spacer is located on the first portion of the isolation region between the first fin and the second fin, and a source / drain region on the first fin and the second fin of the gate structure includes adjacent.

Description

USING A PRIORITY AND CROSS-REFERENCE

This application claims the benefit of US Provisional Application 62 / 327,135, filed on Apr. 25, 2016, entitled "FINFETS AND METHODS OF FORMING FINFETS", which patent application is incorporated herein by reference.

GENERAL PRIOR ART

As the semiconductor industry has progressed to nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges for both manufacturing and design problems have involved the development of three-dimensional designs, such as a fin field effect transistor (FinFET ). A typical FinFET is fabricated with a thin vertical "fin" (or fin structure) that extends from a substrate and is formed, for example, by etching away a portion of a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin (eg, wrapping). The presence of a gate on both sides of the channel allows gate control of the channel from both sides. However, there are challenges in performing such features and methods in semiconductor manufacturing.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure will be best understood upon reading the following detailed description in conjunction with the accompanying drawings. It should be noted that various features are not to scale according to standard industry practice. In fact, the dimensions of the various features may have been arbitrarily increased or decreased for clarity of discussion.

1 FIG. 12 is an example of a fin field effect transistor (FinFET) in a three-dimensional view.

2 to 6 . 7A - 7C . 8A - 8C . 9A - 9C and 10 to 14 FIG. 3 are three-dimensional and cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. FIG.

15 and 16 12 illustrate cross-sectional views of intermediate stages of processing a gate-load structure according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for carrying out various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course only examples and no limitation is intended. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are interposed between the first and second features second feature may be formed such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and as such does not dictate any relationship between the various embodiments and / or embodiments discussed.

Further, terms describing a spatial relationship, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of an element or feature to another element (s) or feature (s), as illustrated in the figures. It is intended that terms describing a spatial relationship encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spacial designations used herein may also be construed accordingly.

According to various embodiments, a fin field effect transistor (FinFETs) and methods of forming the same are provided. Intermediates of the formation of FinFETs are illustrated. Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate first method. In other embodiments, a gate-load method may be used (sometimes also referred to as a replacement gate method referred to as). Some variations of the embodiments will be discussed. One of ordinary skill in the art will readily appreciate other modifications that can be made and contemplated within the scope of other embodiments. Although method embodiments are discussed in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps described herein.

Before the illustrated embodiments are specifically treated, certain advantageous features and aspects of the presently disclosed embodiments are generally discussed. In general terms, the present disclosure is a semiconductor device and a method of forming it to provide a simple and economical process flow to an epitaxial source / drain in a FinFET with fewer errors (such as dislocations), at least in the vicinity a channel region of the FinFET to improve the device to accomplish. In addition, a simple and economical procedure can provide better isolation between adjacent fins by reducing the leakage between adjacent fins, and can also reduce the contact resistance to the source / drain region. In particular, embodiments such as the sequential disclosed methodology and structure include the epitaxially grown source / drain regions with some of the isolation material of the isolation region (eg, trench isolation region (STI)) and some of the sidewall Spacer material that remains between the adjacent fins in the source / drain regions. This residual insulation material and spacer material suppresses the generation of dislocations because it reduces the amount of epitaxial volume between adjacent fins. Furthermore, the remainder of the insulating material and spacer material can reduce the capacitance between the epitaxial source / drain structure. This reduced capacity may allow for better AC power (AC) for the device. Further, an upper surface of the epitaxial source / drain structure may have a non-planar (eg, undulating and / or undulating) upper surface, which may increase the contact surface for the overlying contact. This increased contact surface can reduce the contact resistance to the source / drain region.

1 illustrates an example of a FinFET 30 in a three-dimensional view. The FinFET 30 includes a fin 36 on a substrate 32 , The substrate 32 includes isolation areas 34 and the Finn 36 stands above and from between neighboring isolation areas 34 out. A gate dielectric 38 is located along sidewalls and over an upper surface of the fin 36 and a gate electrode 40 is located above the gate dielectric 38 , The source / drain regions 42 and 44 are in relation to the gate dielectric 38 and to the gate electrode 40 in opposite sides of the fin 36 arranged. 1 further illustrates reference cross sections used in subsequent figures. The cross section BB extends transversely through a channel, the gate dielectric 38 and the gate electrode 40 of the FinFET 30 , The cross section CC runs parallel to the cross section BB and extends transversely through a source / drain region 42 , The cross section AA is perpendicular to the cross section BB and extends along a longitudinal axis of the fin 36 and in a direction of, for example, a current flow between the source / drain regions 42 and 44 , The following figures refer to the clarity of these reference cross-sections.

2 to 6 . 7A - 7C . 8A - 8C . 9A - 9C and 10 to 14 FIG. 3 are three-dimensional and cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. FIG. 2 to 6 . 7A - 7C . 8A - 8C . 9A - 9C and 10 to 16 illustrate a FinFET associated with the FinFET 30 in 1 is similar to several Finns. 2 to 6 illustrate the cross section BB. In 7A to 9C For example, figures whose designation ends with an "A", three-dimensional views, figures whose designation ends with a "B" illustrate the cross section BB, and figures whose designation ends with a "C" illustrate the cross section CC. 10 and 12 to 14 illustrate the cross section CC and 11 illustrates the cross section AA.

2 illustrates a substrate 50 , The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, with a p- or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as a multilayer or gradient substrate. In some embodiments, the semiconductor material of the substrate 50 Silicon; germanium; a compound semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, Indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

The substrate 50 may include integrated circuit devices (not shown). As one of ordinary skill in the art will appreciate, a wide variety of integrated circuit devices, such as transistors, diodes, capacitors, resistors, the like, or combinations thereof may be incorporated in and / or on the substrate 50 to create the structural and functional requirements of the design for the FinFET. The integrated circuit devices may be formed using any convenient method.

3 illustrates the formation and patterning of a mask layer 56 above the substrate 50 and the structuring of the substrate 50 using the mask layer 52 for forming semiconductor strips 60 , In some embodiments, the mask layer is 52 a hard mask and can subsequently be used as a hard mask 52 be designated. The hard mask 52 may be formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof.

In some embodiments, the semiconductor strips may 60 by etching trenches in the substrate 50 be formed. The etching may be any acceptable etching technique, such as Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or a combination thereof. The etching can be anisotropic.

4 illustrates the formation of an insulating material between adjacent semiconductor strips 60 for forming isolation areas 62 , The insulating material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be obtained by high density plasma chemical vapor deposition (HDP-CVD) or flowable CVD (FCVD) (US Pat. for example, a CVD-based material deposition in a remote plasma system and a post-cure to convert it to another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any acceptable method may also be used. In the illustrated embodiment, the insulating material is a silicon oxide formed by a FCVD process. After the formation of the insulating material, a tempering process may be performed. Furthermore, in 4 a planarization process, such as chemical mechanical polishing (CMP), any excess insulating material (and, if present, the hard mask 56 ) and remove top surfaces in the isolation areas 62 and upper surfaces of the semiconductor strips 60 that are coplanar form.

5 illustrates the depression of the isolation areas 62 such as for forming trench isolation areas (shallow trench isolation - STI) 62 , The isolation areas 62 are deepened such that the upper portions of the semiconductor strips 60 from between adjacent isolation areas 62 stand out and semiconductor fins 64 form. The upper surfaces of the isolation areas 62 For example, a flat surface as illustrated may have a convex surface, a concave surface (such as dishing), or a combination thereof. The upper surfaces of the isolation areas 62 can be formed flat, convex and / or concave by appropriate etching. The isolation areas 62 can be recessed using an acceptable etching process, such as that for the material of the isolation regions 62 is selective. For example, a chemical oxide removal using a CERTAS ^® etch or an Applied Materials SICONI tool or diluted hydrofluoric acid (Dilute Hydrofluoric - DHF) are used.

2 to 5 illustrate an embodiment for forming fins 64 but Finns can be formed in many different ways. In one example, the fins may be formed by etching trenches in a substrate to form semiconductor strips; the trenches can be filled with a dielectric layer; and the dielectric layer may be recessed such that the semiconductor strips protrude from the dielectric layer to form fins. In another example, a dielectric layer may be formed over an upper surface of a substrate; Trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In yet another example, heteroepitaxial structures may be used for the fins. For example, the semiconductor strips may be recessed, and a material different from the semiconductor strips may be epitaxially grown in their place. In yet another example, a dielectric layer may be formed over an upper surface of a substrate; Trenches can be etched through the dielectric layer; Heteroepitaxial structures can be epitaxially grown in the trenches using a material that differs from the substrate; and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins. In some embodiments, where homoepitaxial or heteroepitaxial structures are grown epitaxially, the grown materials may be doped in place during growth, thereby avoiding previous and subsequent implantations, although on-site doping and implantation may be shared , Further, it may be advantageous to epitaxially grow a material in an NMOS region that is different from the material in a PMOS region. In various embodiments, the fins may include silicon germanium (SixGe1-x, where x may be between about 0 and 100), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, an II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

6 illustrates the formation of a gate structure over the semiconductor fins 64 , A dielectric layer (not shown) is on the semiconductor fins 64 and the isolation areas 62 educated. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. In some embodiments, the dielectric layer may be a high-k dielectric, and in these embodiments, the dielectric layer may have a k value that is greater than about 7.0, and may be a metal oxide or a silicate of Hf, Al, Zr, La , Mg, Ba, Ti, Pb, multiple layers thereof, and combinations thereof. The methods for forming the dielectric layer may include Molecular Beam Deposition (MBD), Atomic Layer Deposition (ALD), Plasma Enhanced CVD (PECVD), and the like.

A gate layer (not shown) is formed over the dielectric layer and a mask layer (not shown) is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of polysilicon, for example, although other materials may be used. In some embodiments, the gate layer may comprise a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. The mask layer may be formed of silicon nitride or the like, for example.

After the layers are formed, the mask layer may be patterned using acceptable photolithography and etching techniques to form the mask 70 to build. The structure of the mask 70 can then be transferred by an acceptable etching technique to the gate layer and the dielectric layer to the gate 68 and the gate dielectric 66 to build. The gate 68 and the gate dielectric 66 cover corresponding channel areas of the semiconductor fins 64 from. The gate 68 may also have a longitudinal direction which is substantially perpendicular to the longitudinal direction of the corresponding semiconductor fins 64 is.

7A . 7B and 7C illustrate the formation of gate seal spacers 72 on exposed surfaces of isolation areas 62 , Semiconductor fins 64 , the gate 68 and the mask 70 , The gate sealing spacers 72 may be formed by a thermal oxidation or a deposition process. In some embodiments, the gate sealing spacers 72 may be formed of a nitride such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof.

8A . 8B and 8C illustrate the removal of portions of the gate seal spacers outside the sidewalls of the gate structures. In some embodiments, an anisotropic etch process, such as a dry etch process, may be used to extend portions of the gate seal spacers 72 outside the sidewalls of the gate structures. In some embodiments, after the etching process, some portions of the gate sealing gap remain 72 in the isolation areas 62 between the adjacent semiconductor fins 64 (please refer 8C . 9C . 10 and 12 to 14 ). The reason that some gate sealer spacer material 72 in the isolation areas 62 may at least partly rely on the gate seal spacer material 72 in the isolation areas 62 compared to the upper surface of the semiconductor fins 64 (please refer 7C ) is formed thicker.

Furthermore, in 8A . 8B . 8C and 9A . 9B and 9C Finns 64 removed outside the gate structures. The gate structures may be during the removal of the fins 64 be used as a mask. In some embodiments, the removal of the fins is 64 outside the gate structure, a multi-step removal process. In an embodiment, the method of removal in several steps a first method for dry etching and a second method for wet etching. As in 8A . 8B and 8C 1, the first dry etching process removes the upper portions of the fins 64 outside the gate structure while gate-sealing spacer material 72 ' on the isolation areas between adjacent fins 64 is maintained. The second method of wet etching selectively etches the remaining portions of the fins 64 and, in some embodiments, etches into the semiconductor strips 60 under an upper surface of the isolation areas 62 to depressions 76 in the semiconductor fins 64 and / or isolation areas 62 to build.

The dry etching method of the first step may be any acceptable etching method such as RIE, NBE, the like, or a combination thereof. In one embodiment, the dry etching process of the first step is a plasma dry etching process with less bombardment such that the gate seal spacer material 72 ' in the isolation areas 62 is maintained between the adjacent semiconductor fins. The etching can be anisotropic. In some embodiments, the dry step method of the first step has a bias of less than or equal to about 50 volts in an environment having a pressure greater than or equal to about 100 millitorr (mTorr). The plasma may be generated by any convenient method of generating the plasma, such as a plasma generator coupled to a transformer, inductively coupled plasma systems, magnetically assisted reactive ion etching, electron cyclotron resonance, a remote plasma generator, or the like.

As in 9A . 9B and 9C FIG. 1 illustrates that, after the first dry etching process, the second wet etching process further removes the fins 64 / 60 between the remaining isolation areas 62 and the remaining gate seal spacer material 72 ' to depressions 76 to build. In some embodiments, the wells have 76 Surfaces on, extending below upper surfaces of the isolation areas 62 extend. This second method of wet etching may be any acceptable etching method, such as a tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH ₄ OH), a wet etchant that is capable of fines 64 / 60 with a good etch selectivity between the material of the fins 64 / 60 and a material of the isolation areas 62 and the gate seal spacer material 72 to etch. The etching can be isotropic. In some embodiments, after performing both the dry and wet etch processes, the remaining gate seal spacer material may be used 72 ' due to the etching process have rounded upper surfaces (see 9C ). In some embodiments, the top surfaces of the semiconductor strips lie 60 at least at portions of the lower surfaces of the recesses 76 free.

10 illustrates the formation of the source / drain regions 80 , The source / drain regions 80 be in the wells 76 formed by epitaxial growth of a material in the wells, such as by metalorganic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. As in 10 illustrated, due to the barrier of the remaining isolation area material 62 and the remaining gate seal spacer material 72 ' between the neighboring Finns 64 / 60 the source / drain regions 80 first vertically in the wells 76 (Section B in 10 ), with the source / drain regions 80 do not grow horizontally during this time. After the wells 76 have been completely filled, become the source / drain areas 80 both vertically and horizontally grown to form facets (section A in FIG 10 ). As in 10 illustrates the remaining gate seal spacer material 72 ' due to the etching steps and / or force from the growth of the epitaxial source / drain regions 80 have round top surfaces and uneven sidewalls (ie wavy or wavy sidewalls).

In 10 is a bi-layer-like epitaxial source / drain structure 80 illustrated with sections A and B. The structure between the epitaxial structures (sometimes referred to as an inter-epitaxial structure) includes both the remaining isolation region material 62 as well as the remaining gate seal spacer material 72 ' and may also be referred to as an inter-epi bi-layer structure. In some embodiments, the remaining gate seal spacer material extends 72 ' between both A-sections of the source / drain region 80 on the neighboring fins 64 / 60 and contact her. The inter-epi bi-layer structure comprises a first layer (L1) of gate-seal spacer material 72 ' over a second layer (L2) of insulation area material 62 , In some embodiments, L1 has a height in a range of about 9 nm to about 15 nm. The height of L1 helps control the epitaxial volume of the source / drains 80 and this will directly affect the WAT performance of the device. In some embodiments, L2 has a height in a range of about 14 nm to about 20 nm. The height of L2 will help determine the electrical isolation between adjacent fins and will also control the epitaxial volume of the source / drains 80 help. In some embodiments, the width (W1) of the inter-epi-bi-layer structure ranges from about 17 nm to about 23 nm. The larger the width W1 of the inter-epi-bi-layer structure, the higher the Pressure the inter-epi-bi-layer structure on the epitaxial volume of the source / drains 80 which may degrade WAT performance and, in particular, may degrade (Isat / Ion) performance.

As in 10 illustrates, the source / drain regions merge 80 the neighboring Finns 64 / 60 to an uninterrupted epitaxial source / drain region 80 to build. In some embodiments, the source / drain regions merge 80 for neighboring Finns 64 / 60 not with each other and remain separate source / drain regions 80 , In some example embodiments, where the resulting FinFET is an n-FinFET, the source / drain regions include 80 Silicon carbide (SiC), silicon phosphorus (SiP), phosphorus doped silicon carbon (SiCP), or the like. In alternative exemplary embodiments, where the resulting FinFET is a p-type FinFET, the source / drain regions comprise 80 SiGe and a p-type impurity such as boron or indium.

The epitaxial source / drain regions 80 can be implanted with dopants to source / drain regions 80 to form, followed by annealing. The implantation method may include forming and patterning masks, such as a photoresist, to cover the areas of the FinFET that are to be protected prior to the implantation process. The source / drain regions 80 may have an impurity concentration in a range of about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . In some embodiments, the epitaxial source / drain regions may be doped in place during growth.

11 illustrates the intermediate processing of 10 along the cross section AA of 1 , As in 11 illustrates, the epitaxial source / drain regions 80 Have surfaces corresponding to corresponding surfaces of the fins 64 sublime (eg over the non-recessed sections of the fins 64 are sublime) and can have many facets. 11 further illustrates gate sealing spacer 86 on the gate sealing spacers 72 along sidewalls of the gate structure. The gate spacers 86 can be formed by conformally depositing a material and then anisotropically etching the material. The material of the gate spacer 86 may be silicon nitride, SiCN, a combination thereof, or the like. The gate spacers 86 may be before or after the epitaxial source / drain regions 80 be formed. In some embodiments, dummy gate spacers become on the gate sealing spacers 72 before the epitaxial process of the epitaxial source / drain regions 80 formed and the dummy gate spacers are removed and with the gate spacers 86 replaced after the epitaxial source / drain regions 80 were formed.

After formation of the source / drain regions 80 becomes a cover layer 84 on the source / drain regions 80 educated. The cover layer 84 can be considered as part of the source / drain regions. In some embodiments, the cover layer becomes 84 epitaxially on the source / drain regions 80 let grow. The cover layer 84 helps to protect the source / drain regions 80 against loss of dopants during subsequent processing (eg, etching, temperature processing, etc.). The topography of the source / drain regions 80 can not be controlled, as in 10 and 12 shown, or just to be (not shown).

The source / drain regions 80 may have a Ge concentration higher than 40%. The higher concentration of source / drain regions 80 allows the source / drain regions 80 to apply a higher load to the channel region of the FinFET. This high dopant concentration section of the source / drain regions 80 can also act as a stressor layer 80 be designated. In addition, the dopant concentration of the cover layer 84 and the one of the stressor layer 80 differ. For example, the cover layer 84 have a Ge concentration lower than about 40% while the stressor layer 80 has a Ge concentration higher than 40%.

In some embodiments, the stressor layer 80 and the topcoat 84 be formed in a single, uninterrupted epitaxial process. In other embodiments, these structures may be formed in separate processes. In the single continuous process embodiment, the processing parameters of the epitaxial process (eg, process gas flow, temperature, pressure, etc.) may be varied to form these structures with the varying material compositions. For example, during epitaxy, the flow rate of the germanium-containing precursor (such as GeH ₄ ) may be during the initial formation of the stressor layer 80 (sometimes referred to as a buffer layer) is at a first level and may transition to the formation of the majority of the stressor layer 80 be increased to a second level. Furthermore, the flow velocity of the Germanium-containing precursor in the transition to the formation of the cover layer 84 be reduced from the second level to a third level. The cover layer 84 and the buffer layer may be considered part of the source / drain regions.

Subsequently, the processing of the FinFET device may be performed, such as the formation of one or more interlayer dielectric layers and the formation of contacts. These methods are described below with reference to 13 and 14 discussed.

In 13 is a dielectric interlayer (Interlayer Dielectric - ILD) 90 over the in 12 illustrated structure deposited. The ILD 90 is formed of a dielectric material such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG) or the like, and may be formed by any convenient method such as CVD, PECVD or FCVD. be deposited.

In 14 becomes a contact 92 through the ILD 90 educated. The opening for the contact 92 is through the ILD 90 educated. The opening can be formed using acceptable photolithography and etching techniques. In some embodiments, at least a portion of the cover layer becomes 84 removed during the formation of the opening. In the openings, a lining such as a diffusion barrier layer, an adhesive layer or the like and a conductive material are formed. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel or the like. A planarization process, such as a CMP, may be performed to remove excess material from an area of the ILD 90 to remove. The remaining liner and conductive material form the contacts 92 in the openings. An annealing process may be performed to remove a silicide at the interface between the source / drain regions 80 (if present, the topcoat 84 ) and the contact 92 to build. The contact 92 is physically and electrically connected to the source / drain regions 80 (if present, the topcoat 84 ) coupled.

Although not expressly shown, one of ordinary skill in the art will readily appreciate that further method steps are based on the structure in FIG 14 can be performed. For example, various intermetal dielectrics (IMDs) and their corresponding metallizations may be over the ILD 90 be formed. Furthermore, contacts to the gate 68 are formed by overlapping dielectric layers.

Further, in some embodiments, a gate-load method may be used (sometimes referred to as a replacement gate method). In these embodiments, the gate 68 , the gate dielectric 66 are considered as dummy structures and are removed during subsequent processing and replaced with an active gate and an active dielectric.

15 and 16 12 illustrate cross-sectional views of intermediate stages of processing a gate-load structure according to some embodiments. 15 and 16 are cross-sectional views along the cross section AA of 1 ,

15 illustrates a structure after the processing of 13 but with additional steps being taken. These additional steps include the removal of the gate 68 (sometimes called the dummy gate in this embodiment) 68 is designated), the gate sealing spacer 72 and portions of the gate dielectric layer 66 (sometimes referred to as a dummy gate dielectric layer in this embodiment) 66 referred to) directly under the gate 68 lies. In some embodiments, the gate 68 and the gate dielectric 66 , and the gate sealing spacers 72 in an etching step (s) such that pits are formed. Each well defines a channel region of a corresponding fin 64 free. Each channel region is between adjacent pairs of epitaxial source / drain regions 80 arranged. During the removal, the dummy gate dielectric layer may 66 be used as an etch stop layer when the dummy gate 68 is etched. The Dummy Gate Dielectric Layer 66 and the gate sealing spacers 72 can then after the removal of the dummy gate 68 be removed.

Furthermore, in 15 , the gate dielectric layer 96 and the gate electrode 98 formed for replacement gates. The gate dielectric layer 96 is conformally deposited in the recess, such as on the top surfaces and the side walls of the fins 64 and on sidewalls of the gate spacers 86 and on an upper surface of the ILD 90 , According to some embodiments, the gate dielectric layer comprises 96 Silicon oxide, silicon nitride or multiple layers thereof. In other embodiments, the gate dielectric layer comprises 96 a high-k dielectric, and in these embodiments, the gate dielectric layers 96 have a k value higher than about 7.0, and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The methods of forming the gate dielectric layer 96 may include MBD, ALD, PECVD and the like.

Next will be the gate electrode 98 over the gate dielectric layer 96 deposited or fills the remaining portions of the recess. The gate electrode 98 may be made of a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof or multiple layers thereof. After filling the gate electrode 98 For example, a planarization process, such as a CMP, may be performed to cover the excess portions of the gate dielectric layer 96 and the material of the gate electrode 98 Remove the excess sections above the top surface of the ILD 90 are located. The resulting remaining portions of material of the gate electrode 98 and the gate dielectric layer 96 thus form a replacement gate of the resulting FinFET.

In 16 is an ILD 100 over the ILD 90 deposited. Furthermore, as in 16 illustrates contacts 92 through the ILD 100 and the ILD 90 formed and the contact 102 is through the ILD 100 educated. In one embodiment, the ILD 100 a flowable thin film formed by a flowable CVD process. In some embodiments, the ILD is 100 is formed of a dielectric material such as a PSG, BSG, BPSG, USG or the like, and may be formed by any convenient method such as CVD and PECVD. Openings for the contacts 92 are through the ILDs 90 and 100 educated. The opening for the contact 102 is through the ILD 100 educated. These openings can all be formed simultaneously in a same process or in separate processes. The openings may be formed using acceptable photolithography and etching techniques. In the openings, a lining such as a diffusion barrier layer, an adhesive layer or the like and a conductive material are formed. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel or the like. A planarization process, such as a CMP, may be performed to remove excess material from an area of the ILD 100 to remove. The remaining liner and conductive material form the contacts 92 and 102 in the openings. An annealing process may be performed to remove a silicide at the interface between the epitaxial source / drain regions 80 or the contacts 92 to build. The contacts 92 are physically and electrically connected to the epitaxial source / drain regions 80 coupled and the contact 102 is physically and electrically connected to the gate electrode 98 coupled.

With embodiments, benefits can be accomplished. For example, the present disclosure is a semiconductor device and a method of forming it to provide a simple and economical process flow to an epitaxial source / drain in a FinFET with fewer errors (such as dislocations) at least near a channel region FinFET to accomplish the improvement of the device. In addition, a simple and economical procedure can provide better isolation between adjacent fins by reducing the leakage between adjacent fins, and can also reduce the contact resistance to the source / drain region. In particular, embodiments such as those disclosed below will include the epitaxially grown source / drain regions with some of the isolation material of the isolation region (eg, trench isolation region (STI)) and some of the sidewall seal spacer material which remains between the adjacent fins in the source / drain regions. This residual insulation material and spacer material suppresses the generation of dislocations because it reduces the amount of epitaxial volume between adjacent fins. Furthermore, the remainder of the insulating material and spacer material can reduce the capacitance between the epitaxial source / drain structure. This reduced capacity may allow for better AC power (AC) for the device. Further, an upper surface of the epitaxial source / drain structure may have a non-planar (eg, undulating and / or undulating) upper surface, which may increase the contact surface for the overlying contact. This increased contact surface can reduce the contact resistance to the source / drain region.

One embodiment is a structure having a first fin over a substrate, a second fin above the substrate, the second fin adjacent to the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region is located between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, wherein the gate structure defines channel regions in the first fin and the second fin, a gate sealing spacer Side walls of the gate structure, wherein a first portion of the gate-sealing spacer is located on the first portion of the isolation region between the first fin and the second fin, and a source / drain region on the first fin and the second fin of the gate structure includes adjacent.

Another embodiment is a method of forming fins on a substrate, forming an isolation region surrounding the fins, wherein a first portion of the isolation region is between adjacent fins, forming a gate structure over the fin, forming a gate seal spacer on sidewalls of the gate structure, wherein a first portion of the gate seal spacer is on the first portion of the isolation region between adjacent fins and includes forming source / drain regions on opposite sides of the gate structure at least one of the source / drain regions extends over the first portion of the gate seal spacer.

Another embodiment is a method of forming a first fin and a second fin over a substrate, the second fin adjacent to the first fin, depositing an insulating material surrounding the first fin and the second fin, wherein a first portion of the insulating material is between the first fin and the second fin, upper portions of the first fin and the second fin extending over an upper surface of the insulating material, forming a gate structure along sidewalls and over upper surfaces of the first fin and second fin, wherein the gate structure defines channel regions in the first fin and the second fin, depositing a gate sealing spacer on sidewalls of the gate structure, wherein a first portion of the gate sealing spacer is on the first portion of the insulating material between the first Finn and the second fin is located, the deepening de r first fin and the second fin outside the gate structure to form a first recess in the first fin and a second recess in the second fin and epitaxially grow a first source / drain region in the first recess of the first fin and the second Recess of the second fin, wherein the first portion of the gate sealing spacer between the first portion of the insulating material and the first source / drain region is interposed.

Previously, features of several embodiments have been presented so that those skilled in the art can better understand the aspects of the present disclosure. It should be understood by those skilled in the art that the present disclosure may readily serve as a basis for designing or modifying other methods and structures to accomplish the same purposes and / or achieve the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that it can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims (20)

Structure comprising: a first fin over a substrate; a second fin above the substrate, the second fin adjacent to the first fin; an isolation region surrounding the first fin and the second fin, wherein a first portion of the isolation region is between the first fin and the second fin; a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin; a gate seal spacer on sidewalls of the gate structure, wherein a first portion of the gate seal spacer is on the first portion of the isolation region between the first fin and the second fin; and a source / drain region on the first fin and the second fin adjacent to the gate structure. The structure of claim 1, wherein the source / drain region is an uninterrupted source / drain region between the first fin and the second fin. The structure of claim 1 or 2, wherein the source / drain region comprises: a first portion on the first fin, wherein the first portion of the source / drain region extends vertically from the first fin; and a second portion on the first portion, the second portion extending both horizontally and vertically. The structure of claim 3, wherein the source / drain region comprises: a third portion on the second fin, wherein the third portion of the source / drain region extends vertically from the second fin; and a fourth section on the third section, the fourth section extending both horizontally and vertically. The structure of claim 4, wherein the first portion of the gate seal spacer contacts the first portion and the third portion of the source / drain region. A structure according to any one of the preceding claims, wherein the source / drain region has a non-planar top surface. A structure according to any one of the preceding claims, wherein the source / drain region is an epitaxial source / drain region. A structure according to any one of the preceding claims, wherein the source / drain region comprises: a buffer layer on the first fin and the second fin, the buffer layer having a first dopant concentration of a first dopant; a stressor layer on the buffer layer, the stressor layer having a second dopant concentration of the first dopant, the second dopant concentration being higher than the first dopant concentration; and a cover layer on the stressor layer, wherein the cover layer has a third dopant concentration of the first dopant, wherein the third dopant concentration is lower than the second dopant concentration. A structure according to any one of the preceding claims, wherein the first dopant is germanium. A method comprising: Forming fins on a substrate; Forming an isolation region surrounding the fins, wherein a first portion of the isolation region is located between adjacent fins; Forming a gate structure over the fin; Forming a gate seal spacer on sidewalls of the gate structure, wherein a first portion of the gate seal spacer is on the first portion of the isolation region between adjacent fins; and Forming source / drain regions on opposite sides of the gate structure, wherein at least one of the source / drain regions extends over the first portion of the gate seal spacer. The method of claim 10, wherein the source / drain regions are continuous source / drain regions between adjacent fins. The method of claim 10 or 11, wherein the at least one source / dranium region has a non-planar top surface. The method of any one of claims 10 to 12, wherein forming the source / drain region comprises: Recessing the fins outside the gate structure to have upper surfaces under an upper surface of the isolation region; and epitaxially growing the source / drain regions from the recessed fins on opposite sides of the gate structure. The method of claim 13, wherein recessing the fins outside the gate structure to have top surfaces below an upper surface of the isolation region comprises: Performing a dry etching process to recess the fins outside the gate structures; and after the dry etching process, performing a wet etching process to further deepen the fins outside the gate structures. The method of claim 13 or 14, wherein the epitaxial growth of the source / drain regions of the fins comprises: epitaxially growing a buffer layer on the fins, the buffer layer having a first dopant concentration; epitaxially growing a stressor layer on the buffer layer, the stressor layer having a second dopant concentration, the second dopant concentration being higher than the first dopant concentration; and epitaxially growing a cover layer on the stressor layer, wherein the cover layer has a third dopant concentration, wherein the third dopant concentration is lower than the second dopant concentration. A method comprising: Forming a first fin and a second fin over a substrate, the second fin adjacent to the first fin; Depositing an insulating material surrounding the first fin and the second fin, wherein a first portion of the insulating material is located between the first fin and the second fins, upper portions of the first fin and the second fin extending over an upper surface of the insulating material; Forming a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin; Depositing a gate seal spacer on sidewalls of the gate structure, wherein a first portion of the gate seal spacer is on the first portion of the insulating material between the first fin and the second fin; Recessing the first fin and the second fin outside the gate structure to form a first recess in the first fin and a second recess in the second fin; and epitaxially growing a first source / drain region in the first recess of the first fin and the second recess of the second fin, wherein the first portion of the gate seal spacer is interposed between the first portion of the insulating material and the first source / drain region. The method of claim 16, wherein the first source / drain region comprises: first portions extending from lower surfaces of the first and second recesses to an upper surface of the first portion of the gate seal spacer; and second portions on the first portions, the second portions extending over the first portion of the gate seal spacer. The method of claim 16 or 17, wherein recessing the first fin and the second fin outside the gate structure comprises: Performing a dry etching process to recess the first fin and the second fin outside the gate structures; and after the dry etching process, performing a wet etching process to further deepen the first fin and the second fin outside the gate structures. The method of any one of claims 16 to 18, further comprising: Forming a first dielectric interlayer over the first fin, surrounding the second fin, the first source / drain region, and the gate structure; Replacing the gate structure with an active gate structure; Forming a second interlayer dielectric layer over the first interlayer dielectric and the gate structure; Forming a first contact through the first inter-level dielectric layer and the second inter-level dielectric layer to be electrically coupled to the first source-drain region; and Forming a second contact by the second dielectric interlayer to be electrically coupled to the active gate structure. The method of any one of claims 16 to 19, wherein the first source / drain region is an uninterrupted source / drain region between the first fin and the second fin.

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