DE102016115177A1 - Method for operating a memory device and memory device - Google Patents

Abstract

In various embodiments, a method of operating a memory device is provided. The method may comprise first storing a plurality of data elements forming a data record in the memory cells, wherein each data element of the plurality of data elements is stored in a respective memory cell of the plurality of memory cells such that the data elements of the data set are stored in memory cells be driven by a common first word line, so that there is a first assignment of the data elements to the bit lines, and a second storage of the plurality of data elements in the memory cells, each data element of the plurality of data elements in each case a separate memory cell from the A plurality of memory cells are stored as a first redundant data set such that the data elements of the data set are stored in memory cells driven by a common second wordline and in which the driving bitlines are the same as in FIG first storing, so that there is a second assignment of the data elements to the bit lines, wherein the first assignment is different from the second assignment.

Description

The invention relates to a method for operating a memory device and a memory device.

Typical semiconductor memory devices (also referred to as memory for short) may be a field of memory cells (also referred to as a cell array; in some contexts, this cell array, eg, without word or bitline drivers, etc., is also referred to herein as a memory, if the difference is relevant is, becomes clear from the context, as the term is to be understood).

In 1 is an example of a flash memory device 100 shown. The cell field 102 one into a memory controller 112 (eg a microcontroller, eg a so-called Flash Standard Interface, FSI) embedded flash memory 110 can typically be between some 100 kByte and a few 1 Mbyte. The memory 110 can be divided into several sectors, as exemplified in 3 is shown, for example, a configuration sector (Config sector CFS), LogSectors and PhysSectors as sectors of a so-called PFlash area (with numbered sectors PS0, ..., PSn) and data sectors (eg in different modules) DS0, .. ., DSm in a so-called Dflash area.

Sector boundaries between the sectors may be parallel to word lines (WL). This means that WLen can be grouped into sectors. The word lines may be from an address decoder 106 be controlled. Unselected WLen can be deselected, selected WLen can be selected.

Upon successful selection, the wordline driver associated with the selected wordline may generate an increased output voltage which may be connected in series to gates of a plurality of flash cells.

The cells of the cell field 102 can usually be realized as NMOS FETs. By means of a built-in, insulating floating gate, a threshold voltage of a through-connection can be programmed via charge injection via a tunnel oxide. With the charge state of the floating gate, an emitter-collector current of the transistor can be set with a defined gate drive. The current flow is called cell current. A time course of the cell current Icell is in 1B shown.

The comparison of the cell current with a reference current determines the logical bit state (in the simplest case 0 or 1). In general, a distinction can be made between single-transistor (UCP) for "Uniform Channel Program" cells and two-transistor flash memory cells (split-gate cells).

While in the two-transistor flash cell, the deselection of the cell and the memory information from a transistor are set, in the one-transistor cell, the memory information and the memory cell selection are determined from a gate. In the two-transistor flash cell, the select gate is disconnected from the memory transistor and additionally suppresses leakage currents to a bit line.

A wordline may have one or more so-called memory "pages". A page group of memory information along a page is characterized in that the gates of the select transistors along the WL path can be driven in parallel. Pages can be "meshed" along a WL drive.

A memory access can be addressed by means of a so-called "page address".

The bit lines BL can run perpendicular to the word lines WL or to the sectors. A binary information of a page may be addressed and evaluated in parallel along the BL.

At the end of a sector, the bitlines, also referred to as local bitlines, can be switched to so-called global bitlines. The bit lines may terminate in so-called sense amplifier circuits (SA). The evaluation amplifier circuit SA can compare the bit stream from the cell (Icell) with a defined reference current (IRef), as shown in FIG 2 is illustrated.

A cell-individual contribution of the reading bit-line current can be evaluated by means of different evaluation methods: in addition to a cell field comprehensive assessment (so-called IRef-sensing), there are the methods of differential sensing, and of the cell-field-specific reference cell evaluation, to cell - / BL- / WL-eliminate individual differences in rating offset.

A period of time from the beginning of the word line selection via the driving of the word line voltage, the opening of the transistor and driving of the static current strength to the subsequent evaluation in the evaluation amplifier is referred to as latency. This waiting time is essentially due to an RC time constant of the word and Bit line capacity determined. Here, for example, plays a so-called RAS-to-CAS delay (row-to-column delay, in German line-to-column delay), which describes the time that must elapse after the activation of a word line (activate) before a read command (read) may be sent, a role. Waiting time is taken into account by setting enough wait clocks (wait states) between data request and rating.

The intrinsic waiting time for error-free evaluation of functional memory cells lies within a narrow distribution, the fluctuation range of which depends on the individual fluctuation ranges of the evaluation duration, the RC times of BL and WL and the basic cell programming strength. Each cell of the cell array is therefore read (after eliminating all defective cells along wordlines and bitlines by redundancy replacement) with a defined (trimmed) set of operational parameters. the read voltage on the word line VGate and the reference voltage IRef in the evaluation amplifier. The more accurately the operating parameters for erasing / programming / reading the cell array are adjustable and the smaller the fluctuation range of the cell-to-cell fluctuation is, the more binary-coded memory states can be stored in a memory cell. In the case of a cell with a single rating level, this is referred to as a single level cell (so-called single level cell) with the storable states 0 and 1. In the case of multi-level cells (so-called multi-level cells), several evaluation levels can be used to determine 2, 3 - and multi-digit binary logic states store.

By means of error code correction using error correcting codes (ECC, for Error Correcting Code), individual, incorrectly stored or interpreted cell information can be consistently corrected.

A magnitude of a used ECC correction method determines how many erroneous bits can be detected and corrected. Typical are ECC methods that include 64 payload bit data and 8 ECC bit data on a 72 bit ECC word (where ECC word or ECC word denotes the combination of word data and ECC data) and correct single bit error (SBE) errors , Double Bit Error (DBE) for Double Bit Error.

In 4 and 5 The typical ECC correction performed by a Program Memory Unit (PMU) is shown schematically.

The ECC method can be applied to ECC word width bit line oriented. There may be several ECC words on a page.

In 6 different distributions of ECC words are shown on individual pages, the white areas (EW0 to EW7) each symbolizing a data area, the adjacent gray areas respectively the ECC belonging to the word. In view 660 For example, in a WL, a word including ECC is stored in view 662 two ECC words, in view 664 eight ECC words (EW0 to EW7 each with ECC), in view 666 also eight ECC words (on two sides controllable by the same word line, the identical words EW0 to EW3 with ECC), in view 668 four words EW0 to EW3 with ECC, spread across four pages.

In 7 By way of example, various possibilities for error, which in each case or in combination can impair a correct retrieval of ECC words are shown schematically: A word line driver error 742 , a faulty opening 744 the WL and a faulty via structuring 746 ,

If the transistors can no longer be turned on (i.e., driven open) by a WL failure, neither the payload nor the check data of all the pages associated with the WL can be read. The data along the WL can not be reconstructed due to multiple errors.

In order to also be able to recognize that a WL does not open to recognize faulty ECC words (for example, a failure / read signature of a 72-bit ECC word is shown, with 64 data bits and 8 ECC bits: Stuck @ 1ECCword: 0xFFFF_FFFF_FFFF_FFFF / 0xFF), a so-called Address ECC method is used. Generation and checking of the check bits in case of errors includes an address from which the data is read. In this way it can be ensured, inter alia on the basis of the ECC check, that the read ECC word was also read from the expected address.

If it is determined that an ECC word contains uncorrectable bit errors, the software / firmware must try to read the expected data without errors on a known redundant memory area. Does a WL include two ECC words, as exemplified in 6 in view 662 and in 8th in view 801 is shown, in which each of the words (EW0, EW1) within the word line once redundantly stored (as EW0 'or EW1'), both ECC words can not complement each other redundantly with respect to a WL failure.

Multiple occurring bit errors of adjacent physical bit lines can be addressed by means of skilful scramblings, ie, "distributed" to different ECC words of a WL so that a "cluster" of bit errors or a local / global BL-oriented failure will still always be SBE-correctable may,

In view 802 of the 8th is a redundant storage of an entire WL containing four ECC words (EW0 to EW3) represented in another WL with identical sequence (EW0 'to EW3'). Software-controlled reloading of erroneous ECC words may only make sense for data, not for an OpCode, because if an OpCode is affected, this can lead to a program execution error that can be uncorrectable. Therefore, it may be necessary to include the firmware already while reloading code.

However, accessing a WL in a sector can be problematic because of the physical driving process and evaluation history, which is relatively time consuming. Would you like for the entire memory 102 Provide redundant information storage, this would not only lead to an additional interconnection and test effort. It should also be noted that in case of an erroneous access further read attempts on other WLen lead to an additional read-out delay.

This could delay instruction code execution of instruction codes (OpCodes) to be loaded, which would be detrimental to the processing of time-critical real-time applications.

It would be conceivable that complete sectors or even flash modules 110 (or her cell field 102 ) are redundantly programmed to prevent the WL / Sector / Flash module failure. However, typically not all information in a program memory is equally significant and time-critical in code execution. In addition, the excessive storage requirements would be disadvantageous, because silicon area is precious, and a waste of space is sought.

Increasing the reliability (previously often provided) by correcting single bit errors for a more powerful ECC correction (e.g., correction of two-bit errors or more) might be possible. However, this would be a disadvantage that would have to be increased from home for an entire flash module, the ECC word width, and that in a first programming by the user from the outset in the full extent, if necessary, set and used. The increase in ECC correction power is achieved by paralleling BL paths for ECC and redundancy bits.

The power of the ECC is determined by an objective to avoid a failure error, including (eg computationally) estimating how high the expected single bit (or multiple bit) error rate will be at the end of the life cycle and how many bits can be statistically reconstructed must be to correct an ECC word error.

If the power is too low, you run the risk of having a failure during the life cycle. If the power is too high, space for silicon production has been wasted.

There are ways to provide a certain number of ECC bits for the correction and to use only a part of them initially. However, if the device fails, the ECC bit wide extension does not help, because the ECC bit information is stored in the program memory of the controller at the time of initial programming of the software, not during operation.

In various exemplary embodiments, a user can be provided with a possibility of individual multiple storage for a word line, whose data can be determined when reading back with increased WL fault tolerance with known read delay, without the user having to worry about the concept of fault-tolerant information distribution.

In various embodiments, even absolutely error-free to read data from the configuration sector (also referred to as config sector) are read and initialized during block boot and which must set the block configuration absolutely error-free, can be stored fault-tolerant or read. For example, in the config sector, encoded repair replacement instructions can be read with higher reliability than with the WL-wise BL correction capability.

In various embodiments, the block would be at least bootable in the case of Configsektorfehlern even with WL and multiple BL failure conditions.

In various exemplary embodiments, the config sector that can not be written by the user or parts of the config sector can also be protected by means of WL-redundant storage. The redundant storage may be factory set, including, for example, a reload instruction.

In various embodiments, extremely failure-critical WL programming can be minimized during operation and handled in an uncomplicated manner. Thus, it would be possible to counteract the programming failure of a defective WL which is to be expected in the case of a so-called EEPROM emulation in the wearout. With the EEPROM emulation, information is continuously stored in the DF at regular intervals, which should at least be read without errors. Conventionally, on the other hand, although it is intended to avoid non-programmability of a WL, read loss of written data can not be countered. It can also be attempted to store data redundantly several times if there is a read error.

In order to counter a WL error with several ECC words of a WL-redundantly stored information of a page, in various embodiments the error-free read ECC words are kept and the reading is continued on a page following the WL.

In various embodiments, a configuration of a redundant memory depth may be stored, for example, preconfigured in the config sector CFS. It may also be in the config sector where the individual word line substitutions are to be addressed. In other words, a redundancy table for redundancy storage with a recharge option can be stored in the config sector, as it were.

In such a replacement table, besides the physical address, the provided depth of the recharge option (in other words, the number of redundant data records) and the correction method to be used for this purpose could also be stored in a characteristic manner. In an extreme case, in the redundancy table with the reload option, two individual, non-contiguous individual WLs with different reloading depths and simultaneously different reload correction powers to be used can be displayed for the redundant programming and subsequent reloading.

In various embodiments, the user may himself after an error itself by means of an Opcode or by means of a special command sequence read.

In various embodiments, read access to information in the event of a fault with the other WLs may be continued by accessing a single linear WL address, to be redefined (in place of the usual read opcode), from the It is assumed that the next page contains the redundant information. In various embodiments, access may be by the user. The opcode may indicate and instruct to reload the data redundantly.

In various embodiments, read access to information in the event of a fault with the other WLs may be continued by using a special command sequence (Command Sequence, as is common for erasure, programming, or protection in Flash) to move from read the redundant WL storage. In various embodiments, access may be by the user. The command sequence may indicate that the data can be reloaded distributed.

In various embodiments, both in using the opcode and in using the instruction sequence, memory control, e.g. a microcontroller, e.g. an FSI to control access to the redundantly stored information or regulate.

In various embodiments, read access to information in the event of a fault with the other WLs may be continued by having a program counter automatically run by a memory controller, e.g. a microcontroller, e.g. an FSI for which reloading is directed to the corresponding pages if an uncorrectable error is found during initial reading.

In various embodiments, regardless of whether the redundant data is determined to be accessed by means of a particular instruction sequence or by the program counter, the reloading may be determined by the memory controller. In this case, details of reloading may be determined by the memory controller, e.g. how often and which pages from the memory controller, e.g. The FSI should be reloaded, as the contents must be reformatted, and when the reading of the information is completed successfully. In this time, a BUSY flag can be set or the wait states automatically extended in various embodiments.

In the simplest case, a sequence of WLen is read according to various embodiments in the event of an error, in which the information has been stored completely redundant. If, for example, 8 WLs are written redundantly, up to 7 complete WL failures could be compensated until the WL is completely correctly detected in the eighth read attempt.

A BL-oriented multi-bit failure across several WLen can be done in different Embodiments are met by the ECC words of the WL can be stored stored with a different assignment of the respective words to the bit lines, for example, stored cyclically.

In various embodiments, with each new read attempt of a successor WL, further error-free read ECC words may be added to a page buffer to be completed.

This approach may be comparable to simple 1: 1 reading in various embodiments, but may provide additional degrees of freedom in the BL-oriented correction capability.

In various embodiments, an extreme case that all WLen are subject to a non-correctable multiple error, and that it would not be possible to correctly ECC words from the sequence programming (ie the redundant, in their bit line assignment stored information information) to determine and ECC words to prevent complete, correct page content (also referred to as page content) from being prevented by reconstructing the ECC word signature with the aid of a check or correction signature stored in sequence pages.

In various embodiments, if only one ECC information is stored on a page, the redundantly stored information may be bit-wise interchanged on neighbor pages, e.g. cyclically reversed, programmed.

In various exemplary embodiments, if the advantage of block-wise correct paging sections is to be used for the compilation in addition to the main ECC marking for the correctness of the subblocks, additionally ECC (eg CRC, Cyclic Redundancy Check) signatures can be provided evaluable in the case of a 1ECC word page WL storage become. In this case, the ECC / CRC signature may be included in the page.

In various embodiments, the page carrying the payload data and ECC / CRC may be redundantly cyclically permutated sequentially bit by bit or bit-by-bit, and in one or more subsequent pages a signature derived for the bit line may be stored. In this way, a local BL signature can be retrieved, which in various embodiments can also contain the bit address in the check word.

In various embodiments, one or each WL driver may serve exactly one page. Then the page and all subsequent pages can be separate from the WL driver and be independent. A WL error would extend only locally to the WL or into coupling to a neighbor WL. In such a case, a pagewise redundant storage can be used.

In various embodiments, an or each WL driver may serve a plurality of pages that may be grouped into one sector. In such a case, all WLen of a memory area combined to a sector can be stored sector-redundant.

In a case that the sector redundancy is important for the possibility of correction, in various embodiments the information may be distributed among a plurality of sectors to be read out in parallel.

In various embodiments, the page-wise redundant and BL-ECC correctable information may be distributed across memory modules. Thus, all sector information may be decoupled from a memory module supply and drive. In other words, the information can also be retrievable in the event of a failure of a supply and / or activation of a memory module. Because of a high activation current, these distributed information stores, which can provide additional added security, can be associated with performance or performance degradation in addition to unavoidable space consumption.

In various embodiments, the "simple" BL-ECC protected memory may be optionally expandable by one way of holistically securing WL-BL correct storage of word lines.

In various embodiments, the optionally operable sub-storage area may be configurable to permit multiple storage, wherein at the same time the e.g. continuous linearity in the address space is maintained.

In various embodiments, the storage area of the program memory at an address space end may be divided into logically smaller sectors with the same physical size. Alternatively, the physical quantity may be or may be adapted to the fixed redundancy option to preserve the logical.

In various embodiments, the user may deposit in this program area his important security-relevant, WL-BL error-insensitive program kernels, which allow safe operation for elementally important controls via BL-ECC correction.

In various embodiments, completely factory-protected sectors may include, for example, configuration sectors or key sectors for security-relevant / trust-related data storage.

In various embodiments, downstream correction stages may be used in EEPROM applications where the data storage is knowingly stressed to its limit by erase programming and WL failures are likely or inexplicably provoked.

In various embodiments, the "simple" ECC tolerant read access (i.e., the read access that enables ECC kernel error correction) to that memory area may be replaced by the FSI with slower WL fault tolerant multi-read accesses. The power of the additional WL-BL correction can be configurable, and the CRC / ECC check can be carried out after compiling the data on all involved WLen afterwards.

In various embodiments, uncorrectable simple ECC-assisted read access may be treated so that it does not stop the flow, but informs about the success of the (downstream) correction.

In various embodiments, depending on the thickness of the optionally selected partially correct compilation of redundantly read WL information, an access speed reduction can be calculated as a lump sum. At least in the error correction case, a maximum occurring waiting time for the simple BL error tolerant access can be extended by a factor of additional WLen to be evaluated in various embodiments.

Since the checksum calculation and possibly the ECC correction in various embodiments can already be used when compiling the page information, in the exemplary embodiments the ECC calculation / checking can be carried out directly by means of the FSI during the page evaluation (and not by means of a program). Memory Unit PMU during data transmission).

In various embodiments, frequently-written read-write memories in sectors that may lead to WL failure can be completely protected by post-programming for anticipated degradation errors.

In various embodiments, a possibility is provided for responding to a word line oriented error associated with a loss of the programmed data content that can not be reconstructed by ECC.

In various embodiments, it may be possible to store particularly important information in dedicated memory areas redundantly and with adaptive ECC power. In this case, a thickness of the redundant word line storage can be determined adaptively by a user as required. In this way, page / WL data that is affected by WL failures, multiple bitline bit errors, or a combination of wordline and bitline errors can be read by combining multiple pages with adjusted correction power.

In various embodiments, the method may be applied to both volatile and nonvolatile memory cell arrays, but preferably to nonvolatile cell array memories, particularly of the flash type.

In various embodiments, a manner by which WL correction capability the memory is to be sectioned described and / or read may be selected by the user.

In various embodiments, isolated WLen can be secured with higher power by means of an integration of unused WL redundancies, without disturbing a linear address space of the WL addressing.

In various embodiments, redundant storage of WL information across pages, which individually provides for BL signature checking and correction capability by BL scrambling and ECC correction unit, may be provided.

In various embodiments, a block-wise (and optionally ECC word-wise) corrected readout of information that may have been compiled and reconstructed across pages may be provided.

In various embodiments, a way may be provided of defining storage areas (sectors) that enable multiple storage for recoverability of the data in the case of WL-oriented outages.

In various embodiments, a way of labeling individual pages for utilizing the redundancy feature may be provided to perform read-only on redundancy WLs in redundancy sectors. By reloading from a separate redundancy sector or redundancy WL area, the linear address space can be maintained despite the read-in option.

In various embodiments, maintaining the linear address space by providing decreasing smaller sectors at the end of the cell array (eg Pflash) or factory-wide for an entire cell array (configuration sector), or optionally downstream in the operation of the data flash (EEPROM emulation operation) become.

In various embodiments, a memory controller, e.g. a microcontroller, e.g. an FSI, a possibly necessary multiple access and the necessary physically necessary WL address jumps control.

In various embodiments, a memory controller, e.g. a microcontroller, e.g. an FSI, a logical WL memory depth regulate. In this case, WL addresses can sometimes no longer be physically reproducible 1: 1, but be understood as logical WL addresses depending on the memory redundancy design.

In various embodiments, a depth of the multiple storage can be adjustable by means of user configuration.

The depth of multiple storage may be different in different embodiments for different sectors, such as a first sector and a second sector.

For example, a user may be allowed to adjust the depth of reload during operation, for example, when he realizes that one memory area (e.g., data flash 0) should be operated with a higher post-load depth over a second memory area (e.g., data flash1) because signs of wear are already beginning to appear.

In various embodiments, an option of cyclic swap and checksum generation across pages may be adjustable in programming a page buffer to be written and a memory area that can be read in the same mode. The generation of a redundant page pattern can be initiated with a command sequence executed by the FSI.

In various embodiments, secure page reading (also known as page read) may be provided in EEPROM mode that can handle non-programmable WL error signatures in a simpler and more user-friendly manner. For example, a user does not need to worry about redundantly rewriting or interpreting the erroneous data.

In various embodiments, a documented register set may be provided to a user with which he may configure the memory area with optional WL-overlapping correction capability in the width.

The configuration of the option can be stored in various embodiments in the Config-Sector.

In various embodiments, a method of operating a memory device is provided. The memory device may include an array of a plurality of memory cells, a plurality of word lines; and a plurality of bit lines, wherein each word line is connected to a plurality of the memory cells, each bit line being connected to a plurality of the memory cells, and wherein each of the memory cells is drivable by means of a unique combination of one of the word lines and one of the bit lines. The method may comprise first storing a plurality of data elements forming a data record in the memory cells, wherein each data element of the plurality of data elements is stored in a respective memory cell of the plurality of memory cells such that the data elements of the data set are stored in memory cells be driven by a common first word line, so that there is a first assignment of the data elements to the bit lines, and a second storage of the plurality of data elements in the memory cells, each data element of the plurality of data elements in each case a separate memory cell from the A plurality of memory cells are stored as a first redundant data set such that the data elements of the data set are stored in memory cells driven by a common second wordline and in which the driving bitlines are the same as in FIG first storing, so that there is a second assignment of the data elements to the bit lines, wherein the first assignment is different from the second assignment.

In various embodiments, the method may further include storing check / correction information for checking and, if necessary, correcting the data elements.

In various embodiments, in the second association, each of the data elements may be associated with a different bitline than in the first association.

In various embodiments, in the second assignment, the plurality of data elements may be cyclically interchanged with respect to the first assignment.

In various exemplary embodiments, the method may further comprise a further one or more times further storing the plurality of data elements in each of its own memory cell of the plurality of memory cells as a further redundant data record such that the data elements are stored in memory cells that are shared by another Word line are driven and in which the driving bit lines are the same as in the first storage, so that there is a further assignment of the data elements to the bit lines, the further assignment is different from all previous assignments.

In various embodiments, the method may include erasing prior to the first store. The deletion may represent a second type of programming (also referred to as inverse programming). This allows a programming capability to be prepared.

In various embodiments, the method may further comprise reading the record stored at the first save, checking and possibly correcting the read data items based on the check / correct information in a case that the check indicates that at least one of the stored data items is uncorrectably erroneous , reading the first redundant data set, and checking and possibly correcting the data elements based on the check / correct information.

In various embodiments, the method may further comprise buffering the data elements read without error prior to reading the first redundant data set, in a case that checking the read first redundant data set indicates that at least one of the stored data elements is uncorrectably erroneous, checking whether from a combination of the error-free cached data elements in combination with error-free data elements of the first redundant data set, the error-free data set can be generated, and in a case that the error-free data set can be generated, generating the error-free data set.

In various embodiments, the method may further comprise, in a case that the error-free data set is not producible, repeatedly executing: caching the data elements read without error, reading the further redundant data set; Checking and possibly correcting the read data elements based on the check / correction information, and checking whether a combination of the error-free cached data elements in combination with error-free data elements of the further redundant data record an error-free data set can be generated until the error-free data set is generated or to one fixed maximum number of redundant data records is reached.

In various embodiments, the method may further comprise, prior to the second storing, setting a maximum number of redundant data sets by a user.

In various exemplary embodiments, the first storage can be carried out under a first address and the second storage can take place at an address directly following the first address.

In various embodiments, the second storage may be done in a dedicated sector designated for the second storage.

In various embodiments, a memory device is provided. The memory device may comprise a plurality of memory cells, which may be configured as an array of memory cells, which may be controllable by means of a plurality of word lines and a plurality of bit lines, wherein each word line may be connected to a plurality of the memory cells, each bit line a plurality of the memory cells may be connected, and each of the memory cells may be controllable by means of a unique combination of one of the word lines and one of the bit lines, wherein the memory device may be configured to perform the method according to various embodiments.

In various embodiments, the memory device may include a non-volatile memory.

In various embodiments, the memory device may comprise a memory of a group of memories, the group comprising a FLASH memory, an EEPROM, an RRAM, a CBRAM, a PCRAM and an MRAM.

In various embodiments, the plurality of data elements may comprise data elements from a configector.

In various embodiments, the storage device may include a first storage area for storing a first data set having a first maximum number of redundant data sets, and a second storage area for storing a second data set having a second maximum number of redundant data sets, wherein the second maximum number may be greater than the first maximum number.

In various embodiments, the memory device may further include a controller for controlling the storage of the data set according to various embodiments and for reading the data set according to various embodiments.

In various embodiments, the memory device according to various embodiments may further include a latch for latching the data elements read without error.

In various embodiments, the memory cell array may include a plurality of memory cell areas (sectors), with a size of the sectors increasing towards an end of the memory cell array.

In various embodiments, the memory device may include a first memory area for storing a first data set having a first number of redundant data sets and a second memory area for storing a second data set having a second number of redundant data sets, wherein the second number may be greater than the first number.

In various embodiments, the memory device may include a redundancy reload table stored in a config sector of the memory cell array that has an individually configurable or pre-configured in the config sector redundant data sets for at least a single WL, for a portion of a sector or for an entire sector.

In various embodiments, a reload correction method may be further determined in the redundancy reload table.

In various embodiments, factory-backed reloading of the factory pre-configured redundancy reload table may be provided to properly detect the WL or sector individual number of redundant data sets and reload correction methods assigned to the data sets.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

Show it

1A a schematic representation of a flash memory device;

1B a schematic representation of a time course of a cell stream of the flash memory device;

2 a schematic representation of a bit distribution within a sector;

3 a schematic representation of a division of a memory in sectors;

4 an illustration of an operation of a memory;

5 an illustration of a read at a memory;

6 a schematic representation of different types of data storage with ECCs;

7 an illustration of various exemplary error possibilities;

8th an illustration of additional conventional measures for an increased recovery probability of correct data;

9A to 9C schematic diagrams of distributions of redundant information on wordlines and restoration of correct information according to various embodiments;

10A and 10B schematic diagrams of distributions of redundant information on word lines according to various embodiments;

11A and 11B a comparison of a conventional read operation and a read operation according to various embodiments in a memory;

12A and 12B a comparison of a conventional write operation and a write operation according to various embodiments in a memory;

13 a schematic representation of a distribution of redundant information according to various embodiments on sectors of a memory;

14A and 14B schematic diagrams illustrating sector formatting to support redundant WL storage with adaptive correction capability according to various embodiments; and

15 a flowchart for a method of operating a memory device according to various embodiments.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "front", "rear", etc. is used with reference to the orientation of the described figure (s). Because components of embodiments can be positioned in a number of different orientations, the directional terminology is illustrative and is in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be understood that the features of the various exemplary embodiments described herein may be combined with each other unless specifically stated otherwise. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

As used herein, the terms "connected," "connected," and "coupled" are used to describe both direct and indirect connection, direct or indirect connection, and direct or indirect coupling. In the figures, identical or similar elements are provided with identical reference numerals, as appropriate.

9A to 9C show schematic representations 901 . 902 . 903 distributing redundant information to word lines WL and recovering the correct information according to various embodiments.

As in 9A can represent a cell field 102 a memory device, eg a volatile (volatile) or a non-volatile (non-volatile) memory device, eg a FLASH memory, an EEPROM, an RRAM, a CBRAM, a PCRAM, an MRAM, or any other suitable electronic memory device, eg semiconductor memory device, According to various embodiments, have a plurality of memory cells, which can be controlled by means of a plurality of word lines WL0, WL1, etc. and by means of a plurality of bit lines.

In this case, each word line can be connected to a plurality of the memory cells, each bit line can be connected to a plurality of the memory cells, and each of the memory cells can be controlled by means of a unique combination of one of the word lines and one of the bit lines. In other words, the plurality of memory cells form an array which can be controllable by means of the word and bit lines. An activation can (see eg 11B (View 1101 ) and 12B (View 1201 )) based on an address unique for each memory cell address by means of an address decoder 106 , a WL driver 104 and a BL driver 108 respectively.

In a plurality of the memory cells, which may be associated with the first word line WL0, data words (four by way of example here) EW0 to EW3 may be stored as data elements.

Each assigned ECC can be in areas adjacent to the word areas 994 be symbolized, wherein brighter represented ECC areas symbolize that the associated ECC word is error-free or at least correctable by means of the associated ECC code, darker areas symbolize that either the word or the ECC code are so buggy that the associated Word can not be corrected by means of the ECC. In 9A are exemplary the words error-free or at least correctable with areas 990 and 992 are marked.

The memory cells of the cell field 102 can also be controlled by means of bit lines, as for example in 11B (View 1101 ) and 12B (View 1201 ) is shown. The bit lines may run in the direction of an indicated BL path (in the direction of the arrow) in such a way that each of the memory cells can be driven by means of one of the word lines and one of the bit lines. In this case, each of the memory cells can be controlled by means of a unique combination of word line and bit line (see also eg 16 , View 1601 ).

In various embodiments, as in 9A is exemplified in memory cells which a common Word line from the plurality of word lines (here the word line WL0) are assigned to be stored as data elements four data words EW0 to EW3 (with their associated ECC codes). This can also be expressed herein as "four data words stored in the WL", "four data words stored along the WL", "the WL contains four data words", or equivalent phrases accordingly. This storage of the original data may also be referred to as first storage or first storage. Based on an assignment of the data elements to the plurality of bit lines, a first assignment may be determined.

In further data lines WL1, WL2, WL3, the same data words EW0, EW1, EW2, EW3 as in WL0 can be stored redundantly (with the same information content) as data elements, in each case with the associated ECC. This can also be referred to as second storage or second storage. Based on an assignment of the data elements to the plurality of bit lines in the second storage, a second allocation may be determined.

In this case, an assignment of the data elements (the data words) to the bit lines may be different for each of the redundant memories. For illustration, a bit line BL is shown, which is assigned the data word EW2 in the first assignment (in WL0), the data word EW3 in the second assignment (in WL1), and the data words EW0 and WL3 in further assignments EW1. The first and the second assignment can therefore be different. For example, as in the example in 9A The data words are stored cyclically interchanged (EW0, EW1, EW2, EW3 in WL0, EW1, EW2, EW3, EW0 in WL1, EW2, EW3, EW0, EW1 in WL0, EW3, EW0, EW1, EW2 in WL1). ,

In various embodiments, e.g. if the address of the data word is included in the formation of the ECC associated with the respective data word, the ECCs can be adapted to the changed addresses in the case of the redundant memories with regard to the data information.

In 9A . 9B and 9C For example, the fields of those ECC codes are marked darker, whose associated data words are uncorrectably erroneous, or which have an ECC error.

In 9A If all word lines and all bit lines are functional, however, uncorrectable errors are present in WL0, WL1, WL3, BL0, BL2 and BL3 for at least one data word (for every three data words).

In various embodiments, when reading the data words EW0 to EW3 stored along the WL0, it can be recognized that at least one of the data words (in this case three, namely EW0, EW2 and EW3) has at least one non-correctable error.

Then, in various embodiments, read access may be continued with the other WLs (here, e.g., WL1, WL2, WL3), e.g. by accessing, with a read-opcode to be redefined, a single linear WL address, which is assumed to contain the redundant information of the next page (here WL1). In various embodiments, access may be by the user.

In various embodiments, the read access to the information in the event of failure with the other WLs may be continued by using a special instruction sequence to extract from the redundant WL storage, e.g. in WL1, read. In various embodiments, access may be by the user.

In various embodiments, the read access to the information in the event of failure may be continued with the further WLen by a program counter automatically from a memory controller, e.g. a microcontroller (e.g., an FSI) for reloading to the appropriate pages.

In various embodiments, regardless of whether the redundant data is determined by means of a read opcode, by means of a command sequence or determined by the program counter, a memory controller is used 112 , eg a microcontroller (eg an FSI; 9A not shown, but see eg 11B . 12B , Views 1101 respectively. 1201 , in which 11B illustrates read access 12B the appropriate write), how often and which pages from the memory controller 112 should be reloaded, as the contents must be reformatted, and when the reading of the information completed successfully. During this time, in various embodiments, a BUSY flag can be set or wait-states can be automatically extended.

In the example off 9A would retrieve the correct content on the third read access (when reading WL2), because all data words stored in WL2 (in the order EW2, EW3, EW0 and EW1) are either correct or at least correctable by the associated ECC.

In 9B the same memory pattern is used as in 9A , Here is the error, however an entire WL (WL0, as indicated by the lightning bolt symbol). Again, the data, as well as related 9A described, by means of a read access to the redundantly stored data, retrieved correctly, for example from WL1, in which, as by means of the marker 992 is indicated, all data words are at least correct by means of the respective associated ECCs correctly retrieved.

In 9C the same memory pattern is used as in 9A , Here, the error may involve a plurality of bit lines (or associated evaluation amplifier circuits SA numbered 0 to 71, respectively) as indicated by the lightning symbol.

Here too, by means of a read access to the redundantly stored data, for example as in connection with 9A described, correct information can be retrieved.

Unlike in connection with 9A and 9B However, in this case the entire correct data content of WL0 can not be provided from the content of a single other redundant WL, because in the first and last data word of WL0 to WL3, for example, two bit lines may be disturbed (as illustrated by the lightning symbol), which means the example 1-bit correcting ECC is not correctable), the third data word may have a bit line error in the data word, which is also due to a faulty, the corresponding ECC bit line is also not correctable.

Here can, for example by means of memory control 112 , eg of the microcontroller, eg of the FSI, eg as in 11B (View 1101 ) is shown ( 12B (View 1201 after the read access, an ECC correction is made (and not, as usual, by means of the PMU, as in 11A (View 1100 ) respectively. 12A (View 1200 ). This makes it possible to buffer individual correct data words in an intermediate memory (eg the PMU), and thus to assemble the entire correct original data content (eg the data EW0 to EW3) by means of several consecutive read accesses.

In this case, the buffer (also referred to as buffer) can be filled with individual correct data words and subsequent read accesses are carried out until a rating, e.g. by means of the memory controller, e.g. of the microcontroller, e.g. FSI results in a complete complete record being created.

Alternatively or additionally, in various embodiments, prior to read access, e.g. when storing, a maximum number of read accesses (which may correspond, for example, a number of redundant memories) are set so that a maximum of the predetermined maximum number of read accesses can be made.

In various exemplary embodiments, for example when provision of the read data contents has to take place at a predetermined point in time, a waiting time (also referred to as wait state) can be set up which can be adapted such that the correctly read / compiled data contents only become available be provided after the time at which the data could be provided after processing the maximum number of read accesses, even if the correct data contents would already be available after fewer read accesses.

10A and 10B show schematic representations 1000 . 1001 distributions of redundant information for data words EW0 to EW3 on word lines WL0 to WL63 according to various embodiments. It can be a related to 9A to 9C explained principle of exchanged storage of data elements are applied.

In contrast to 9A to 9C can in 10A However, individual bits of the respective data words EW0 to EW3 form the data elements that are stored reversed during redundant storage (eg cyclically).

For each of the data words EW0 to EW3, a bit is marked in each of the illustrated word lines WL0 to WL63, which is in each case assigned to a common bit line.

In the embodiment 10A Thus, for example, bit No. 62 of bit line BL63 may be assigned in first word line WL0 from bit data EW0, bit No. 63 from data word EW0 in second word line WL1, bit number 0 from third word line WL2 Data word EW0, etc.

In various embodiments, for example, if the ECC is 1-bit error correcting and 2-bit error detecting, and, for example, the erroneous bits can be identified, the correctly read bits, similar to the example set forth above, can be pinned in the correctly read words, is written to the buffer, which is further filled with correctly read bits when reading the next word line. The reading can be continued with new word lines until all bits of all words have been read correctly, or until a predetermined maximum number of read accesses (which may correspond to a maximum number of redundant stores) has been reached.

In various embodiments, as in 10B illustrated, a word may be stored as a plurality of partial words TW. An assignment of the partial words to bit lines may be different for redundant memories in different word lines. Im in 10B For example, an exemplary bit line BL may, for example, be assigned to one bit of the partial word TW1 in the WL0, one bit of the TW2 in the WL1, one bit of the TW3 in the word line WL2 and one ECC of the partial words TW1, TW2 and TW3 in the WL3. That is, the ECC value in the fourth subword may have an ECC rating of the preceding subwords of the corresponding TW column.

In various embodiments, ECC calculation may be done over a larger WL range of greater thickness than just for a single one alone. For example, 4 × 64 bit and 24 bit ECC could also be stored with 3 × 64 bit and 1 × 64 ancillary ECC, or with 2 × 64 data and 2 × ancillary ECC in addition to the 24 regular ECC bits per 280 bit ECC word.

Also, when dividing words into subwords, as described above for the words and the bits, the correctly read or at least correctable subwords TW can be cached in a buffer before each new read access until all subwords have been read correctly, or until a fixed maximum number of read accesses. In this case, the subword ECC (e.g., TW_ECC1) may be formed over all the subwords TW of a column. In this case, the specified maximum number of read accesses can correspond to the number of redundant storages.

11A and 11B show a comparison of a conventional reading (in 11A ) and a read operation according to various embodiments at a memory (in 11B ).

Portions of the storage device, operations, etc., may be similar or identical to those discussed in connection with other embodiments.

In various embodiments, a memory controller 112 , eg an FSI, by means of an address decoder 106 the WL assigned to a given address by means of a WL driver 105 and drive the associated BL by means of a BL driver to output the information stored in the addressed memory cell to an evaluation amplifier SA and from there - uncorrected and possibly including ECC information - to the memory controller 112 ,

In various embodiments, by means of the memory controller 112 from the uncorrected data by means of the ECC information corrected data words EW0, EW1, etc. of the data record are generated and optionally, for example, if no completely correct record was read, at least already read correctly parts of the record in a cache, for example, part of the memory control 112 be or with the memory controller 112 be stored until a complete correct record is present. Such a process may be missing in a conventional read operation.

In various embodiments, the memory controller 112 , which is arranged to support a read (and a write) of redundantly stored data sets exchanged in different WLs, cause redundantly stored information to be retrieved if at least partially (uncorrectably) erroneously read data record is retrieved.

In various embodiments, a program counter can be set for such that when the program counter is incremented, the next read access automatically accesses a page with redundant information. Alternatively or additionally, a read opcode may be used which accesses a single linear WL address, which is assumed to contain the redundant data retrieved page. Furthermore, alternatively or additionally, a special command sequence (command sequence) can be used to allow the read access to the redundant data in the presence of an uncorrectable error in the already read data.

The redundantly stored data used in various embodiments as above, for example, in connection with 9A to 9C . 10A and 10B may be formed, for example, may be stored in adjacent word lines, in a redundant WL sector, or in a dedicated sector.

In various embodiments, the re-read access may occur so frequently until either a complete correct record is present or until a predetermined maximum number of read accesses has occurred.

The maximum number of read accesses may be or may be determined in various embodiments, eg by the user, that they are the Number of redundant memories corresponds. In embodiments, the maximum number may also be determined to be a numerical value less than the number of redundant memories, for example, to increase speed (eg, in a case of reading data associated with operation of the memory device or its associated Facilities are not critical).

In various embodiments, the read record may be from the memory controller 114 to the PMU 1110 where in some embodiments another ECC correction may be performed.

From the PMU the (possibly corrected a second time) record in various embodiments to a central processor 114 (the CPU) are passed.

12A and 12B FIG. 12 shows a comparison of a conventional write operation and a write operation according to various embodiments in a memory.

Here, the in 12B illustrated write operation according to various embodiments, essentially a reverse process to in 11B be shown reading. Portions of the storage device, operations, etc., may be similar or identical to those discussed in connection with other embodiments.

In various embodiments, a record of the PMU 1110 from the CPU 114 be or be provided. In the PMU test / correction information (eg in the form of an ECC) can be added to the data record. The ECC information record may be referred to as ECC words.

In various embodiments, the memory controller 112 the ECC words from the PMU 1110 retrieve, for example by means of a command sequence access, which may be or may be supported by a cache.

In various embodiments, the memory controller 112 the original data set, eg the ECC words, as usual (eg as in 12A shown).

In various embodiments, the memory controller 112 be set up to prepare the record for the redundant storage, for example, the data record as data words with one ECC per data word (such as in 9A to 9C shown) as data bits with associated ECC (which is shown in FIG 12B and eg in 10A is shown), or as subwords (such as in 10B shown).

For redundant storage, the record may be changed in its sequence in which it can be stored on a page, for example permuted, e.g. cyclically interrogated.

If, during the generation of the ECC information, an absolute (eg when the address is included) or a relative (eg with respect to the other data words) positioning of the data set or data elements can have an influence, these can be used to form the ECC information, eg by means of the memory controller 112 be taken into account.

By means of the address decoder 106 , the BL driver 108 and the WL driver 104 For example, the redundant data may then be stored in redundant storage (for associated redundant storage) word lines for redundant data storage, where the assignment of the pages may be as described above.

13 shows a schematic representation 1300 for distributing redundant information according to various embodiments to sectors of a memory.

A construction of the memory in 13 can be substantially similar to the one in 3 be shown memory.

However, the memory and the memory controller, e.g. the FSI, in various embodiments, may be configured such that a degree of redundancy may be configurable, for example, configurable by the user.

In other words, in various embodiments, a number of redundant storages, which may be performed as discussed above in connection with various embodiments, may be adjustable.

The number of redundant storages may be adjustable and / or changeable, for example, during manufacture of the memory device, during startup, or later during operation.

In this case, the number of redundant storages in different embodiments can be set sector by sector.

For example, a sector (in 13 exemplified for sector PS5) may be provided for a quadruple redundant storage. Illustrated is a storage of four ECC words EW0 to EW3, which are stored in each Word line of the redundant storage with respect to the bit lines are arranged cyclically shifted, but of course, any other explained herein in connection with various embodiments, assignment can be selected.

In such a sector with relatively high redundancy, for example, system-relevant program data or the like can be used. be saved or be.

For other sectors (here exemplary sector PS4), other stages of redundancy can be selected, for example a double-redundant storage (here too, the cyclically shifted storage in the redundant word line is shown as an example).

Alternatively or additionally, in various embodiments, sectors may be provided, for example, an in 13 a sector adjacent to DF0, which may contain reserved wordlines for redundant storage, and / or one or more sectors having a page data format with scalable redundancy (exemplified in FIG 13 represented as sector DF1).

In various embodiments, a user may be provided with a configuration option (eg, sector wise) to balance their backup and space requirements and tailor (e.g., specify) the degree of redundant storage (possibly sector wise).

In various embodiments, the memory may have sectors of decreasing size at one end of its cell array to allow for an adaptable and flexible degree of redundancy.

14A and 14B 10 are schematic diagrams illustrating sector formatting to support redundant WL storage with adaptive correction capability according to various embodiments.

This illustrates this in a view 1601 Example shown sector formatting for a 32 kbyte sector.

Each page can have 128 bytes, each wordline can have two pages, and each has 8 bytes of ECC words. Each word line can thus drive two pages with 16 ECC words each.

An associated addressable address range may be, for example, 0x0000 - 0x7FFF (e.g., 0x80 bytes / page, 0x100 bytes / WL, i.e. 256 pages, or 128 WLs in 32k bytes).

In view 1602 is illustrated a corresponding linear address space, wherein address elements A ₁₄ to A ₈ can address the 128 WLen, address elements A ₁₄ to A _7, the corresponding pages (ie address element A ₇ may be a so-called PageAddressSelector (a page selector)), and Address elements A ₆ to A ₀ may have intrapage addresses for the 128 bytes per page.

view 1603 illustrates the distribution of the data as ECC words on the two respective pages of the total of 128 word lines.

In 16B 1 illustrates that, in a redundant WL storage according to various embodiments, a coupling of word lines can be made.

In other words, in various embodiments, only a portion of a (linear) address range A ₁₄ to A _{0 may be} addressable for independent data storage (eg, the range 1676 in view 1605 ), the rest of the illustrated address range can then be used, for example, for eightfold redundant storage of the data according to various embodiments. Accordingly, upon release of an address range 1674 the remainder of the address range for a quadruple redundant storage and a release of an address range 1672 the remainder of the address range for dual redundant storage according to various embodiments.

In order to enable redundant storage in independent word lines within the address range, a so-called "page scrambling" can be used, in which, according to various embodiments, a data content, eg a redundant storage of a data record, externally a linearly assigned address can be assigned, but a physical storage can be stored by means of an internally applied page addressing in a page, which is controlled by a different word line. This is an example in view 1604 illustrated.

17 shows a flowchart 1800 for a method of operating a memory device according to various embodiments.

In various embodiments, a method of operating a memory device is provided. In this case, the memory device may comprise an array of a plurality of memory cells, a plurality of word lines; and a plurality of bit lines, each word line being connectable to a plurality of the memory cells, each bit line being connectable to a plurality of the memory cells, and each of the memory cells being controllable by means of a unique combination of one of the word lines and one of the bit lines can be.

In various embodiments, the method may include first storing a plurality of data elements forming a data set in the memory cells, wherein each data element of the plurality of data elements is stored in each of a separate memory cell of the plurality of memory cells such that the data elements of the data set are stored in memory cells, which are driven by a common first word line, so that there is a first assignment of the data elements to the bit lines (in 1710 a second storage of the plurality of data elements in the memory cells, wherein each data element of the plurality of data elements is stored in a respective memory cell of the plurality of memory cells as a first redundant data set such that the data elements of the data set are stored in memory cells, which are driven by a common second word line and in which the driving bit lines are the same as in the first storage, resulting in a second assignment of the data elements to the bit lines, wherein the first assignment is different from the second assignment (in 1720 ).

Further embodiments of the method may be described in connection with the device and vice versa.

Claims (20)

 A method of operating a memory device, the memory device comprising: An array of a plurality of memory cells, • a plurality of word lines; and • a plurality of bit lines; Wherein each word line is connected to a plurality of the memory cells; Wherein each bit line is connected to a plurality of the memory cells; and Wherein each of the memory cells is controllable by means of a unique combination of one of the word lines and one of the bit lines; the method comprising: • first storing a plurality of data elements forming a data record in the memory cells, wherein each data element of the plurality of data elements is stored in each case a separate memory cell of the plurality of memory cells such that the data elements of the data set are stored in memory cells that from a common first word line are driven, so that there is a first assignment of the data elements to the bit lines; and Second storage of the plurality of data elements in the memory cells, wherein each data element of the plurality of data elements is stored in each of its own memory cell of the plurality of memory cells as a first redundant data set such that the data elements of the data set are stored in memory cells which are stored in memory cells common second word line are driven and in which the driving bit lines are the same as in the first storage, so that there is a second assignment of the data elements to the bit lines; • where the first assignment differs from the second assignment.  The method of claim 1, further comprising: Storing check / correction information for checking and, if necessary, correcting the data elements.  Method according to claim 1 or 2, wherein in the second assignment each of the data elements is assigned to a different bit line than in the first assignment.  Method according to one of claims 1 to 3, wherein in the second assignment, the plurality of data elements are cyclically reversed to the first assignment associated.  The method of any one of claims 1 to 4, further comprising: one or more times carrying out a further storing of the plurality of data elements in the memory cells, wherein each data element of the plurality of data elements is stored in each case a separate memory cell of the plurality of memory cells as another redundant data record such that the data elements of the data set stored in memory cells be driven by a common further word line and in which the driving bit lines are the same as in the first storage, so that there is a further assignment of the data elements to the bit lines; the further allocation differs from all previous assignments. The method of one of claims 2 to 5, further comprising: reading the record stored in the first save; Checking and possibly correcting the read data elements based on the check / correction information; in a case that the checking reveals that at least one of the stored data items is uncorrectably erroneous, reading the first redundant data set; and checking and possibly correcting the data elements based on the check / correction information.  The method of claim 6, further comprising: Caching the error-free read data elements before reading the first redundant data set; and in a case that the checking of the read first redundant data set reveals that at least one of the stored data elements is uncorrectably erroneous, checking whether the error-free data set can be generated from a combination of the error-free buffered data elements in combination with error-free data elements of the first redundant data record; and in a case that the error-free data set can be generated, generating the error-free data record.  The method of claim 7, further comprising: in a case that the error-free record can not be generated, repeated execution of: Buffering of the correctly read data elements; Reading the further redundant data record; Checking and possibly correcting the read data elements based on the check / correction information; and Check whether a fault-free data record can be generated from a combination of the error-free buffered data elements in combination with error-free data elements of the further redundant data record, until the error-free data record is generated or until a defined maximum number of redundant data records has been reached.  The method of any one of claims 1 to 8, further comprising: prior to the second save, setting a number of redundant records by a user.  Method according to one of claims 1 to 9, wherein the first storage takes place under a first address and the second storage at a first address directly following the first address.  A method according to any one of claims 1 to 10, wherein the second storage is done in a dedicated sector predetermined for the second storage.  Storage device comprising: An array of a plurality of memory cells, • a plurality of word lines; • a plurality of bit lines; and • a memory controller; Wherein each word line is connected to a plurality of the memory cells; Wherein each bit line is connected to a plurality of the memory cells; and Wherein each of the memory cells is controllable by means of a unique combination of one of the word lines and one of the bit lines; and Wherein the memory controller is configured to carry out the method according to one of claims 1 to 10.  The memory device of claim 12, wherein the memory device comprises a non-volatile memory.  The memory device of claim 12, wherein the memory device comprises a memory of a group of memories, the group comprising: a FLASH memory; an EEPROM; an RRAM; a CBRAM; a PCRAM; and an MRAM.  The storage device of any one of claims 12 to 14, further comprising: a buffer for buffering the data elements read without error according to one of claims 5 to 9.  The memory device of claim 12, wherein the memory cell array has a plurality of sectors, wherein a size of the sectors increases toward an end of the memory cell array.  The storage device of any one of claims 12 to 16, comprising: a first storage area for storing a first data set having a first number of redundant data sets; and a second storage area for storing a second data set with a second number of redundant data sets, wherein the second number is greater than the first number.  The storage device of any one of claims 12 to 17, further comprising: a redundancy reload table stored in a config sector of the memory cell array, which has an individually configurable or pre-configured in the config sector number of redundant data sets for at least a single word line, for a part of a sector or for a whole sector. The memory device of claim 18, wherein a reload correction method is further defined in the redundancy reload table.  The memory device of claim 18 or 19, wherein factory-backed reloading of the factory pre-configured redundancy reload table is provided for correctly detecting the WL or sector individual number of redundant data sets and reload correction methods assigned to the data sets.

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