DE102016112291A1 - Optoelectronic semiconductor chip and method for producing an optoelectronic semiconductor chip - Google Patents

Abstract

An optoelectronic semiconductor chip (100) and a corresponding production method are specified. The semiconductor chip (100) comprises a semiconductor layer stack (10); a metallic contact layer (21) disposed on the semiconductor layer stack (10); a metallic core (25) arranged on a side of the contact layer (21) remote from the semiconductor layer stack (10) has a cover surface on a side facing away from the semiconductor layer stack (10) and side surfaces extending from the cover surface to the semiconductor layer stack (10); and a metallic shell (23) encapsulating the core (25) covering the top surface and side surfaces of the core (25). The contact layer (21), the core (25) and the jacket (23) form a contact web (20) for electrical contacting of the semiconductor layer stack (10).

Description

The invention relates to an optoelectronic semiconductor chip and to a method for producing an optoelectronic semiconductor chip.

In the case of optoelectronic semiconductor chips, current bridges are used for contacting, which, for example, consist of gold and can have a layer thickness of up to 3.25 μm. In the case of radiation-emitting semiconductor chips in particular, effects such as a reduction in the brightness and a shift in the color locus can occur due to absorption on a surface of the current ridge. In addition, the cost of a power surge is a significant contribution to the total cost of an optoelectronic semiconductor chip.

The invention has for its object to provide an optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip, or contributes to circumvent the aforementioned problems. In particular, an optoelectronic semiconductor chip is to be specified which can be produced inexpensively and is distinguished by improved emission efficiency.

These objects are achieved by the subject matter of the independent claims. Advantageous embodiments and further developments of the invention are characterized in the subclaims.

According to a first aspect, the invention relates to an optoelectronic semiconductor chip. The optoelectronic semiconductor chip can be, for example, light-emitting diode chips or photodiode chips.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a semiconductor layer stack. The semiconductor layer stack may include, for example, semiconductor layers of different types and an active layer for generating or detecting electromagnetic radiation.

The semiconductor layers of the semiconductor chip are preferably based on a III-V compound semiconductor material. The semiconductor material is preferably a nitride compound semiconductor material such as Al _n In _{1 nm} Ga _m N or else a phosphide compound semiconductor material such as Al _n In _{1 nm} Ga _m P, where 0 ≦ n ≦ 1, 0 ≦ m ≤ 1 and n + m ≤ 1. Likewise, the semiconductor material may be Al _x Ga _1-x As with 0 ≤ x ≤ 1. In this case, the semiconductor layer sequence may comprise dopants and additional constituents. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, that is to say Al, As, Ga, In, N or P, are indicated, even if these may be partially replaced and / or supplemented by small amounts of further substances.

In particular, the semiconductor layer sequence has a main extension direction, which is also referred to below as the lateral direction. A direction oblique or perpendicular to the lateral direction is also referred to below as the vertical direction. The layers of the semiconductor layer sequence are arranged one above the other, in particular in the vertical direction.

That one layer is arranged on or above another layer denotes here and below that the layer is arranged directly or indirectly in electrical and / or mechanical contact with the other layer. In the case of indirect contact, further layers or further elements may be arranged at least in regions between the said layers.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a metallic contact layer arranged on the semiconductor layer stack.

The metallic contact layer is advantageously designed for making electrical contact with a p-doped or n-doped semiconductor layer. In particular, the metallic contact layer is designed to be electrically conductive and directly coupled to a first semiconductor layer of the semiconductor layer stack, that is to say arranged in direct contact therewith. Alternatively, the metallic contact layer is indirectly coupled to the first semiconductor layer. The metallic contact layer is formed, for example, for n-contacting the optoelectronic semiconductor chip, wherein the metallic contact layer advantageously directly contacts the n-doped semiconductor layer. The metallic contact layer is alternatively formed, for example, for p-contacting the optoelectronic semiconductor chip, wherein a current spreading layer is advantageously arranged between the metallic contact layer and the p-doped semiconductor layer.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a metallic core arranged on a side of the metallic contact layer facing away from the semiconductor layer stack. The metallic core has a cover surface on a side facing away from the semiconductor layer stack, and side surfaces extending from the cover surface toward the semiconductor layer stack.

The metallic core is advantageously formed electrically conductive and with the metallic Contact layer directly or at least indirectly coupled. In particular, the metallic core may consist of a material that differs from a material of the metallic contact layer. Side surfaces of the metallic core are understood to be those surfaces of the metallic core which delimit the latter in the lateral direction.

In at least one embodiment according to the first aspect, the semiconductor chip includes a metallic shell encapsulating the metallic core covering the top surface and the side surfaces of the metallic core.

The metallic shell is advantageously formed electrically conductive. In particular, the metallic shell is directly coupled to the metallic core. Advantageously, the metallic sheath is designed to protect the metallic core from oxidation. In particular, the metallic core is made of a material different from a material of the metallic core.

An encapsulation of the metallic core is understood to mean an oxidation-inhibiting sealing of its surfaces. In the encapsulation by the metallic shell more than 90%, preferably more than 95% of the top surface and the side surfaces of the metallic core are covered in particular.

In at least one embodiment according to the first aspect, the metallic contact layer, the metallic core and the metallic shell form a contact web for electrical contacting of the semiconductor layer stack.

The semiconductor chip may, for example, have one or more such contact webs. A contact bar can also be referred to as a power bar.

In at least one embodiment according to the first aspect, an optoelectronic semiconductor chip is specified which comprises a semiconductor layer stack, a metallic contact layer arranged on the semiconductor layer stack, and a metallic core arranged on a side of the metallic contact layer remote from the semiconductor layer stack. The metallic core has a cover surface on a side facing away from the semiconductor layer stack and side surfaces extending from the cover surface to the semiconductor layer stack. Moreover, the semiconductor chip comprises a metal shell encapsulating the metallic core. The metallic shell covers the top surface and the side surfaces of the metallic core. The metallic contact layer, the metallic core and the metallic shell form a contact land for electrical contacting of the semiconductor layer stack.

Advantageously, the contact web allows a targeted adaptation of the specific electrical resistance, in particular a reduction of this compared to a contact web, which consists only of a single material such as gold. As a result, a cross-section of the contact web in the lateral direction can be reduced and thus advantageously an absorbent surface of the contact web with respect to a purely golden contact web can be reduced. Alternatively, a voltage contribution can also be reduced in the case of, for example, the same cross section of the contact web in the lateral direction with respect to a purely gold contact web. In addition, due to the reduced electrical resistivity and / or metallic sheath, electromigration can be prevented.

The contact web described also allows a targeted adaptation of its reflection and / or absorption coefficient compared to a purely golden contact web. In this way, an emission efficiency of the semiconductor chip can advantageously be increased and / or a shift of the color location can be avoided.

In at least one embodiment according to the first aspect, the metallic core comprises or consists of silver and / or copper. A semiconductor chip with such a core can be produced in a particularly cost-effective manner with regard to a semiconductor chip with a purely gold contact land. In addition, this can be lowered, the specific electrical resistance of the contact land. Thus, at 20 ° C. for gold, it is about 2.44 × 10 ^-8 Ωm, while for silver and copper it is only 1.59 × 10 ^-8 Ωm or 1.68 × 10 ^-8 Ωm. As a result, with the same cross-sectional area in the lateral direction, the voltage drop at the current webs and thus the power loss resulting therefrom can be reduced, or with the same voltage drop, the cross-sectional area and thus a radiation-absorbing metal surface can be reduced. Further, since electromigration causes ion flux to linearly depend on resistivity, the use of silver or copper as the material for the core can help reduce electromigration.

In at least one embodiment according to the first aspect, the metallic sheath comprises or consists of platinum and / or palladium and / or rhodium and / or gold.

In particular, the metallic sheath is designed to prevent oxidation of the core. For example, from a metallic core Silver and / or copper can be advantageously prevented by migrating water-soluble silver (I) oxide or copper (II) oxide in the electric field. By way of example, in the case of a metallic core of copper, a shell formed of palladium can contribute to a significant increase in the service life of the optoelectronic semiconductor chip.

In at least one embodiment according to the first aspect of the metallic shell of platinum, palladium or rhodium is formed. In contrast to gold, whose reflection coefficient massively breaks down at a wavelength below 550 nm, these materials have a nearly constant reflection coefficient over a wavelength range between 400 nm and 750 nm, whereby a substantially wavelength-independent absorption coefficient can be achieved, thus contributing to a shift in the Color places to avoid. The total absorbed at the side surfaces and the surface of the contact pad light is influenced by the wavelength distribution in the semiconductor chip, so that a decrease in brightness in a trained example of rhodium metallic sheath, which has a comparatively high reflection coefficient, be reduced in terms of a purely golden contact web advantageous can.

In at least one embodiment according to the first aspect, the metallic shell covers a side of the metallic core facing the semiconductor layer stack. Advantageously, this encapsulation allows particularly effective protection of the metallic core from oxidation.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a barrier layer arranged on the side of the metallic contact layer remote from the semiconductor layer stack. The barrier layer is in particular designed to prevent intermetallic mixtures between the metallic contact layer and the metallic shell. In particular, in the case where the metallic shell is formed of gold and the metallic contact layer comprises or consists of aluminum, intermetallic compounds such as e.g. the so-called purple plague can be prevented. The barrier layer comprises, for example, titanium or platinum or consists thereof.

In at least one embodiment according to the first aspect, the metallic contact layer comprises or consists of titanium and / or chromium and / or aluminum and / or copper and / or molybdenum and / or nickel and / or silver. In particular, a use of aluminum or aluminum-copper as the contact layer is in this case both in a semiconductor chip with gold-containing sheath and barrier layer conceivable, as well as in the case of a semiconductor chip with a gold-free sheath, which has no barrier layer or only one formed with a comparatively small layer thickness barrier layer.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a gold terminating layer arranged on a top surface of the metallic shell. This advantageously makes possible a simple contacting of the semiconductor chip by means of bonding wire. In particular, the terminating layer in this context may have a surface suitable for a bonding process with a gold wire.

In addition, gold advantageously has a high reflection coefficient for wavelengths greater than 550 nm, so that, for example, light can be reflected through the terminating layer, which has been converted by means of a conversion layer in the potting of the semiconductor chip and thrown back onto the semiconductor chip.

A cover surface of the metallic shell is understood to mean a side of the metallic shell which faces away from the semiconductor layer stack in the vertical direction. In at least one embodiment according to the first aspect, a thickness of the final layer is between 100 nm and 2000 nm.

In particular, the layer thickness of the outer layer is less than 3250 nm, for example less than 2000 nm, preferably less than 1200 nm, particularly preferably less than 500 nm. Advantageously, material costs can be saved by the low layer thickness.

In at least one embodiment according to the first aspect, the metallic core has a layer thickness that is greater than or equal to the layer thickness of the terminal layer of the metallic core. By a metallic core with a relatively large layer thickness, especially if it is formed of silver and / or copper, the electrical resistance of the contact land with respect to a purely golden contact web can be reduced with advantage.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a sapphire substrate, a SiC substrate or a GaN substrate. The semiconductor chip is advantageously a volume emitter. In other words, in contrast to a surface radiator (thin-film component), such a semiconductor chip emits light on all sides and in particular also over the substrate volume. Conveniently, the substrate may be transparent such that light is at least partially through the transparent substrate can be emitted. Transparent substrates are, for example, SiC or sapphire or GaN.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a first semiconductor layer, a second semiconductor layer and an active layer arranged between the first and second semiconductor layer.

The first semiconductor layer and the second semiconductor layer each denote semiconductor layers of different types and may each comprise one or more n-doped or p-doped semiconductor layers. In the case of the semiconductor layer stack, either the n-doped or the p-doped semiconductor layer advantageously forms an emission side of the semiconductor layer stack or of the semiconductor chip.

The contact web of the semiconductor chip is used in particular for the electrical contacting of the first semiconductor layer. In addition, for contacting the second semiconductor layer, the semiconductor chip can additionally have a bonding pad, an external contact point or one or more analogously formed contact webs.

In at least one embodiment according to the first aspect, the active layer is provided for generating or detecting electromagnetic radiation. The active layer may, for example, be in the form of a double heterostructure, a single quantum well structure or a multiple quantum well structure.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a conversion layer arranged on a side of the first semiconductor layer facing away from the second semiconductor layer. The conversion layer can, for example, be incorporated into an encapsulation or encapsulation of the semiconductor chip. For example, the active layer generates blue light, which is transmitted through the first semiconductor layer and at least partially converted in the encapsulation by the conversion layer.

In at least one embodiment according to the first aspect, the semiconductor chip comprises an electrically conductive current spreading layer. The electrically conductive layer is advantageously designed for making electrical contact with a p-doped or n-doped semiconductor layer. The electrically conductive layer may cover a comparatively large proportion of the corresponding semiconductor layer for current spreading.

The current spreading layer is formed, for example, for p-contacting the optoelectronic semiconductor chip, wherein it advantageously directly contacts the p-doped semiconductor layer.

The current spreading layer may be transparent. In particular, it is permeable to the emitted radiation. The current spreading layer preferably contains a transparent, conductive oxide (TCO) oxide, such as ITO.

Transparent, electrically conductive oxides (TCO) are transparent, electrically conductive materials, usually metal oxides, such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, indium tin oxide (ITO) or aluminum zinc oxide (AZO) or copper oxide. In addition to binary metal oxygen compounds such as ZnO, SnO2 or In2O3 also include ternary metal oxygen compounds such as Zn2SnO4, CdSnO3, ZnSnO3, MgIn2O4, GaInO3, Zn2In2O5 or In4Sn3O12 or mixtures of different transparent, conductive oxides to the group of TCOs. Furthermore, the TCOs do not necessarily correspond to a stoichiometric composition and may also be p- or n-doped.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a passivation layer arranged on one side of the second semiconductor layer facing the first semiconductor layer.

The mirror layer advantageously comprises an electrically insulating material. Moreover, the mirror layer may comprise a reflective material, for example for reducing the coupling-out of radiation. As a result, an intensity of the radiated radiation can advantageously be increased at a radiating surface of the semiconductor chip provided for this purpose.

The mirror layer comprises, for example, at least one of the materials Al 2 O 3, TaO 5, ZrO 2, ZnO, SiN x, SiO x N y, SiO 2, TiO 2, ZrO 2, HfO 2, Nb 2 O 5 or MgF 2 or consists thereof. The passivation layer can be a reflection-enhancing layer and advantageously has one or more dielectric layers which have the highest possible reflection in the region of the emission spectrum of the active layer, in particular at a dominant wavelength and a dominant angle of the emitted radiation. In particular, the passivation layer may be formed as a dielectric Bragg mirror (DBR).

Contacting of the first semiconductor layer by means of the contact web can be effected, for example, by a passage opening in the passivation layer, through which material of the contact web extends. Alternatively, the Passivation layer extend laterally over the first semiconductor layer, for example, only in a region of the contact web, wherein contacting of the first semiconductor layer can then take place by means of a current spreading layer, which is arranged between the contact web and the passivation layer and laterally from the contact web to an uncovered by the passivation layer Surface of the first semiconductor layer extends.

In at least one embodiment according to the first aspect, the semiconductor chip comprises a core-encapsulating passivation covering the top surface and the side surfaces of the core and having two or more dielectrics. The passivation can be arranged in particular on an outer surface of the metallic shell.

For example, the passivation layer comprises or consists of two or more of the materials Al 2 O 3, TaO 5, ZrO 2, SiN x, SiO x N y, SiO 2, TiO 2, ZrO 2, HfO 2, Nb 2 O 5 or MgF 2. In particular, the passivation layer is formed moisture-proof. This advantageously contributes to a particularly long service life of the optoelectronic semiconductor chip. In particular, fault tolerances can be compensated in the encapsulation of the core by means of the metallic shell. By way of example, the passivation layer has a moist, dense layer of aluminum oxide facing the jacket and a terminating layer of silicon oxide facing away from the jacket.

In at least one embodiment according to the first aspect, the metallic shell completely covers the top surface and the side surfaces of the metallic core.

According to a second aspect, the invention relates to a method for producing an optoelectronic semiconductor chip. In the method, a semiconductor layer stack is provided and a metallic contact layer is deposited on the semiconductor layer stack. Furthermore, a metallic core is applied to a side of the metallic contact layer facing away from the semiconductor layer stack, which has a cover surface on a side facing away from the semiconductor layer stack and side surfaces extending from the cover surface to the semiconductor layer stack. Finally, a metallic shell encapsulating the metallic core is applied such that the top surface and side surfaces of the metallic core are covered. The metallic contact layer, the metallic core and the metallic shell in this case form a contact web for electrical contacting of the semiconductor layer stack.

Preferably, the optoelectronic semiconductor chip according to the first aspect is produced by the method according to the second aspect. That is, all features disclosed for the method are also disclosed for the optoelectronic semiconductor chip and vice versa.

In at least one embodiment according to the second aspect, a structured mask is applied to the side of the first semiconductor layer facing away from the second semiconductor layer prior to the application of the metallic contact layer.

For example, the mask comprises photoresist, silicon dioxide or silicon nitride.

In at least one embodiment according to the second aspect, material of the metallic contact layer, the metallic core, the metallic cladding and the terminating layer are respectively vapor-deposited. The application of the layers by means of vapor deposition is advantageously characterized in that they can be applied in a structured manner with a high degree of accuracy, for example by means of a lithography method.

In at least one embodiment according to the second aspect, material of the metallic shell is vapor deposited using spreading gas. Advantageously, this allows a sufficient encapsulation of the metallic core also of its side surfaces.

Further advantages, advantageous embodiments and developments emerge from the embodiments described below in conjunction with the figures.

Show it:

1a - 1f Method steps for producing an optoelectronic semiconductor chip according to a first exemplary embodiment, illustrated in a schematic sectional view,

2 A second embodiment of the optoelectronic semiconductor chip in a schematic sectional view,

3 wavelength-dependent reflection coefficients of different contact web materials,

4 A third embodiment of the optoelectronic semiconductor chip in a schematic sectional view,

5 A fourth embodiment of the optoelectronic semiconductor chip in a schematic sectional view.

Identical or equivalent elements are in the figures each with the same reference numerals Mistake. The components shown in the figures and the size ratios of the components with each other are not to be regarded as true to scale.

1a shows an optoelectronic semiconductor chip 100 with a semiconductor layer stack 10 comprising a first semiconductor layer 11 , a second semiconductor layer 17 and an active layer disposed between the semiconductor layers 19 , In the first and second semiconductor layer 11 . 17 are semiconductor layers of different types. In this embodiment, the first semiconductor layer is 11 around p-doped GaN and in the second semiconductor layer 17 around n-doped GaN.

The semiconductor layer stack 10 is advantageous on a substrate 40 arranged, wherein, for example, the n-doped second semiconductor layer 17 this is facing. At the substrate 40 it may be advantageous to a sapphire substrate, wherein the semiconductor chip 100 can be designed as a volume emitter.

When manufacturing the semiconductor chip 100 According to the first embodiment, first a structured mask 50 on the p-doped semiconductor layer 11 applied. The textured mask 50 Advantageously comprises photoresist, for example a negative varnish. The structuring of the mask 50 will be advantageous for a subsequent formation of one or more contact webs 20 (please refer 1f ).

In a subsequent process step, a metallic contact layer 21 by means of the structured mask 50 in a predetermined area on the first semiconductor layer 11 deposited, for example by vapor deposition. The contact layer 21 is formed in this embodiment of titanium or chromium.

1b shows the semiconductor chip 100 in a subsequent process step. For the sake of simplicity, only the first semiconductor layer is hereafter 11 the semiconductor layer sequence 10 shown. In the illustrated method step, material of a metallic shell (cf. 1d ) on the contact layer 21 deposited. For example, a resulting layer 23a of the jacket produced by vapor deposition. The layer 23a is formed in this embodiment of a noble metal such as platinum, palladium or rhodium. Alternatively, the layer is also conceivable 23a made of gold.

In a subsequent process step ( 1c ) becomes a metallic core 25 on the layer 23a applied. The core 25 is used for electricity transport and is made of silver or copper.

Subsequently ( 1d ) becomes the core 25 with further material of the aforementioned coat 23 encapsulated, leaving the core 25 is completely covered on its side surfaces as well as on its top. This is the coat 23 For example, produced by vapor deposition using litter gas.

In an optional, subsequent process step ( 1e ) becomes a thin topcoat 29 of gold on the coat 23 deposited, which provides a suitable surface for a bonding process with a gold wire.

Finally ( 1f ) can be the structured mask 50 are removed, and the semiconductor chip 100 For example, be provided with a potting and / or a conversion layer (not shown). The contact layer 21 , the core 25 , the coat 23 as well as the finishing layer 29 form a contact bridge 20 for electrically contacting the semiconductor layer sequence 10 , in particular the first semiconductor layer 11 , In an advantageous manner, no mixing of material of the final layer takes place at the temperatures occurring in the production process 29 and the coat 23 he follows.

2 shows a second embodiment of an optoelectronic semiconductor chip 100 , which can be made essentially analogous to the first embodiment.

The semiconductor chip 100 According to the second embodiment differs from the first embodiment in that the contact layer 21 made of aluminum or aluminum-copper. As in 2 the layer can also be shown 23a (see. 1b and 1c ) through a barrier layer 27 be replaced from titanium and / or platinum. Alternative to the illustration in 2 can the barrier layer 27 be formed with reduced layer thickness or completely eliminated, so that the core 25 directly on the contact layer 21 made of aluminum or aluminum-copper. As material for the coat 23 is suitable in this case, in particular rhodium, platinum or palladium.

The side surfaces of the contact bridge 20 be through material of the coat 23 formed and can in the blue wavelength range at about 450nm have a higher reflection coefficient Γ than gold (see 3 ), which in particular for at a shallow angle to a contact web 20 facing surface of the semiconductor layer sequence 10 leaking light L1 is advantageous. The golden finishing layer 29 on the other hand has a high reflection coefficient Γ for wavelengths above 550 nm, which is advantageous for potting the semiconductor chip 100 converted and onto the semiconductor chip 100 reflected light L2 is.

4 shows a third embodiment of an optoelectronic semiconductor chip 100 , In contrast to the two previous embodiments, the first semiconductor layer is 11 around p-doped GaN and n-doped GaN in the second semiconductor layer (not shown). In addition, the semiconductor chip 100 in this embodiment, an electrically conductive current spreading layer 13 on, which is the first semiconductor layer 11 at least partially covered. The current spreading layer 13 preferably contains a transparent, conductive oxide (TCO Transparent Conductive Oxide), such as ITO.

Analogous to the second embodiment, in this embodiment, the layer 23a or the barrier layer 27 completely eliminated, leaving the core 25 directly on the contact layer 21 is arranged. The contact layer 21 is formed in this embodiment of aluminum or aluminum-copper.

In addition, the semiconductor chip 100 a mirror layer 15 which can also be referred to as "p-blocking oxide". This can be formed as a silicon dioxide layer or as a multilayer / DBR of, for example, silicon dioxide and titanium (IV) oxide. Other common magnesium fluoride Mg2f, niobium oxide Nb2O5. As a result, a reflection coefficient at the first semiconductor layer 11 facing interface of the mirror layer 15 be increased, creating an absorption coefficient of the overlying metals of the contact bar 20 can be neglected. Thus, for example, the reflective layer 23a between the contact layer 21 and the core 25 omitted.

4 moreover shows by way of example a final applied passivation 30 which may have a silicon dioxide layer.

Based on 5 is a fourth embodiment of an optoelectronic semiconductor chip 100 shown in expanded form. Analogous to the first two exemplary embodiments, the first semiconductor layer is concerned 11 around n-doped GaN and in the second semiconductor layer 17 around p-doped GaN. In addition, the semiconductor chip 100 in this embodiment, analogous to the third embodiment, a mirror layer 15 which can also be referred to as "n-blocking oxide" here. This can likewise be formed as a silicon dioxide layer or as a multilayer / DBR of, for example, silicon dioxide and titanium (IV) oxide. As a result, a reflection coefficient at the first semiconductor layer 11 facing interface of the mirror layer 15 be increased, creating an absorption coefficient of the overlying metals of the contact bar 20 can be neglected.

The contact bridge 20 is for example arranged in a mesa trench. This is before applying the contact layer 21 a mesa structure in the semiconductor layer sequence 10 introduced and with the mirror layer 15 been covered. In a region of the mesa structure or of the contact web 20 is the mirror layer 15 for example, removed and has a through hole, so that the contact layer 21 in direct contact with the first semiconductor layer 11 is arranged.

The invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

100

 Semiconductor chip

10

 Semiconductor layer sequence

11

 first semiconductor layer

13

 Current spreading layer

15

 mirror layer

17

 second semiconductor layer

19

 active layer

20

 contact web

21

 metallic contact layer

23

 metallic coat

25

 metallic core

27

 barrier layer

29

topcoat

30

 passivation

40

 substratum

50

 mask

L1, L2

 reflected light

Γ

 reflection coefficient

λ

 wavelength

Claims (16)

Optoelectronic semiconductor chip ( 100 ), comprising - a semiconductor layer stack ( 10 ), - one on the semiconductor layer stack ( 10 ) arranged metallic contact layer ( 21 ), - one on the semiconductor layer stack ( 10 ) facing away from the contact layer ( 21 ) arranged metallic core ( 25 ) deposited on one of the semiconductor layer stacks ( 10 ) facing away from a top surface and from the top surface to the Semiconductor layer stack ( 10 ) has extending side surfaces, and - one the core ( 25 ) encapsulating metallic shell ( 23 ), which covers the top surface and side surfaces of the core ( 25 ), wherein the contact layer ( 21 ), the core ( 25 ) and the coat ( 23 ) a contact bridge ( 20 ) for electrically contacting the semiconductor layer stack ( 10 ) form. Optoelectronic semiconductor chip ( 100 ) according to claim 1, wherein the core ( 25 ) Comprises or consists of silver and / or copper. Optoelectronic semiconductor chip ( 100 ) according to one of the preceding claims, wherein the jacket ( 23 ) comprises or consists of at least one of the following materials: platinum, palladium, rhodium or gold. Optoelectronic semiconductor chip ( 100 ) according to one of the preceding claims, wherein the jacket ( 23 ) a the semiconductor layer stack ( 10 ) facing side of the core ( 25 ) covered. Optoelectronic semiconductor chip ( 100 ) according to any one of the preceding claims, wherein the contact layer ( 21 ) comprises or consists of at least one of the following materials: titanium, chromium, aluminum, copper, molybdenum, nickel or silver. Optoelectronic semiconductor chip ( 100 ) according to one of the preceding claims, comprising one on a top surface of the shell ( 23 ) arranged finishing layer ( 29 ) of gold. Optoelectronic semiconductor chip ( 100 ) according to claim 6, wherein a layer thickness of the finishing layer ( 29 ) is between 100nm and 2000nm. Optoelectronic semiconductor chip ( 100 ) according to one of the preceding claims 6 or 7, wherein the core ( 25 ) has a layer thickness which is greater than or equal to the layer thickness of the final layer ( 29 ). Optoelectronic semiconductor chip ( 100 ) according to any one of the preceding claims comprising a sapphire substrate, a SiC substrate or a GaN substrate. Optoelectronic semiconductor chip ( 100 ) according to one of the preceding claims, comprising a first semiconductor layer ( 11 ), a second semiconductor layer ( 17 ) and one between the first and second semiconductor layers ( 11 . 17 ) arranged active layer ( 19 ). Optoelectronic semiconductor chip ( 100 ) according to claim 10, wherein the active layer ( 19 ) is provided for the generation or detection of electromagnetic radiation. Optoelectronic semiconductor chip ( 100 ) according to one of claims 10 or 11, comprising one on one of the second semiconductor layer ( 17 ) facing away from the first semiconductor layer ( 11 ) arranged conversion layer. Optoelectronic semiconductor chip ( 10 ) according to one of claims 10 to 12, comprising one on one of the first semiconductor layer ( 11 ) facing side of the second semiconductor layer ( 17 ) arranged mirror layer ( 15 ). Optoelectronic semiconductor chip ( 10 ) according to one of the preceding claims, comprising a core ( 25 ) encapsulating passivation ( 30 ) covering the top surface and side surfaces of the core ( 25 ) and having two or more dielectrics. Optoelectronic semiconductor chip ( 100 ) according to one of the preceding claims, wherein the jacket ( 23 ) the top surface and side surfaces of the core ( 25 completely covered. Method for producing an optoelectronic semiconductor chip ( 100 ), in which: - a semiconductor layer stack ( 10 ), - a metallic contact layer ( 21 ) on the semiconductor layer stack ( 10 ), - a metallic core ( 25 ) on a semiconductor layer stack ( 10 ) facing away from the contact layer ( 21 ) deposited on a semiconductor layer stack ( 10 ) facing away from a cover surface and from the top surface to the semiconductor layer stack ( 10 ) has extending side surfaces, and - a core ( 25 ) encapsulating metallic shell ( 23 ) is applied such that the top surface and the side surfaces of the core ( 25 ), wherein the contact layer ( 21 ), the core ( 25 ) and the coat ( 23 ) a contact bridge ( 20 ) for electrically contacting the semiconductor layer stack ( 10 ) form.

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