DE102016100584A1 - bus system - Google Patents

Abstract

The invention relates to a bus system with a number of bus subscribers (5) which exchange information via a PCI Express protocol, wherein at least one bus subscriber (5) forms a single functional unit (6). This bus subscriber (5) has a single function block (7) with logic of the PCI Express protocol. Logic blocks 12, 13, 14 are assigned to the simple function block (7), by means of which the simple function units (6) are developed further to a multiple participant (11) without changing the single function block (7).

Description

The invention relates to a bus system according to the preamble of claim 1.

Such a bus system is a bidirectional high-speed bus system in which a communication according to the PCI Express protocol takes place between a CPU and other bus subscribers. The PCI Express protocol itself was specified by the PCI Special Interest Group (PCISIG), a US American consortium.

Due to the high data rate of 2.5 GBit per second and higher, only point-to-point connections are made in this bus system. In order to network several bus subscribers via this bus system, so-called switches, that is to say data packet distributors, can be provided, to which several bus subscribers are connected. Using such switches, data packets from the CPU can be assigned to the correct bus subscriber. After switching on the bus system, the CPU scans all bus users of the bus system via the PCI Express access. During this enumeration phase, the CPU assigns each bus user a unique identification ID. After the enumeration phase, the CPU's operating system allocates a software driver to each bus user in order to be able to address the peripheral unit (for example, serial interface, Ethernet controller, graphics card, etc.) connected to the respective bus subscriber from the software side. Subsequently, the communication of the bus system is released, so that the bus users of the bus system can exchange data.

Such bus systems find application in computer systems of all kinds, especially in desktop or laptop PC systems.

In the case of the PCI Express bus system, a bus subscriber can be provided as a simple single subscriber, that is to say the bus subscriber couples a single peripheral unit to the bus system. In this embodiment case of the simple subscriber, the bus subscriber is assigned an identification ID and a software driver on the operating system side.

In order to save switches and thus construction costs, the PCI Express specification allows to build bus subscribers, which consist of several subcontractors. Each subparticipant of the multiple subscriber thereby couples a separate peripheral unit to the PCI Express bus system. Each subparticipant of the multiple subscriber is assigned an own unique identification ID and a separate software driver on the operating system side for operation in the bus system. This embodiment of the bus subscriber is referred to below as a multiple subscriber. All sub-participants of the multiple subscriber are on the same integrated circuit (IC), which is coupled via a point-to-point connection to the PCI Express bus system.

Such PCI Express bus subscribers (single subscribers, as well as multiple subscribers) are very often constructed with FPGA (field programmable gate array) modules. They have single-function digital units and Gigabit transceivers that are hard-wired hard macro cells that form pre-fabricated, certified units within the FPGA structure.

A disadvantage of such Hardmacrozellen is that their function is predefined in large parts and can not be changed later. For a single-function unit designed as a simple user by means of a PCI-Express hard macro cell, this means that its limitation to a simple subscriber can no longer be subsequently extended to a multiple subscriber.

In principle, it would be possible to circumvent this restriction with a commercially available soft-IP core by configuring the FPGA structure such that the limiting PCI Express hard macro cell of the single-function unit is not used and the multiple subscriber realizes it purely with the programmable logic of the FPGAs becomes. However, this requires a very large number of programmable FPGA logic resources, resulting in large and expensive FPGA sizes.

The invention is based on the object with minimal additional logic resources to extend a pure PCI Express single subscriber to a PCI Express multiple subscriber of the type mentioned.

To solve this problem, the features of claim 1 are provided. Advantageous embodiments and expedient developments of the invention are described in the dependent claims.

The invention relates to a bus system with a number of bus subscribers, which exchange information via the PCI Express protocol, wherein at least one bus subscriber forms an individual subscriber. This bus user has a single function block with logic of the PCI Express protocol. The simple function block is associated with new logic blocks, by means of which, without changing the simple function block, the individual subscriber is trained to form a multiple subscriber.

Thus, the basic idea of the invention is not to extend an individual subscriber to a multiple subscriber by excluding the simple function block and completely reprogramming the FPGA structure to provide the multiple subscriber functionality. Rather, according to the invention, the single-function block is included in its structure completely unchanged in order to achieve the multiple subscriber functionality. The multiple subscriber functionality is achieved by specific control of the single functional unit through additional logic blocks that are implemented with very little digital logic. In particular, no larger sizes of the FPGA structure have to be accepted in order to realize the multiple subscriber.

Particularly advantageous is the simple function block of a hard-wired PCI-Express Hardmacrozelle.

The hard macrocell forming the single function block is part of an FPGA module.

In this case, the logic blocks are part of the reconfigurable logic of the FPGA device.

The realization of the aforementioned units in FPGA structures is by no means mandatory. Rather, these units can also be realized in ASIC structures.

An essential element of the invention is that by means of additional logic blocks - using the present in the simple function block PCI Express Hardmacrozelle - a configurable number of sub-participants is generated, thereby creating a multiple participant.

In this case, by means of the additional logic blocks-within certain limits freely selectable-a number of address areas of the single-function block are assigned to certain sub-users.

The elements present in the simple function block, in particular address areas, are distributed by the additional logic blocks to a plurality of subunits, so that a multiple subscriber is created solely by the reprogrammed use of the elements of the simple function block by the logic blocks. An essential aspect of the logic blocks within the meaning of the invention is, in particular, that these write or read requests can change to the configuration area and thus can redirect to predefined sub-participants. This is possible because in an incoming write or read request, the destination identification ID and thus the sub-subscriber number is included and can be changed by the logic blocks.

Another essential aspect of the invention is that response packets to write or read requests are only generated in the simple function block in order to minimize the space requirements of the logic blocks.

Another advantage is that the redirection mechanism can be accomplished by the introduction of additional information in the incoming data packets without complex additional memory tables, which in turn leads to a significant saving in area and thus to a very small solution.

The functionality of the extended by a single subscriber to a multiple subscriber bus subscriber can be further increased by the fact that CRC errors in the data transmission are detected by the logic blocks and can be made of quantitative and qualitative statements on the stability of the PCI Express bus connection.

According to an advantageous embodiment of the invention, the assignment of located in the configuration area revision ID register, the newly added simple subscriber, which serves to associate the software driver, in two ways possible.

In principle, the revision ID register can have identical values for the individual sub-users, so that the individual software sub-users are each assigned the same software driver.

However, the revision ID register can also have different values for each individual subunit user of the multiple subscriber. This is achieved as a significant advantage of the invention that each subcontractor own software driver can be assigned. These software drivers have a much simpler design compared to a software driver associated with multiple bus users. This leads to significantly shorter development times when creating software drivers. In addition, improved and simplified maintenance of the software drivers is achieved.

According to a further advantageous embodiment of the invention, a logic block is provided, by means of which interrupts from each subunits within the multiple subscriber can be sent to the CPU.

This leads to an improved reliability of the bus system, since the logic block interrupts are assigned in advance to the correct sub-users, whereby incorrect control by the interrupts are avoided.

The invention will be explained below with reference to the drawings.

1 : Embodiment of a PCI Express Bus System.

2 : Schematic structure of a single functional unit for the PCI Express bus system according to 1 ,

3 : Extension of the single functional unit to a multiple functional unit.

4 : Structure of a Configuration Space Header.

5 : Configuration of several subunits for the Configuration Space Header.

6 : Schematic representation of the process when accessing the subunit 0 as shown by 4 ,

7 : Schematic representation of the process when accessing the subunit 1 as shown by 4 ,

8th : Structure of a PCI Express Configuration Request.

8a : Structure of the Complete ID of the Configuration Request according to 4 ,

8b : Structure of the requestor ID of the configuration request according to 4 ,

1 schematically shows the structure of a PCI Express bus system. The PCI Express bus system includes a CPU 1 (central processing unit) with associated memory units 2 and a PCI Express bus access 3 ,

To the CPU 1 can be directly or through a switch 4 several bus participants 5 be connected to the PCI Express bus system. Between the CPU 1 and a directly connected bus participant 5 a point-to-point connection is formed. The switch 4 serves to several bus participants 5 to the CPU 1 to join. The switch 4 distributes data packets of the CPU 1 to the connected bus subscribers 5 ,

After switching on the PCI Express bus system, the CPU scans 1 all bus participants 5 and assigns to each bus participant 5 a unique identification ID. After this enumeration phase, every bus participant becomes 5 a software driver is assigned by the operating system running on the CPU. After that, the bus participants 5 of the PCI Express bus system via the PCI Express protocol to exchange data with each other.

2 schematically shows a single subscriber 6 trained bus participants 5 of the PCI Express bus system. The simple participant 6 is built in FPGA logic and includes a single function block 7 , which is designed in the form of a hard-wired PCI-Express Hardmacrozelle in the FPGA structure.

Furthermore, for a serial / parallel conversion of over a PCI Express interface 8th incoming data packets (RX) and transmitted data packets (TX) a gigabit transceiver 9 provided, which is also present in hardwired form as a hard macro. Via a user interface 10 a user can enter the data path between simple function block 7 and gigabit transceivers 9 intervention.

3 shows the extension of the single functional unit according to the invention 6 according to 2 to a multiple participant 11 , within the PCI Express bus system. The multiple participant 11 points like the single functional unit 6 , a simple function block 7 , a gigabit transceiver 9 , a PCI Express interface 8th and a user interface 10 on. In addition, three logic blocks are provided, which are made up of the freely configurable logic component of the FPGA module.

Two of the logic blocks form bypass blocks, namely an RX redirect 12 for incoming data packets and a TX redirect 13 for outgoing data packets. Furthermore, it forms a MIF remap 14 a logic block for the interrupt assignments.

The logic blocks become the function of the simple function block 7 extended to a multi-user functionality.

Via a management interface 15 is the multiple subscriber configurable.

The simple function block 7 according to 2 (as well as according to 3 ) has a bus subscriber executed as an individual subscriber 5 on, for this individual subscriber via the PCI Express protocol physically write / readable configuration area, as in 4 represented exists. The configuration area comprises a predetermined number of registers R1-R10 and six specific registers in the form of base address registers, which in 4 are designated BAR0 to BAR5, these registers are assigned to certain address areas from the 64-bit PCI Express address space.

To extend a single functional unit 6 to a multiple participant 11 are via the logic blocks RX redirection 12 and TX redirection 13 the number and the form of expression of individual sub-participants of the multiple subscriber configured.

This is in 5 schematically shown where left the physically existing configuration area of the simple function block 7 , that is the Configuration Space header, is shown. For this configuration space header, in the present case, three individual subscribers are within a multiple subscriber, corresponding to three bus subscribers 5 derived from the PCI Express bus system.

For the formation of the three subscribers of the multiple subscriber, the address range of the base address registers BAR0 to BAR5 is divided among the three sub-subscribers. How out 5 As can be seen, the first base address registers BAR1, BAR2 of the configuration space header are assigned to the subparticipant 0 as base address registers BAR1, BAR2. The base address registers BAR3, BAR 4 of the configuration space header are assigned to the sub-subscriber 1 as base address registers BAR0, BAR1. The base address register BAR4 of the configuration space header is assigned as the base address register BAR0 of the slave 2. The base address register BAR5 of the Configuration Space header is not assigned to a sub-participant.

Since the Configuration Space header has a total of six base address registers BAR0 to BAR5, a maximum of six subcontractors can be generated within a multiple subscriber. Since only three subcontractors are generated in the present case, the number and assignment of the base address registers BAR0 to BAR5 of the Configuration Space header to the subcontractors can be freely selected.

How out 5 As can be seen, the registers Rl, R2 and R4 to R10 remain the same for all individual subscribers. Only the value of register R3, the so-called revision ID register, is incremented for the individual sub-subscribers (N, N + 1, N + 2). As a result, different software drivers can be assigned to the individual subcontractors. If the same values are provided for registers R3 of all subcontractors, all subcontractors are assigned the same software driver.

In the diagram according to 5 the subcontractor 0 already corresponds to the one originally in the single function unit 6 existing simple-participants.

The other subunits 1 and 2 correspond to additionally generated bus subscribers 5 within the multiple participant.

For the configuration write and read requests that are received via the PCI Express protocol over the bus system, only the one physically existing Configuration Space header is used for all the single subscribers within the multi-subscriber. Nevertheless, with configuration write and read requests, individual subscribers within the multiple party can be targeted, such as the following 5 to 8th demonstrate.

For communication with the first bus user 5 (according to the participant 5 the original single functional unit 6 In a configuration write or read request, an access is made to subparticipant 0, as in 6 shown. In this case, the base address registers BAR0, BAR1 of the simple subscriber 0 are accessed, which correspond to the base address register BAR0, BAR1 of the physical configuration area, that is to say the configuration space header, such that the logic blocks RX redirection 12 and TX redirection 13 No diversion is made, that is, the request is forwarded unprocessed (arrows I in 6 ).

However, if a request, for example, during the enumeration phase, accesses a base address register BAR2 to BAR5 of the configuration space header, that request will be redirected to a disabled register, in this case the register R8 which contains the address range of an optional expansion ROM which is disabled in most cases and shows the same behavior as a disabled base address register. This redirect is in 6 with the arrows II characterized. For communication with another bus participant 5 In the case of a read and write request, access is made to the sub-subscriber 1, as in 7 shown. In order to ensure access to this subunit 1, a request is made with the RX redirection 12 an RX redirection (arrow I ) to the base address registers BAR2, BAR3, which are assigned as base address registers BAR0, BAR1 of the subunit 1 ( 5 ). Therefore, through the RX redirect 12 specifically the further bus participant 5 assigned sub-participants 1 addressed. The RX redirection 12 then RX redirection will be done with that of TX Redirect 13 undone TX redirection (arrow II ). Redirection to register R8 (expansion ROM) when accessing deactivated base address registers (arrows III ) takes place analogously to 6 , As the 6 . 7 show, the data packets for write or read requests are only in the simple function block 7 generated. With the logic blocks these data packets are changed only in a suitable manner, so that several subcontractors and thus bus subscribers 5 to define and specifically address. Through this function of logic blocks RX redirection 12 and TX redirection 13 can thus be used for requests to the simple function block 7 the Configuration Space header can be used in unchanged form for the other sub-participants, so that without changing the simple function block 7 the extension of a single functional unit 6 can be performed on a multiple function unit.

8th shows the structure of a so-called configuration request from the PCI Express. A configuration request is a read or write request to the configuration space header. This request contains the subcontractor number (contained in the Completer ID) to be addressed, the memory address (register number of the Configuration Space Header) to be read or written and the identification ID of the requesting bus user (requester ID). ,

The structure of the Completer ID is in 8a shown. The structure of the requestor ID is in 8b shown.

The configuration request checks which sub-subscriber is accessed by evaluating bits 2: 0 of the sub-station number from the completer ID of an incoming request. If these 3 bits show a value other than 0 and thus signal access to one of the additionally configured subunits, these 3 bits are copied to position 7: 5 of the bus number of the requestor ID and the 3-bit subpart number of the Completer ID is deleted.

This redirects all accesses to subdevice 0, so the single function block 7 this will answer correctly. If this modification were not performed, the simple function block would 7 who is only an ordinary participant 5 supported with a single sub-participant, the request only with an error (so-called Unsupported Request) answer.

Since the requester ID with the information of the original subnumber number (inserted by the RX redirection block) in the response of the simple function block 7 is output unchanged, receives the TX redirection 13 returns the original subnumber number and can now copy it back to its original position and set the bits 7: 5 in the Requester ID to 000.

By using bits 7: 5 in the Requester-ID, the restriction arises that no requesting bus user is allowed to use these bits, ie they are always at 0. To make this restriction as small as possible, only as many bits as needed are used according to the number of sub-users used. The following table shows how many bits are actually used in which configuration:
To make the activated and de-activated base address registers (BAR1 to BAR5) of all subscribers appear at the respective correct positions in the configuration space header of all subscribers, the RX redirection block is used 12 Addresses changed in a suitable manner and further information encoded in bits 4: 2 of the device ID within the Requester-ID.

The following table shows the meaning of the code contained in these bits. code number importance 000 No change in block TX redirection necessary 001 Show answer as access to BAR0 010 Show answer as access to BAR1 011 Show answer as access to BAR2 100 Show answer as access to BAR3 101 Show answer as access to BAR4 110 Show answer as access to BAR5 111 Flag indicating that the revision ID register has been accessed

By introducing this additional information, it is now possible to redirect an incoming configuration request, by changing the address, and the response from the simple function block 7 again to be modified to appear in response to the original request.

Since the bits of the device number are used elsewhere within the requester ID, it is imperative that no bus participant 5 with a device number greater than three, access to the multifunction unit 11 power. Since in most cases the device ID is 00000, this restriction is acceptable.

This redirection approach eliminates the need to keep a list of incoming requests and the replies of the simple function block generated later 7 together, but each answer contains all the information for post-processing through the additional information. This leads to significant logic resource savings.

The PCl-Express bus system distinguishes between two different mechanisms for interrupt triggering, the legacy interrupt and the MSI interrupt.

In so-called legacy interrupt mode, each subcontractor issues the same interrupt, which must be treated by the operating system in conjunction with the associated software driver on the CPU system as a so-called "shared interrupt".

MSI interrupts require special treatment. Since MSI interrupts are triggered by writing a specific data word ("message data register") to the assigned address of the interrupt controller, the so-called message data register must be stored for each subparticipant. This does the RX redirection 12 , which recognizes write accesses to the message data register for each subunit participant and stores the specific value of the message data register for each subunit participant in a small SRAM in the FPGA.

If an MSI interrupt is now triggered via the user interface, this is first of all triggered by the MIF remap 14 retained and the correct message data register from SRAM mentioned above in the simple function block 7 loaded. Thereafter, the MSI interrupt is triggered and the interrupt to the user interface 10 marked as treated. term Explanation in the PCI Express context inquiry A request is a so-called request, which is made either by the requester to the completer as a read request or as a write request. ASIC Application specific integrated circuit. This is a customer-specific, hardwired electronic component. answer Upon request, the requested bus participant (Completer) responds with his answer. The answer is called completion. Base address register (BAR) Each PCI Express feature has 6 base address registers (BARs). BARs are used to define the size as well as the location of a memory window within the PCI Express address space. bus users A bus participant we call a so-called endpoint. An endpoint can contain 1-8 PCI Express functions. If only one function is realized, it is an individual participant, if more functions are realized, it is a multiple participant Data packet transfer A data packet distributor is called a switch in the PCI Express context. A switch consists of a number of input and Output ports. The logic contained in the switch makes it possible to assign a running data packet to the correct output. Simple function block Digital logic unit containing the data exchange according to the rules of the PCI Express protocol for a single function device. In FPGAs, this logic unit is usually designed as a hardwired hard macro. simply participants This is a so-called single function device Enumerierungsphase The enumeration phase will be completed before the operation of the PCI Express bus system. In the enumeration phase, all configuration space headers are initialized and, in particular, the BARs are set up. FPGA Field programmable gate array. FPGAs are programmable logic devices that contain user-defined logic functions. Hard Macro A hard macro is a hard-wired interconnection of logic elements, such as flip-flops and Boolean logic functions. IC Integrated Circuit: Integrated Circuit Identification ID The identification ID is a 16-bit word that uniquely identifies a PCI Express bus subscriber. It consists of 3 parts, the so-called Bus-ID, Device-ID and Function-ID. configuration area Configuration space header. Each function has its own Configuration Space header, which in particular carries the BAR settings for each function. Multiple participants The multiple subscriber is referred to in the PCI Express specification as a Multi Function Device. The configured functions contained in the multi-function device are referred to in this patent as sub-participants. PCI Express bus access Via the PCI Express bus access the CPU communicates with the Bus stations. In the PCIe specification, the PCI Express bus access is called the Root Complex. PCISIG The PCI Special Interest Group (PCISIG) is a US American consortium that advances the specifications and evolution of the PCI Express system. peripheral unit Peripheral units are I / O units that extend the functionality of the CPU. This can be, for example, graphics cards, serial ports, Ethernet controllers or other. Revision ID Register The Revision ID Register is located in the Configuration Space Header and is used (among other registers) to map a Software Driver (Device Driver) to a PCI Express Function. Shared interrupt A shared interrupt is an interrupt, ie a common interrupt line which is shared by several bus users. The interrupt service routine of the CPU in shared interrupts must have the possibility of being able to identify the interrupting bus subscriber. Soft IP Core A Soft IP Core is a description of a digital functional unit in the form of a hardware description language (eg VHDL or Verilog). Through a logic compiler (also referred to as a synthesis tool), the Soft IP Core transitions into a digital circuit and can then be placed in an FPGA or ASIC and wired. Unsupported Request This is the default response of a PCI Express bus user if the requested operation is not possible. This occurs, for example, when a subcontractor is requested that does not exist.

LIST OF REFERENCE NUMBERS

1

 PCI Express bus access

2

 storage unit

3

 CPU

4

 Switch

5

 bus users

6

 simply participants

7

 Simple function block

8th

 PCI Express interface

9

 Gigabit transceivers

10

 User interface

11

 Multiple participants

12

 RX redirection

13

 TX redirection

14

 MIF redirection

15

 Management interface

Claims (15)

Bus system with a number of bus participants ( 5 ), which exchange information via the PCI Express protocol, whereby at least one bus subscriber ( 5 ) a simple functional unit ( 6 ), this bus subscriber ( 5 ) a simple function block ( 7 ) with a logic of the PCI Express protocol, characterized in that the simple function block ( 7 ) Logic blocks are assigned by means of which without changing the simple function block ( 7 ) the simple functional units ( 6 ) to a multiple participant ( 11 ) are further developed. Bus system according to claim 1, characterized in that the simple function block ( 7 ) consists of a hard-wired hard macro cell. Bus system according to claim 2, characterized in that the single-function block ( 7 ) forming Hardmacrozelle is part of an FPGA chip. Bus system according to claim 3, characterized in that the logic blocks are part of a reconfigurable logic of the FPGA module. Bus system according to one of claims 1 to 4, characterized in that by means of the logic blocks using the single function block ( 7 ) existing structure a configurable number of sub-participants is generated. Bus system according to Claim 5, characterized in that, by means of the logic blocks, it is possible to select a number of base address registers of the simple function block ( 7 ) is assigned to specific subcontractors. Bus system according to one of claims 1 to 6, characterized in that data packets for configuration write or read requests only in the simple function block ( 7 ) and that such data packets are changed by the logic blocks. Bus system according to Claim 7, characterized in that the subcontractor number characterizing an individual subscriber is contained in a read or write request. Bus system according to one of claims 1 to 9, characterized in that a revision ID register is provided for the assignment of a software driver to a subcontractor Bus system according to claim 9, characterized in that the revision ID registers for the individual subunits, which form the multiple subscriber, may have different values, so that the individual simple subscribers, which form the multiple subscriber, are assigned different software drivers. Bus system according to claim 10, characterized in that the revision ID registers for the individual participants can be configured so that they have identical values, so that the individual sub-participants each have the same software driver is assigned. Bus system according to one of Claims 5 to 11, characterized in that logic blocks designed as diversion blocks are provided by means of which write or read requests are diverted to predetermined sub-users within the multiple subscriber. Bus system according to claim 12, characterized in that by means of the diversion blocks errors in the data transmission are reported, which can be used for quantitative and qualitative statements on the stability of the PCI Express bus. Bus system according to claim 13, characterized in that the logic blocks formed as diversion blocks are described by means of a hardware description language, whereby the number and the form of expression of the individual subscribers contained in the multiple subscriber can be fixed by means of parameters. Bus system according to one of Claims 5 to 14, characterized in that a logic block ( 14 ) is provided by means of which interrupts using the simple function block ( 7 ) are discontinued by predetermined subcontractors within the multiple participant.

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