DE102015201419B4 - Methods for forming low-defect stretch-relaxed layers on lattice-mismatched substrates and corresponding semiconductor device structures and devices - Google Patents

Abstract

A stretch-relaxing method, comprising: forming (500) a porous region (120) in a surface of a semiconductor substrate (110); forming (510) a first semiconductor layer (130) integral with the semiconductor substrate (110) on the porous region ( 120) is lattice-matched in the surface of the semiconductor substrate (110);forming (520) a second semiconductor layer (140) on the first semiconductor layer (130), the second semiconductor layer (140) being a strained formed layer;relaxing (530) the second semiconductor layer (140);forming (540) a third semiconductor layer (150) on the relaxed second semiconductor layer (140), the third semiconductor layer (150) being a strained formed layer; andrelaxing (550) the third semiconductor layer (150),wherein the semiconductor substrate (110) comprises a silicon substrate, the first semiconductor layer (130) comprises a silicon layer, the second semiconductor layer (140) comprises a first silicon-germanium layer having a first germanium concentration, and the third semiconductor layer (150) comprises a second silicon germanium layer having a second germanium concentration that exceeds the first germanium concentration.

Description

AREA

The invention relates generally to semiconductor devices, and more particularly to methods of forming strain-relaxed layers in lattice-mismatched semiconductor substrates and semiconductor devices having such strain-relaxed layers.

BACKGROUND

There are a number of applications where it may be desirable to grow a strained semiconductor layer. For example, strained silicon layers are routinely used in high performance complementary metal-oxide-semiconductor (CMOS) devices because strained semiconductor layers can have higher charge carrier mobility, and therefore the transistors with channels formed in such strained silicon layers can have higher switching speeds. For example, a strained silicon layer can be formed by growing a relatively thin silicon layer on top of a thicker silicon-germanium layer, often referred to as a silicon-germanium "buffer" layer.

1 Figure 12 shows a strained silicon layer formed by a conventional method. Referring to 1 , a graded silicon germanium (Si _1-x Ge _x ) layer 20 is epitaxially grown on a bulk silicon substrate 10 according to this conventional technique. The value of x can be very low (or zero) at the interface between the graded Si1-xGex layer 20 and the bulk silicon substrate 10, and x can increase with increasing distance from the substrate 10. Due to the lattice mismatch between the silicon substrate 10 and the graded Si _1-x Ge _x layer 20, the Si _1-x Ge _x layer 20 can be grown in a stretched manner. After the Si _1-x Ge _x graded layer 20 is grown over a certain thickness, dislocations 22 may be generated at the interface between the bulk silicon substrate 10 and the Si _1-x Ge _x graded layer 20 . A pair of threading dislocations 24 may extend from each misdislocation 22 up through the Si _1-x Ge _x graded layer 20 toward the surface of the Si _1-x Ge _x graded layer 20 . Techniques can be used during growth to increase the length of the dislocations 22, which can help limit the number of filamentous dislocations 24 that are formed. The formation of these dislocations 22, 24 can cause the relaxation (relax) of the graded Si _1-x Ge _x layer 20. The Si _1-x Ge _x graded layer 20 can then be further relaxed by a thermal anneal.

A silicon layer 30 can then be grown on the graded Si _1-x Ge _x layer 20 . Because of the lattice mismatch between the relaxed Si _1-x Ge _x graded layer 20 and the silicon layer 30, the silicon layer 30 can be grown strained. Unfortunately, filamentous dislocations 24 that reach the top of the graded Si _1-x Ge _x layer 20 can cause dislocations or other defects in the strained silicon layer 30. These defects/dislocations 24 in the strained silicon layer 30 can adversely affect the performance of a semiconductor device formed in the silicon layer 30. While the filiform dislocation density at the top surface of the Si _1-x Ge _x graded layer 20 can generally be reduced by increasing the thickness of the Si _1-x Ge _x graded layer 20, growth of a thicker Si _1-x Ge _x -layer 20 significantly increases the required growth time and can also lead to other problems such as an increased incidence of semiconductor wafers becoming unusable due to particles falling into the wafer during epitaxial growth. Furthermore, to reduce filiform dislocation levels to 1×10 ⁶ /cm ² or less, it may be necessary to grow the Si _1-x Ge _x graded layer 20 to a thickness of tens or hundreds of microns. The growth times and material costs associated with the growth of such thick layers can be prohibitively expensive in many applications.

In another approach, stretched-relaxed Si _1-x Ge _x layers were formed by growing Si _1-x Ge _x layers on a silicon-on-insulator substrate. Prior to the growth of such a Si _1-x Ge _x layer, the silicon-on-insulator substrate is etched or milled so that only a 50 nm thick silicon layer remains on the insulator of the silicon-on-insulator substrate. After the Si _1-x Ge _x layer is grown, it is then relaxed via a thermal annealing process. However, this method requires a more expensive silicon-on-insulator substrate and has only been shown to work with a relatively low germanium concentration in Si _1-x Ge _x layers (ie x=0.15).

From the U.S. 2002/0 146 892 A 1, a method for forming a strained silicon layer on a substrate is known. In this case, a porous layer is formed on a silicon substrate, a silicon layer on the porous layer, a silicon-germanium layer on the silicon layer and a further silicon layer on the silicon-germanium layer.

From the U.S. 2005/0 221 591 A1 discloses a method of forming a semiconductor structure in which a relaxed silicon germanium layer is formed on a bulk silicon substrate.

the US 2001/0 048 119 A1 discloses a silicon germanium layer formed on a silicon wafer, a silicon germanium layer including a buried oxide layer formed thereon, and another silicon germanium layer on which a strained silicon layer is formed.

SUMMARY

It is an object of the present invention to provide improved stretch-relaxing processes for the production of semiconductor layers suitable for semiconductor devices.

This object is achieved by the subject matter of the main claim and the dependent claims. Preferred embodiments are the subject matter of the dependent claims.

Methods for forming stretched-relaxed semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer lattice-matched with the semiconductor substrate is formed on the porous region. A second elongated semiconductor layer is formed on the first semiconductor layer. The second semiconductor layer is then relaxed.

In some embodiments, a third semiconductor layer may be formed on the relaxed second semiconductor layer. This third semiconductor layer may be an elongated layer. The third semiconductor layer can then be relaxed to provide a stretch-relaxed semiconductor layer.

In some embodiments, the porous region may be formed in the surface of the semiconductor substrate by wet etching a top surface of the semiconductor substrate with a wet etchant having an electrical potential applied between the semiconductor substrate and the wet etchant.

In some embodiments, the first semiconductor layer may be under yield stress and the second semiconductor layer may be under compressive stress before the second semiconductor layer relaxes.

In some embodiments, the first semiconductor layer can have a thickness of less than 20 nm.

In some embodiments, the first semiconductor layer may only be weakly bonded to the semiconductor substrate such that the first semiconductor layer may move with respect to the semiconductor substrate when a yield stress is applied to the first semiconductor layer.

The first semiconductor layer may be formed directly on the porous area in the surface of the semiconductor substrate, and the second semiconductor layer may be formed directly on the first semiconductor layer.

In some embodiments, the semiconductor substrate may be a silicon substrate, the first semiconductor layer may be a silicon layer, and the second semiconductor layer may be a first silicon germanium layer having a first germanium concentration, and the third semiconductor layer may be a second silicon germanium layer having a second germanium concentration which exceeds the first germanium concentration.

In some embodiments, a germanium concentration of the second silicon germanium layer may exceed 75 percent (or 85 percent) and a filamentary dislocation density in the second silicon germanium layer may be less than about 1×10 5 /cm ² .

In some embodiments, a total thickness of the silicon layer, the first silicon germanium layer, and the second silicon germanium layer may be less than 75 nm.

In some embodiments, the second semiconductor layer may be a III-V compound semiconductor.

In some embodiments, a fourth semiconductor layer may be formed on the second silicon germanium layer and a semiconductor device may be formed at least partially in or on the fourth semiconductor layer.

According to further embodiments of the invention, methods are provided for forming a first semiconductor layer on a compliant region of a semiconductor substrate that is lattice-matched with the first semiconductor layer such that the first semiconductor layer is only weakly bonded to the compliant region of the semiconductor substrate and laterally on the surface of the compliant region of the semiconductor substrate. A second semiconductor layer that is lattice mismatched with the first semiconductor layer is formed on the first semiconductor layer. A relaxation process is performed for the second semiconductor layer, the filamentary dislocations in the first Semiconductor layer generated while the second semiconductor layer remains substantially free of thread dislocations.

In some embodiments, a third semiconductor layer that is lattice mismatched with the second semiconductor layer can be formed on the second semiconductor layer, and a relaxation process can be applied to the third semiconductor layer that creates filamentary dislocations in the second semiconductor layer while the third semiconductor layer is substantially free of Thread displacement remains.

In some embodiments, the first semiconductor layer may be under yield stress before relaxation and the second semiconductor layer may be under compressive stress before relaxation.

In some embodiments, the semiconductor layer may be a silicon layer having a first thickness, the second semiconductor layer may be a silicon germanium layer, which may have a first germanium concentration and a second thickness that exceeds the first thickness, and the third semiconductor layer may be a second silicon-germanium layer having a second germanium concentration that exceeds the first germanium concentration and having a third thickness that exceeds the second thickness.

In some embodiments, a porous region is formed in a top surface of a semiconductor substrate and the semiconductor substrate is then heated to close at least a portion of the surface pores while the interior of the porous region remains porous to convert the region of the semiconductor substrate into the compliant region of the Semiconductor substrate to convert, and then the first semiconductor layer can be grown epitaxially on the porous region by chemical vapor deposition.

In some embodiments, the first and second semiconductor layers may each have a thickness of less than 25 nm.

In some embodiments, the compliant region of the semiconductor substrate may be a porous region in a top surface of a silicon substrate, the first semiconductor layer may be a silicon layer, the second semiconductor layer may be a first silicon-germanium layer having a first germanium concentration, and the third semiconductor layer may be a second silicon -Germanium layer with a second germanium concentration which exceeds the first germanium concentration.

In some embodiments, a germanium concentration of the second silicon germanium layer may exceed 75 percent and a filamentary dislocation density in the second silicon germanium layer may be less than about 1×10 5 /cm ² .

In some embodiments, a total thickness of the silicon layer, the first silicon germanium layer, and the second silicon germanium layer may be less than 75 nm.

In some embodiments, the porous region can have a porosity of at least 30%.

In some embodiments, the relaxation process can be a thermal anneal.

In some embodiments, a fourth semiconductor layer may be formed on the third semiconductor layer and a semiconductor device may be formed at least partially in or on the fourth semiconductor layer.

According to still further embodiments of the present invention, methods are provided for forming a semiconductor device in which a porous region is formed in a surface of a silicon substrate. A silicon layer is formed on the porous area in the surface of the silicon substrate. A first silicon germanium layer having a first germanium concentration is formed on the silicon layer. The first silicon germanium layer is then relaxed. A second silicon germanium layer having a second germanium concentration higher than the first germanium concentration on the relaxed first silicon germanium layer is then formed, the second silicon germanium layer being a strained grown layer the second silicon-germanium layer relaxes. A semiconductor layer is formed on the second silicon germanium layer. Finally, the semiconductor device is at least partially formed in the semiconductor layer.

In some embodiments, forming the porous region in the surface of the semiconductor substrate may include wet etching a top surface of the semiconductor substrate with a wet etchant having an electrical potential applied between the semiconductor substrate and the wet etchant. The method may also include annealing the silicon substrate to close at least some of the pores in an upper surface of the porous region prior to forming the first silicon germanium layer.

In some embodiments, the first semiconductor layer may have a thickness less than 20 nm, and a total thickness of the silicon layer, the first silicon germanium layer, and the second silicon germanium layer may be less than 75 nm.

In some embodiments, the silicon layer may only be weakly bonded to the silicon substrate such that the silicon layer may move with respect to the silicon substrate when a yield stress is applied to the silicon substrate.

In some embodiments, a germanium concentration of the second silicon germanium layer may exceed 75 percent and a filamentary dislocation density in the second silicon germanium layer may be less than about 1×10 5 /cm ² .

According to still further embodiments of the invention, semiconductor structures are provided that include a silicon substrate, a region of porous silicon in a top surface of the silicon substrate, a silicon layer on a top surface of the porous silicon region, a first silicon-germanium layer having a first germanium concentration on the top surface of the silicon layer, and a stretched-relaxed second silicon-germanium layer having a second germanium concentration that exceeds the first germanium concentration on the top surface of the first silicon-germanium layer.

In some embodiments, the porous region can have a porosity of at least 30%.

In some embodiments, a first plurality of dislocations may be present at the interface between the silicon layer and the first silicon germanium layer, and the silicon layer may have a filamentary dislocation density of at least 1×10 ⁶ /cm ² and one of the second plurality of dislocations may be present at the interface between the first silicon-germanium layer and the second silicon-germanium layer, and the first silicon-germanium layer may have a filamentary dislocation density of at least 1×10 6 /cm ² , and the second silicon-germanium layer may have a filament dislocation density of less than 1×10 5 /cm ² .

In some embodiments, a germanium concentration of the second silicon germanium layer may exceed 75 percent.

In some embodiments, a total thickness of the silicon layer, the first silicon germanium layer, and the second silicon germanium layer may be less than 75 nm.

In some embodiments, a first plurality of dislocations may be present at the interface between the silicon layer and the first silicon-germanium layer, and a plurality of filamentary dislocations may extend downward from the dislocations into the silicon layer.

In some embodiments, the silicon layer may have a thickness less than 20 nm and the silicon layer may be only weakly bonded to the silicon substrate such that the silicon layer may move with respect to the silicon substrate when a yield stress is applied to the silicon substrate.

In some embodiments, the silicon layer can have a first thickness, the first silicon germanium layer can have a second thickness that exceeds the first thickness, and the second silicon germanium layer can have a third thickness that exceeds the second thickness.

character list

• 1 12 is a sectional diagram schematically showing a conventional method of forming a strained silicon layer on a strained-relaxed silicon-germanium layer.
• 2 12 is a sectional diagram schematically showing a semiconductor structure including a stretch-relaxed layer, according to certain embodiments of the invention.
• 3 Fig. 12 is a sectional diagram schematically showing a semiconductor structure comprising a stretch-relaxed layer according to further embodiments of the invention.
• 4 12 is a schematic diagram showing the formation of mismatches and thread dislocations that may be formed in sacrificial layers produced by techniques according to embodiments of the invention.
• 5A-5F 12 are diagrams schematically showing a method of forming a semiconductor structure comprising a stretch-relaxed layer, according to some embodiments of the invention.
• 6A Fig. 12 is a schematic sectional view showing a silicon germanium thin film grown on a silicon thin film.
• 6B Figure 12 is a schematic sectional view showing a thicker silicon germanium layer grown on a thin silicon layer.
• 7 12 is a perspective view of a semiconductor device including a stretch-relaxed layer, in accordance with certain embodiments of the invention.
• 8th 12 is a flow diagram of a method of forming a stretch-relaxed layer, according to certain embodiments of the invention.
• 9 12 is a flow diagram of a method of forming a stretch-relaxed layer, according to further embodiments of the invention.

DETAILED DESCRIPTION

According to embodiments of the invention, methods of forming a stretch-relaxed layer on a semiconductor substrate are provided. For example, the stretch-relaxed layer may be a silicon-germanium layer with high germanium concentration, and the semiconductor substrate may be a bulk silicon substrate. In some embodiments of these methods, a porous region may be formed in a top surface of the bulk silicon substrate by, for example, a hydrofluoric acid wet etch. A heat treatment can then be performed to close the pores in the upper surface of the porous region of the silicon substrate. A thin silicon layer can then be epitaxially grown on the top surface of the porous region. This thin silicon layer can serve as a first sacrificial layer. Due to the porous region in the top portion of the bulk silicon substrate, the bonds between the thin silicon epitaxial layer and the top surface of the silicon substrate may be weaker than normal, making the top surface of the substrate somewhat "slippery" or compliant relative to the thin silicon layer is.

A first silicon germanium layer having a first germanium concentration can then be epitaxially grown on the silicon layer. The first silicon germanium layer may be thin (e.g. 10 to 20 nm thick). The first silicon-germanium layer may have a relatively high germanium concentration, such as a 50% germanium concentration. In some embodiments, the first silicon-germanium layer and the underlying silicon layer can be grown fully stretched and can be grown substantially defect-free. A thermal annealing process can then be performed to relax the silicon layer and the first silicon germanium layer. As these layers relax, dislocations will form along the interface between the silicon layer and the first silicon-germanium layer, and filamentous dislocations can propagate through the silicon layer, but the first silicon-germanium layer may have lower levels of filamentous dislocations or even in the Be essentially free of thread displacements.

In some embodiments, a second silicon germanium layer having a second germanium concentration higher than the first germanium concentration may then be epitaxially grown on the first silicon germanium layer. During growth, the second silicon germanium layer may be fully stretched, and the underlying first silicon germanium layer will also be stretched during the epitaxial growth process. A thermal annealing process can then be performed to relax the first and second silicon germanium layers. As these layers relax, dislocations will form along the interface between the first and second silicon germanium layers, and filamentary dislocations can propagate through the first silicon germanium layer, but the second silicon germanium layer can have lower levels of faults exhibit or even be essentially free of errors. The second silicon-germanium layer can then be used as a seed layer for the growth of, for example, additional semiconductor materials that can be used as active areas of semiconductor devices, such as an epitaxially grown germanium or silicon-germanium fin for a FIN-FET transistor or strained silicon channel layers can be used. The additional semiconductor material can also be used as a donor wafer material for the formation of active areas of semiconductor devices on an insulator layer over a semiconductor substrate.

The stretched-relaxed silicon-germanium layers according to embodiments of the invention may be relatively thin layers (eg, the series of layers that are grown may have a total thickness over a top surface of the silicon substrate of less than 50-100 nm in some embodiments ) and may have reduced defect densities (e.g., filament dislocation densities of 1 × 105/cm ² or even less may be possible). In addition, the stretched-relaxed silicon-germanium layers according to embodiments of the invention can be grown to have very high germanium concentrations, such as germanium concentrations of 0.9 or 1.0 (ie, rei nes germanium), while still having relatively low filamentary dislocation densities. Additionally, the strained-relaxed silicon-germanium layers according to embodiments of the invention can be inexpensively formed on conventional bulk silicon substrates using conventional chemical vapor deposition epitaxial growth processes suitable for high-volume manufacturing.

While the above-described embodiments of the invention involve growing a stretched-relaxed silicon-germanium layer on a silicon substrate, it should be understood that the techniques disclosed herein can be used in a wide variety of material systems. For example, in other embodiments, a stretched-relaxed III-V compound semiconductor layer may be grown on a lattice-mismatched substrate, such as a sapphire, silicon, or silicon carbide substrate.

Methods and semiconductor devices according to embodiments of the invention will now be discussed in more detail with reference to the accompanying figures, in which exemplary embodiments of these methods and semiconductor devices and intermediate structures are shown.

2 12 is a cross-sectional diagram that schematically shows a semiconductor structure 100 including a stretch-relaxed layer, according to certain embodiments of the invention. The semiconductor structure can, for example, comprise a semiconductor wafer or a part of such a semiconductor wafer.

As in 2 As shown, the semiconductor structure 100 includes a silicon substrate 110, such as a bulk silicon substrate, or a thick silicon epitaxial layer. The silicon substrate 110 may comprise a p-type silicon substrate, or an n-type silicon substrate and may or may not be doped with impurities. A top surface of the silicon substrate 110 may include a porous region 120 . The porous region 120 may comprise the entirety of the top surface of the silicon substrate 110 or may be one or more discrete porous regions formed in selected locations in the top surface of the silicon substrate 110 . The pores on the top surface of the porous region 120 can be closed by an appropriate treatment so that the porous region 120 can serve as a good seed layer during a subsequent epitaxial growth process. A thin silicon layer 130 is provided on an upper surface of the porous region 120 . Finally, a silicon germanium layer 140 is provided on a top surface of the thin silicon layer 130 .

The silicon germanium layer 140 may be a stretched-relaxed silicon germanium layer 140 . A plurality of dislocations 132 may be formed in the semiconductor structure 100, primarily along the interface between the thin silicon layer 130 and the silicon germanium layer 140. Filamentous dislocations 134 may extend from the dislocations 132. FIG. As in 2 As shown, the filamentary dislocations 134 may extend primarily downward from the misdislocations 132 to extend through the thin silicon layer 130 . The filamentary dislocations 134 can only propagate through the silicon layer 130 and not into the porous region 120 of the silicon substrate 110. The silicon germanium layer 140 can have a low filamentary dislocation density, or can be substantially free of filamentary dislocations 134. FIG.

In some embodiments, the silicon layer 130 may be a thin silicon layer 130 having a thickness of less than 25 nm, for example. In some embodiments, the silicon layer 130 may have a thickness of less than 15 nm, such as a thickness of about 10 nm , which are formed at the interface between the lattice-mismatched silicon layer 130 and the silicon-germanium layer 140. FIG.

The silicon-germanium layer 140 can have a variety of different germanium concentrations. The germanium concentrations can be selected to be at a level such that the silicon layer 130 can relax the silicon-germanium layer 140 . Thus, in some cases, this may set a practical upper limit on the germanium concentration. The silicon germanium layer 140 may comprise a graded layer in some embodiments, although more typically the silicon germanium layer 140 will have a constant germanium concentration. If the silicon germanium layer 140 is a graded layer, the average germanium concentration of the layer is taken as the germanium concentration of the layer.

The thickness of the silicon germanium layer 140 can be selected to meet several criteria in some embodiments. For example, the silicon germanium layer 140 may have a thickness sufficient to to store sufficient strain energy to allow relaxation of the underlying silicon layer 130 during a subsequent relaxation process. Additionally, the thickness of the silicon germanium layer 140 may be close to a "critical thickness" of the silicon germanium layer 140 . The "critical thickness" refers to a thickness of the silicon germanium layer 140 that is sufficiently small that the layer will be elastically stretched but will remain stable, meaning that the layer will remain elastically stretched even when pushed to very high levels temperatures is heated. The critical thickness for the silicon germanium layer 140 is a function of, for example, the germanium concentration of the layer. The thickness of silicon germanium layer 140 may also be at, or near, a maximum metastable thickness for silicon germanium layer 140 . The metastable thickness refers to a range of thicknesses for a layer grown on an underlying lattice-mismatched layer thicker than the critical thickness, up to a thickness at which relaxation will occur during growth. In other words, for thicknesses greater than the maximum metastable thickness, the dislocation layer will relax from growing since the strain energy is greater than the lattice can withstand. The range of layer thicknesses between the critical thickness and the maximum metastable thickness is referred to as the metastable range. Layers with thicknesses in the metastable range are stretched during growth but may relax (and form dislocations) in response to, for example, a thermal anneal. The maximum metastable thickness for the silicon germanium layer 140 may depend, for example, on the germanium concentration of the layer and the temperature at which the layer is grown. By fabricating the silicon-germanium layer 140 to a thickness in the metastable range, the silicon-germanium layer 140 can be grown with relatively few or no defects, and can impart a tensile stress on the underlying silicon layer 130 that stretches the silicon layer 130 so that the filiform dislocations form in the silicon layer 130 rather than in the silicon germanium layer 140. In some embodiments, the silicon germanium layer 140 may have a thickness of, for example, about 10 nm to about 20 nm. The silicon germanium layer 140 can be thicker than the silicon layer 130 .

For example, the silicon germanium layer 140 can be used as a growth surface for additional semiconductor material that can be used as active areas of semiconductor devices, such as a strained silicon layer (not shown). In other cases, the silicon germanium layer 140 can be used as a seed surface for the growth of additional semiconductor material that can be used as active areas of semiconductor devices, such as a germanium fin for a FIN-FET transistor. A wide variety of other uses are possible. Additionally, as further below in relation to 3 As will be explained, the silicon germanium layer 140 can be used as a sacrificial layer for the growth of a higher concentration silicon germanium layer on a top surface thereof.

3 FIG. 12 is a sectional diagram schematically showing a semiconductor device 100′ including a stretch-relaxed layer, according to certain embodiments of the invention.

As in 3 As shown, the semiconductor device 100' comprises the silicon substrate 110, the porous region 120 and the silicon layer 130 of the semiconductor device 100 referred to above with reference to FIG 2 have been described. The semiconductor device 100' further includes a silicon germanium layer 140'. The silicon germanium layer 140' may be similar to the silicon germanium layer 140 as described above. However, the silicon germanium layer 140' includes a plurality of dislocations 142 formed at an interface between the silicon germanium layer 140' and a second silicon germanium layer 150 formed thereon, and a plurality of Filamentous dislocations 144 extending from misdislocations 142 down into first silicon germanium layer 140'.

The second silicon germanium layer 150 may have a higher germanium concentration than the first silicon germanium layer 140 . For example, in some embodiments, the second silicon germanium layer 150 may have a germanium concentration of 90% or higher. In some embodiments, the second silicon germanium layer 150 can be replaced with a pure germanium layer. In some embodiments, the second silicon germanium layer 150 may be a relatively thin layer, for example less than 50 nm thick. In some embodiments, the silicon germanium layer 150 may have a thickness of about 20 nm to about 40 nm, for example. The second silicon germanium layer 150 may be thicker than the first silicon germanium layer 140'. The second silicon germanium layer 150 may have a low filamentary dislocation density, or may be substantially free of filamentary dislocations.

4 Fig. 12 is a schematic perspective diagram showing how dislocations and filamentary dislocations can form when a strained silicon-germanium layer containing the grown on an underlying silicon layer or substrate relaxes. As in 4 As shown, a silicon germanium epitaxial layer 220 may be grown on a bulk silicon substrate 210. FIG. The silicon germanium layer 220 is lattice mismatched with the underlying silicon substrate and thus the silicon germanium layer 220 is grown strained. The silicon-germanium layer 220 may be relaxed either by thermal annealing and/or during growth after the maximum metastable thickness is exceeded. During relaxation, dislocations 222 and threading dislocations 224 are generated. As in 4 As shown, two thread dislocations 224 are created for each misdisplacement 222, and the thread dislocations 224 thread to a surface. In the silicon/silicon-germanium structure of 4 the filamentary dislocations 224 are typically at 60° angles as they slide on the Si(111) lattice plane. As also in 4 1, since the bulk silicon substrate 210 tends to be rigid, relaxation tends to occur exclusively in the silicon germanium layer 220 and thus the filamentary dislocations 224 propagate through the silicon germanium layer 220. FIG. The filiform dislocation density in the silicon germanium layer 220 can be very high when the silicon germanium layer 220 is relaxed. For example, assuming that 1% strain is produced during the formation of the silicon germanium layer 220, which is then fully relaxed, and assuming that each filamentary dislocation has a Burgers vector magnitude of about 5 angstroms (where 1 angstrom = 1Å = 0.1 nm), then the threading dislocation density (TDD) can be calculated as follows: $$\text{TDD}=\text{0}\text{.01*1cm/5A}=\text{2}\times {10}^5/\text{cm(length unit)}$$

This corresponds to a thread dislocation density of about 1 × 10 ¹⁰ / cm ²

In many cases, the goal may be to form a stretched-relaxed silicon-germanium layer that has a low filamentary dislocation density so that stretched device layers can then be formed on the stretched-relaxed silicon-germanium layer. According to embodiments of the invention, stretched-relaxed silicon-germanium layers can be grown on silicon substrates under conditions where the filamentary dislocations will propagate through the silicon layer, as opposed to the silicon-germanium layer. This can yield stretch-relaxed silicon-germanium layers that have low filamentary dislocation densities.

To achieve this, a sacrificial silicon layer can be grown on an underlying silicon layer, such as a bulk silicon substrate. This sacrificial silicon layer can be a thin layer so that it is not rigid as is the case with a bulk silicon substrate. In addition, the sacrificial silicon layer may be formed such that the interface between the sacrificial silicon layer and the underlying silicon substrate may be weak such that the sacrificial silicon layer may move relative to the silicon substrate rather than becoming a substantial extension of the silicon substrate. This weak interface can be achieved, for example, by forming a porous region in the top surface of the silicon substrate that is only weakly bonded to the sacrificial silicon layer. Under these conditions, the strain in the silicon germanium layer during the relaxation process can be transferred to the slippery interface between the sacrificial silicon layer and the silicon substrate, and therefore the filamentary dislocations will flow through the sacrificial silicon layer instead of the silicon layer.

5A until 5F 12 are diagrams schematically showing a method of forming the semiconductor device 100' 3 illustrate, according to embodiments of the invention.

As in 5A As shown, a silicon substrate 110, such as a bulk silicon substrate, or a thick epitaxially grown silicon layer will be provided. A porous region 120 may be formed in a top surface of silicon substrate 110 . The porous region 120 may be formed on the entire top surface of the silicon substrate 110, or may be a pattern of porous regions formed in the top surface of the silicon substrate 110, for example. In an exemplary embodiment, silicon substrate 110 may comprise a p-type silicon substrate and the top surface thereof may be converted into porous region 120 by electrochemical dissolution in a 40% hydrofluoric acid solution with a voltage drop applied between the wafer and the hydrofluoric acid solution to induce an anodic reaction. The voltage drop can be chosen to produce a current density of, for example, 1 microampere/cm ² to set a pore generation rate of about 0.1 nm/second. In some embodiments, the porous region may have a porosity of about 30-60%, where the porosity is defined as the volume of void space in the porous region 120 divided by the total volume of the region 120. Different porosity values can be used, with a compromise that ensures that the porous region 120 has sufficient mechanical integrity while the shear forces binding the silicon layer 130 to the porous region 120 are sufficiently weakened. The degree of porosity can also be chosen to be low enough so that the surface pores can be easily closed in a subsequent processing step. The degree of porosity in the porous region 120 can be controlled, for example, by adjusting the current used for the reaction. The thickness of the porous portion 120 can be suitably varied. In some embodiments, the porous region 120 may be a layer approximately 50-2000 nm thick.

With an n-type silicon substrate 110, the same wet etch technique described above can be used and can be assisted by shining light onto the substrate during the wet etch treatment. Photons of light can act as a catalyst to increase the etch rate, which may otherwise tend to be slower in n-type silicon.

While a wet etch is one possible method for forming the porous region 120, it is understood that other techniques can be used in other embodiments. For example, the porous region 120 can alternatively be formed by ion bombardment, for example with electrically neutral ions such as nitrogen (N ₂ ) or helium (He ₂ ). Other techniques can also be used.

After the porous region 120 is formed in the top surface of the silicon substrate 110, the pores in a top portion of the porous region 120 may be sealed by, for example, thermally annealing the semiconductor structure 100' in hydrogen (H ₂ ). The annealing temperature can be chosen high enough to collapse the top surface of porous portion 120 via a reflow process, thereby enclosing at least some of the surface pores, but low enough to reduce sintering that may tend to occur that collapse internal pores. In some embodiments, lower anneal temperatures may be used by applying an in situ chlorine (Cl 2 ) anneal to the porous region 120 prior to the hydrogen anneal. Closing the pores in the top surface of the porous region may allow the porous region 120 to serve as a good seed layer during subsequent silicon epitaxial layer 130 growth. The hydrogen anneal may also facilitate the removal of native oxides from the top surface of the porous region 120.

In some embodiments, the porous region 120 can have a high degree of porosity, such as 50%. This high degree of porosity can weaken the shear strength between the porous region 120 and the subsequently grown silicon epitaxial layer 130 .

With reference to 5B For example, a thin silicon layer 130 can be epitaxially grown on the top surface of the porous region 120 by, for example, chemical vapor deposition. The silicon layer 130 can be a thin layer with a thickness of, for example, 5-10 nm in some embodiments. The silicon layer 130 can be of sufficient thickness to ensure that the pores in the porous region 120 are completely covered. Because of the weak shear strength between porous region 120 and thin silicon layer 130, silicon layer 130 can behave as a thin membrane that is relatively free to move relative to porous region 120 when silicon layer 130 is subjected to yield stress. The silicon layer 130 is lattice-matched with the porous region 120 on which it is grown, and thus the silicon layer 130 may be a relaxed grown layer.

With reference to 5C Next, a relatively thin first silicon germanium layer 140 may be epitaxially grown on a top surface of the thin silicon layer 130. FIG. The first silicon germanium layer 140 may have a relatively high germanium concentration, such as a germanium concentration of 50 percent or more in some embodiments (ie, a Si _0.5 Ge _0.5 layer). In some embodiments, the thickness of the first silicon germanium layer 140 may be chosen such that the first silicon germanium layer 140 is grown substantially fully strained, has a low dislocation density, is thick enough so that they transfer all of their strain energy can be transferred onto the silicon layer 130 during the relaxation step, and is thin enough to relax via an anneal step. The first silicon germanium layer 140 can be thicker than the silicon layer 130 . In some embodiments, the first silicon-germanium layer may have a thickness of, for example, about 10-20 nm, assuming a germanium concentration of about 40-60%. The thickness of the first silicon-germanium layer 140 can be varied based on a number of parameters including, for example, the germanium concentration thereof and the thickness of the underlying silicon layer 130. Optimum thicknesses may exist that increase the filamentous dislocation density in the first silicon-germanium Reduce and/or minimize layer 140. The first sili zium germanium layer 140 is not lattice matched with the underlying silicon layer 130 . Thus, both the silicon layer 130 and the first silicon-germanium layer 140 can be grown in a fully stretched manner. Both the silicon layer 130 and the first silicon-germanium layer 140 may be grown substantially defect-free in some embodiments.

With reference to 5D The semiconductor structure 100 ′ can then be thermally annealed to relax the silicon layer 130 and the first silicon germanium layer 140 . This thermal anneal can be performed, for example, in situ in the epitaxial growth reactor. In an exemplary embodiment, the semiconductor structure 100' may be annealed at a temperature of 800°C for 0.5 to 30 minutes in a hydrogen ambient. After this thermal anneal is complete, both the silicon layer 130 and the first silicon germanium layer 140 may be relaxed. During growth (ie, prior to thermal annealing), the silicon layer 130 may be under yield stress and the first silicon germanium layer 140 formed thereon may be under compressive stress. As in 5D As shown, dislocations 132 may be formed along the interface between the silicon layer 130 and the first silicon germanium layer 140 as these layers relax during the thermal anneal. Layers that are under yield stress can be more prone to thread dislocation formation. The silicon layer 130 responds to the yield stress of the first silicon germanium layer 140 formed on top thereof and completely relaxes to form a large defect layer. In contrast, since the stress is channeled into the underlying silicon layer 130, the first silicon germanium layer 140 can relax with little or no failure. Consequently, the net result is that the filamentary dislocations 134, which may extend from either end of each misdislocation 132, may form generally in the silicon layer 130, and the first silicon-germanium layer 140 may have a reduced filamentary dislocation density, or even in Be essentially free of thread displacements.

As discussed above, the silicon layer 130 may tend to behave like a floating membrane since the porous region 120 may have weak shear strength with the silicon layer 130 such that the porous region 120 is somewhat compliant or "slippery" with respect to the silicon layer 130 . The silicon layer 130 can respond to the yield stress imparted to it from the first silicon-germanium layer 140 above and can relax substantially completely with the filamentary dislocations formed therein as relaxation occurs. On the other hand, because most of the stress is channeled into the silicon layer 130 during the thermal anneal, the first silicon germanium layer 140 can relax with reduced or minimal formation of defects. Thus, the silicon layer 130 can act as a sacrificial layer that facilitates the growth of a first silicon germanium layer 140 with fewer defects. If the weakened bonds were not provided, the silicon layer 130 would form a unitary structure with the underlying silicon substrate 110, and would appear as a relatively unyielding structure such that the first silicon germanium layer 140 would not be able to bear stress on the To transfer silicon layer 130 / the silicon substrate during the relaxation anneal.

With reference to 5E A second silicon germanium layer 150 may then be epitaxially grown on a top surface of the first silicon germanium layer 140 . The second silicon germanium layer 150 may have a higher germanium concentration than the first silicon germanium layer 140 . In some embodiments, very high germanium concentrations may be included in the second silicon germanium layer 150, such as germanium concentrations of 0.9 or higher (e.g., a Si _0.1 Ge _0.9 layer). In fact, in some embodiments, the second silicon germanium layer can be replaced with a pure germanium layer. The higher concentration of germanium contained in the second silicon-germanium layer 150 (or the pure germanium layer 150) may impart a yield stress to the first silicon-germanium layer 140 of lower germanium concentration below. The thickness of the second silicon germanium layer 150 can again be chosen such that the second silicon germanium layer 150 will be substantially fully stretched, will have a low dislocation density, and yet be thick enough to absorb all of its strain energy the first silicon germanium layer 140 can transfer during the relaxation step. In some embodiments, the second silicon germanium layer may have a thickness on the order of, for example, about 20-40 nm. The thickness may be chosen to be large enough so that the second silicon germanium layer 150 may be able to store sufficient strain energy such that the first silicon germanium layer 140 on which it is grown is, can relax completely in a subsequent process step. The second silicon germanium layer 150 may be thicker than the first silicon germanium layer 140 . The second silicon-germanium layer 150 is on not lattice-matched with the underlying first silicon-germanium layer 140 due to the higher germanium concentration. Consequently, the first and second silicon germanium layers 140, 150 can be grown fully stretched. The second silicon germanium layer 150 can be grown substantially free of defects.

With reference to 5F the semiconductor structure 100' can then be thermally annealed to relax the first and second silicon germanium layers 140,150. This thermal anneal can be performed, for example, in situ in the epitaxial growth reactor. In an exemplary embodiment, the semiconductor structure 100' may be annealed at a temperature of 800°C for a period of 30 seconds to 30 minutes in a hydrogen ambient. As in 5F 1, after this thermal anneal is complete, the first and second silicon germanium layers 140, 150 may be relaxed. During the thermal anneal, the first silicon germanium layer 140 may be under yield stress and the second silicon germanium layer 150 formed thereon may be under compressive stress. As these layers relax during the thermal anneal, dislocations 142 may be formed along the interface between the first and second silicon germanium layers 140,150. The filamentary dislocations 144 may be prone to form in the first silicon germanium layer 140 because of the yield stress, and the second silicon germanium layer 150 may have a lower filamentary dislocation density, or may even be substantially free of filamentary dislocations. The second silicon-germanium layer 150 can be used as a seed layer for the subsequent formation of thicker silicon-germanium or germanium layers, or alternatively can be used as a seed layer for one or more semiconductor layers serving as active regions for various semiconductor devices.

In some embodiments, the total thickness of the silicon layer 130 and the first and second silicon germanium layers 140, 150 may be less than about 50-100 nm. This can be orders of magnitude thinner than strained-relaxed silicon-germanium layers grown on bulk silicon wafers using conventional stepped growth techniques (which can be tens or hundreds of microns thick). In addition, the stretched-relaxed silicon-germanium layer 150 can have a very high germanium concentration, have a low dislocation density, and can be grown on, for example, a conventional bulk silicon substrate without the need for expensive silicon-on-insulator substrates.

The high germanium concentration, low defect, strained-relaxed silicon-germanium layers according to some embodiments of the invention can be used to enable a variety of different technologies, such as SiGe-CMOS technology n-type silicon/p- type germanium systems, or SiGe CMOS technology n-type germanium/p-type germanium systems. These technologies can be implemented on a common silicon substrate.

As mentioned above, the porous region 120 can be formed on the entire upper surface of the silicon substrate 110, and then a thin silicon layer 130 followed by a series of one or more silicon germanium layers 140, 150 can be grown thereon, the Silicon germanium layers 140, 150 may have increasing germanium concentrations, with a top silicon germanium layer having a desired germanium concentration. After this final (top) silicon germanium layer is formed, a masking layer may be formed on the top surface of the semiconductor structure and the structure etched to remove portions of the series of silicon germanium layers from selected areas of the structure , thereby exposing the silicon layer (or alternatively portions of the silicon substrate beneath the porous regions). Then layers of silicon can be epitaxially grown in some or all of the areas where the silicon-germanium layers have been removed, thereby providing a structure containing both silicon areas and silicon-germanium areas with high germanium concentration (or pure germanium areas ) formed on the same bulk silicon substrate.

It is believed that the techniques according to embodiments of the invention provide silicon germanium layers with medium germanium concentrations (e.g. germanium concentration of 40-75%) or high germanium concentrations (e.g. germanium concentrations of 75% to 100%) on a standard bulk silicon substrate which have thread dislocation densities of less than 1×10 6 /cm ² or even less than 1×10 5 /cm ² or 1×10 4 /cm ² .

Embodiments of the present invention may exploit the strain energy imbalance between two different semiconductor materials. For example, it should be noted that in 6A Material system 300 is shown in which a thick silicon-germanium layer 320 having a germanium concentration of epitaxially grown on a thick silicon layer 310 is shown. In doing so, the tension that caused by the lattice mismatch will balance in this two-layer structure with opposite signs, namely the silicon-germanium layer 320 will be in compressive stress and the silicon-germanium layer 310 will be in yield stress. In this situation, filamentary dislocations are unlikely to form in the silicon germanium layer 320 during a relaxation anneal since the silicon germanium layer 320 is under compressive stress. Whether filiform dislocations will form in the silicon layer 310 is difficult to predict.

As in 6B shown, the in 6A The situation shown can be modified so that a 30 nm thick silicon germanium layer 370 with a germanium concentration of 50% can be epitaxially grown on a 10 nm thick silicon layer 360. In this case, the strain energy of the thicker silicon germanium layer 370 is forced into the thinner silicon layer 360, which is under yield stress, to create misdislocations 362 at the interface between the two layers and filamentous dislocations 364 that extend into the silicon layer 360. whereby the silicon germanium layer 370 relaxes. 6B 14 thus shows a mechanism that can be used to guide the filamentary dislocations 364 down into the silicon layer 360. FIG. However, to achieve this, a thin silicon layer 360 that can be yielded by the silicon germanium layer 370 is required. As discussed above, in some embodiments, this may be accomplished by growing the silicon layer 360 on a porous region of a silicon substrate so that the silicon layer can act like a thin membrane that floats on the substrate.

According to further embodiments of the invention, a bottom surface of the thin silicon layer grown on the silicon substrate can be made "slippery". This can be done instead of forming the porous region in the top surface of the silicon substrate, or can be done in addition to forming the porous region. In some embodiments, the bottom surface of the silicon layer can be grown at a low temperature to form highly defective silicon that cannot bond well to the silicon substrate. The remaining part of the silicon layer can be grown at higher temperatures in an effort to limit the defects of the lower part of the thin silicon layer.

It should be understood that although the embodiments described above show an example in which a ( 2 ) or two ( 3 and 5A-5F ) silicon germanium layers are formed on a silicon substrate, in other embodiments a larger number of silicon germanium layers can be formed. For example, in another embodiment, a first Si _0.7 Ge _0.3 layer can be formed on a thin silicon layer, then a second Si _0.4 Ge _0.6 layer can be formed on the Si _0.7 Ge _0.3 layer, and then a Si _0.1 Ge _0.9 layer can be formed on the Si _0.4 Ge _0.6 layer. This "three-layer" approach can (1) help silicon-germanium layers to be grown that have thicknesses less than the maximum metastable thickness and (2) exhibit lower defect levels due to the closer lattice matching between adjacent layers. It will be appreciated that the germanium concentration of each layer may be varied from that given in the example above, that the number of layers may be in excess of three, and/or that the same approach can be used in other lattice mismatched material systems other than silicon/silicon-germanium material systems can be used.

One application for which devices formed according to embodiments of the invention may be particularly useful is in the formation of the germanium fins for FIN-FET transistors. The maximum height of the germanium ridge that can be grown relatively defect-free is a function of the germanium concentration of the underlying stretched-relaxed silicon-germanium layer. For example, a fully relaxed and defect-free Si _0.3 Ge _0.7 stretch-relaxed layer may have less than 10 nm of a defect-free germanium ridge grown thereon. This ridge height may be insufficient to support desired integration densities. In contrast, a fully relaxed and defect-free Si _0.1 Ge _0.9 stretch-relaxed layer can support more than 100 nm of defect-free germanium ridge grown thereon. This ridge height can support significantly higher integration densities. Thus, the ability to grow a relatively defect-free stretched-relaxed silicon-germanium layer with very high germanium concentration using the techniques according to embodiments of the invention may be particularly useful for this application. 7 14 is a perspective view showing a fin field effect transistor 400 that may be grown on semiconductor structures such as semiconductor structures 100 and 100' of FIGS 2-3 .

With reference to 7 , the fin field effect transistor 400 comprises a fin body 410 protruding from the top surface of the semiconductor structure 100' in a first direction D1. The fin body 410 can be formed on the second silicon germanium layer 150 of the semiconductor 100' (or a semiconductor layer formed over the silicon germanium layer 150, which is not in 7 shown), which may, for example, have a germanium concentration of 90% (or even be a pure germanium layer, as discussed above). The fin body 410 can be made of the same semiconductor material as the upper surface of the semiconductor structure 100', and therefore can also be a silicon germanium layer with a germanium concentration of 90% in this embodiment. Thus, the fin body 410 may be lattice-matched with the underlying semiconductor structure 100'. The ridge body 410 may extend longitudinally in a second direction D2 that is perpendicular to the first direction D1. A lower sidewall of the fin body 410 may be covered by a device isolation layer 450 while upper sidewalls of the fin body 410 may be exposed.

A gate electrode 430 extending in a third direction D3 perpendicular to both the first and second directions D1 and D2 is formed on and crossing the ridge body 410 . The gate electrode 430 surrounds the top surface and both top sidewalls of the fin body 410. The gate electrode 430 may be a metal layer. A gate insulating layer 440 may be interposed between the gate electrode 430 and the fin body 410 . Gate insulating layer 440 may be a metal oxide layer having a dielectric constant greater than silicon oxide. Source/drain regions doped with dopants can be arranged in the fin body 410 on both sides of the gate electrode 430 .

The part of the fin body 410 covered by the gate electrode 430 may correspond to a Chanel region.

8th 12 is a flow diagram of a method of forming a stretch-relaxed layer, according to certain embodiments of the invention. As in 8th As shown, a porous region may be formed in a surface of a semiconductor substrate (block 500) according to these methods. A semiconductor layer lattice-matched to the semiconductor substrate may then be formed on the porous region of the semiconductor substrate (block 510). Next, a second semiconductor layer that is lattice mismatched with the first semiconductor layer may be formed on the first semiconductor layer (block 520). The second semiconductor layer can be grown in a stretched manner. Then, the second semiconductor layer may be relaxed (block 530) by a relaxation method such as a thermal anneal. A third semiconductor layer that is lattice-matched with the second semiconductor layer may then optionally be formed on the second semiconductor layer (block 540). The third semiconductor layer can be grown in a stretched manner. Then, the third semiconductor layer may be relaxed (block 550) by a relaxation method such as a thermal anneal.

9 12 is a flow diagram of a method of forming a stretch-relaxed layer, according to further embodiments of the invention. As in 9 As shown, according to these methods, a first semiconductor layer lattice-matched with a compliant semiconductor substrate may be formed on the compliant semiconductor substrate (block 600). Next, a second semiconductor layer that is lattice mismatched with the first semiconductor layer may be formed on the first semiconductor layer (block 610). The first and second semiconductor layers may then be relaxed (block 620) by a relaxation process such as a thermal anneal. A third semiconductor layer that is lattice-matched with the second semiconductor layer may then optionally be formed on the second semiconductor layer (block 630). The second and third semiconductor layers may then be relaxed (block 640) by a relaxation process such as a thermal anneal.

Thus, according to embodiments of the invention, stretched-relaxed silicon-germanium layers can be formed on a bulk lattice-mismatched silicon substrate in which the stretched-relaxed silicon-germanium layer can (1) have a high germanium concentration and (2) be relatively free of filamentary dislocations can. These stretch-relaxed buffer layers can be formed to have a relatively small total thickness, such as a thickness of less than 100 nm or even a thickness of less than 50 nm can be formed using conventional chemical vapor deposition epitaxial growth processes suitable for large scale manufacturing.

Here, the thread dislocation density is defined as the number of dislocations per square centimeter. It can be seen that filamentary dislocation densities can be measured in a variety of ways, including, for example, measuring etch pit density, TEM, planar view TEM, and HR-XRD.

While the concept of the invention has been described above primarily with reference to embodiments in which one or more When stretched-relaxed silicon-germanium layers were formed on a silicon substrate, it should be understood that the techniques disclosed herein can be used in a wide variety of material systems. For example, in other embodiments, stretched-relaxed III-V compound semiconductor layers can be grown using the techniques disclosed herein, such as growing stretched-relaxed In _x Ga _1-x As layers on GaAs, growing stretched- relaxed GaAs layers on silicon substrates, and/or the growth of short wavelength II-VI or long wavelength III-V laser structures on GaAs substrates. In addition, it should be understood that the techniques used herein can be used not only to produce elongated channel layers for semiconductor devices that have higher carrier mobilities, but also for other purposes, such as changing the bandgap of a semiconductor material for optical purposes.

Claims (17)

Stretch-relaxing procedure that includes: forming (500) a porous region (120) in a surface of a semiconductor substrate (110); forming (510) a first semiconductor layer (130) lattice-matched to the semiconductor substrate (110) on the porous region (120) in the surface of the semiconductor substrate (110); forming (520) a second semiconductor layer (140) on the first semiconductor layer (130), the second semiconductor layer (140) being a strain-formed layer; relaxing (530) the second semiconductor layer (140); forming (540) a third semiconductor layer (150) on the relaxed second semiconductor layer (140), the third semiconductor layer (150) being a strained formed layer; and relaxing (550) the third semiconductor layer (150), wherein the semiconductor substrate (110) comprises a silicon substrate, the first semiconductor layer (130) comprises a silicon layer, the second semiconductor layer (140) comprises a first silicon germanium layer having a first germanium concentration, and the third semiconductor layer (150) comprises a second silicon Includes germanium layer having a second germanium concentration that exceeds the first germanium concentration. procedure after claim 1 wherein forming (500) the porous region (120) in the surface of the semiconductor substrate (110) comprises wet etching an upper surface of the semiconductor substrate (110) with a wet etchant having an electrical potential applied between the semiconductor substrate (110) and the wet etchant is. procedure after claim 1 , wherein the first semiconductor layer (130) is under yield stress and the second semiconductor layer (140) is under compressive stress before the second semiconductor layer (140) relaxes. procedure after claim 1 wherein the first semiconductor layer (130) is only weakly bonded to the semiconductor substrate (110) such that the first semiconductor layer (130) can move relative to the semiconductor substrate (110) when a yield stress is applied to the first semiconductor layer. procedure after claim 1 wherein the first semiconductor layer (130) is formed directly on the porous region (120) in the surface of the semiconductor substrate (110), and the second semiconductor layer (140) is formed directly on the first semiconductor layer (130). procedure after claim 1 wherein a germanium concentration of the second silicon germanium layer (150) exceeds 75 percent and a filamentary dislocation density in the second silicon germanium layer (150) is less than about 1×10 ⁵ /cm ² . procedure after claim 1 , wherein a total thickness of the silicon layer (130), the first silicon-germanium layer (140) and the second silicon-germanium layer (150) is less than 75 nm. procedure after claim 1 , further comprising: forming a fourth semiconductor layer on the third semiconductor layer (150); and forming a semiconductor device at least partially in or on the fourth semiconductor layer. A method of forming a stretched-relaxed semiconductor layer, the method comprising: forming (600) a first semiconductor layer (130) on a compliant region of a semiconductor substrate (110) lattice-matched with the first semiconductor layer (130) such that the first semiconductor layer (130) is only weakly bonded to the compliant area of the semiconductor substrate (110) and can move laterally on the surface of the compliant area of the semiconductor substrate (110); forming (610) a second semiconductor layer (140) on the first semiconductor layer (130) lattice mismatched with the first semiconductor layer (130); performing (620) a relaxation process on the second semiconductor layer (140) that creates filamentary dislocations in the first semiconductor layer (130) while the second (140) semiconductor layer remains substantially free of filamentary dislocations; forming (630) a third semiconductor layer (150) on the second semiconductor layer 140) lattice mismatched with the second semiconductor layer (140); and performing (640) a relaxation process of the third semiconductor layer (150) that generates filamentary dislocations in the second semiconductor layer (140) while the third semiconductor layer (150) remains substantially free of filamentary dislocations, the first semiconductor layer (130) comprising a silicon layer, the second semiconductor layer (140) comprises a first silicon germanium layer having a first germanium concentration, and the third semiconductor layer (150) comprises a second silicon germanium layer having a second germanium concentration that exceeds the first germanium concentration. procedure after claim 9 wherein the first semiconductor layer (130) is under yield stress before relaxation and the second semiconductor layer (140) is under compressive stress before relaxation. procedure after claim 9 , wherein forming (600) the first semiconductor layer (130) on the compliant region of the semiconductor substrate (110) that is lattice-matched with the first semiconductor layer (130) such that the first semiconductor layer (130) is only weakly attached to the compliant region of the semiconductor substrate (110) and can move laterally on the surface of the compliant region of the semiconductor substrate (110) comprises: forming a porous region (120) in a top surface of a semiconductor substrate (110) and then heating the semiconductor substrate (110) to at least closing some of the surface pores while leaving the interior of the porous region (120) porous to convert a region of the semiconductor substrate (100) into the compliant region of the semiconductor substrate (110); and then epitaxially growing the first semiconductor layer (130) on the porous region (120) by chemical vapor deposition. procedure after claim 9 wherein the compliant region of the semiconductor substrate (110) comprises a porous region (120) in a top surface of a silicon substrate (110). procedure after claim 9 wherein a germanium concentration of the second silicon germanium layer (150) exceeds 75 percent and a filamentary dislocation density in the second silicon germanium layer (150) is less than about 1×10 ⁵ /cm ² . procedure after Claim 13 , wherein a total thickness of the silicon layer (130), the first silicon-germanium layer (140) and the second silicon-germanium layer (150) is less than 75 nm. procedure after claim 12 , wherein the porous region (120) has a porosity of at least 30%. A method of forming a semiconductor device, the method comprising: forming (500) a porous region (120) in a surface of a silicon substrate (110); forming (510) a silicon layer (130) having a first germanium concentration on the porous region (120) in the surface of the silicon substrate (110); forming (520) a first silicon germanium layer (140) having a first germanium concentration on the silicon layer (130); relaxing (530) the first silicon germanium layer (140); forming (540) a second silicon germanium layer (150) having a second germanium concentration higher than the first germanium concentration on the relaxed first silicon germanium layer (140), the second silicon germanium layer ( 150) is a stretch grown layer; relaxing (550) the second silicon germanium layer (140); forming a semiconductor layer on the second silicon germanium layer (150); and forming a semiconductor device at least partially in the semiconductor layer. procedure after Claim 16 , wherein the forming (500) of the porous region (120) in the surface of the silicon substrate (110) comprises wet etching of a top surface of the silicon substrate (110) with a wet etchant with an electrical voltage between the silicon substrate (110) and the wet etchant, wherein the The method further comprises annealing the silicon substrate (110) to close at least some of the pores in the top surface of the porous region (120) prior to forming the first silicon germanium layer (140).

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