DE102015119795B4 - OPC UA specific, hierarchical coder structure for exchanging data and associated procedures - Google Patents

Abstract

Method for exchanging data streams between at least a first device (1, 2, 3) and a second device (8), the data streams being transmitted using a communication protocol via an interface according to the OPC UA standard, the data streams to be exchanged being divided into partial data streams that can be processed independently of one another divided, with a processing time of the partial data streams being determined deterministically and routed to them via dynamically allocated paths between dedicated and hierarchically arranged encoders (4) and processed in real time by means of programmable data stream processors, characterized in that encoders not required for the exchange of data streams ( 8) a hierarchical level (5) are deactivated and thus the energy consumption is minimized and the energy consumption is minimized by scaling the voltage and/or clock domains.

Description

The invention relates to a method for exchanging data streams between at least a first device and a second device, the data streams being transmitted using a communication protocol via an interface according to the OPC UA standard, the data streams to be exchanged being divided into partial data streams that can be processed independently of one another, with a processing time of the partial data streams is determined deterministically and routed to them via dynamically allocated paths between dedicated and hierarchically arranged encoders and processed in real time by means of programmable data stream processors.

The invention further relates to a real-time capable OPC UA server comprising an OPC UA specific, hierarchical coder structure, and a design method for assembling performance-specific system configurations, which uses the structural features of the OPC UA specific, hierarchical coder structure.

The OPC UA (OPC Unified Architecture, IEC62541) is an industrial machine-to-machine (M2M) communication protocol, whereby the OPC UA specification is designed for the exchange of object-oriented data models and information content that uses the OPC in the automation, which is widely used in automation to replace the next generation of industrial networks. The OPC UA expands OPC with essential properties and enables standardized and manufacturer-independent data exchange between different components, independent of the programming language and operating system. It is primarily characterized by the ability not only to transport machine data (e.g. controlled variables, measured values, parameters, etc.), but also to describe it semantically in a machine-readable manner. The OPC UA protocol according to the specification (in software and hardware) can be implemented as an OPC UA communication stack, for example. Unlike its predecessor, OPC UA does not use the proprietary COM/DCOM interfaces. The OPC UA standard protocol thus enables manufacturer-independent communication between OPC UA clients (in short: clients) and OPC UA servers (in short: servers).

The basic mechanisms and the structure of model elements are described in the OPC UA specification using object-oriented approaches (basic types, typing, inheritance, object relations), which form a graph-based data model (namespace) at runtime. The self-modeling of the OPC UA specification content is referred to as "namespace 0", in contrast, application-specific models are identified by higher namespace numbers. The namespace is a term from programming and is mainly used in object-oriented programming, with each name uniquely designating an object within such a namespace. In a different namespace, the same name can be freely used to designate another object. At the same time, the OPC UA specification defines several server-client interfaces (services) in order to be able to examine, monitor and manipulate namespaces via common network technologies (e.g. TCP/IP) between communication endpoints. These interfaces (i.e. using the specified communication stack) enable the client to interact with nodes or objects in the server’s namespace or their individual attributes.

In summary, OPC UA defines a generic object model including the associated type system. In addition to this data model, rules have been defined that describe how to transform each physical system into a UA-compliant model in order to represent it in the OPC server. Any type of device, function or system information can be described with this meta model. The base type system supports relationships between objects, called references, and multiple inheritance is supported. It is thus comparable to a modern object-oriented programming language. The base model provides object and variable types, as well as reference and data types. With this basis, OPC UA can map any type of data including its metadata and semantics. The OPC UA data model thus forms the basis for the UA information models, which, as specialized models, extend the basis and supplement certain functionalities, such as data access, alarms and conditions, historical access or programs.

The object-oriented representation of nodes in the namespace is left to the individual server implementation at runtime. However, the high degree of abstraction of the data means that large amounts of dynamic runtime memory must be available on the server's computing platform for its representation, with several hundred kilobytes of memory being required just for modeling the namespace 0. An additional 2.5 MB of persistent memory is required to store the output data of namespace 0 in the form of an XML file. While the necessary memory appears negligible on modern computing platforms with several MB/GB memory, it cannot be met by hardware-related, embedded micro-computing platforms.

In addition, neither OPC UA nor TCP/IP in the form detailed by the specification is designed for communication with hard real-time requirements, as is required by systems close to the field.

In order to provide sufficient runtime memory for the operation of an OPC UA server, powerful system-on-a-chip (SoC) computing systems with external memory connections for SDRAM and flash are currently used in practice. Such systems are widespread in the consumer market (e.g. mobile phones, tablets, etc.) and access embedded operating systems such as Linux, eCos, FreeRTOS, etc. back to provide memory allocation and network stacks. However, the given computing systems are generally not designed for hardware-related control tasks and are therefore not suitable for industrial applications, for example.

In order to still be able to operate the OPC UA server on conventional micro-computing platforms in hardware-related applications, the functional scope of the OPC UA server must be reduced in terms of the available services - such given server implementations are referred to as nano or micro profiles of OPC UA. Since only the functions of the server are reduced, but not the requirements for the data models, the storage restrictions described remain in place. External memory modules are also required here to operate an OPC UA server.

Academic attempts to implement on-chip OPC UA servers on standard micro-computing platforms are characterized by extreme limitations in functionality up to and including breach of specification conformity. Both cases therefore rule out industrial use of the OPC UA server implementations.

The use of OPC UA is currently not possible on microcontrollers designed for hardware-related control and data acquisition tasks that do not have external bus interfaces. Nevertheless, it is precisely these systems that bring a number of task-specific advantages to industrial applications. Because the extremely inexpensive architectures with a high degree of integration of analog function blocks, which are widespread in actuators and sensors, will also play a critical role in future industrial applications.

Since only high-performance SoCs can currently be used for OPC UA servers, the lack of real-time capability of the communication stacks is poorly compensated for by the already high clock rates of these systems. It is explicitly spoken of "best effort" and not hard real-time capability.

In the following, the disadvantages of the previously implemented solutions to the problems mentioned above are explained.

The SoCs suitable for OPC UA servers mainly come from the consumer market. These are primarily characterized by short life cycles of 2-5 years and low reliability requirements. The high production number of the chips alone enables low prices. However, the given systems are unsuitable for industrial applications with lifetimes of 10-20 years. Changing the chip in a product line would require a redesign of the affected systems (software and hardware) and reverification of the electrical and programmatic properties after each design change.

Given SoCs but also high-performance microcontrollers are operated with clock rates of more than 100 MHz (up to 1-2 GHz). The given high clock rates lead to considerable electromagnetic emissions, which prohibit the use of such chips in applications sensitive to emissions with strict EMI/EMC requirements, for example in the automotive industry.

The energy consumption of the currently known systems is also critical. In addition to the number of clocks/operations, the number of pins whose signal level has to be changed is decisive for the energy consumption of a chip. Therefore, SoCs with external memory and high clock speeds inherently require more energy for memory transactions than microcontrollers with low pin count and internal memory. External memory modules also lead to significantly more complex circuits and higher production costs. In addition, microcontrollers can be produced much more cheaply than SoCs due to the small space requirement.

The properties of the OPC UA communication protocol also make it necessary to allocate (several) large receive buffers for receiving and sending messages. The time required for such storage operations cannot be derived deterministically in a dynamic system and accordingly affects the real-time capability of the overall system.

Therefore, another disadvantage of the previous solutions is the lack of real-time capability of the software-based server implementations of OPC UA. Current efforts within the framework of the OPC UA Real Time Working Groups are aimed at remedying this deficiency by using TSN technologies (Time-Sensitive Networking - a real-time Ethernet standard that can be used in industry), for example in MARVELL: IEEE TSN Standards Overview & Update. USA, October 2015 company publication, and KUKA: Requirements for Time-Senitive Networks in Manufacturing. Germany, 05/22/2015. 44 pages.-Company typeface. This is for example in the WO 2011/147652 A1 or WO 2016/155856 A1 shown.

It is therefore an object of the invention to reduce the necessary memory requirements, for example for microcontrollers designed for hardware-related control and data acquisition tasks, in order to also be able to use the OPC UA communication protocol in systems close to the field, i.e. industrial applications.

A further object of the present invention is to provide a memory-efficient mapping strategy for OPC UA data structures on serial memory chips.

Furthermore, it is the object of the invention to guarantee system reaction times in such a way that hard real-time capability of the system can be guaranteed.

A further object of the invention is to reduce the energy requirement of the overall system and to ensure the strict EMI/EMC requirements for special applications, for example in the automotive industry.

The object of the invention is achieved according to the main claim 1 in terms of the method. Coders of a hierarchy level that are not required are deactivated for the exchange of data streams, and the energy consumption is thus minimized and the energy consumption is minimized by scaling the voltage and/or clock domains.

This can be done on a chip, for example in the form of a synthesizable, configurable Intellectual Property (IP) for FPGAs or ASIC implementations.

Several user-side first devices, e.g. clients, send their data, for example, via an Ethernet connection and try to interact with a user-remote second device, e.g. an OPC UA server. The data from the clients is divided into partial data streams, also referred to as partial messages, and fed to different encoders of a first hierarchical level. The encoders contain data stream processors that process the received data. Depending on the size of the partial message received and the clock rate of the data stream processor, it is possible to determine the processing time of a message in a deterministic manner and thus ensure the real-time capability of the system.

The data is forwarded from an encoder on one hierarchical level to an encoder on the next hierarchical level via bidirectional communication paths (paths for short), with the encoders on adjacent hierarchical levels being connected to one another via a bus line. Equal access to the communication buses allows the derivation of hard limits for the minimum data throughput (assuming maximum bus utilization through the bilateral communication of all bus participants, i.e. the coders).

The coders process the partial data streams independently of one another, with the processing taking place sequentially in the order in which they were received and with a determined expenditure of time. The advantage of deterministic data processing is the derivation of hard real-time characteristics depending on the number and arrangement of hierarchical encoders. As previously explained, this ensures that the data is processed in real time.

In one refinement of the proposed method, the paths between the coders in adjacent hierarchical levels are interconnected in a service-specific manner. This means that the arrangement of the encoders within and between the hierarchical levels of the structure and the scope of functions is taken from the OPC UA specification (OPC UA Facets).

In a further refinement of the method, coders of a hierarchy level which are not required for the exchange of data streams are deactivated. In this way, the energy consumption can be minimized. The coders can be put into a kind of waiting state by scaling the voltage and clock domains, i.e. by reducing the voltage or reducing the coder clock, and they can be activated again at any time as required. Dynamic scaling of the voltage and clock domains (dynamic frequency-voltage scaling) is carried out by the target technology depending on the performance requirements and utilization characteristics of the specific implementation. In this way, the energy requirement of the overall system can be reduced because this means that only the communication stages that are actually used consume energy.

In one embodiment of the method, the dynamically allocated paths between the coders in adjacent hierarchical levels are determined on the basis of features of the communication protocol in the current hierarchical level. The communication protocol contains, among other things, features that characterize the type of message to be transmitted, the system properties and the prioritization of data processing. Based on these characteristics, the most suitable paths for data exchange can be automatically determined and dynamically adjusted.

In one embodiment of the method, paths for the high-priority data processing can also be dedicated by means of prioritization mechanisms. Possible prioritization mechanisms include reserving encoder paths for a specific client, assigning a priority value to a client either during connection establishment or by a specific OPC UA service, or preferentially handling messages from a client based on such a priority, or interrupting current ones Decoding processes of a coder in order to preferentially process a higher-priority message. Prioritization mechanisms are therefore understood to mean precautions that serve to process messages from a specific remote station in preference to others or to be able to guarantee such processing within a predefined period of time. In this way, the number and the capabilities of prioritized paths and the levels of prioritization can be determined automatically according to the given requirement specifications.

A major advantage of this dynamic path allocation is that data can be transmitted and adapted in real time because the transmission times of the data can be guaranteed via the paths. This is supported by the fact that optimization criteria such as energy consumption, processing time and the current system load are taken into account when selecting the path and thus the type of coder selected at runtime.

The object of the invention is achieved on the arrangement side by a real-time capable OPC UA server according to independent claim 5 . A real-time capable OPC UA server includes a cross-protocol, hierarchical encoder structure for exchanging data between at least a first device and a second device using a communication protocol via an interface according to the OPC UA standard, with encoders being arranged in at least two hierarchy levels and encoders from adjacent hierarchy levels through paths are connected via a respective bus line between the adjacent hierarchical levels, the coders being implemented as special hardware in a chip, the paths being bidirectional communication channels, the paths being formed by on-chip network structures.

Due to the hierarchical structure, different protocol data streams can be processed in dedicated hardware encoders that can be operated in parallel and can be deactivated. This also makes it possible to implement language-specific, programmable OPC UA data stream processors with integrated memory management according to the respective system requirements. The memory requirement can be limited as a result, since extensive memories (>512 bytes) only have to be installed in coders that have to assemble messages from separately received partial streams. Another advantage is that downstream encoders can access data on demand through a connection-oriented bus or write data to be sent into the memory of the upstream encoders. Data from the namespace can be stored as a static component on non-volatile memory, while dynamic content (e.g. changed variables, node relations, etc.) is passed on transparently to the coder via an address-oriented cache.

In one refinement of the proposed coder structure, the coders are configured such that they can be activated and deactivated in a hierarchy level. The energy requirement of the overall system can thus be reduced because only the communication stages that are actually used consume energy.

In a further refinement of the encoder structure, the encoders are implemented as special hardware on a chip in order to increase processing speed and energy efficiency. In another embodiment, the coders can also be designed as protocol-specific, programmable processing units or as generic, general-purpose computing cores.

In another embodiment of the proposed coder structure, the paths are in the form of bidirectional communication channels, with the paths being in the form of on-chip network structures. However, the paths can also be designed in such a way that they connect two chips in a coupling manner, or the paths can connect several discrete on-board encoders to one another. The bidirectional communication channels allow the encoders from neighboring hierarchical levels to exchange data in both directions. A subsequent coder of a subsequent hierarchical level can thus access data from a preceding coder or also write data to the memory of preceding coders, where this can significantly reduce the memory requirement.

In order to ensure that the functionality of the design can be guaranteed, the design is checked for acceptance criteria after generation using defined test methods.

The object on which the invention is based is also achieved in terms of the method in accordance with the independent claim 11 . The number of encoders and at least one encoder type in a hierarchical level and the paths connecting the encoders, as well as the topology of the paths are selected and interconnected using software-based, parameterized tool chains according to the system's specified requirement specifications. The parameterized tool chain thus enables an automatic derivation of the necessary coder and path structures in order to compile or design an efficient system configuration. A tool chain is understood to mean a series of supporting software that can generate system-relevant, implementation-dependent configurations and data according to user specifications.

In one embodiment of this method, the tool chains optimize the OPC UA data to be transmitted on 8-bit serial memory, with the data containing static content stored on non-volatile memory and dynamic content transparently passed on to the coder by an address-oriented cache. include. The representation of the data by software-based tool chains on 8-bit serial memory makes it possible to minimize and optimize the memory requirements required for OPC UA information models through static binary namespace coding. The memory requirement can also be reduced by removing unused components of the OPC UA object model.

Furthermore, the static binary data of the namespace can be stored off-chip in non-volatile memory. However, it is also possible to store the static binary data of the on-chip namespace in non-volatile memory. A further embodiment variant of the method consists in the static binary data being transferred to volatile memory at system start in order to speed up the processing of the data.

In a further embodiment of the design method, any content of an OPC UA information model is expanded in real time in an on-chip memory for dynamic data. This means that data can also be displayed dynamically. The division of the data into a static memory and a dynamic part minimizes the amount of memory required for mapping the OPC UA information models.

In another embodiment of the method according to the invention, the OPC UA data is compressed and decompressed at runtime in order to increase the information density.

In one embodiment of the proposed method, the tool chain is used to translate OPC UA information models into a binary representation, taking into account boundary parameters of a hardware version of an application system.

On the one hand, the tool chain for the direct creation of synthesizable hardware descriptions can be provided by the manufacturer, on the other hand, the tool chain can also be created by the customer for the description of requirements and test generation, with key parameters then being transmitted to the manufacturer for further development of the specification requirements. Another possibility is to create the customer-side tool chain for the description of requirements and the generation of synthesizable hardware based on licensable, encrypted partial hardware descriptions in order to be able to use real-time-capable OPC UA servers with the proposed coder structure for microcomputer platforms in hardware-related systems at the field level using the proposed method.

The range of functions, i.e. the number of services available and the performance, i.e. the number of available data stream processors/service) can be defined automatically in synthesizable hardware descriptions. The simple scaling of the design through dynamic path allocation between encoders on bus segments allows additional encoders to be easily connected to the bus to cover specific application scenarios.

The invention will be explained in more detail below using exemplary embodiments.

• 1 Eine erfindungsgemäße Kodiererstruktur;
• 2 das Prinzip der dynamischen Kodierersuche, d.h. der dynamischen allokierten Pfade zwischen den Kodierern.

Show in the accompanying drawings

• 1 An encoder structure according to the invention;
• 2 the principle of the dynamic encoder search, ie the dynamically allocated paths between the encoders.

1 shows an OPC UA hardware architecture 100 with multiple redundant encoders 4 per hierarchy level 5, wherein the reference numerals 5.1, 5.2, 5.3, etc. indicate different hierarchical levels. At least one encoder 4, but preferably several encoders 4 are each in a hierarchy level 5 (e.g. 5.1, 5.2, 5.3, ...) arranged, the encoder 4 in adjacent hierarchy levels 5 (e.g. 5.3 and 5.4) connected by a bus line 6 with each other are connected, but the individual connections of the encoder to the bus line are not shown for the sake of clarity. The coders 4 of the individual hierarchical levels 5 (5.1, 5.2, 5.3, . . . ) communicate with one another via bidirectional paths 7. In 1 the paths 7 of the messages of the clients 1 to 3 shown by way of example are characterized by different types of lines (dotted; dash-dot; and dash-dot-dot). Solid lines show active (parallel) data transmissions in the present exemplary embodiment.

The encoders 4 with a gray background are inactive and can be activated if required.

Client 3 has reserved the encoder path marked with small circles, so that encoder 4 is only used for messages from the corresponding client (ie client 3 in the example). The transmission of the partial messages from client 3 has priority on all buses 7. The coder structure can, for example, be implemented on a chip 11 in the form of a synthesizable, configurable intellectual property (IP) for FPGAs or ASIC implementation.

The number of hierarchy levels is not limited to the in 1 number shown is limited.

2 shows the principle or method of dynamic encoder search, i.e. how the data streams to be exchanged between a client 1,2,3 and a server 8 are divided into partial data streams 9.1-9.3 that can be processed independently of one another and via dynamically allocated paths 7 between dedicated and hierarchically arranged encoders 4 forwarded to them and processed in real time by means of programmable data stream processors. while showing 2a for example the encoder H3 searches for a successor coder for the message it is processing using a key feature of the successor protocol (character string “052”) that is known to it. All encoders 4 located on the subsequent bus are queried by broadcast.

2 B shows how the coders JO and Jl of the subsequent hierarchical level 5 process the protocol contained in the message and what answers they give to the coder H3 to the query. JO refuses to connect because it is already processing a message for encoder H2. The encoder J1 allows a connection to the encoder H3.

In 2c is shown schematically how the encoder H3 sends its message to the next encoder Jl the next hierarchical level 5. This automatically activates the encoder J1. The H3 encoder can be disabled after transmission is complete to save power.

In an exemplary embodiment for implementing the encoder structure 10 according to the invention and using the method according to the invention for exchanging data streams between at least one client 1 and a server 8, the data streams being transmitted using a communication protocol via an interface according to the OPC UA standard, it is particularly advantageous , if a binary mapping strategy for OPC UA data structures on 8-bit data fields is defined. Character strings (ie strings, byte strings) are compressed by the hardware-based Huffmann coding when accessing the corresponding data fields, with this coding method being able to take into account an appropriate data size. In order to display the data without redundancy, the source symbols are coded with code words of different word lengths in Huffmann coding. The length of the code words ideally corresponds to their information content. It is particularly advantageous to implement a compiler for XML-based namespace models in the given form of representation.

In a further developed exemplary embodiment, it is particularly advantageous to implement a non-blocking, packet-based bus system on chip (network on chip) for dynamic identification and for data exchange between protocol coders of different coding levels 5.1, 5.2, etc., i.e. hierarchy levels 5. A round-robin scheduler can be used for equal access of all communication participants to the data bus. With this scheduling method, the limited resources, which usually cause the greatest difficulties when using OPC UA servers in hardware-related control tasks for industrial applications, are allocated to several competing processes. The implementation of the inventive dynamic search for successor encoders using broadcast requests with key parameters of the current data content and a bidirectional, connection-oriented data exchange between connection terminals can significantly reduce the memory requirements of such systems and implement data processing in real time.

The real-time capable OPC UA server 8 according to the invention can also be used for micro-computing platforms in hardware-related systems at the field level will. The derivation of the real-time capability is not based, for example, on the use of a TSN/IRTE specification such as IEEE802.1Q, but is ensured by the architecture of the protocol decoding hierarchy. The high- and low-priority paths of the application are always inherently real-time capable, and there are no requirements for the design of the communication channel or the network topology. In particular, this ability is not linked to the design of a server/client or master/slave communication.

In a further embodiment of the invention, the range of functions, i.e. the number of available services, and the performance, i.e. the number of available data stream processors/service are automatically defined in synthesizable hardware descriptions. The simple scaling of the design through the dynamic path allocation between the encoders on bus segments allows additional encoders 4 to be easily connected to the bus 6 in order to cover specific application scenarios.

In a further exemplary embodiment, object-oriented data models are mapped using common graphical environments from third parties in XML descriptions, with the data models then being able to be easily translated to 8-bit serial memory modules (on-chip or on-board). No further implementation processes are necessary for the commissioning of the server, in particular no knowledge of OPC UA server processes.

Reference List

1

first device, e.g. client 1

2

first device, e.g. client 2

3

first device, e.g. client 3

4

encoder

5

Hierarchy level, each 5.1, 5.2 etc.

6

bus line

7

Bidirectional Paths

8th

second device, e.g. server

9

Data streams of the respective clients (here e.g. 9.1, 9.2, 9.3)

10

OPC UA hardware architecture

11

Chip with OPC UA specified hardware

Claims (14)

Method for exchanging data streams between at least a first device (1, 2, 3) and a second device (8), the data streams being transmitted using a communication protocol via an interface according to the OPC UA standard, the data streams to be exchanged being divided into partial data streams that can be processed independently of one another divided, with a processing time of the partial data streams being determined deterministically and routed to them via dynamically allocated paths between dedicated and hierarchically arranged encoders (4) and processed in real time by means of programmable data stream processors, characterized in that encoders not required for the exchange of data streams ( 8) a hierarchical level (5) are deactivated and thus the energy consumption is minimized and the energy consumption is minimized by scaling the voltage and/or clock domains. procedure after claim 1 , characterized in that the paths (7) between coders (4) in adjacent hierarchical levels (5) are interconnected in a service-specific manner. procedure after claim 1 , characterized in that the dynamically allocated paths (7) between the coders (4) in adjacent hierarchical levels (5) are determined on the basis of features of the communication protocol in the current hierarchical level. Procedure according to one of Claims 1 , 2 or 3 , characterized in that the paths are dedicated by means of prioritization mechanisms for high-priority data processing. Realtime-capable OPC UA server comprising an OPC UA-specific, hierarchical coder structure for exchanging data between at least a first device (1, 2, 3) and a second device (8) using a communication protocol via an interface according to the OPC UA standard, with server-side coders (4) arranged in at least two hierarchical levels (5.1, 5.2) and encoders (4) from adjacent hierarchical levels are connected by paths (7) via a respective bus line (6) between the adjacent hierarchical levels (5), the encoders (4) are implemented as special hardware in a chip (11), the paths (7) being in the form of bidirectional communication channels, the paths being in the form of on-chip network structures. Real-time capable OPC UA server claim 5 , characterized in that the coders (4) are designed to be activated and deactivated in a hierarchical level (5). Real-time capable UPC UA server according to one of the Claims 5 or 6 , characterized in that the coders (4) are designed as protocol-specific, programmable processing units. Real-time capable OPC UA server according to one of the Claims 5 or 6 , characterized in that the coders (4) are designed as generic, general-purpose computing cores. Real-time capable OPC UA server claim 5 , characterized in that the paths are designed to couple two chips or the paths are designed to connect a plurality of discrete on-board encoders (4). Design method for compiling performance-specific system configurations, which takes into account the structural features of the Claims 5 until 9 uses, characterized in that the number of encoders (4) and at least one encoder type in a hierarchy level (5) and the encoders (4) connecting paths (7), and the topology of the paths by means of software-based, parameterized tool chains according to predetermined requirement specifications of the systems can be selected and interconnected. Design methods for compiling performance-specific system configurations claim 10 , characterized in that the tool chains optimize the OPC UA data to be transmitted on 8-bit serial memory, the data being static content that is stored on non-volatile memory and dynamic content that is transparent to the encoders (4) through an address-oriented cache be passed on include. Design method for assembling performance-specific system configurations according to any of the preceding Claims 10 or 11 , characterized in that any contents of an OPC UA information model are expanded in real time in an on-chip memory for dynamic data. Design method for assembling performance-specific system configurations according to any of the preceding Claims 10 until 12 , characterized in that the OPC UA data is compressed and decompressed at runtime. Design method for assembling performance-specific system configurations according to any of the preceding Claims 10 until 13 , characterized in that the tool chain is used to translate OPC UA information models into a binary representation, taking into account boundary parameters of a hardware version of an application system.

Images