DE102015119201A1 - A method of configuring an interface unit of a computer system - Google Patents

Abstract

A method of configuring an interface unit of a computer system having a first processor and a second processor deposited on the interface unit, wherein a data connection is established between the first processor and the second processor and the interface unit comprises at least one input data channel and one output data channel. A periphery of the computer system is arranged to store input data in the input data channel and to read output data from the output data channel, and the second processor is arranged to read the input data from the input data channel and store output data in the output data channel. A sequence of processor instructions for the second processor is created such that a number of subsequences are created, wherein a first subsequence represents a routine for reading in and processing at least the data stored in the first input data channel and a second subsequence is a routine for reading and processing at least represents the data stored in a second input data channel or represents a routine for processing data generated by the first processor and for storing the processed data in the first output data channel, the sequence is created by assembling the subsequences and the sequence is loaded onto the second processor.

Description

Objects of the invention described below are a method for configuring an interface unit of a computer system according to the preamble of patent claim 1 and a computer system according to the preamble of patent claim 12.

Many computer systems have interface units for data exchange between a main processor and peripheral devices. Such an interface unit can be designed, for example, as a pluggable I / O card. Many interface units are equipped with their own processors for processing incoming and outgoing data, with some interface units making it possible to flexibly adapt the programming of the processor stored on the interface unit to the requirements of the program executed by the main processor.

For example, Digi International Inc. offers a user-programmable interface unit under the product name RabbitCore RCM4100. Another known approach is to deposit a variety of program functions for the processing of incoming and outgoing data persistently on the interface unit. Such an approach describes, for example, the document US 6,189,052 B2 ,

If the computer system is intended to process the program executed by the main processor in hard real time, then the processes running on the computer system, in particular also the processes executed by the processor stored on the interface unit, must be guaranteed to be completed within a predefined period of time. The processor on the interface unit should therefore operate efficiently, i. The largest possible proportion of the processor instructions executed by him should be purposefully linked to the program-specific processing of incoming and outgoing data. Furthermore, the processor stored on the interface unit should work as deterministically as possible, ie have a low jitter, so that the time required for the execution of processes can be estimated sufficiently well.

Against this background, it is an object of the invention to develop the state of the art. In particular, it is an object of the invention to provide a method of configuring an interface unit of a computer system which ensures fast and low-jitter execution of the program code stored on one or more processors of the interface unit for processing data exchanged between a main processor and a peripheral of the computer system.

The object is achieved by a method having the features of patent claim 1. Advantageous embodiments of the invention are the subject of dependent claims.

The invention accordingly provides a method for configuring an interface unit of a computer system, wherein the computer system has a first processor and a first data connection between the first processor and the interface unit and a second processor is deposited or deposited on the interface unit. The interface unit has at least two data channels, wherein a first input data channel is designed as a data channel for storing input data and a first output data channel as a data channel for storing output data. Furthermore, a periphery of the computer system is set up such that the periphery comprises a number of peripheral devices and the periphery is configured to deposit input data in the first input data channel or read out output data from the first output data channel by means of a second data connection. The interface unit is configured to provide a data connection for reading out the input data stored in the first input data channel by the second processor and for providing a data connection for storing output data in the first output data channel by the second processor. A computer program is deposited on the computer system and the first processor is programmed to execute the computer program and to assign, during the execution of the computer program, a value to a variable of the computer program defined by the input data stored in the first input data channel.

According to the invention, it is provided that a sequence of processor commands is created and loaded onto the second processor, after the sequence has been loaded onto the second processor, the processing of the computer program by the first processor and the execution of the sequence by the second processor are started and during processing the sequence of the value defined by the data stored in the first input data channel is written to a first memory address. The sequence of processor instructions is generated in such a way that a number of subsequences of processor instructions are created, a first subsequence representing a routine for reading in and processing at least the data stored in the first input data channel, and a second subsequence for reading a routine and processing at least the data stored in a second input data channel or represents a routine for processing data generated by the first processor and for storing the processed data in the first output data channel, and the sequence is created by assembling the subsequences.

A subsequence in an embodiment of the method according to the invention is a sequence of processor instructions executable by the second processor, which in their entirety constitute a routine for forwarding input data, i. a routine for reading out the input data from an input data channel and storing the read-out input data at a memory address readable by the first processor, or which in its entirety constitute a routine for forwarding output data, i. a routine for reading out the output data from a memory address which can be written by the first processor and for storing the read-out output data in an output data channel. In another embodiment of the method according to the invention, a subsequence additionally means information which uniquely defines a sequence of processor instructions which can be executed by the second processor, wherein the processor instructions defined by the subsequence in their entirety each include a routine for forwarding input data or form output data. In the latter embodiment, each subsequence is initially in the form of such information and is translated into a sequence of processor instructions executable by the second processor prior to loading the sequence onto the second processor. In particular, in one embodiment of the invention, each subsequence is initially in the form of source code automatically written by a processor of the computer system in a high-level language, and each subsequence is compiled for the second processor prior to loading the sequence onto the second processor.

Input data and output data can be forwarded by a sequence in unchanged form. However, a sequence may also include processor instructions to process or process read-in data and to forward the read-in data in processed or processed form.

According to the invention, a sequence is to be understood as a sequence of subsequences created by combining subsequences, regardless of whether the subsequences are present as a sequence of processor instructions executable by the second processor or in the form of information defining a sequence of processor instructions.

Input data is understood to mean data generated by a peripheral component of the computer system and intended for processing by the computer program executed by the main processor. Examples of input data are measured values of a sensor or a real load integrated into an automotive simulation. An input data channel is a data channel of the interface unit established for storing input data through a peripheral component. Output data is understood to be data generated by the computer program and intended to be read by a peripheral component. Examples of output data are control commands for an actuator of a real load integrated in an automotive simulation. An output data channel is a data channel of the interface unit established for storing output data for reading by a peripheral component.

An advantage of the method according to the invention is that the routine executed by the second processor for processing input data and output data is created on the first processor, which is also supplied with the processing of the computer program. In a preferred embodiment of the method, different subroutines of the computer program, which exchange data with the periphery during execution of the computer program, each create its own subsequence corresponding to the requirements of the respective subroutine. The sequence loaded on the second processor is thereby always adapted to the individual requirements of the computer program stored on the first processor. This eliminates the need to maintain a large number of data processing, processing and routing capabilities persistently on the second processor. During execution of the computer program, the second processor successively operates the sequence, i. executes the processor instructions contained in the sequence in the order received, and invests little computational capacity, in particular no computational capacity, in the execution of unproductive, i. not directly expedient, processor instructions such as jump instructions and function calls. Furthermore, eliminating the need for processor-side optimization arrangements to speed up the processing of stored on the second processor program code, for example by caching, whereby a deterministic processing of the sequence is ensured by the second processor.

Another advantage of the invention is a cost reduction over known from the prior art solutions. Because the second processor only needs to process the sequence of processor instructions successively, it is sufficiently fast Processing the sequence guaranteed even when using a technically simple, inexpensive processor on the interface unit.

Preferably, the computer program includes at least a first I / O driver and a second I / O driver, wherein the first I / O driver creates the first subsequence and the second I / O driver creates the second subsequence. In the context of the invention, an I / O driver is to be understood as a subroutine of a task of the computer program, wherein the I / O driver includes a subroutine for the exchange of data between the task and the peripheral.

Particularly preferably, a configuration phase of the computer system is started before the start of the processing of the computer program, wherein a software instance generates the sequence during the configuration phase, wherein the sequence is empty immediately after being generated by the software instance, ie no processor instructions yet contain any processor-defining information and wherein the first I / O driver writes the first subsequence into the sequence and the second I / O driver writes the second subsequence into the sequence. In this embodiment, the software instance generates the sequence as an object adapted to receive a number of subsequences.

In a preferred embodiment, the sequence is automatically optimized by a software instance before loading the sequence onto the second processor. An optimization of the sequence is to be understood in particular as the cleaning up of the sequence of redundant processor instructions, for example by removing redundant processor instructions or by inserting a command to execute a strobe. Due to the independent creation of the individual subsequences, redundant processor instructions in the not yet optimized sequence can not be ruled out.

A strobe is understood to mean that at least two processor instructions for issuing a date, i. at least a first processor command and a second processor command for writing a value to a memory address, not immediately after the respective processor command by the second processor are performed, but the first value to be written according to the first processor command and the second value to be written according to the second processor command first, and that when the strobe is executed by the second processor, the first value and the second value are written simultaneously or immediately one after the other. A strobe thus causes a synchronization of the output of data of a sequence.

Particularly preferably, the subsequences are created such that the sequence has a minimized number of jump instructions, in particular no jump instructions. Further preferably, the creation of the subsequences takes place in such a way that the sequence contains no function calls.

Furthermore, the second processor is preferably set up or is set up to use no caching during the processing of the sequence, so that the time required for the execution of the sequence results unambiguously from the number of processor instructions contained in the sequence and from the timing of the second processor.

In an advantageous embodiment of the method, the interface unit has at least two second processors operating in parallel, an individual sequence being created for each second processor. A second processor in this embodiment is understood to mean any processor deposited on the interface unit, which has the characteristics of the second processor defined in one of the methods claimed in claims 1 to 6 and which is provided according to one of the claims 1 to 6 processed method processed sequence of processor commands to work off.

Particularly preferably, the interface unit has an FPGA, and the second processors deposited on the interface unit are or will be implemented as softcores on the FPGA, in particular in such a way that the softcores are / are implemented as flow control processors.

In an advantageous embodiment of the method, the computer program includes more than one task, and each second processor is uniquely assigned to a task, the sequence loaded on a particular second processor containing only subsequences of I / O drivers of the task assigned to the particular processor is.

Preferably, each task is assigned a priority with at least one I / O driver, and the second processors are preferably assigned to the task with the highest priority.

In a further preferred refinement, the execution of the sequence on a second processor is started by a trigger signal, with a second processor processing the sequence exactly once after registration of a trigger signal by the second processor. The trigger signal is thereby transmitted by an I / O driver or at predefined times by a timer, i. a timer, generated.

The invention furthermore relates to a computer system having a first processor and an interface unit with a second processor deposited on the interface unit, which is set up to carry out, by means of the first processor, a method for configuring the interface unit claimed by one of claims 1 to 11. Preferably, the computer system is designed to process a computer program by means of the first processor in hard real time, in particular wherein the computer system is designed as a hardware-in-the-loop simulator or as a rapid control prototyping system.

In the context of the invention, a hardware-in-the-loop simulator is to be understood as meaning, in particular, a computer system which is set up and provided for being connected to the data inputs and data outputs of an embedded system, for example an electronic control unit or a mechatronic component , and which is further adapted, in particular also with regard to the hardware installed in the computer system, in order to simulate the real environment of the embedded system in hard real-time.

In the context of the invention, a rapid-control prototyping system is to be understood in particular as a portable computer system that is set up and intended to be integrated in a network of electronic control units, for example in an automobile, in the network temporarily as an electronic control unit and to exchange data with electronic control units in hard real-time, to read data from sensors and to control actuators.

The invention will be explained in more detail with reference to the drawings. Here similar parts are labeled with identical names. The illustrated embodiments are highly schematic, i. the distances and the lateral and the vertical extensions are not to scale and, unless stated otherwise, have no derivable geometrical relations to one another. Show in it

1 a schematic view of a trained for carrying out the method according to the invention computer system,

2 a representation of method steps for creating a sequence of processor commands and

3 a representation of the creation of multiple sequences by the first processor and their distribution to multiple second processors.

The figure of the figure shows a schematic representation of a hardware-in-the-loop simulator, short HIL, designed computer system HIL. The computer system HIL has a first processor CN and an interface unit IO designed as a pluggable I / O card, and a serial first data connection DL1 is set up between the first processor CN and the interface unit IO. The computer system HIL is set up to process in hard real time by means of the first processor CN a computer program for simulating an environment of an electronic control unit ECU, for example an automotive control unit for testing the software of the control unit ECU.

An FPGA is installed on the interface unit IO, and the interface unit has eight data channels, of which four input data channels IN1,..., IN4 and four output data channels OUT1,..., OUT4. On the FPGA, five interface processors ION1, ..., ION5 are stored as second processors, which are programmed as so-called softcores into the logic circuit of the FPGA.

The term interface processor is used below synonymously with the term "second processor" according to the patent claims. The term interface processor is used solely for the purpose of facilitating the readability of the following explanations and, taken as such, does not include any technical specifications, unless expressly stated.

The implementation of a softcore in a programmable logic circuit, such as an FPGA, is well known to those skilled in the art. The five interface processors ION1, ..., ION5 are implemented identically and configured as flow control processors (FCPs), i. Their design and instruction set are optimized for the routing, processing and processing of input data and output data. Each of the interface processors ION1, ..., ION5 has only one arithmetic core and is designed and provided to process a sequence of processor instructions successively. In particular, the interface processors ION1, ..., ION5 have no devices for speeding up the execution of a command sequence, as they have many processors, such as caching or parallelization by multiple cores. Research has shown that it is possible to implement eight FCPs that are so simple in design as softcores on an FPGA.

In a preferred embodiment, the interface processors ION1, ..., ION5 are not stored persistently on the FPGA, but are as Kompilat stored on a flash memory of the computer system HIL and are programmed in a configuration phase of the computer system HIL before the start of the processing of the computer program in the logic circuit of the FPGA, the interface processors ION1, ..., ION5 are stored as unprogrammed processors, ie The interface processors ION1, ..., ION5 initially no processor instructions are stored.

The interface unit IO is connected to a peripheral PER via a second data link DL2. The peripheral PER includes three peripheral components: a real load THR, an electronic control unit ECU and an expansion box XB. The second data connection DL2 is set up as a plurality of cable connections laid between the peripheral components THR, ECU, XB of the peripheral PER and the data channels IN1, ..., IN4, OUT1, ..., OUT4 of the interface unit IO. The real load THR is, for example, a throttle valve of an automobile. Since the computer program is not able to simulate a throttle, the throttle is integrated as a physical component in the simulation. The first processor CN generates according to the specifications of the computer program, a control signal for an actuator of the real load THR, and the control signal is transmitted via a data output OUT1 of the interface unit IO to the actuator. A sensor of the real load THR is read out via a data input IN1 of the interface unit IO and the read-out sensor signal is utilized by the first processor CN on the basis of the specifications of the computer program.

The electronic control unit ECU is a physical control unit, for example an automotive control unit, which is integrated in the simulation in order to check the software stored on the electronic control unit ECU for correct functioning. To this end, the first processor CN simulates in hard real-time the surroundings of the electronic control unit, in particular further electronic control units, sensors, actuators and driving maneuvers of the simulated vehicle, and exchanges data with the electronic control unit ECU. The electronic control unit is set up to read in output data generated from two output data channels OUT2, OUT3 of the interface unit IO by the first processor CN, and is set up to store input data generated in an input data channel IN4 by the electronic control unit for utilization by the first processor CN For example, a control signal for a simulated by the first processor CN component.

The expansion box XB contains further computer components in the form of plug-in printed circuit boards that assist the first processor CN during the execution of the computer program. The extension box XB is set up to read in output data from an output data channel OUT4 and to store input data in an input data channel IN2.

The interface processors ION1, ..., ION5 are connected to the first data connection DL1 via a first multiplexer MUX1 programmed into the logic circuit of the FPGA and driven by a first arbiter, not shown, and the first arbiter is set up to the first one by means of the first multiplexer To grant processor CN access to exactly one interface processor ION1, ..., ION5. The interface processors ION1,..., ION5 are furthermore connected to the data channels IN1,..., IN4, OUT1,..., OUT4 via a demultiplexer MUX2 and a second multiplexer MUX3, and a second arbiter (not shown) is arranged to to grant access to one of the data channels IN1, ..., IN4, OUT1, ..., OUT4 to one of the interface processors ION1,..., ION5 by driving the demultiplexer MUX2 and the second multiplexer MUX3.

In each of the four input data channels IN1,..., IN4 there is deposited an unillustrated processor arranged to receive an input data from a peripheral component of the peripheral PER and to read the input data to one of the interface processors ION1,..., ION4 for reading out To make available. In each of the four output data channels OUT1, ..., OUT4, there is stored an unillustrated processor adapted to receive an output data from one of the interface processors ION1, ..., ION5 and to a peripheral component of the peripheral PER for reading out put.

The picture of the 2 shows method steps for creating a sequence of processor instructions for an interface processor ION1 in a preferred embodiment of the method according to the invention. A first task TSK1 of the computer program stored on the first processor CN includes a first I / O driver IOD1, a second I / O driver IOD2 and a third I / O driver IOD3. In a first method step S1, each I / O driver IOD1, IOD2, IOD3 of the first task TSK1 generates a subsequence for execution by the interface processor ION1. The first I / O driver IOD1 creates a first subsequence SUB1, the second I / O driver IOD2 creates a second subsequence SUB2, and the third I / O driver IOD3 creates a third subsequence SUB3.

The first subsequence SUB1, the second subsequence SUB2 and the third subsequence SUB3 each provide a routine for forwarding data stored in an input data channel Input data for storage at a memory address which can be read out by the first processor CN or for transmission of output data generated by the first processor CN for storage in an output data channel. The subsequences SUB1, SUB2, SUB3 contain no function calls.

After performing the first method step, the first subsequence SUB1, the second subsequence SUB2 and the third subsequence SUB3 are in the form of a sequence of program instructions formulated in a high-level language, for example a sequence of C ++ commands. Each subsequence SUB1, SUB2, SUB3 contains at least one program instruction for forwarding an input datum or an output datum, for example a command from the family of memcpy commands, as defined in the C ++ language. An example is the command memcpy32, whose syntax in the simplest form is as follows:
memcpy32 (add2, add1, n);

The instruction reads, starting at the memory address add1, a number of n data of the word length 32 bits and writes the data to the memory address add2. If the command is for forwarding an input data, then add1 is a memory address in an input data channel, that is, a memory address writable and readable by the processor stored in an input data channel, and add2 is a memory address readable by the first processor CN. If the command is for forwarding an output data, then add1 is a memory address writable by the first processor CN, and add2 is a memory address in an output data channel, that is, a memory address writable and readable by the processor stored in an output data channel. Each I / O driver IOD1, ..., IOD3 creates the memcpy32 relative memory address instructions as values for add1 and add2 in relation to a memory address defined as zero within the respective I / O driver IOD1, ..., IOD3 ,

Each subsequence SUB1, SUB2, SUB3 is automatically created based on the requirements of the task TSK1, in which the respective I / O driver is integrated, as well as on the basis of user-defined configuration data and is adapted to the individual requirements of the task TSK1. In an exemplary application, the first I / O driver IOD1 is provided to read out on a input data channel IN1 a control signal for pulse width modulation of an actuator signal, and a user can set by means of a configuration software, whether only the duty cycle of the actuator signal is to be modulated or the Duty cycle and the frequency of the actuator signal to be modulated. In the first case, the first I / O driver IOD1 only writes a memcpy32 command for forwarding a duty setpoint to the first subsequence SUB1. In the second case, the first I / O driver IOD1 writes two memcpy32 instructions into the first subsequence SUB1, one for passing a reference for the duty cycle and one for forwarding a reference for the frequency. The first I / O driver IOD1 may create a subsequence SUB1 such that it contains only one or more memcpy32 instructions. The first I / O driver IOD1 can optionally also write, in addition to a number of memcpy32 instructions, further program instructions for processing or processing the input data into the first subsequence SUB1.

Similarly, each subsequence SUB1, ..., SUB3 consists of at least a number of memcpy32 instructions, but may optionally include other program instructions for conditioning or processing input data or output data, such as program instructions to scale or equalize input data or output data ,

In a second method step S2, the subsequences SUB1, SUB2, SUB3 are combined to form a sequence SEQ1. To do this, a software instance first creates a software object SEQO. The software object SEQO contains a header field H with information about the first I / O driver IOD1, the second I / O driver IOD2 and the third I / O driver IOD3, and the software object SEQO is arranged to store a number in one High-level language formulated sub-sequences SUB1, ..., SUB3 record and save. The I / O drivers of the first task TSK1 then successively write their respective subsequences SUB1, ..., SUB3 into the software object SEQ0, i. First, the first I / O driver IOD1 writes the first subsequence SUB1 into the software object SEQO, then the second I / O driver IOD2 writes the second subsequence SUB2 into the software object SEQO after the first subsequence SUB1, then writes the third I / O Driver IOD3, the third sub-sequence SUB3 in the software object SEQO after the second sub-sequence SUB2. The software object SEQO now includes the header field H and a first sequence SEQ1, composed of the first subsequence SUB1, the second subsequence SUB2 and the third subsequence SUB3.

In a third method step S3, the sequence SEQ1 is processed in order to be loaded onto an interface processor ION1. In a first optimization, the relative memory addresses in the memcpy32 instructions are replaced by absolute memory addresses, with the information necessary for this being taken from header field H, and the first sequence SEQ1 is supplemented with a command to execute a strobe. After completion of the first optimization will be the first Sequence SEQ1 translated into an executable by an interface processor ION1 executable sequence of processor commands. In a second optimization, redundant processor instructions are removed from the first sequence SEQ1.

After completion of the third method step S3, the first sequence SEQ1 is present as a sequence of twelve processor instructions COM1,..., COM12, wherein the first subsequence SUB1, the second subsequence SUB2 and the third subsequence SUB3 are each contained as a contiguous sequence of processor instructions. Three consecutive processor instructions COM1, ..., COM3 map the functionality of the first subsequence SUB1, four successive processor instructions COM4, ..., COM7 the functionality of the second subsequence SUB2 and four further successive processor instructions COM8, ..., COM11 the functionality of the third subsequence SUB3. A strobe command COM12 terminating the first sequence SEQ1 effects the synchronous output of the data of the first subsequence SUB1, the second subsequence SUB2 and the third subsequence SUB3. The successive execution of the first sequence SEQ1 by a second processor ION1 thus corresponds to a successive execution of the first subsequence SUB1, the second subsequence SUB2 and the third subsequence SUB3. The first sequence SEQ1 contains no function calls and no jump instructions.

In a fourth method step S4, the optimized sequence SEQ1 is loaded onto an interface processor ION1 assigned to the task TSK1.

The picture of the 3 shows the creation according to the invention of several sequences SEQ1, ..., SEQ5 and the distribution of the sequences SEQ1, ..., SEQ5 on several interface processors ION1, ..., ION5. The creation of each sequence SEQ1, ..., SEQ5 is carried out in the same way as the creation of the first sequence SEQ1, as in the description of FIG 2 described. In the illustrated embodiment, the computer program stored on the first processor CN includes a first task TSK1 with a first I / O driver IOD1, a second I / O driver IOD2 and a third I / O driver IOD3, a second task TSK2 with a fourth I / O driver IOD4 and a fifth I / O driver IOD5, and a third task TSK3 with a sixth I / O driver IOD6, a seventh I / O driver IOD7, and an eighth I / O driver IOD8 , The first task TSK1, the second task TSK2 and the third task TSK3 are each assigned a priority defined by a parameter PRIO, the value of PRIO being a natural number and the value PRIO = 1 indicating a task with the lowest possible priority. A software instance assigns at least one interface processor ION1, ..., ION5 during the configuration phase of each task TSK1, TSK2, TSK3, which has at least one I / O driver IOD1,..., IOD8. The number of interface processors ION1,..., ION5 stored on the interface unit IO is accordingly an upper limit for the number of tasks TSK1,..., TSK3 on the first processor CN which can be set up to exchange data with the peripheral PER , ie to store output data in an output data channel OUT1, ..., OUT4 or to read input data from an input data channel IN1, ..., IN4. The software instance is adapted to prefer highly prioritized tasks in the allocation of interface processors ION1,..., ION5, ie to allocate interface processors ION1,..., ION5 not yet assigned to a task with high priority. Upon completion of the configuration phase, each interface processor ION1, ..., ION5 is uniquely assigned to a task TSK1, ..., TSK3.

The first task TSK1 and the second task TSK2 are each assigned the lowest priority (PRIO = 1), and therefore only one interface processor ION1,..., ION5 is assigned to both. A first interface processor ION1 is assigned to the first task TSK1. The I / O drivers of the first task TSK1, that is, the first I / O driver IOD1, the second I / O driver IOD2, and the third I / O driver IOD3, jointly create a first sequence SEQ1, i. the first sequence SEQ1 contains the subsequences created by the first I / O driver IOD1, the second I / O driver IOD2 and the third I / O driver IOD3. A second interface processor ION2 is assigned to the second task TSK2. The I / O drivers of the second task TSK2, that is, the fourth I / O driver IOD4 and the fifth I / O driver IOD5, jointly create a second sequence SEQ2, i. the second sequence SEQ2 contains the subsequences created by the fourth I / O driver IOD4 and the fifth I / O driver IOD5.

The third task TSK3 is prioritized higher than the first task TSK1 and the second task TSK2, for example because the fast processing of the input data read in by the third task TSK3 is of particular importance or because the third task TSK3 processes large amounts of input data and therefore many computation resources required to process the input data read in by the third task TSK3 in hard real time. The priority assigned to the third task is PRIO = 5. The third task TSK3 is therefore assigned three interface processors ION3, ION4, ION5, so that the I / O drivers of the third task TSK3, ie the sixth I / O driver IOD6, the seventh I / O driver IOD7 and the eighth I / O driver IOD8, each have their own interface processor ION1, ..., ION5 for depositing a sequence SEQ3, ..., SEQ5 is available, and for each I / O driver the third task TSK3 a separate sequence SEQ3, ..., SEQ5 is created. The sixth I / O driver IOD6 created a subsequence and writes the subsequence into a third sequence SEQ3. The seventh I / O driver creates a subsequence and writes the subsequence into a fourth sequence SEQ4. The eighth I / O driver creates a subsequence and writes the subsequence into a fifth sequence SEQ5. The third sequence SEQ3, the fourth sequence SEQ4 and the fifth sequence SEQ5 each contain only a single subsequence.

The generated sequences SEQ1, ..., SEQ5 are, as in the description of 2 are converted and optimized into an executable sequence of processor instructions readable and executable for an interface processor ION1, ..., ION5, and the converted and optimized sequences SEQ1, ..., SEQ5 are loaded onto the interface processors ION1, ..., ION5. The first interface processor ION1 is assigned to the first task TSK1, the first sequence SEQ1 is therefore loaded onto the first interface processor ION1. The second interface processor ION2 is assigned to the second task TSK2, the second sequence SEQ2 is therefore loaded onto the second interface processor ION2. The third interface processor ION3, the fourth interface processor ION4 and the fifth interface processor ION5 are each assigned to the third task TSK3. The third sequence SEQ3 is loaded on the third interface processor ION3, the fourth sequence SEQ4 on the fourth interface processor ION4 and the fifth sequence SEQ5 on the fifth interface processor ION5.

After completion of the configuration phase, the processing of the computer program by the first processor CN and the processing of the sequences SEQ1, ..., SEQ5 by the interface processors ION1, ..., ION5 is started. The sequences SEQ1, ..., SEQ5 contain processor instructions to read input data from an input data channel IN1, ..., IN4, process and write a result of the processing of the input data to a memory address readable by the first processor CN, and a task TSK1, ..., TSK3 reads out the value stored at the memory address and assigns a value to a variable of the computer program based on the value stored at the memory address. The sequences SEQ1, ..., SEQ5 further contain processor instructions to read values from a memory address writable by the first processor CN, to process the read-out value and to store the results of the processing as output data in an output data channel OUT1, ..., OUT4 , Each sequence SEQ1, ..., SEQ5 is adapted individually and to the requirements of the respective task TSK1, ..., TSK3, and each interface processor ION1, ..., ION5 operates on the sequence SEQ1, ..., SEQ5 stored on it successively from. Due to the parallel processing of the sequences SEQ1, ..., SEQ5 on several interface processors ION1, ..., ION5, it is also excluded that the processing of a sequence SEQ1, ..., SEQ5 in favor of the processing of another sequence SEQ1, .. ., SEQ5 a higher priority task TSK1, ..., TSK3 is interrupted. In this way, a fast, i. Time-optimized, and low-jitter processing of the sequences SEQ1, ..., SEQ5 ensured.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 6189052 B2 [0003]

Claims (16)

Method for configuring an interface unit (IO) of a computer system (HIL), wherein the computer system (HIL) has a first processor (CN) and a first data connection (DL1) between the first processor (CN) and the interface unit (IO) and on the Interface unit (IO) a second processor (ION1, ..., ION5) is deposited or deposited, wherein the interface unit (IO) at least two data channels (IN1, ..., IN4, OUT1, ..., OUT4), wherein a first input data channel (IN1, ..., IN4) is configured as a data channel for storing input data, and a first output data channel (OUT1, ..., OUT4) is configured as a data channel for storing output data, wherein a periphery (PER) of the Computer system (HIL) is set up such that the periphery (PER) comprises a number of peripheral devices (THR, ECU, XB) and the periphery (PER) is designed to receive data by means of a second data link (DL2) input data channel (IN1,..., IN4) or to read out output data from the first output data channel (OUT1,..., OUT4), wherein the interface unit (IO) is designed to provide a data connection for reading out data in the first input data channel (IN1,..., OUT4). IN1, ..., IN4) provided by the second processor (ION1, ..., ION5) and a data connection for storing output data in the first output data channel (OUT1, ..., OUT4) by the second processor ( ION1, ..., ION5), wherein a computer program is stored on the computer system (HIL) and the first processor (CN) is programmed to execute the computer program and assign a value to a variable of the computer program during the execution of the computer program is defined by the input data stored in the first input data channel (IN1, ..., IN4), wherein a sequence (SEQ1, ..., SEQ5) is created by processor instructions and stored on the zw After loading the sequence (SEQ1, ..., SEQ5) onto the second processor (ION1,..., ION5), the processing of the computer program by the first processor (FIG. CN) and the processing of the sequence (SEQ1, ..., SEQ5) by the second processor (ION1, ..., ION5) is started and during the execution of the sequence (SEQ1, ..., SEQ5) by the in the first input data channel (IN1, ..., IN4) data written to a first memory address is written, characterized in that a number of sub-sequences (SUB1, ..., SUB3) of processor commands is created, wherein a first sub-sequence (SUB1 , ... SUB5) represents a routine for reading in and processing at least the data stored in the first input data channel (IN1, ..., IN4) and a second subsequence (SUB1, ..., IN5) representing a routine for reading in and processing at least the data stored in a second input data channel (IN1, ..., IN4) or ei 3 is a routine for processing data generated by the first processor and storing the processed data in the first output data channel (OUT1, ..., OUT4), and by assembling the subsequences (SUB1, ..., SUB5), the sequence (SEQ , ..., SEQ5s) is created.  The method of claim 1, wherein the computer program includes at least a first I / O driver (IOD1, ..., IOD8) and a second I / O driver (IOD1, ..., IOD8), the first I / O Driver (IOD1, ..., IOD8) creates the first subsequence (SUB1, ..., SUB3) and the second I / O driver (IOD1, ..., IOD8) creates the second subsequence (SUB1, ... , SUB3).  Method according to Claim 2, wherein a configuration phase is started before the start of the processing of the computer program, during the configuration phase, a software instance generates the sequence (SEQ1, ..., SEQ5), the sequence (SEQ1, ..., SEQ5) being empty immediately after being generated by the software entity and the first I / O driver (IOD1, ..., IOD8) writes the first subsequence (SUB1, ..., IUB3) in the sequence (SEQ1, ..., SEQ5) and the second I / O driver (IOD1, ..., IOD8) writes the second subsequence (SUB1, ..., SUB3) into the sequence (SEQ1, ..., SEQ5).  Method according to one of the preceding claims, wherein the sequence (SEQ1, ..., SEQ5) before the loading of the sequence (SEQ1, ..., SEQ5) on the second processor (ION1, ..., ION5) is optimized, in particular in that redundant instructions are removed from the sequence or redundant memory accesses are removed from the sequence or a processor instruction is added to the sequence to execute a strobe.  Method according to one of the preceding claims, wherein the sequence (SEQ1, ..., SEQ5) contains a minimized number of jump instructions, in particular no jump instructions, or the sequence (SEQ1, ..., SEQ5) contains no function calls. Method according to one of the preceding claims, wherein the second processor (ION1, ..., ION5) is set up or is set up to not use caching during the execution of the sequence (SEQ1, ..., SEQ5).  Method according to one of the preceding claims, wherein the interface unit (IO) has at least two second processors (ION1, ..., ION5) and for each second processor (ION1, ..., ION5) an individual sequence (SEQ1, ... , SEQ5) is created.  The method of claim 7, wherein the interface unit (IO) comprises an FPGA and the second processors (ION1, ..., ION5) are implemented or implemented as softcores on the FPGA, in particular wherein the softcores are implemented as flow control processors or implemented.  Method according to one of claims 7 or 8, wherein the computer program includes more than one task (TSK1, ..., TSK3) and each second processor (ION1, ..., ION5) is uniquely assigned to a task, wherein the one to a certain second processor (ION1, ..., ION5) loaded sequence (SEQ1, ..., SEQ5) only subsequences (SUB1, ..., SUB3) of I / O drivers (IOD1, ..., IOD8) of the task (TSK1, ..., TSK3) to which the particular processor (ION1, ..., ION5) is assigned.  Method according to claim 9, wherein each task (TSK1, ..., TSK3) is assigned a priority with at least one I / O driver (IOD1, ..., IOD5) and the second processors (ION1, ..., ION5 ) preferably the task (TSK1, ..., TSK3) are assigned the highest priority.  Method according to one of the preceding claims, wherein the processing of the sequence (SEQ1, ..., SEQ3) on a second processor (ION1, ..., ION5) is started by a trigger signal, wherein the trigger signal by an I / O driver (IOD1, ..., ION8) or generated by a timer. Computer system (HIL) having a first processor (CN) and an interface unit (IO), wherein the interface unit (IO) has at least two data channels (IN1, ..., IN4, OUT1, ..., OUT4), wherein a first input data channel (IN1, ..., IN4) is set as a data channel for storing input data in the input data channel (IN1, ..., IN4) by a peripheral (PER) and a first output data channel (OUT1, ..., OUT4) for storage output data for a peripheral (PER), wherein the interface unit (IO) has a second processor (ION1, ..., ION5) and the interface unit (IO) is designed to provide a data connection for reading out in the first input data channel (PER). IN1, ..., IN4) provided by the second processor (ION1, ..., ION5) and a data connection for storing output data in the first output data channel (OUT1, ..., OUT4) by the second processor ( ION1, ..., ION5) in which the computer system (HIL) has a data connection (DL1) between the first processor (CN) and the second processor (ION1, ..., ION5), the computer system (HIL) being set up in order to start a processing Computer program by the first processor (CN) to start a configuration phase during the configuration phase to create a sequence (SEQ1, ..., SEQ5) of processor commands and the sequence (SEQ1, ..., SEQ5) on the second processor (ION1, ..., ION5), wherein on the first processor (CN) at least a first I / O driver (IOD1, ..., IOD5) and a second I / O driver (IOD1, ..., IOD5 ), characterized in that the computer system (HIL) is arranged to create a number of subsequences (SUB1, ..., SUB3) of processor instructions during the configuration phase, the first I / O driver (IOD1, .. ., IOD8) is set up in order during the configuration phase, a first sub-sequence (SUB1, ..., SUB3) vo n to create processor commands, the first subsequence (SUB1, ..., SUB3) representing a routine for reading in and processing at least the data stored in a first input data channel (IN1, ..., IN4), the second I / O driver (IOD1, ..., IOD8) is set up to create a second subsequence (SUB1, ..., SUB3) of processor instructions during the configuration phase, the second subsequence (SUB1, ..., SUB3) being a read-in routine and processing at least the data stored in a second input data channel (IN1, ..., IN4) or a routine for processing data generated by the first processor (CN) and storing the processed data in the first data output channel (OUT1, .. ., OUT4), and the computer system (HIL) is set up to combine the first subsequence (SUB1, ..., SUB3) and the second subsequence (SUB1, ..., SUB3) to form the sequence (SEQ1, .. ., SEQ5).  Computer system (HIL) according to claim 12, wherein the computer system (HIL) is designed to process the computer program by means of the first processor (CN) in hard real time, in particular wherein the computer system (HIL) as a hardware-in-the-loop simulator or designed as a rapid-control prototyping system.  Computer system according to claim 12 or 13, wherein the computer system (HIL) is arranged to create the sequence (SEQ1, ..., SEQ5) with a minimized number of branch instructions, in particular without branch instructions. A computer system according to any one of claims 12 to 14, wherein the second processor (ION1, ..., ION5) is arranged not to use caching in processing the sequence (SEQ1, ..., SEQ5).  Computer system (HIL) according to one of claims 12 to 15, wherein the interface unit (IO) has at least two second processors (ION1, ..., ION5) and the computer system (HIL) is set up for every second processor (ION1, .. ., ION5) to create an individual sequence (SEQ1, ..., SEQ5) and to load an individual sequence (SEQ1, ..., SEQ5) on each second processor (ION1, ..., ION5).

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