DE102015115260A1 - Method for determining an electrical conductor current flowing in an electrical conductor in a pulsed manner and power electronic module - Google Patents

Abstract

The invention relates to a method for determining an electrical conductor current (I1, I2) that flows in a pulsed fashion in an electrical conductor (1, 1a, 1b) by means of a Rogowski coil (2, 2a, 1, 1a, 1b) arranged around the electrical conductor (1, 1a, 1b). 2b), wherein between current pulses (10, 12) of the conductor current (I1, I2), which flow through the electrical conductor (1, 1a, 1b), no current flows, wherein a pulse information signal (P1, P2) the beginning (B) and the end (E) of a respective current pulse (10, 12), wherein a measurement signal (U1m, U2m) generated by the Rogowski coil (2, 2a, 2b) due to the electrical conductor current (I1, I2) is received from an integrator ( 4, 4a, 4b) in its integration memory (C, Ca, Cb) is integrated, wherein the integration of the measurement signal (U1m, U2m) of the integration memory (C, Ca, Cb), controlled by the pulse information signal (P1, P2), in the period from the end (E) of a current pulse (10, 12) to the beginning (B) of a current pulse (10, 12) immediately following Current pulse (10, 12) is deleted, wherein a current measurement signal (U1a, U2a) is generated in dependence of the value of the integration memory (C). Furthermore, the invention relates to a power electronics module (14).

Description

The invention relates to a method for determining a pulse conductor in an electrical conductor flowing electrical conductor current and a power electronics module.

From the state of the art it is generally known to determine an electric conductor current flowing through an electrical conductor by means of a Rogowski coil arranged around the electrical conductor. In 2 of the US 2014/0306690 A1 is exemplified a Rogowski coil shown, which runs around an electrical conductor, whose current flowing through it by the Rogowski coil, runs. The one wire end of the wire from which the Rogowski coil is wound is at the in the US 2014/0306690 A1 again shown Rogowski coil along the Rogowski coil returned to the other end of the wire Rogowski coil, so that it is in the 2 of the US 2014/0306690 A1 shown Rogowski coil is an open Rogowski coil, which can be easily arranged around the electrical conductor. It should be noted that in general a Rogowski coil can also be designed such that the wire end is not returned, so that the Rogowski coil is formed as a closed Rogowski coil. Furthermore, it should be noted that the Rogowski coil does not necessarily have to run in a circle around the electrical conductor, but may generally have the shape of a loop.

A Rogowski coil generates as an output signal to the time derivative dI / dt of the current flowing through the electrical conductor conductor current I proportional voltage signal, so that the output signal of the Rogowski coil must be integrated by means of an integrator in the integration memory to receive the conductor current I. In this case, especially when the conductor current I Gleichstomanteile, the problem arises that, especially if the integrator is realized in analog technology, the value of the integration memory drifts away, so that this has an increasingly deviating over time from a value of zero basic value, which leads to an inaccurate determination of the conductor current I. From the US 2014/0306690 A1 it is known to be a capacitor C1 in the US 2014/0306690 A1 forms the integration memory, electrically connect a low-pass filter in parallel.

It is an object of the invention to determine a pulse conductor in an electrical conductor flowing electrical conductor current with high accuracy.

This object is achieved by a method for determining an electrical conductor in a pulsed electric current flowing through a conductor arranged around the electrical conductor Rogowski coil, wherein between current pulses of the conductor current flowing through the electrical conductor, no current flows, a pulse information signal the Beginning and indicating the end of a respective current pulse, wherein a measurement signal generated by the Rogowski coil due to the electrical conductor current is integrated by an integrator in its integration memory, wherein integrating the measurement signal of the integration memory, controlled by the pulse information signal, in the period from the end of a current pulse until is cleared to the beginning of a current pulse immediately following this current pulse, wherein a current measurement signal is generated in dependence on the value of the integration memory.

Preferably, the current measurement signal corresponds to the value of the integration memory.

Furthermore, this object is achieved by a power electronics module having an electrical first conductor and a first power semiconductor switch electrically connected in series with the first conductor, with an electrical second conductor and a second power semiconductor switch electrically connected in series with the second conductor, the first and second power semiconductor switches being electrically are connected in series with the first power semiconductor switch, a first diode is electrically connected in anti-parallel and the second power semiconductor switch, a second diode is electrically connected in anti-parallel, electrically between the first and second power semiconductor switch, an electrical Mittenschaltungsknoten electrically connected to an electrical third conductor is, is arranged, wherein the power electronic module electrically connected to a control input of the first power semiconductor switch first drive means a It is designed to switch the first power semiconductor switch on and off by means of a first drive signal generated in front of it and to have a second drive device electrically connected to a control input of the second power semiconductor switch, which is designed to connect the second power semiconductor switch by means of a second drive signal generated before it. and turn off, wherein the power electronics module comprises a first pulse information signal generating means, which is designed to generate a first and a second value having first Pulse information signal based on switching states of the first and / or second power semiconductor switch, wherein the power electronics module comprises a second pulse information signal generating means which is adapted to generate a first and a second value having second pulse information signal based on switching states of the first and / or second power semiconductor switch,
wherein the power electronics module has first measuring input terminals for connecting a first Rogowski coil and second measuring input terminals for connecting a second Rogowski coil,
wherein the power electronics module has a first integrator configured to integrate in its integration memory a first measuring signal applied between the first measuring input terminals, wherein the integration of the first measuring signal in the integration memory of the first integrator, controlled by the first pulse information signal, takes place in such a way that in the period of one change of the first pulse information signal from its first value to its second value until a change of the first pulse information signal from its second value to its first value, the integration memory of the first integrator is deleted,
wherein the power electronics module is designed to generate a first current measuring signal as a function of the value of the first integration memory,
wherein the power electronics module has a second integrator which is designed to integrate in its integration memory a second measuring signal applied between the second measuring input terminals, wherein the integration of the second measuring signal in the integration memory of the second integrator, controlled by the second pulse information signal, takes place such that in the period of one change of the second pulse information signal from its first value to its second value until a change of the second pulse information signal from its second value to its first value, the integration memory of the second integrator is deleted,
wherein the power electronics module is designed to generate a second current measuring signal as a function of the value of the integration memory of the second integrator.

Preferably, the first current measurement signal corresponds to the value of the integration memory of the first integrator and the second current measurement signal corresponds to the value of the integration memory of the second integrator.

Advantageous embodiments of the invention will become apparent from the dependent claims.

Advantageous embodiments of the method result analogously to advantageous embodiments of the power electronics module and vice versa.

It proves to be advantageous if the integration memory is in the form of an electrical capacitor, wherein the integration memory, controlled by the pulse information signal, in the period from the end of a current pulse until the beginning of this current pulse immediately following current pulse is deleted by the capacitor by turning on with the Capacitor electrically connected switch, which is arranged in a parallel to the capacitor electrically connected current branch is discharged, wherein the switching on and off of the switch controlled by the pulse information signal, since then the integration memory is particularly simple and reliable deleted.

Furthermore, it proves to be advantageous if the integrator has an operational amplifier, the capacitor and an electrical resistance, wherein the Rogowski coil is electrically connected via a first branch to the first input of the operational amplifier and via a second branch current to the second input of the operational amplifier is electrically connected, wherein the electrical resistance is arranged electrically between an electrical first output of the Rogowski coil and the first input of the operational amplifier, wherein the capacitor is electrically connected between the first input of the operational amplifier and an output of the operational amplifier, wherein the current measurement signal at the output the operational amplifier is applied, since then the integrator is particularly simple.

Furthermore, it proves to be advantageous if the integration memory, controlled by the pulse information signal, is deleted at the end of a current pulse and remains until the beginning of a current pulse immediately following current pulse in the erased state, since then occurring in the measurement signal between the end and beginning of the current pulse noise in the Integration can not be integrated with and thus suppressed.

Furthermore, it proves to be advantageous if the integration memory, controlled by the pulse information signal at the beginning of a current pulse is deleted or deleted at the end of a current pulse or between the end of a current pulse and the beginning of this current pulse immediately following current pulse is deleted, since then the integration memory after the Deletion process is immediately unlocked for integration. It is particularly advantageous if the integration memory, controlled by the pulse information signal, is deleted immediately after the end of a current pulse.

Furthermore, it proves to be advantageous if a power semiconductor switch is electrically connected in series to the electrical conductor, wherein the pulse-shaped electrical current flowing conductor is generated by the power semiconductor switch of a Control device, which is electrically connected to a control input of the power semiconductor switch is turned on and off by means of a drive signal, wherein the pulse information signal is generated such that turning on the power semiconductor switch indicates the beginning of each current pulse and turning off the power semiconductor switch indicates the end of each current pulse , As a result, the pulse-shaped current flowing electrical conductor current and the pulse information signal is generated in a simple manner.

Furthermore, there is a method of determining a first electrical current in a first electrical conductor in a pulsed electrical current flowing conductor by means of a first electrical conductor arranged around the first Rogowski coil, wherein between the current pulses flowing through the electrical first conductor, no current flows, and for determining an electrical second conductor current flowing in a pulse-shaped manner in an electrical second conductor by means of a second Rogowski coil arranged around the electrical second conductor, wherein no current flows between the current pulses flowing through the electrical second conductor, the first and second conductor current respectively be determined by the method according to the invention and in such a way a first current measurement associated with the first phase current and a second conductor current associated second current measurement signal are determined as advantageous, wherein the first conductor, a first power semiconductor scarf ter is electrically connected in series and the second conductor, a second power semiconductor switch is electrically connected in series, wherein the first and second power semiconductor switches are electrically connected in series, wherein the first power semiconductor switch, a first diode is electrically connected in anti-parallel and to the second power semiconductor switch, a second Electrically connected in anti-parallel with the electrically, between the first and second power semiconductor switch, a center electrical node, which is electrically connected to an electrical third conductor is arranged, wherein the first and second conductor current are generated by the first power semiconductor switch from a first drive means, the is electrically connected to a control input of the first power semiconductor switch is turned on and off by means of a first drive signal and the second power semiconductor switch from a second on Control means, which is electrically connected to a control input of the second power semiconductor switch is turned on and off by means of a second drive signal, wherein the first and second power semiconductor switches are switched on and off such that the first and the second power semiconductor switch are not turned on simultaneously,
wherein the pulse information signal for the determination of the first conductor current and the pulse information signal for the determination of the second conductor current are respectively generated based on switching states of the first and / or second power semiconductor switch. As a result, the first and second conductor currents are reliably and accurately determined in a simple manner in the case of a half-bridge circuit.

Furthermore, it proves to be advantageous if the method additionally serves to determine a third conductor current flowing through the third conductor, wherein a third current measurement signal is determined by adding or subtracting the first and second current measurement signals, or if the first current measurement signal is not zero in that the first current measuring signal is output as the third current measuring signal and when the first current measuring signal is zero, the second current measuring signal is output as the third current measuring signal. As a result, the third conductor current is reliably and accurately determined in a simple manner in a half-bridge circuit.

Furthermore, it proves to be advantageous if the first pulse information signal generating means is adapted to generate the first pulse information signal based on the switching states of the second power semiconductor switch such that the first pulse information signal assumes the first value when the second power semiconductor switch is turned off and takes the second value when the second Power semiconductor switch is turned on, and the second pulse information signal generating means is adapted to generate the second pulse information signal based on the switching states of the first power semiconductor switch such that the second pulse information signal assumes the first value when the first power semiconductor switch is turned off and the second value assumes when the first power semiconductor switch is turned on , As a result, the first and second pulse information signal are generated in a particularly simple manner.

Furthermore, it proves to be advantageous if the first pulse information signal generating device is designed to generate the first pulse information signal based on the switching states of the first power semiconductor switch such that the first pulse information signal assumes the first value when the first Power semiconductor switch is turned on and the second value assumes when the first power semiconductor switch is turned off, and the second pulse information signal generating means is adapted to generate the second pulse information signal based on the switching states of the second power semiconductor switch such that the second pulse information signal assumes the first value when the second power semiconductor switch is turned on and takes the second value when the second power semiconductor switch is turned off. As a result, the first and second pulse information signal are generated in a particularly simple manner.

Furthermore, it proves to be advantageous if the integration of the first measurement signal in the integration memory of the first integrator, controlled by the first pulse information signal, is such that when changing the first pulse information signal from its first value to its second value of the integration memory of the first integrator is deleted and up to a change of the first pulse information signal from its second value to its first value, remains in the cleared state, and that the integration of the second measurement signal in the integration memory of the second integrator, controlled by the second pulse information signal, is such that when changing the second pulse information signal of its first value to its second value of the integration memory of the second integrator is cleared and remains until a change of the second pulse information signal from its second value to its first value, in the erased state, since then in the Mes ssignale between the end and the beginning of the respective current pulse occurring noise during integration are not integrated with and thus suppressed.

Furthermore, it proves to be advantageous if the integration of the first measurement signal in the integration memory of the first integrator, controlled by the first pulse information signal, such that is deleted when changing the first pulse information signal from its second value to its first value, the integration memory of the first integrator and that the integration of the second measuring signal in the integration memory of the second integrator, controlled by the second pulse information signal, takes place such that when the second pulse information signal is changed from its second value to its first value, the integration memory of the second integrator is deleted,
or,
if the integration of the first measuring signal in the integration memory of the first integrator, controlled by the first pulse information signal, takes place such that upon a change of the first pulse information signal from its first value to its second value, the integration memory of the first integrator is deleted and that integrating the second measuring signal in the integration memory of the second integrator, controlled by the second pulse information signal, in such a way that when the second pulse information signal is changed from its first value to its second value, the integration memory of the second integrator is deleted,
or,
when the integration of the first measurement signal in the integration memory of the first integrator, controlled by the first pulse information signal, such that in the period between a change of the first pulse information signal from its second value to its first value and a change of the first pulse information signal from its first value to its second Value, the integration memory of the first integrator is deleted and that integrating the second measurement signal in the integration memory of the second integrator, controlled by the second pulse information signal, such that in the period between a change of the second pulse information signal from its second value to its first value and a change of second pulse information signal from its first value to its second value, the integration memory of the second integrator is deleted. As a result, the respective integration memory is immediately released again for integration after the deletion process. It is particularly advantageous if the integration of the first measurement signal in the integration memory of the first integrator, controlled by the first pulse information signal, takes place such that the integration memory of the first integrator is cleared immediately after a change of the first pulse information signal from its second value to its first value the integration of the second measurement signal in the integration memory of the second integrator, controlled by the second pulse information signal, takes place such that immediately after a change of the second pulse information signal from its second value to its first value, the integration memory of the second integrator is deleted.

Furthermore, it proves to be advantageous if the integration memory of the first integrator is in the form of an electrical first capacitor, wherein the integration memory of the first Intergartors, controlled by the first pulse information signal is deleted by the first capacitor by turning on a first electrically connected to the first capacitor Switch, which is arranged in a to the first capacitor electrically connected in parallel current branch, is discharged, wherein the switching on and off of the first switch is controlled by the first pulse information signal, wherein the integration memory of the second integrator is in the form of an electric second capacitor, wherein the Integration memory of the second Intergartors, controlled by the second pulse information signal, is deleted by the second capacitor by turning on a second switch electrically connected to the second switch, the ele in a to the second capacitor ctrically arranged parallel current branch is discharged, wherein the switching on and off of the second switch is controlled by the second pulse information signal, since then the integration memory special is simple and reliable deleted.

Furthermore, it proves to be advantageous if the first integrator has a first operational amplifier, the first capacitor and an electrical first resistor, wherein a first measuring input terminal of the first measuring input terminals is electrically connected via a first current measuring branch to the first input of the first operational amplifier and a second measuring input terminal the first measuring input terminals being electrically connected to the second input of the first operational amplifier via a second current measuring branch, the first resistor being electrically connected between the first measuring input terminal of the first measuring input terminals and the first input of the first operational amplifier, the first capacitor electrically connected between the first input of the first operational amplifier the first operational amplifier and an output of the first operational amplifier is connected, wherein the first current measuring signal at the output of the first operational amplifier Anlie gt, and that the second integrator comprises a second operational amplifier, the second capacitor and an electrical second resistor, wherein a first measuring input terminal of the second measuring input terminals via a third current measuring branch to the first input of the second operational amplifier is electrically connected and a second measuring input terminal of the second measuring input terminals a fourth current measuring branch is electrically connected to the second input of the second operational amplifier, the second resistor being electrically connected between the first measuring input terminal of the second measuring input terminals and the first input of the second operational amplifier, the second capacitor electrically connected between the first input of the second operational amplifier and a second operational amplifier Output of the second operational amplifier is connected, wherein the second current measuring signal is applied to the output of the second operational amplifier, since then the In tegrator is particularly simple.

Furthermore, it proves to be advantageous if the power electronics module has a conductor current determining device which is designed to determine a third conductor current flowing through the third conductor in the form of a third current measurement signal from the first and second current measurement signal by adding or combining the first and second current measurement signal from the conductor current determination device be subtracted from each other, or if the first current measuring signal is not zero, the first current measuring signal is output as a third current measuring signal from the conductor current detecting means and if the first current measuring signal is zero, the second current measuring signal from the conductor current detecting means will output as a third current measuring signal. As a result, the third conductor current is reliably and accurately determined in a simple manner in a half-bridge circuit.

Furthermore, a power electronics device with a power electronics module according to the invention and with a first Rogowski coil arranged around the first conductor and with a second Rogowski coil arranged around the second conductor, wherein the first Rogowski coil is electrically connected to the first measuring input terminals and the second Rogowski coil Coil electrically connected to the second measuring input terminals, as advantageous.

Embodiments of the invention are illustrated in the figures and are explained in more detail below. Showing:

1 an electrical circuit which generates an electrical conductor current which flows in a pulsed fashion in an electrical conductor, the conductor current being determined according to the invention,

2 in accordance with the circuit 1 occurring schematic signal curves,

3 a power electronics device with a power electronics module according to the invention and with a first and second Rogowski coil and

4 in accordance with the circuit 3 occurring schematic signal waveforms.

In 1 is an electrical circuit 1 represented by means of a power semiconductor switch T1, which is electrically connected in series with an electrical conductor 1 is switched, one in the electrical conductor 1 pulsed electrical current flowing conductor I1 generated by the power semiconductor switch T1 from a drive device 5 , which is electrically connected to a control terminal G of the power semiconductor switch T1, is switched on and off by means of a drive signal A1, wherein when power semiconductor switch T1 is turned on, a current through the electrical conductor 1 flows and switched off power semiconductor switch T1 no current through the electrical conductor 1 flows. The drive device 5 Switches the power semiconductor switch T1 as a function of a control signal (not shown), for example, generated by a control signal S1 several times in succession and out, so that the in 2 exemplified, pulsed by the electrical conductor 1 flowing, electrical conductor current I1 arises. The electrical conductor current I1 thus consists of successively following current pulses 10 , The current pulses 10 respectively a beginning B and an end E on. The current pulses 10 In the context of the exemplary embodiment, they have an identical electrical polarity and height, which does not necessarily have to be generalized in the invention. The current pulses 10 can be generalized in the invention also have different electrical polarities and different heights. Furthermore, in the invention, the time intervals T1 between the current pulses 10 also be different in length and current pulses 10 have different durations. From a pulse information signal generating device 16 a pulse information signal P1 is generated such that switching on of the power semiconductor switch T1 by the drive means 5 the beginning B of the respective current pulse 10 in the pulse information signal P1 indicates and turning off the power semiconductor switch T1 by the drive means 5 the end E of a respective current pulse 10 in the pulse information signal P1 indicates. The pulse information signal P1 is in 2 shown. The pulse information signal P1 has a first value of, for example, logic "1" when the power semiconductor switch T1 by the drive means 5 is turned on and thus a current through the conductor 1 flows, and a second value of, for example, logic "0" when the power semiconductor switch T1 by the drive means 5 is switched off and therefore no current through the conductor 1 flows. A change from the second value to the first value gives the time of the beginning B of the respective current pulse 10 in the pulse information signal P1 and a change from the first value to the second value gives the time of the end E of the respective current pulse 10 in the pulse information signal P1. The pulse information signal generating means 16 generates, the pulse information signal P1 preferably from the drive signal A1. The pulse information signal generating means 16 may be in the form of a level converter, for example, which converts the drive signal A1 into a logic signal level. Alternatively, the pulse information signal P1 also directly internally from the drive device 5 be generated or the pulse information signal P1 is directly in the form of the drive means 5 generated drive signal A1 before. The pulse information signal generating means 5 can thus also be an integral part of the control device 5 be and can therefore also in the form of the drive device 5 available. Furthermore, the pulse information signal P1 can also be in the form of the control signal S1. In this case, within the meaning of the invention, the pulse information signal generating device is designed in a particularly simple manner in the form of an electrical line section (eg printed circuit trace) that supplies the pulse information signal P1 to the integrator 4 passes.

The circuit 1 continues, one around the ladder 1 guided Rogowski coil 2 on, which produces at its output a measurement signal U1m. The measuring signal U1m is in the form of a time derivative dI1 / dt of the electrical conductor 1 flowing conductor current I1 proportional electrical voltage in front, so that the measurement signal of the Rogowski coil 2 must be integrated by means of an integrator in the integration memory to get the conductor current I1. In this case, the problem arises that, in particular when the integrator is implemented in analog technology, the value of the integration memory drifts away, so that it has an increasingly deviating from a value of zero over time base value, which leads to an inaccurate determination of the phase current I1. In 2 is the current measurement signal U1a ', which results in a conventional technology implementation of the integration or in a conventional technology training of the integrator (without switch S) at the output of the integrator shown. The height of the thus conventionally determined current pulses 10 ' , drifts further and further over time, because an increasing DC component remains as the basic value in the integration memory of the integrator.

In the invention, this is done by the Rogowski coil 2 generated measurement signal U1m from an integrator 4 integrated in the integration memory C, wherein in the integration of the measurement signal U1m of the integration memory C, controlled by the pulse information signal P1, in the period T from the end E of a current pulse 10 until the beginning B of this current pulse 10 immediately following current pulse 10 is cleared, that is set to zero, wherein a current measurement signal U1a is generated depending on the value of the integration memory. In the context of the exemplary embodiment, the current measurement signal U1a corresponds to the value of the integration memory C. Since the value of the integration memory C after its erasure is zero, the integration of the measurement signal U1m at each current pulse becomes 10 started with an initial value of zero. In 2 are the thus determined current pulses 10 '' the current measuring signal U1a, the current pulses 10 match, so that in the electrical conductor 1 pulse-shaped flowing electrical conductor current I1 is determined with high accuracy.

It is generalized in the invention for determining an electrical conductor current flowing in a pulsed electrical conductor by means of a Rogowski coil arranged around the electrical conductor, wherein no current flows between current pulses of the conductor current flowing through the electrical conductor, sufficient if additional information is available in the form of a pulse information signal indicating the beginning and the end of a respective current pulse. In many electrical circuits in which a circuit results in a conductor, a pulse-shaped electrical current flowing conductor, such a pulse information signal is available or can be generated.

The integration memory C can, controlled by the pulse information signal P1, at the end E of a respective current pulse 10 to be deleted.

Furthermore, as in the embodiment, the integration memory C, controlled by the pulse information signal P1, also at the end E of a respective current pulse 10 be cleared and until the beginning of this current pulse 10 immediately following current pulse 10 remain in the cleared state, ie as long as the pulse information signal P1 assumes its first value, the integration memory C is in an erased state, ie its value is set to zero. As long as the pulse information signal P1 assumes its second value, the integration memory C is released for integration.

Furthermore, the integration memory C, controlled by the pulse information signal P1, even at the beginning B of a respective current pulse 10 to be deleted.

Furthermore, the integration memory C, controlled by the pulse information signal P1, between the end E of a respective current pulse 10 and start of this current pulse 10 immediately following current pulse 10 to be deleted. It is particularly advantageous if the integration memory C, controlled by the pulse information signal P1, immediately after the end E of a respective current pulse 10 is deleted.

The Rogowski coil 2 is connected to the integrator via measurement input terminals C1 and C2 to which it is electrically connected 4 electrically connected.

In the context of the embodiment, the integration memory C is in the form of an electrical capacitor C (see 1 ), wherein the integration memory C, controlled by the pulse information signal P1, in the period T from the end E of a current pulse 10 until the beginning B of this current pulse 10 immediately following current pulse 10 is cleared by the capacitor C by switching on an electrically connected to the capacitor C switch S, in a parallel to the capacitor C in parallel current branch 9 is arranged, is discharged, wherein the switching on and off of the switch S is controlled by the pulse information signal P1.

A control electronics (in 1 not shown separately) of the switch S controls the switch S in response to the pulse information signal P1 to the integration memory C to delete and possibly to keep in response to the pulse information signal P1 for a certain time in the cleared state. The switch S is preferably in the form of two electrically anti-parallel connected semiconductor switches including the above-described control electronics for driving the semiconductor switches. Optionally, in the current branch 9 to the switch S, an electrical resistance is electrically connected in series (in 1 not shown) which limits the short-circuit current through the capacitor C and the switch S when the switch S is turned on. The switch S is closed when switched on and open when switched off.

In the context of the embodiment is the integrator 4 implemented in analog technology and has an operational amplifier 3 , the capacitor C as an integration memory, the switch S and an electrical resistance R on. The Rogowski coil 2 is via a first branch 7 with the first input - (negative input) of the operational amplifier 3 is electrically connected and via a second branch 8th with the second input + (positive input) of the operational amplifier 3 is electrically connected, wherein the electrical resistance R is electrically connected between an electrical first output of the Rogowski coil 2 and the first input - the operational amplifier 3 is arranged, wherein the capacitor C is electrically connected between the first input - the operational amplifier 3 and an output of the operational amplifier 3 is connected, wherein the current measurement signal U1a depending on the value of the integration memory C from the operational amplifier 3 at the output of the operational amplifier 3 is produced. In the context of the exemplary embodiment, the current measurement signal U1a corresponds to the value of the integration memory C.

That at the output of the operational amplifier 3 applied current measurement signal U1a, which represents the value of the integration memory C in the embodiment, is in the form of a voltage signal and results in
U1a (t) = 0, ie to 0V with switch S closed,
and to U1a (t) = - 1 / R * C * ∫U1m (t) dt The amount of the value of the integration memory C thus decreases from a value of zero in the integration period from the opening of the switch S to the time of closing of the time interval t from the time of opening of the switch S to the time of closing the switch S. Switch S, by which the value of the integration memory again erased, ie set to zero, over the time t to. With R in the above relationship, the ohmic resistance of the resistor R and C, the capacitance of the capacitor C is designated.

The value of the integration memory is due to the minus sign in the above relationship in the embodiment at the output of operational amplifier 3 voltage in negated or inverted form.

It should be noted that, for the purposes of the invention, a value of an integration memory also means the value of the integration memory in negated or inverted form.

It should be noted that for the purposes of the invention, an integration of a measurement signal in an integration memory, in addition to the purely mathematical integration of the measurement signal, may also include a multiplication by a proportionality factor and / or other adaptations, e.g. by a low-pass filter is electrically connected in parallel to the integration memory, may include. In the embodiment, the proportionality factor according to the above relationship is -1 / (R * C).

It is particularly advantageous if the integration memory C, controlled by the pulse information signal P1, at the end E of a current pulse 10 is deleted and until the beginning of this current pulse 10 immediately following current pulse 10 remains in the cleared state, ie when the switch S, controlled by the pulse information signal P1, at the end E of a current pulse 10 is turned on and until the beginning of this current pulse 10 immediately following current pulse 10 remains in the on state, because by the temporary closing of the switch S both the integration memory C of the integrator 4 cleared, and as a result of the current measurement signal U1a for the period T set to zero, so that disturbances in the measurement signal U1m, which may be in the period T between two directly temporally lagereheingenden current pulses 10 can be suppressed.

In 3 is a power electronic device 15 with a power electronics module according to the invention 14 and with one around an electrical first conductor 1a of the power electronics module 14 arranged first Rogowski coil 2a and with one around an electrical second conductor 2 B of the power electronics module 14 arranged second Rogowski coil 2 B , being the first Rogowski coil 2a electrically with first measuring input terminals C1 and C2 of the power electronics module 14 and the second Rogowski coil 2 B electrically second measuring input terminals D1 and D2 of the power electronics module 14 is connected shown.

The power electronics module 14 has one to the electrical first conductor 1a of the power electronics module 14 electrically connected in series first power semiconductor switch T1 and one to the electrical second conductor 1b electrically connected in series second power semiconductor switch T2, wherein the first and second power semiconductor switches T1 and T2 are electrically connected in series. To the first power semiconductor switch T1, a first diode D1 is electrically connected in anti-parallel and to the second power semiconductor switch T2, a second diode D2 is electrically connected in anti-parallel. Between the first and second power semiconductor switches T1 and T2 is a center electrical circuit node M connected to an electrical third conductor 1c is electrically connected, arranged. The third leader 1c is electrically connected between an AC voltage terminal AC of the power electronics module 14 and the center circuit node M.

Above the series connection of the first and second power semiconductor switches T1 and T2, there is a DC voltage Udc, which is the series connection of the first and second power semiconductor switches T1 and T2 via a positive and a negative DC voltage connection DC + and DC- of the power electronics module 14 is supplied. An external electrical load (eg an electric motor), which in the exemplary embodiment electrically via the AC voltage terminal AC to the power electronics module 14 or with the power electronics device 15 is connected, has an inductance L. The first leader 1a is in the context of the embodiment electrically connected between the positive DC voltage terminal DC + and a first load current terminal C of the first power semiconductor switch T1. The first leader 1a but may also be electrically connected between the second load current terminal E of the power semiconductor switch T1 and the middle circuit node M. The second leader 1b is in the context of the embodiment electrically connected between the negative DC voltage connection DC and a second load current connection E of the second power semiconductor switch T2. The second leader 1b but can also be electrically connected between the first load current terminal C of the second power semiconductor switch T2 and the middle circuit node M.

Furthermore, the power electronics module 14 an electrically connected to a control terminal G of the first power semiconductor switch T1 first drive means 5a on, which is designed to turn on and off the first power semiconductor switch T1 by means of a first drive signal A1 generated before it, and a second drive device electrically connected to a control terminal G of the second power semiconductor switch T2 5b which is designed to switch the second power semiconductor switch T2 on and off by means of a second drive signal A2 generated in front of it.

Such a power electronics module 14 is often used in conjunction with one or more others Power electronics modules 14 an AC voltage between the mid-point terminals M of the power electronics modules 14 to create. In 3 are the sake of clarity, the other power electronics modules 14 not shown.

The first drive device 5a Switches the first power semiconductor switch T1 on and off in response to a first control signal S1, for example generated by a control device (not shown), and the second control device 5b switches the second power semiconductor switch T2 on and off as a function of a second control signal S2, for example generated by the control device (not shown), so that the in 4 exemplified, pulsed through the first conductor 1a flowing, electrical first phase current I1 and the in 4 exemplified in a pulse shape through the second conductor 1b flowing, second electrical conductor current I2 arise. The first conductor current I1 thus consists of successively following current pulses 10 and the second conductor current I2 consists of such successive current pulses 12 , The current pulses 10 and 12 in each case have a beginning B and an end E and in the context of the embodiment a different time duration. When the first power semiconductor switch T1 is turned on, the second power semiconductor switch T2 is turned off, and when the second power semiconductor switch T2 is turned on, the first power semiconductor switch T1 is turned off. In the context of the exemplary embodiment, the first and second power semiconductor switches T1 and T2 are switched on and off alternately with one another. The first and second power semiconductor switches T1 and T2 respectively have the two switching states on and off. The first and second conductor currents I1 and I2 add in the predetermined in the embodiment counting direction of the first and second conductor currents I1 and I2 in the middle circuit node M to one through the third conductor 1c flowing electrical third conductor current I3. The third conductor current I3 in the embodiment has a ripple coarse sinusoidal course, wherein in 4 the period of the positive half (0 ° to 180 °) of the sinusoidal waveform is shown.

The power electronics module 14 has a first pulse information signal generating means 6a , which is designed to generate a first and a second value having first pulse information signal P1 based on switching states of the first and / or second power semiconductor switch T1 and T2. Furthermore, the power electronics module 14 a second pulse information signal generating means 6b , which is designed to generate a first and a second value having second pulse information signal P1 based on switching states of the first and / or second power semiconductor switch T1 and T2. In the context of the embodiment, the first pulse information signal generating device 6a configured to generate the first pulse information signal P1 based on the switching states of the second power semiconductor switch T2, such that the first pulse information signal P1 takes the first value when the second power semiconductor switch T2 is turned off and the second value assumes when the second power semiconductor switch T1 is turned on. In the context of the embodiment, the second pulse information signal generating device 6b configured to generate the second pulse information signal P2 based on the switching states of the first power semiconductor switch T1, such that the second pulse information signal assumes the first value when the first power semiconductor switch is turned off and assumes the second value when the first power semiconductor switch is turned on.

The first pulse information signal generating means 6a can, as exemplified in 3 indicated by dashed lines, also be designed to generate the first pulse information signal P1 based on the switching states of the first power semiconductor switch T1 such that the first pulse information signal P1 assumes the first value when the first power semiconductor switch T1 is turned on and the second value assumes when the first power semiconductor switch T1 is turned off, and the second pulse information signal generating means 6b can also be configured to generate the second pulse information signal P2 based on the switching states of the second power semiconductor switch T2 such that the second pulse information signal P2 assumes the first value when the second power semiconductor switch T2 is turned on and the second value assumes when the second power semiconductor switch T2 is turned off.

The first and second pulse information signals P1 and P2 are in 4 shown. The first pulse information signal and the second pulse information signal P1 and P2 respectively have a first value of logical "1" and a second value of logical "0" in the exemplary embodiment.

Generalized, it may also be useful, in particular in other temporal sequences of the switching states of the first and second power semiconductor switches T1 and T2 as in the embodiment, the first pulse information signal generating means 6a such that it generates the first pulse information signal P1 based on the switching states of the first and second power semiconductor switches T1 and T2, and the second pulse information signal generating means 6b such that it the second pulse information signal P2 based on the switching states of the first and second power semiconductor switch T1 and T2 generated. The first and second pulse information signal generating means 6a and 6b For example, this may include logic gates (eg, AND, OR, NOT) which logically combine the switching states (on, off) of the first and second power semiconductor switches T1 and T2 to produce the first and second pulse information signals P1 and P2, respectively.

Optionally, from the first and second pulse information signal generating means 6a and 6b in the generation of the first and second pulse information signals P1 and P2, in addition to the switching states of the T1 and T2 power semiconductor switch, the time sequences of the switching states of the power semiconductor switches T1 and T2 are additionally taken into account.

The first pulse information signal generating means 6a generates the pulse information signal P1 in the embodiment of the second drive signal A2 and the second pulse information signal generating means 6b generated, the pulse information signal P2 in the embodiment of the first drive signal A1. The first and second pulse information signal generating means 6a and 6b For example, they may each be in the form of a level converter which converts the first or second drive signal A1 or A2 into a logic signal level. Alternatively, the respective pulse information signal P1 or P2 also directly internally from the relevant drive device 5a or 5b or the respective pulse information signal P1 or P2 is present directly in the form of the relevant drive signal A1 or A2. The respective first and second pulse information signal generating means 6a respectively. 6b can thus also be an integral part of the relevant control device 5a or 5b be and can therefore also in the form of the relevant control device 5a or 5b available. Furthermore, the pulse information signal P1 or P2 can also be present, for example, in the form of the control signal S1 or S2. In these cases, according to the invention, the first or second pulse information signal generating device is located 6a respectively. 6b specially designed in the form of a respective electrical line section (eg conductor track), which transmits the respective pulse information signal P1 or P2 to the associated integrator 4a or 4b passes.

Furthermore, the power electronics module 14 as already described, first measuring input terminals C1 and C2 for connecting a first Rogowski coil 2a and second measuring input terminals D1 and D2 for connecting a second Rogowski coil 2 B on.

Furthermore, the power electronics module 14 a first integrator 4a auf, which is formed in its integration memory Ca aufeingieren a between the first measurement input terminals C1 and C2 applied first measurement signal U1m, wherein the integration of the first measurement signal U1m in the integration memory Ca of the first integrator 4a controlled by the first pulse information signal P1, such that in the period of a change of the first pulse information signal P1 from its first value to its second value to a change of the first pulse information signal P1 from its second value to its first value, the integration memory Ca of the first Integrators 4a is deleted, with the power electronics module 14 for generating a first current measuring signal U1a as a function of the value of the integration memory Ca of the first integrator 4a is trained. In the context of the exemplary embodiment, the first current measuring signal U1a corresponds to the value of the integration memory Ca of the first integrator 4a ,

Furthermore, the power electronics module 14 a second integrator 4b auf, which is formed in its integration memory Cb aufeingieren an occurring between the second measuring input terminals D1 and D2 second measuring signal U2m, wherein the integration of the second measuring signal U2m in the integration memory Cb of the second integrator 4b controlled by the second pulse information signal P2, such that in the period of a change of the second pulse information signal P2 from its first value to its second value to a change of the second pulse information signal P2 from its second value to its first value, the integration memory Cb of the second Integrators 4b is deleted, with the power electronics module 14 for generating a second current measuring signal U2a as a function of the value of the integration memory Cb of the second integrator 4b is trained. In the exemplary embodiment, the second current measurement signal U2a corresponds to the value of the integration memory Cb of the second integrator 4b ,

In the context of the embodiment, the first integrator 4a realized in analog technology and has a first operational amplifier 3a , a first capacitor Ca as integration memory, a first switch Sa and a first resistor Ra. Furthermore, in the context of the embodiment, the second integrator 4b also realized in analog technology and has a second operational amplifier 3b , a second capacitor Cb as integration memory, a second switch Sb and a second resistor Ra. The first and second integrator 4a and 4b are inclusive of advantageous embodiments, respectively, as the same 1 described integrator 4 trained and vote respectively with respect to their functioning and your electrical components with the 1 described integrator 4 match. The first measuring input terminal C1 of the first measuring input terminals C1, C2 is via a first Current measuring branch 7a with the first input - (negative input) of the first operational amplifier 3a is electrically connected and the second measuring input terminal C2 of the first measuring input terminals C1, C2 via a second current measuring branch 8a with the second input + (positive input) of the first operational amplifier 3a electrically connected. The first resistor Ra is electrically connected between the first measuring input terminal C1 of the first measuring input terminals C1, C2 and the first input - the first operational amplifier 3a arranged. The first capacitor Ca is electrically connected between the first input - the first operational amplifier 3a and an output of the first operational amplifier 3a connected. The first current measuring signal U1a is located at the output of the first operational amplifier 3a at. The first measuring input terminal D1 of the second measuring input terminals D1, D2 is connected via a third current measuring branch 7b with the first input - (negative input) of the second operational amplifier 3b electrically connected. The second measuring input terminal D2 of the second measuring input terminals D1, D2 is connected via a fourth current measuring branch 8b to the second input + of the second operational amplifier 3b electrically connected. The second resistor Rb is electrically connected between the first measuring input terminal D1 of the second measuring input terminals D1, D2 and the first input - the second operational amplifier 3b arranged. The second capacitor Cb is electrically connected between the first input - the second operational amplifier 3b and an output of the second operational amplifier 3b connected. The second current measuring signal U2a is located at the output of the second operational amplifier 3b at.

The integration memory Ca of the first integrator 4a is controlled, controlled by the first pulse information signal P1, preferably cleared by the first capacitor Ca by turning on the first capacitor Sa electrically connected to the first switch Sa, which in an electrically connected in parallel to the first capacitor Ca current branch 9a is arranged, unloaded. The switching on and off of the first switch Sa is controlled by the first pulse information signal P1. The integration memory Cb of the second integrator 4b is controlled, controlled by the second pulse information signal P1, preferably erased by the second capacitor Cb by turning on a second capacitor Sb electrically connected to the second switch Sb, which in an electrically parallel to the second capacitor Cb current branch 9b is arranged, unloaded. The switching on and off of the second switch Sb is controlled by the second pulse information signal P2.

The integration of the first measurement signal U1m in the integration memory Ca of the first integrator 4a , controlled by the first pulse information signal, is carried out in the context of the exemplary embodiment such that upon a change of the first pulse information signal P1 from its first value to its second value, the integration memory Ca of the first integrator 4a is cleared and remains until a change of the first pulse information signal P1 from its second value to its first value, in the cleared state. The integration of the second measurement signal U2m in the integration memory Cb of the second integrator 4b , controlled by the second pulse information signal P2, takes place within the scope of the exemplary embodiment such that upon a change of the second pulse information signal P2 from its first value to its second value, the integration memory Cb of the second integrator 4b is cleared and remains until a change of the second pulse information signal P2 from its second value to its first value, in the cleared state.

The integration of the first measurement signal U1m in the integration memory Ca of the first integrator 4a can, controlled by the first pulse information signal P1, also be such that when changing the first pulse information signal P1 from its second value to its first value, the integration memory Ca of the first integrator 4a is cleared and the integration of the second measurement signal U2m in the integration memory Cb of the second integrator 4b , Controlled by the second pulse information signal P2, also be such that when changing the second pulse information signal P2 from its second value to its first value, the integration memory Cb of the second integrator 4b is deleted.

Furthermore, the integration of the first measurement signal U1m in the integration memory Ca of the first integrator 4a , controlled by the first pulse information signal P1, also take place in such a way that when the first pulse information signal P1 changes from its first value to its second value, the integration memory Ca of the first integrator 4a is cleared and the integration of the second measurement signal U2m in the integration memory Cb of the second integrator 4b , Controlled by the second pulse information signal, also be such that when changing the second pulse information signal P2 from its first value to its second value, the integration memory Cb of the second integrator 4b is deleted.

Furthermore, the integration of the first measurement signal U1m in the integration memory Ca of the first integrator 4a controlled by the first pulse information signal P1, also carried out such that in the period between a change of the first pulse information signal P1 from its second value to its first value and a change of the first pulse information signal P1 from its first value to its second value, the integration memory Ca of the first Integrators 4a is cleared and that the integration of the second measurement signal U2m in the integration memory Cb of the second integrator 4b , controlled by the second pulse information signal P2, also be such that in the period between a change of the second pulse information signal P2 from its second value to its first value and a change of the second pulse information signal P2 from its first value to its second value, the integration memory Cb of second integrator 4b is deleted. Preferably, the integration of the first measuring signal U1m in the integration memory Ca of the first integrator takes place 4a controlled by the first pulse information signal P1, such that immediately after a change of the first pulse information signal P1 from its second value to its first value, the integration memory Ca of the first integrator 4a is cleared and the integration of the second measurement signal U2m in the integration memory Cb of the second integrator 4b controlled by the second pulse information signal, is carried out such that immediately after a change of the second pulse information signal P2 from its second value to its first value, the integration memory Cb of the second integrator 4b is deleted.

A respective control electronics (in 3 not separately shown) of the respective switch Sa or Sb controls the respective switch Sa or Sb in response to the respective pulse information signal P1 or P2 to delete the respective integration memory Ca or Cb and optionally in response to the pulse information signal P1 and P2 for to keep a certain time in an erased state. The respective switch Sa or Sb is preferably in the form of two semiconductor switches connected electrically in antiparallel, including the control electronics described above for driving the semiconductor switches. Optionally, in the respective current branch 9a respectively. 9b to the respective switch Sa or Sb, an electrical resistance is electrically connected in series (in 3 not shown), which limits when switching on the respective switch Sa or Sb, the short-circuit current through the respective capacitor Ca or Cb and the respective switch Sa or Sb. The respective switch Sa or Sb is closed when switched on and open when switched off.

In 4 Furthermore, the first and second current measuring signal U1a 'and U2a', which result at the output of the first or second integrator in the case of a customary implementation of the integration or in the case of a technically customary design of the first or second integrator (without switches Sa or Sb) would, presented.

Furthermore, the power electronics module 14 preferably a conductor current determining device 12 , which is designed to determine the by the third conductor 1c flowing third conductor current I3 from the first and second current measurement signal U1a and U2a. The third conductor current I3 is the third current measurement signal U3 from the conductor current determining device 12 determined and output by the first and second current measurement signal Ua1 and Ua2 (depending on the counting direction of the first and second conductor currents I1 and I2) are added or subtracted from each other, or if the first current measurement signal U1a is not zero, the first current measurement signal U1a as a third Current measurement signal U3 is output and when the first current measurement signal is zero, the second current measurement signal Ua2 will output as a third current measurement signal U3.

It should be noted that the power semiconductor switches are generally in the form of transistors, e.g. IGBTs (Insulated Gate Bipolar Transistor) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) or in the form of thyristors. In the embodiments, the power semiconductor switches are formed as IGBTs, wherein the first load current terminal C of the power semiconductor switch in the form of the collector of the IGBTs, the second load current terminal E of the power semiconductor switch in the form of the emitter of the IGBTs and the control terminal G are formed in the form of the gate of the IGBTs. If the power semiconductor switches are in the form of MOSFETs, then the diode D1 or D2 connected in antiparallel with the respective power semiconductor switches T1 and T2 is generally an integral part of the respective MOSFET and is not present as a discrete component. Due to its semiconductor structure, a MOSFET already has a diode connected electrically in antiparallel to the actual semiconductor switch.

It should be noted that, for the purposes of the invention, a value of an integration memory also means the value of the integration memory in negated or inverted form.

It should also be noted that, in the sense of the invention, an integration of a measurement signal in an integration memory may, in addition to the purely mathematical integration of the measurement signal, also be multiplied by a proportionality factor and / or other adaptations, e.g. by a low-pass filter is electrically connected in parallel to the integration memory, may include.

Furthermore, it should be noted that in the invention, the respective pulse information signal generating means may also be an integral part of a respective control device and thus also in the form of the relevant respective Control device may be present. The respective pulse information signal generation device and the respective activation device therefore do not necessarily have to be separate components.

Furthermore, it should be noted that in the invention, the respective integrator can also be implemented in digital technology.

It should also be noted that for the purposes of the invention a value of zero is also understood to mean a value which is close to zero.

It should also be noted that for the purposes of the invention, erasing an integration memory not only as in the exemplary embodiments, setting the integration memory to a value of zero, but alternatively setting the integration memory to a specific value other than zero is understood. By setting the integration memory to a specific value other than zero, the respective current measurement signal can be provided with a specific offset in a simple manner.

It should also be noted that, of course, features of various embodiments of the invention, as long as the features are not mutually exclusive, can be combined as desired.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 2014/0306690 A1 [0002, 0002, 0002, 0003, 0003]

Claims (17)

Method for detecting an in an electrical conductor ( 1 . 1a . 1b ) pulsed electrical current flowing conductor (I1, I2) by means of a to the electrical conductor ( 1 . 1a . 1b ) arranged Rogowski coil ( 2 . 2a . 2 B ), whereby between current pulses ( 10 . 12 ) of the conductor current (I1, I2) passing through the electrical conductor ( 1 . 1a . 1b ) flow, no current flows, wherein a pulse information signal (P1, P2) the beginning (B) and the end (E) of a respective current pulse ( 10 . 12 ), one of the Rogowski coil ( 2 . 2a . 2 B ) due to the electrical conductor current (I1, I2) generated measuring signal (U1m, U2m) from an integrator ( 4 . 4a . 4b ) is integrated in its integration memory (C, Ca, Cb), wherein during the integration of the measurement signal (U1m, U2m) the integration memory (C, Ca, Cb), controlled by the pulse information signal (P1, P2), in the period from the end (E) a current pulse ( 10 . 12 ) until the beginning (B) of a current pulse ( 10 . 12 ) immediately following current pulse ( 10 . 12 ) is cleared, wherein a current measurement signal (U1a, U2a) depending on the value of the integration memory (C) is generated. Method according to Claim 1, characterized in that the integration memory (C, Ca, Cb) is in the form of an electrical capacitor (C, Ca, Cb), the integration memory (C, Ca, Cb) being controlled by the pulse information signal (P, P1 , P2), in the period from the end (E) of a current pulse (E) 10 . 12 ) until the beginning of a current pulse ( 10 . 12 ) immediately following current pulse ( 10 . 12 ) is extinguished by switching on the capacitor (C, Ca, Cb) by switching on a switch (S, Sa, Sb) electrically connected to the capacitor (C, Ca, Cb), which is connected to the capacitor (C, Ca, Cb ) electrically connected in parallel current branch ( 9 . 9a . 9b ) is discharged, wherein the switching on and off of the switch (S, Sa, Sb) controlled by the pulse information signal (P, P1, P2) takes place. Method according to claim 2, characterized in that the integrator ( 4 . 4a . 4b ) an operational amplifier ( 3 . 3a . 3b ), the capacitor (C, Ca, Cb) and an electrical resistance (R, Ra, Rb), wherein the Rogowski coil ( 2 . 2a . 2 B ) via a first branch ( 7 . 7a . 7b ) to the first input (-) of the operational amplifier ( 3 . 3a . 3b ) is electrically connected and via a second current branch ( 8th . 8a . 8b ) to the second input (+) of the operational amplifier ( 3 . 3a . 3b ), wherein the electrical resistance (R, Ra, Rb) is electrically connected between an electrical first output of the Rogowski coil ( 2 . 2a . 2 B ) and the first input of the operational amplifier ( 3 . 3a . 3b ), wherein the capacitor (C, Ca, Cb) electrically between the first input (-) of the operational amplifier ( 3 . 3a . 3b ) and an output of the operational amplifier ( 3 . 3a . 3b ), wherein the current measurement signal (U1a, U2a) at the output of the operational amplifier ( 3 . 3a . 3b ) is present. Method according to one of the preceding claims, characterized in that the integration memory (C, Ca, Cb), controlled by the pulse information signal (P, P1, P2), at the end (E) of a current pulse ( 10 . 12 ) and until the beginning (B) of a current pulse ( 10 . 12 ) immediately following current pulse ( 10 . 12 ) remains in the cleared state. Method according to one of claims 1 to 3, characterized in that the integration memory (C, Ca, Cb), controlled by the pulse information signal (P, P1, P2), at the beginning (B) of a current pulse ( 10 . 12 ) or at the end (E) of a current pulse (E) 10 . 12 ) or between the end (E) of a current pulse (E) 10 . 12 ) and start of this current pulse ( 10 . 12 ) immediately following current pulse ( 10 . 12 ) is deleted. Method according to one of the preceding claims, characterized in that to the electrical conductor ( 1 ) a power semiconductor switch (T1) is electrically connected in series, wherein the pulse-shaped current flowing electrical conductor current (I1) is generated by the power semiconductor switch (T1) by a drive means ( 5 ), which is electrically connected to a control input (G) of the power semiconductor switch (T1) is switched on and off by means of a drive signal (A1,), wherein the pulse information signal (P1) is generated such that turning on the power semiconductor switch (T1) Start (B) of the respective current pulse ( 10 ) and turning off the power semiconductor switch (T1) the end (E) of a respective current pulse ( 10 ) indicates. Method for detecting a in an electrical first conductor ( 1a ) pulsed electrical first conductor current (I1) by means of a to the electrical first conductor ( 1a ) arranged first Rogowski coil ( 2a ), whereby between the current pulses ( 10 ) through the electrical first conductor ( 1a ) flow, no current flows, and for detecting a in an electrical second conductor ( 1b ) electrically pulsed electrical second conductor current (I2) by means of a to the electrical second conductor ( 1b ) arranged second Rogowski coil ( 2 B ), whereby between the current pulses ( 12 ), through the electrical second conductor ( 1b ) flow, no current flows, wherein the first and second conductor current (I1, I2) respectively by a method according to one of claims 1 to 5 are determined and thus to the first conductor current (I1) associated first current measurement signal (U1a) and one to the second Conductor current (I2) associated second current measurement signal (U2b) are determined, wherein the first conductor ( 1a ) a first power semiconductor switch (T1) electrically connected in series and to the second conductor ( 1b ), a second power semiconductor switch (T2) is electrically connected in series, wherein the first and second power semiconductor switch (T1, T2) are electrically connected in series, wherein to the first power semiconductor switch (T1), a first diode (D1) is electrically connected in anti-parallel and to a second diode (D2) is electrically connected in anti-parallel to the second power semiconductor switch (T2), wherein electrically connected between the first and second power semiconductor switch (T1, T2) is a central electrical node (M) connected to an electrical third conductor ( 1c is electrically connected, wherein the first and second conductor current (I1, I2) are generated by the first power semiconductor switch (T1) by a first drive means ( 5a ) which is electrically connected to a control input (G) of the first power semiconductor switch (T1) is switched on and off by means of a first drive signal (A1) and the second power semiconductor switch (T2) by a second drive means ( 5b ) electrically connected to a control input (G) of the second power semiconductor switch (T2) is turned on and off by means of a second drive signal (A2), thereby turning on and off the first and second power semiconductor switches (T1, T2) in that the first and second power semiconductor switches (T1, T2) are not switched on simultaneously, the pulse information signal (P1) for determining the first phase current (I1) and the pulse information signal (P2) for determining the second phase current (I2) being respectively based on of switching states of the first and / or second power semiconductor switch (T1, T2) are generated. The method of claim 7, wherein the method additionally for determining a third conductor current flowing through the third conductor (1c) (I3), wherein a third current measurement signal (U3) is determined by the first and second current measurement signal (U1m, U2m) added or be subtracted from each other, or if the first current measurement signal (U1m) is not zero, the first current measurement signal (U1m) as the third current measurement signal (U3) is output and if the first current measurement signal (U1m) is zero, the second current measurement signal (U2m) as a third current measurement signal (U3) is output. Power electronics module, with an electrical first conductor ( 1a ) and one to the first conductor ( 1a ) electrically connected in series first power semiconductor switch (T1), with an electrical second conductor ( 1b ) and one to the second conductor ( 1b ) electrically connected in series second power semiconductor switch (T2), wherein the first and second power semiconductor switch (T1, T2) are electrically connected in series, wherein the first power semiconductor switch (T1), a first diode (D1) is electrically connected in anti-parallel and to the second Power semiconductor switch (T2), a second diode (D2) is electrically connected in anti-parallel, wherein electrically between the first and second power semiconductor switch (T1, T2) a central electrical switching node (M) connected to an electrical third conductor ( 1c ) is electrically connected, wherein the power electronics module ( 14 ) electrically connected to a control input (G) of the first power semiconductor switch (T1) first drive means ( 5a ), which is designed to switch the first power semiconductor switch (T1) on and off by means of a first drive signal (A1) generated in front of it and has a second drive device (T2) electrically connected to a control input (G) of the second power semiconductor switch (T2), which is designed to switch on and off the second power semiconductor switch (T2) by means of a second drive signal (A2) generated in front of it, wherein the power electronics module ( 14 ) a first pulse information signal generating device ( 6a ) which is configured to generate a first pulse information signal (P1) having a first value and a second value based on switching states of the first and / or second power semiconductor switch (T1, T2), wherein the power electronics module ( 14 ) a second pulse information signal generating device ( 6b ) which is designed to generate a first and a second value having second pulse information signal ( P2 ) based on switching states of the first and / or second power semiconductor switch (T1, T2), wherein the power electronics module ( 14 ) first measuring input terminals (C1, C2) for connecting a first Rogowski coil ( 2a ) and second measuring input terminals (D1, D2) for connecting a second Rogowski coil ( 2 B ), wherein the power electronics module ( 14 ) a first integrator ( 4a ), which is designed to integrate in its integration memory (Ca) a first measuring signal (U1m) present between the first measuring input terminals (C1, C2), wherein the integration of the first measuring signal (U1m) in the integration memory (Ca) of the first integrator ( 4a ), controlled by the first pulse information signal (P1), such that in the period of a change of the first pulse information signal (P1) from its first value to its second value to a change of the first pulse information signal (P1) from its second value to its first Value, the integration memory (Ca) of the first integrator is erased, the power electronics module ( 14 ) is designed to generate a first current measuring signal (U1a) as a function of the value of the first integration memory (Ca), wherein the power electronics module ( 14 ) a second integrator ( 4b ) formed in its integration memory (Cb) between the second measuring input terminals (D1, D2) Aufintegrgendes second measuring signal (U2m) aufintegrieren, wherein the integration of the second measuring signal (U2m) in the integration memory (Cb) of the second integrator ( 4b Controlled by the second pulse information signal (P2), such that in the period of a change of the second pulse information signal (P2) from its first value to its second value to a change of the second pulse information signal (P2) from its second value to its first Value, the integration memory (Cb) of the second integrator ( 4b ), the power electronics module ( 14 ) is designed to generate a second current measuring signal (U2a) as a function of the value of the integration memory (Cb) of the second integrator (Cb). Power electronics module according to claim 9, characterized in that the first pulse information signal generating device ( 6a ) is adapted to generate the first pulse information signal (P1) based on the switching states of the second power semiconductor switch (T2) such that the first pulse information signal (P1) assumes the first value when the second power semiconductor switch (T2) is turned off and assumes the second value when the second power semiconductor switch (T2) is turned on, and the second pulse information signal generating means (T2) 6b ) is configured to generate the second pulse information signal (P2) based on the switching states of the first power semiconductor switch (T1) so that the second pulse information signal (P2) takes the first value when the first power semiconductor switch (T1) is turned off and takes the second value when the first power semiconductor switch (T1) is turned on. Power electronics module according to claim 9, characterized in that the first pulse information signal generating device ( 6a ) is adapted to generate the first pulse information signal (P1) based on the switching states of the first power semiconductor switch (T1) such that the first pulse information signal (P1) assumes the first value when the first power semiconductor switch (T1) is turned on and takes the second value when the first power semiconductor switch (T1) is turned off, and the second pulse information signal generating means (T1) 6b ) is adapted to generate the second pulse information signal (P2) based on the switching states of the second power semiconductor switch (T2) such that the second pulse information signal (P2) assumes the first value when the second power semiconductor switch (T2) is turned on and takes the second value when the second power semiconductor switch (T2) is turned off. Power electronics module according to one of claims 9 to 11, characterized in that the integration of the first measuring signal (U1m) in the integration memory (Ca) of the first integrator ( 4a ), controlled by the first pulse information signal (P1), takes place in such a way that when the first pulse information signal (P1) is changed from its first value to its second value, the integration memory (Ca) of the first integrator (P1) 4a ) is cleared and remains until a change of the first pulse information signal (P1) from its second value to its first value, in the cleared state, and that the integration of the second measurement signal (U2m) in the integration memory (Cb) of the second integrator ( 4b ), controlled by the second pulse information signal (P2), takes place in such a way that upon a change of the second pulse information signal (P2) from its first value to its second value, the integration memory (Cb) of the second integrator ( 4b ) is cleared and remains until a change of the second pulse information signal (P2) from its second value to its first value, in the cleared state. Power electronics module according to one of claims 9 to 11, characterized in that the integration of the first measuring signal (U1m) in the integration memory (Ca) of the first integrator ( 4a ), controlled by the first pulse information signal (P1), takes place such that when the first pulse information signal (P1) is changed from its second value to its first value, the integration memory (Ca) of the first integrator (P1) 4a ) and that the integration of the second measuring signal (U2m) in the integration memory (Cb) of the second integrator ( 4b ), controlled by the second pulse information signal (P2), takes place such that when the second pulse information signal (P2) changes from its second value to its first value, the integration memory (Cb) of the second integrator (P2) 4b ), or that the integration of the first measurement signal (U1m) in the integration memory (Ca) of the first integrator ( 4a ), controlled by the first pulse information signal (P1), takes place in such a way that when the first pulse information signal (P1) is changed from its first value to its second value, the integration memory (Ca) of the first integrator (P1) 4a ) and that the integration of the second measuring signal (U2m) in the integration memory (Cb) of the second integrator ( 4b ), controlled by the second pulse information signal (P2), takes place in such a way that when the second pulse information signal (P2) is changed from its first value to its second value, the integration memory (Cb) of the second integrator (P2) 4b ), or that the integration of the first measurement signal (U1m) in the integration memory (Ca) of the first integrator ( 4a ), controlled by the first pulse information signal (P1), takes place such that in the period between a change of the first pulse information signal (P1) from its second value to its first value and a change of the first pulse information signal (P1) from its first value to its second value, the integration memory (Ca) of the first integrator ( 4a ) and that the integration of the second measuring signal (U2m) in the integration memory (Cb) of the second integrator ( 4b ), controlled by the second pulse information signal (P2), is such that in the period between a change of the second pulse information signal (P2) from its second value to its first value and a change of the second pulse information signal (P2) from its first value to its second value , the integration memory (Cb) of the second integrator ( 4b ) is deleted. Power electronics module according to one of claims 9 to 13, characterized in that the integration memory (Ca) of the first integrator ( 4a ) in the form of an electrical first capacitor (Ca), wherein the integration memory (Ca) of the first intergartor ( 4a ) controlled by the first pulse information signal (P1) is canceled by electrically switching the first capacitor (Ca) by turning on a first switch (Sa) electrically connected to the first capacitor (Ca), which is electrically parallel to the first capacitor (Ca) switched current branch ( 9a ), wherein the switching on and off of the first switch (Sa) controlled by the first pulse information signal (P1) takes place, and that the integration memory (Cb) of the second integrator ( 4b ) in the form of an electrical second capacitor (Cb), wherein the integration memory (Cb) of the second intergartor ( 4b ) controlled by the second pulse information signal (P2) is canceled by electrically switching the second capacitor (Cb) by turning on a second switch (Sb) electrically connected to the second capacitor (Cb) in parallel with the second capacitor (Cb) switched current branch ( 9b ) is discharged, wherein the switching on and off of the second switch (Sb) controlled by the second pulse information signal (P2). Power electronics module according to claim 14, characterized in that the first integrator ( 4a ) a first operational amplifier ( 3a ), the first capacitor (Ca) and an electrical first resistor (Ra), wherein a first measuring input terminal (C1) of the first measuring input terminals (C1, C2) via a first current measuring branch ( 7a ) to the first input (-) of the first operational amplifier ( 3a ) is electrically connected and a second measuring input terminal (C2) of the first measuring input terminals (C1, C2) via a second current measuring branch ( 8a ) to the second input (+) of the first operational amplifier ( 3a electrically connected between the first measuring input terminal (C1) of the first measuring input terminals (C1, C2) and the first input (+) of the first operational amplifier (R1). 3a ), wherein the first capacitor (Ca) electrically between the first input (-) of the first operational amplifier ( 3a ) and an output of the first operational amplifier ( 3a ), wherein the first current measuring signal (U1a) at the output of the first operational amplifier ( 3a ) and that the second integrator ( 4b ) a second operational amplifier ( 3b ), the second capacitor (Cb) and an electrical second resistor (Rb), wherein a first measuring input terminal (D1) of the second measuring input terminals (D1, D2) via a third current measuring branch ( 7b ) with the first input (-) of the second operational amplifier ( 3b ) is electrically connected and a second measuring input terminal ( D2 ) of the second measuring input terminals (D1, D2) via a fourth current measuring branch ( 8b ) to the second input (+) of the second operational amplifier ( 3b electrically connected between the first measuring input terminal (D1) of the second measuring input terminals (D1, D2) and the first input (+) of the second operational amplifier (R). 3b ), wherein the second capacitor (Cb) electrically between the first input (+) of the second operational amplifier ( 3b ) and an output of the second operational amplifier ( 3b ), wherein the second current measuring signal (U2m) at the output of the second operational amplifier ( 3b ) is present. Power electronics module according to one of claims 9 to 15, characterized in that the power electronics module ( 14 ) a conductor current determining device ( 12 ), which is designed to detect one by the third conductor ( 1c ) flowing third conductor current (I3) in the form of a third current measuring signal (U3) from the first and second current measuring signal (U1a, U2a), by the conductor current detecting means ( 12 ) the first and second current measuring signal (U1a, U2a) are added or subtracted from each other, or if the first current measuring signal (U1a) is not zero, the first current measuring signal (U1a) as the third current measuring signal (U3) from the conductor current detecting device ( 12 ) and when the first current measuring signal (U1a) is zero, the second current measuring signal (U2a) is output from the conductor current detecting device ( 12 ) as the third current measurement signal (U3). Power electronic device with a power electronics module according to one of Claims 9 to 16 and with a power conductor around the first conductor ( 1c ) arranged first Rogowski coil ( 2a ) and with one around the second conductor ( 1b ) arranged second Rogowski coil ( 2 B ), the first Rogowski coil ( 2a ) electrically connected to the first measuring input terminals (C1, C2) and the second Rogowski Kitchen sink ( 2 B ) is electrically connected to the second measuring input terminals (D1, D2).

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