DE102015115022A1 - Method for changing the configuration of a programmable logic device - Google Patents

Abstract

In a method for changing the configuration of a programmable logic module, an output configuration of the programmable logic module is read, so that a logic description, in particular a placed network list, the output configuration is at least partially present. One or more logic elements and / or connectors are replaced or reconfigured from the logic description of the programmable logic device output configuration and a logic description of a target configuration is created having no or more additional logic elements, with none or more elements of the output configuration missing in the target configuration. On the basis of allocation information transfer points determined, ie in target and output configuration existing logic elements, in particular registers, and / or Verschaltungselemente to which a modified logic function is applied in the target configuration, wherein at least the unused in the initial configuration logic elements of the programmable logic device marked as free and the additional logic elements of the target configuration are placed on the freely marked logic elements and connected to the transfer points via unused connection elements. From the logic description of the target configuration, a modified bit stream is created and the changed bit stream is written to the programmable logic device.

Description

The invention relates to a method for changing the configuration of a programmable logic module, a method for adapting a control unit, which comprises a programmable logic module set up to execute a control function, and a programming device for writing a programmable logic module.

In many fields of technology, control devices are used to control a physical process, wherein a microcontroller of the control device cyclically executes a program which comprises the determination of new measured values of one or more sensors and the actuation of one or more actuators based on a comparison of the measured values with setpoints. To speed up the design of new control devices or control algorithms is often placed on an existing controller and only single (sub) functions replaced. This procedure, also known as bypassing, can either be completely implemented on the existing control unit (internal bypassing) or resort to a separate Rapid Control Prototyping System (RCP system) for calling the new function (s), the so-called bypass functions (external bypassing). The replacement of individual functions may conveniently be done by the adaptation of jump instructions.

From the EP 2869145 A1 a method for influencing a control program of a control unit is known, wherein the control program comprises a plurality of first functions, of which at least one is designed for the control of an actuator, and wherein a memory is provided, having the first functions associated with subroutines occupied memory areas , The control program is present as a binary program code, wherein in the program code of the control program in the call of one of the first functions there is a jump address pointing to a memory address of the subroutine associated with the function call, and wherein the subroutine is a sequence of binary program code and at the end of the sequence of the program code of the subroutine, there is a return instruction. The program code of the control program is examined for the occurrence of function calls, and the jump addresses associated with the function calls and addresses of the return instructions are determined, wherein the determination of the size determines the memory areas of the memory occupied by the respective subroutines. The identifiers associated with the first functions with the respective first functions and addresses of the memory areas are displayed in a display unit which is formed as part of a computer system. By means of the computer system, at least one of the first functions is selected as to be deleted, the size and address of the selected first function is stored in a function structure, and at least one function call of the selected first function is deactivated and / or the first function is replaced by a second function the program code of the selected first function is overwritten by the program code of the second function.

For the simulation and control of systems with high dynamics increasingly known programmable logic devices are used under the term Field Programmable Gate Array (abbreviated FPGA), which also reliably regulate rapidly changing paths due to parallel processing and a logic circuit custom-tailored for the respective application. Since, unlike microprocessors, there is no sequential processing and there are no jump instructions, so far no bypassing can be performed for the control functions implemented on an FPGA. A further disadvantage of the use of FPGA is that small adaptations to the individual logic functions are only possible to a limited extent since the circuit must be completely re-synthesized, which is time-consuming, in particular due to the optimization of placement and routing. It would therefore be desirable to provide a simple way of adapting logic functions also for programmable logic devices.

• • Bereits im Initialdesign müssen die Partitionsschnittstellen geplant und fest implementiert werden.
• • Unabhängig von der in der zweiten Partition realisierten Funktionalität bzw. implementierten Logikfunktion ist eine feste Anzahl von Logikeinheiten und Verbindungselementen reserviert. Durch die somit erforderliche Reservierung der größten anzunehmenden Anzahl erforderlicher Logikelemente bleiben in vielen Fällen Ressourcen ungenutzt.
• • Alle auf der ersten Partition angeordneten Logikfunktionen bleiben fest; auch dann, wenn die aktuell realisierte Funktionalität der zweiten Partition diese nicht benötigt, bleibt ein Platz- und Energiebedarf der Funktionen erhalten.

A partial reconfiguration is an example from the US 7,902,866 B2 Known procedure to be able to change the configuration of an FPGA later or at runtime. In preparation for this, the FPGA configuration must already be partitioned into partitions during the design phase, for example, creating a first partition and a second partition. The first partition provides immutable or always-on logic functions. The second partition then represents a delimited area for which a partial re-synthesis and a partial reconfiguration are possible, so that in principle the logic functions arranged on the second partition can be changed. However, this approach has a number of disadvantages:

• • Already in the initial design, the partition interfaces have to be planned and firmly implemented.
• • Regardless of the functionality or logic implemented in the second partition, a fixed number of logic units and connectors are reserved. Due to the thus required reservation of the largest the number of required logic elements to be assumed in many cases remains unused resources.
• • All logic functions arranged on the first partition remain fixed; even if the currently implemented functionality of the second partition does not require them, a space and energy requirement of the functions is maintained.

For the design and editing of FPGA configuration has been "Torc: Towards an Open Source Tool Flow," Proceedings of the 19th Annual ACM / SIGDA International Symposium on Field Programmable Gate Arrays, 2011, by N. Steiner et al. which, for example, can read and write a logic description in the form of an unplaced or placed netlist. Based on this description RK Soni et al. in "Open-Source Bitstream Generation," 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines 2013 , a way to make quick modifications to a bitstream that describes an FPGA configuration. With the help of a library of micro-bit streams, which each describe individual basic units, additional logic elements can be added to an existing configuration based on a placed netlist.

With "Rapid Smith: Do-It-Yourself CAD Tools for Xilinx FPGAs", 2011 21st International Conference on Field Programmable Logic and Applications, by C. Lavin et al. Another design tool for FPGA configurations has become known. Building on this is in the paper "Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs," 22nd IEEE Annual International Symposium on Field Programmable Custom Computing Machines 2014, by BL Hutchings and J. Keeley described a way to modify an existing FPGA configuration without recompiling or synthesizing the complete circuit. Using previously unused logic elements or areas of the FPGA, measuring circuits can thus be subsequently introduced into an otherwise unchanged FPGA configuration. An adaptation of individual logic functions and thus a change of the output values or signals does not take place.

Against this background, the object of the invention is to provide a method and a device, which further develop the prior art, and preferably allow a comparable with the known bypassing functionality in the development of programmable logic devices comprehensive control devices.

The object is achieved by a method for changing the configuration of a programmable logic module having the features of claim 1 and a programming device having the features of claim 16.

Advantageous embodiments of the invention are the subject of dependent subclaims.

The invention thus provides a method for changing the configuration of a programmable logic module, in which an output configuration of the programmable logic module is read, so that a logic description, in particular a placed netlist, the output configuration is at least partially present, wherein from the logic description of the output configuration of the programmable logic device or a plurality of logic elements and / or connectors are replaced or reconfigured and a logic description of a target configuration is created that has no, one or more additional logic elements, wherein none, one or more elements of the initial configuration are not used in the target configuration. On the basis of allocation information, transfer points are determined, ie logic elements or their inputs or outputs present in the target and output configuration, in particular registers or drivers, to which a modified logic function is applied in the target configuration, whereby at least the logic elements of the programmable logic elements not already used in the initial configuration Logic blocks are marked as free and the additional logic elements of the target configuration are placed on the freely marked logic elements and connected via unused connecting elements with the transfer points. From the logic description of the target configuration, a modified bit stream is created and the changed bit stream is written to the programmable logic device.

Programmable logic devices include, in particular under the abbreviations FPGA, CPLD and PLD known components, which have a plurality of logic elements and a plurality of connecting elements, the exact configuration is set after a restart of the block based on a read bit stream. For this purpose, programmable logic devices expediently have a configuration memory which comprises at least one bit for each logic element and each switchable connection element and is preferably made up of static memory cells (SRAM, in particular in the case of FPGAs) or nonvolatile memories (FLASH, in particular in the case of PLDs).

Under a logic element here are elementary units of the programmable logic device as registers, truth tables and delay units to understand. Preferably For example, logic elements also include drivers, in particular for an interface pin of an FPGA, as well as fixed, dedicated logic circuits, for example, for multiplying a plurality of values. A reconfiguration of a logic element is expediently meant to change at least one property of the logic element. For example, reconfiguring a truth table would mean that at least one output value of the table has changed from the initial configuration; In the case of a dedicated logic circuit, for example, the reconfiguration could also consist in the application of a clock or the activation or deactivation of the dedicated logic circuit.

The replacement or reconfiguration of one or more logic elements and / or connection elements of the output configuration preferably takes place on the basis of assignment information, which in particular may have been provided by the manufacturer of the output configuration. If there is no complete logic description of the output configuration, then the mapping information expediently includes at least available input signals and possible output points. The mapping information may include a list of handover points specified directly by the manufacturer of the initial configuration; alternatively or additionally, the user can specify one or more transfer points. A modified logic function is applied to a transfer point in particular if the signal path of an input of the transfer point contains at least one additional or reconfigured logic element. Logic functions suitably comprise a number of consecutive logic elements, wherein at least partially an output of a first logic element is connected to an input of a second logic element so that a continuous signal path exists from an input of the logic function to an output. Preferably, logic functions are considered starting from an interface pin of the programmable logic module configured for the reception of signals.

By additional logic elements of the target configuration are meant those logic elements which are located in the target configuration in a signal path but in the initial configuration neither directly nor indirectly, i. via further logic elements, were connected to an output or an interface pin of the programmable logic device. In order to continue to operate the target configuration at high FPGA clock rates, it is preferred to use free logic elements in the vicinity (e.g., within a defined radius) of the particular transfer point. This avoids excessive delays due to long signal paths.

A configuration of the FPGA can be displayed in several levels. At the lowest level there is a bitstream describing the configuration, which can be written directly into the configuration memory of the FPGA. In the next higher level, the logic description is in the form of a placed netlist in which a desired functionality has already been mapped to the logic and interconnection elements and thus can be translated in a bitstream. The next highest level is a logic description in the form of an unplaced netlist, in which no mapping has yet been made to concrete elements of the respective FPGA chip. Depending on the procedure used to create the configuration, even higher abstraction levels may be present, so that a description of the configuration may be available in a hardware description language such as VHDL or SystemC, which is then converted into a netlist. The description in the form of a block diagram of a technical computing environment such as Matlab and Simulink is also possible because e.g. Using the Xilinx System Generator, the block diagram can be translated into a representation of the FPGA configuration in a hardware description language. In this case, it can also be provided that a list of possible transfer points is automatically generated on the basis of the block diagram, which is e.g. contains the logic elements corresponding to the inputs and outputs of a block or subsystem.

The writing of the modified bit stream can be done completely or differentially, so that a modified bit stream is preferably written only for changed logic elements or regions. The writing of the changed bit stream into the programmable logic module means, in particular, a description of the configuration memory of the programmable logic module, whereby only the frames or address areas of the configuration memory which contain one or more reconfigured or additional logic elements or connection elements are expediently described in a differential write. In this case, it may also be provided to describe a nonvolatile memory which is read out during initialization of the programmable logic module and determines the content of the configuration memory; Thus, the writing of the changed bit stream in the programmable logic device can be done indirectly.

An important advantage of the method according to the invention is that small changes to logic functions can be carried out very quickly, since only the newly added parts of a logic function have to be placed and routed. This allows a functionality comparable to internal bypassing, even for ECUs, which include an FPGA. Thus, a variety of incremental changes can be made and tested in a timely manner, allowing retention of the established controller design workflow.

By providing relevant structural or mapping information in addition to the original bitstream, the manufacturer of the output configuration can make changes to logic functions without having to disclose the entire logic description of the configuration. On the one hand, the manufacturer can thus keep the detailed source code secret and, on the other hand, provide interfaces that enable the user to rapidly adapt proven logic functions.

Furthermore, it is advantageous that no pre-implemented partition interfaces or "virtual sockets" are required; The fact that there is no division into several partitions with corresponding empty areas allows the existing logic and connection elements of the FPGA module to be used efficiently.

A further advantage is that by adapting the programming bit stream, which is preferably stored in a non-volatile memory, a desired functionality is immediately available after a restart of the control unit without delay. The non-volatile memory used for the initialization of the programmable logic device can be read via a microcontroller or a correspondingly configured additional logic device such as a CPLD, which are expediently arranged with the programmable logic device on a printed circuit board or integrated in the control unit; In principle, the programmable logic module may also include a non-volatile memory.

If a sufficient number of free logic elements are available in the initial configuration, it may be provided to remove only the connection of disused logic elements to the transfer points and to realize the changed logic functions exclusively by means of already unused logic elements. Even in the case where the allocation information includes only the transfer points and a list of the originally free logic elements, it is thus possible to change the configuration of the programmable logic device.

According to a preferred embodiment of the invention, the logic elements of the output configuration, which are not used in the target configuration and whose outputs are connected only to one or more inputs of at least one of the transfer points, are marked as free. Thus, if an output of a logic element in the output configuration is connected to an input of a transfer point, but the input of the transfer point in the destination configuration is connected to another logic element, then the logic element in the destination configuration is not used and can be marked as free , Preferably, furthermore, the corresponding connection elements are marked as not used. In this case, the corresponding connection elements in particular comprise switchable connection elements which in the output configuration connect the output of the logic element marked as free with one or more interconnects and connect this interconnect to one or more inputs of one or more transfer points, and expediently unlink them in the target configuration. n trace / s. By releasing or cleaning up unused logic elements, the free area or the number of logic elements available for the reconfiguration is maximized. Releasing logic and interconnect elements is particularly advantageous when the output configuration almost completely fills the resources of the FPGA device.

In a particularly preferred embodiment of the invention, all logic elements whose outputs are connected exclusively to the inputs of logic elements marked as free in a previous step recursively are also marked as free. If the output of a logic element is only connected to the input of a logic element marked as free in a previous step, ie the output value would be discarded, then the logic element is no longer used and can also be marked as free. Thus, all logic elements no longer needed and expediently no longer required connecting elements are released gradually.

According to a further particularly preferred embodiment of the invention, all logic elements in a given region are marked as free around one or more replaced logic elements of the initial configuration or an input of a transfer point and the corresponding connection elements marked as unused, all logic elements in the given region except the or then replaced the replaced logic elements and connected to unused fasteners. With a suitable choice of the region (for example based on a defined radius around the respective transfer point), an optimization of the placement or routing can thus also take place, whereby a largely optimal temporal behavior is ensured with only a small increase in the required design time.

In a very particularly preferred embodiment of the invention, the connecting elements used in the initial configuration, which terminate at one of the logic elements in the predetermined region, are marked as unused at least as far as the next connected logic element outside the predetermined region. This ensures that sufficient connection elements for optimized routing are available in the given region.

The step of reading in an output configuration expediently comprises reading in a bit stream and converting the bit stream at least for parts of the bit stream into a logic description. The conversion can in particular be based on architectural information of the programmable logic device used, so that a relationship between position in the bit stream and logic element is made on the programmable logic device based on architectural information of the programmable logic device used.

It is advantageous if the modified bit stream is created on the basis of the target configuration by establishing a relationship between position in the bit stream and logic element on the programmable logic module for the changed and thus to be reconfigured logic elements and the original bit stream is changed at the corresponding positions. In this case, it may be provided to create a differential bit stream which only describes the changed logic and connection elements or only comprises address areas in which at least one changed logic element is located. Thus, if proper architectural or mapping information is available, only a minimum of data needs to be written.

Alternatively, it is advantageous if the modified bitstream is created based on the target configuration by translating the placed netlist of the target configuration into a new complete bitstream. If there is a placed netlist of the entire target configuration, a fast creation of the changed bitstream is possible.

Preferably, for a logic function to be changed, which comprises at least one signal path, a signal propagation time is determined at least after the change. Preferably, a signal transit time is estimated for a signal path in the target configuration of the programmable logic device in the course of which at least one additional or reconfigured logic element or connection element is counted by counting the number of sequentially consecutive logic elements of the signal path in the target configuration and assigning each logic element a constant signal transit time becomes. Alternatively, it can also be provided to compare a signal path in the target configuration of the programmable logic module, in the course of which at least one additional or reconfigured logic element occurs, with the corresponding signal path in the output configuration, in particular by the number of sequentially consecutive logic elements of the signal path in the target configuration and the number of sequentially sequential logic elements of the corresponding signal path is counted and compared in the output configuration and a constant signal transit time is assigned to each logic element. In this way, it can be quickly and easily determined whether the target configuration is expected to operate at the same clock rate as the initial configuration, or whether problems in the timing of the circuit are to be expected.

Particularly preferably, instead of an estimate of the signal propagation times of logic elements based on the number of logic elements in the signal path, the minimum and maximum signal propagation times given by architectural information are determined and used for the further considerations. Appropriately, a summation of each of the minimum and respectively the maximum signal propagation times of the individual logic elements via a signal path can be carried out, and these are checked for compliance with time requirements, in particular the subsequent logic elements.

Particularly preferably, at least one signal transit time is determined for all logic functions to be changed and compared with one or more threshold values, which in particular describe time requirements of the transfer points following the changed logic function. If the change in the estimated or calculated delay exceeds the threshold, a warning and / or modification of the placed netlist of the target configuration occurs. For example, the modification may include a local increase of the clock and / or an insertion of registers. Thus, the user can be notified in advance of a potentially critical timing and measures are taken to ensure a defined temporal behavior of the target configuration.

Preferably, the target configuration comprises at least a first multiplexer, in particular arranged directly in front of a transfer point, with all the added logic elements being arranged in new signal paths comprising a single input of the first multiplexer. By the bypass function is connected to a first input of the multiplexer and the previous logic function is connected to a second input of the multiplexer, thus at runtime, ie while the target configuration is being executed, switching between the bypass function and the original function is made. In this case, a free input of an existing multiplexer can be used or the multiplexer can be inserted.

In particular, the new signal paths comprise at least one interface pin of the programmable logic module, wherein the at least one interface pin is preferably assigned to a debugging interface of the programmable logic module. The interface pin does not have to be used exclusively for the new signal path, but can also provide additional functionalities. Preferably, a protocol is defined so that the data required for the signal path is tunneled through the interface pin. In this respect, this interface pin does not have to be a physically present pin, but may also be an interface or a data channel, which is expediently set up using the debug interface. If at least one interface pin of the FPGA module is unoccupied or can be supplemented in functionality, an external bypassing can therefore take place or else a multiplexer for switching between different internal logic functions can be controlled externally. The interface pins associated with a debugging interface are rarely populated with other functions and thus often available. In principle, if one or more other interface pins are still unoccupied, a higher data rate can also be ensured in the case of external bypassing by transmitting these interface pins for transmission according to a suitable protocol, such as e.g. LVDS can be used.

It is advantageous if the target configuration comprises at least one second multiplexer, which in particular is arranged directly behind a transfer point, wherein the second multiplexer is connected to at least one input of a logic element. This makes it possible to change the input signals of a function, where necessary, the original function can be used with the changed input signal.

Preferably, the target configuration comprises at least one added register, wherein the output of the register is preferably connected to an interface pin, which is assigned in particular to a debugging interface of the programmable logic module. By placing the register in a signal path, the corresponding signal can also be detected and evaluated by an RCP system which is connected to the debugging interface.

The invention further relates to a method for adapting a control device, which comprises a programmable logic device set up to execute a control function, in which the programmable logic device is reconfigured by a method according to the invention. By using a method according to the invention, it is therefore also possible for control devices comprising FPGAs to be adapted quickly and easily, so that an iterative development of the new control function is possible. By the term control function, all functions provided by the control unit or the programmable logic module are expediently meant, in particular a control of an actuator without a closed control loop.

Appropriately, at least the step of writing a changed bit stream into the programmable logic device takes place during the initialization of the programmable logic device, and is carried out in particular by a microprocessor. Thus, the adapted logic function or the bypass function is available directly at the start time of the FPGA or the FPGA comprehensive control unit.

Moreover, the invention relates to a programming device for writing a programmable logic device, comprising a processor, a programming interface and / or a debugging interface, wherein the device is adapted to perform a method according to the invention.

The invention further relates to a computer program product with a computer-readable storage medium, on which instructions are embedded, which, when executed by a computing unit, cause the arithmetic unit to be configured to carry out a method according to the invention.

The invention will be explained in more detail with reference to the drawings. Here similar parts are labeled with identical names. The illustrated embodiments are highly schematic, i. the distances and the lateral and vertical dimensions are not to scale and, unless otherwise indicated, have no derivable geometrical relations to one another.

It shows:

1 a schematic flowchart of a first preferred embodiment of a method according to the invention,

2a a schematic representation of a modified configuration of a programmable logic device,

2 B a schematic representation of a second preferred embodiment of a method according to the invention,

3 a schematic view of a programmable logic device that can be reconfigured with a method according to the invention, and

4 a schematic view of a control device with a programmable logic device and a programming device according to the invention.

An FPGA device comprises a multiplicity of logic elements and connecting elements as well as a clock supply, which can comprise a plurality of clock regions. The logic elements include, for example, registers, truth tables (also known as lookup tables or LUTs), adders, switches and delay units. Frequency generators can also be present. Depending on the granularity of the FPGA module, several of these elements may also be combined into one elementary unit. The connecting elements suitably comprise conductor tracks of different lengths, which are e.g. can also span regions of the FPGA, and switchable connections between the tracks and logic elements. After turning on the power supply, the FPGA is initialized with a bit stream which expediently contains at least one bit for each logic element; this enables a custom-tailored logic circuit on a standard device. In this case, a bit for the configuration of a logic element can also be understood to mean a switch which connects the logic element to a signal. In this sense, one or more configuration bits can also be assigned to an AND gate.

The picture of the 1 shows a schematic flowchart of a first preferred embodiment of a method according to the invention.

In step S1 (read in), the output configuration is read in, the input data being the original bit stream (bit stream 1) and information (info) about the architecture of the FPGA block used and the output configuration being received. The reading may include converting the bitstream into a logic description or placed netlist of the source configuration. Alternatively, it can also be provided to receive as input data in addition to the bit stream also a logic description of at least parts of the output configuration as well as information about possible input signals and possible transfer points of the output configuration. Then can be dispensed with a conversion of the bitstream.

The changes desired in the target configuration are preferably made on a higher level of abstraction, such as the logic description or an unplaced netlist, in step S2 (change). In principle, a hardware description language such as VHDL could also be used to specify the target configuration or the desired changes.

For example, the user can select new input signals and create an adapted logic function at the respective transfer point. This configuration change can also be made interactively in a program executed on a standard PC and / or a special programming device connected to the FPGA module or to the controller; Even a standard PC with externally connected debugging interface, which can be connected to an FPGA, should be understood by the term programming device.

Such a program, hereafter referred to as FPGA manager, could be e.g. the assignment information of the configuration manufacturer, expediently architectural information of the FPGA module used and at least one logic description, in particular a placed netlist, and / or read a bit stream of the output configuration. It is advantageous if the FPGA manager is set up to present the output configuration at least partially in a higher level of abstraction, such as a logic description of an unplaced netlist or a block diagram. Then the user can select and adapt one or more elementary units of the respective abstraction level. Expediently, the deletion or insertion of elementary units is provided. The elementary units may include one or more logic units of the FPGA device. For example, a frequently used functionality can be predefined from a plurality of logic units of the FPGA as an elementary unit. Preferably, the user can continue to select predefined transfer points and / or interface pins of the FPGA to supply the signals of the changed logic functions. Also, a check of predetermined conditions may be provided, in particular, a separate signal can be output via a debugging interface, if the predetermined conditions are not met. Thus, an erroneously defined logic function or invalid input data can be quickly recognized.

In step S3 (purge), unused logic elements are expediently removed from the output configuration in order to make available a larger number of free logic elements for realizing the changed logic functions.

The FPGA Manager can also provide for determining the disused logic elements based on the deleted elementary units.

In step S4 (placement), the logic functions or logic elements added in the target configuration are placed on the free logic elements. Then, the connectors are configured to obtain the desired signal paths. Thus, the destination configuration exists as a placed netlist. In the context of placing and connecting the logic functions or logic elements thereby expediently timing requirements such. observing the required signal propagation delays to achieve predetermined clock frequencies.

The FPGA Manager may also provide for determining added logic elements based on the added elementary units.

In step S5 (convert), the placed netlist is converted into a changed bitstream, which is thus available as output data (bitstream 2).

Especially if the logic description of the output configuration is only partially available, the conversion may also be to generate appropriate micro bitstreams for added logic units and / or connection units and to add them to the original bitstream to obtain the changed bitstream.

The FPGA block is written in step S6 (Write) with the changed bit stream and thus reconfigured. Since a time-consuming placement and routing was done only for the few changed logic elements, this reconfiguration can be done quickly and is in principle possible without a knowledge of the complete network list.

In the picture of the 2a a modified configuration of a programmable logic device is shown schematically.

The configuration 201 includes two transfer points 202 and 203 , which provide input signals a and b, as well as a transfer point 204 to which the function result y is applied. The handover points are preferably determined by the user by means of the FPGA manager or can be manually or automatically selected based on a list of possible handover points provided by the manufacturer of the original configuration.

Schematically, it is shown that the area occupied by the original logic function f 205 has been released, and that the added logic function y = g (a, b) in one area 206 is implemented using free or unused logic and connectors, so that the exterior of the configuration 201 remains unaffected by the change.

The picture of the 2 B shows a schematic representation of a second preferred embodiment of a method according to the invention.

At the beginning of the procedure will be the original configuration 210 of the FPGA and mapping information 211 read. The output configuration in FPGA Bitstream 1 includes a logic function y = f (a, b), which should be replaced. As information about this, the two transfer points are indicated, on which the input signals a and b are applied, as well as the transfer point at which the function value y is to be applied. Depending on the FPGA chip used, bitstream 210 on the one hand have a fixed assignment between position and logic element or on the other hand comprise a list of address / configuration pairs. Thus, in principle starting from a start address, an entire address range (or the entire FPGA) can be rewritten, or the logic elements can be individually reconfigured.

In step 212 the bitstream is converted 210 in a placed netlist 213 , The placed netlist 213 is done using the specified transfer points and expediently architectural information of the FPGA in step 214 analyzed, whereupon in step 215 a cleanup takes place in which unused logic and interconnect elements are marked as free or unused. The adjusted FPGA netlist 216 thus has free logic elements or area, which can be used for the realization of the new function.

The new logic function 217 , which can be described in particular by means of a block diagram, is preferably based on the same input signals a, b as the original function and outputs a changed value y = g (a, b). In step 218 Therefore, a synthesis of the changed logic function, that is, the logic description of the subfunction is in an unplaced part netlist 219 converted.

Based on the information 211 over the transfer points, will step in 220 an insertion the part netlist 219 into the adjusted FPGA netlist 216 so that a netlist describing the complete configuration is made 221 arises.

The still unplaced new logic function 217 will be in step 222 placed on the free logic elements and routed with unused connectors. In step 223 the complete netlist is converted into a new bit stream 224 , Thus, there is a complete FPGA bitstream 2 describing the target configuration, which can be written directly or indirectly into a programmable logic device.

In the picture of the 3 is a programmable logic device 1 shown schematically. Via interface pins 2 . 3 . 4 . 5 . 6 . 7 The FPGA receives 1 input signal. The illustrated example configuration has a plurality of function blocks, which are shown in simplified form and which are basically constructed from a series of elementary logic units such as truth tables and flip-flops. The at the interface pins 2 . 3 . 4 adjacent input signals, for example, function block 8th supplied, which calculates a first logic function. Accordingly, those at the interface pins 5 . 6 . 7 applied input signals function block 9 supplied, which calculates a second logic function. The signals of the function blocks 8th and 9 become another functional block 10 supplied, which calculates a third logic function. Via multiplexer 11 the function result of the third logic function can be an interface pin 12 of the programmable logic device 1 be supplied and is thus output as an output signal. As a dashed line is an exemplary signal path 16 shown. The logic function shown, whose output signal is at the interface pin 12 is output, thus includes 6 Signal paths, each at one of the interface pins 2 . 3 . 4 . 5 . 6 . 7 kick off.

By one of the functional blocks 8th . 9 or 10 changed or replaced, the output logic function can be modified. As an alternative to a complete replacement of the original logic function, switching can also be enabled by maintaining the original logic function and integrating a modified logic function in the configuration, and by arranging a multiplexer at the output of the corresponding function block. In addition, a preprocessing of the input signals of a logic function can be inserted. In particular, it is possible to integrate an additional logic function that outputs a truth value on the validity of the input signals in response to one or more conditions. Also, inserting additional registers to maintain consistent data can be done. If the FPGA 1 is used in a control unit, then an internal bypassing can be made.

By adding another input of the adjacent pin to the output pin 12 arranged multiplexer 11 with one via another interface pin 14 can also connect an external signal to interface pin 12 be issued. To avoid synchronization problems, it is useful if the signal from interface pin 14 a register 15 is fed, so that always a defined signal to multiplexer 11 is applied. Via interface pin 13 can be the desired input from multiplexer 11 selected and thus in the signal path 16 arranged output signal to be changed. It is advantageous if the interface pins 14 and 13 are associated with a debugging interface such as JTAG, since these pins are generally not occupied and / or via this debugging interface, expediently by extending the existing debugging function protocols, signals in or out of the FPGA can be transmitted. If the FPGA 1 is used in a control unit, then an external bypassing is also possible.

The picture of the 4 shows a schematic view of a controller 30 with a programmable logic device 33 and a programming device according to the invention 40 ,

control unit 30 includes a microcontroller 31 that with a non-volatile memory 32 , especially a flash memory, and with the FPGA 33 connected is. microcontroller 31 may also be connected to one or more interfaces, not shown, in particular for a vehicle data bus, and / or other peripherals.

The programmable logic device 33 preferably provides a control function and is in the example shown with a sensor 37 and a drive circuit 35 connected to an actor 36 controls. Furthermore, FPGA has a programming and / or debugging interface 34 on.

Usually is programming interface 34 not connected, and the controller provides one or more control functions; For example, actor 36 a brushless electric motor whose speed and / or output torque from the programmable logic device 33 is regulated.

programmer 40 includes a microcontroller 41 that with a non-volatile memory 42 , in particular a flash memory and a programming and / or debugging interface 44 connected is.

About dashed lines shown connecting lines 43 can the programming device 40 with the control unit 30 or the FPGA arranged thereon 33 get connected. By the programmable logic device 33 can be reconfigured, therefore, the control function can be adjusted with little effort.

In principle, a change of the configuration can also take place in that the programming device with the microcontroller 31 or the nonvolatile memory 32 is connected and the changed configuration first in the non-volatile memory 32 and only indirectly in the programmable logic device 33 is written. This has the advantage that the changed configuration also with every further initialization of the control unit 30 is immediately available.

The use of the debugging interface shown in the figure 34 has the advantage that this allows switching between different logic or control functions during operation of the controller. For this purpose, in the changed configuration, for example, directly in front of the with drive circuit 35 connected interface pin of the FPGA 33 a multiplexer are arranged, wherein a first input of the multiplexer is preferably connected to the original control function and a second input of the multiplexer is connected to a modified control function.

Particularly preferably, the input to be switched through is selected via a register connected to the switching input, so that the content of the register determines the active control function. By having a data channel through the debugging interface 34 is set up, the contents of the register from the programmer 40 to be discribed. Thus, the user can via programming device 40 switch between different control functions. This further speeds up the design of new control devices or control functions.

In a further preferred embodiment of the invention, a register is arranged in a signal path of the output configuration, wherein the output of the register is expediently connected to a pin of the FPGA assigned to the debugging interface. Thus, the register detects a signal of the output configuration and can transmit it to an external RCP system. By adding a trigger logic, the time of detection can be determined by evaluating given conditions. Alternatively or additionally, it can also be provided to buffer the signal on the programmable logic module. The method according to the invention thus makes it possible to add a measuring functionality to the initial configuration even without the presence of the source code or a complete logic description.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• EP 2869145 A1 [0003]
• US 7902866 B2 [0005]

Cited non-patent literature

• "Torc: Towards an Open Source Tool Flow," Proceedings of the 19th Annual ACM / SIGDA International Symposium on Field Programmable Gate Arrays, 2011, by N. Steiner et al. [0006]
• RK Soni et al. in "Open-Source Bitstream Generation", 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines 2013 [0006]
• "Rapid Smith: Do-It-Yourself CAD Tools for Xilinx FPGAs", 2011 21st International Conference on Field Programmable Logic and Applications, by C. Lavin et al. [0007]
• "Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs", 22nd IEEE Annual International Symposium on Field Programmable Custom Computing Machines 2014, by BL Hutchings and J. Keeley [0007]

Claims (17)

 Method for changing the configuration of a programmable logic module, in which an output configuration of the programmable logic module is read, so that a logic description, in particular a placed network list, the output configuration is at least partially present, wherein from the logic description of the output configuration of the programmable logic module one or more logic elements and / or connecting elements are replaced or reconfigured and a logic description of a target configuration is created which has no, one or more additional logic elements, none, one or more elements of the initial configuration in the target configuration are not used, wherein transfer points are determined based on mapping information, ie Target and output configuration existing logic elements, in particular registers or drivers to which a modified logic function is created in the target configuration, wherein at least the logic elements of the programmable logic device that are not already used in the initial configuration are marked as free and the additional logic elements of the destination configuration are placed on the freely marked logic elements and connected to the transfer points via unused connecting elements, wherein a modified bit stream is created from the logic description of the destination configuration and wherein the changed bit stream is written to the programmable logic device. A method according to claim 1, characterized in that the logic elements of the initial configuration, which are not used in the target configuration and whose outputs are connected only to inputs of transfer points, are marked as free, wherein preferably the corresponding connection elements are marked as unused. A method according to claim 2, characterized in that recursively all logic elements whose outputs are exclusively connected to one or more inputs of in a previous step as freely marked logic elements are also marked as free, wherein preferably the corresponding connection elements are marked as unused. A method according to claim 2 or 3, characterized in that all logic elements in a given region around one or more replaced logic elements of the initial configuration or an input of a transfer point marked as free and the corresponding connecting elements are marked as unused, with all logic elements in the given region with Exception of the replaced logic element (s) then re-placed and connected to unused connectors. A method according to claim 4, characterized in that the connecting elements used in the initial configuration, which terminate at one of the logic elements in the predetermined region, are marked as unused at least until the next connected logic element outside the predetermined region. Method according to one of the preceding claims, characterized in that the step of reading in an output configuration comprises reading a bit stream and a conversion of the bit stream made at least for parts of the bit stream into a logic description, the conversion taking place in particular on the basis of architectural information of the programmable logic module used. Method according to one of the preceding claims, characterized in that the changed bit stream is created on the basis of the target configuration by establishing for the changed and thus reconfigured logic elements and / or connection elements a relationship between position in the bit stream and logic element or connection element on the programmable logic device and the original Bitstream is changed at the appropriate positions. Method according to one of claims 1 to 6, characterized in that the changed bit stream is created based on the target configuration by the translated netlist of the target configuration is translated into a new complete bit stream. Method according to one of the preceding claims, characterized in that for a logic function to be changed, which comprises at least one signal path, a signal delay is determined at least after the change, preferably for a signal path in the target configuration of the programmable logic module, in the course of at least one additional or reconfigured logic element or connector, a signal delay is estimated by counting the number of sequentially consecutive logic elements of the signal path in the target configuration and assigning each logic element a constant signal delay. Method according to one of the preceding claims, characterized in that for all logic functions to be changed and / or all signal paths covered by these, at least one signal transit time is determined and compared with one or more threshold values, and that one Warning and / or a modification of the placed netlist of the target configuration occurs when at least one detected signal propagation time exceeds the threshold or is outside a predetermined interval. Method according to one of the preceding claims, characterized in that the target configuration comprises at least a first multiplexer, which is arranged in particular directly before a transfer point, and that all added logic elements are arranged in new signal paths comprising a single input of the first multiplexer. A method according to claim 11, characterized in that the new signal paths comprise at least one interface pin of the programmable logic device, wherein the at least one interface pin is preferably associated with a debugging interface of the programmable logic device. Method according to one of the preceding claims, characterized in that the target configuration comprises at least one second multiplexer, which is arranged in particular directly behind a transfer point, wherein the second multiplexer is connected to at least one input of a logic element. Method according to one of the preceding claims, characterized in that the target configuration comprises at least one added register, wherein the output of the register is preferably connected to an interface pin, which is assigned in particular to a debugging interface of the programmable logic module.  Method for adapting a control device, which comprises a programmable logic device configured to execute a control function, in which the configuration of the programmable logic device is modified by a method according to one of the preceding claims.  A programming device for describing a programmable logic device, comprising a processor, a programming interface and / or a debugging interface, the device being adapted to carry out a method according to one of claims 1 to 15.  A computer program product having a computer-readable storage medium embedded with instructions that, when executed by a computing unit, cause the computing unit to be configured to perform a method according to any one of claims 1 to 15.

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