DE102015112303A1 - Control a scan mask from a fragment shader - Google Patents

Abstract

A method, system and computer program product for controlling a scanning mask from a fragment shading unit are disclosed. The method includes steps of generating a fragment for each pixel that is at least partially covered by a basic shape and determining coverage information for each fragment that corresponds to the basic shape. Thereafter, the method for the fragment includes the steps of generating a scanning mask by a fragment shading unit, replacing the covering information for the fragment with the scanning mask, and writing a result generated by the fragment shading unit into a memory based on the scanning mask. The method may be implemented in a parallel processing unit configured to at least partially implement a graphics processing pipeline.

Description

CLAIM OF PRIORITY

This application claims the benefit of US Provisional Application No. 62 / 030,497 (attorney docket NVIDP1073 +) entitled "Scanning Mask Control from a Fragment Shading Program", filed Jul. 29, 2014, the entire contents of which are hereby incorporated by reference is.

FIELD OF THE INVENTION

The present invention relates to graphics processing, and more particularly to control of a scan mask generated during rasterization of primitives.

BACKGROUND

Many applications, such as games and business office software, are designed to produce graphics for display on computer systems. The graphic may contain a two-dimensional or three-dimensional graphic. The graphics can be generated by software running in a conventional central processing unit (CPU). Alternatively, the graphics may be generated by hardware implemented in a specialized co-processing unit, such as a graphical processing unit (GPU), or by some combination of hardware and software executed by the CPU and / or the GPU. To simplify the programming of such applications, special Graphical Application Programming Interfaces (APIs), such as DirectX and OpenGL, among others, have been created to provide an abstraction between the graphics generation function and the hardware used to establish such functionality ,

An API may specify an abstract graphics generation pipeline that defines different levels in the generation of graphics. For example, a graphics generation pipeline specified by the OpenGL API may include a vertex shading level, a geometry shading level, a raster level, and a fragment shading level. The graphics generation pipeline receives basic graphic shapes specified by the application and processes these primitives in each of the stages of the graphics processing pipeline to produce pixel data for display on a display device. The raster level describes the process of transforming a basic shape, such as a triangle, into a series of fragments for processing by a fragment shading level. In other words, the basic shape indicated by a plurality of vertices is intersected with the pixel (or sub-samples of the pixels) indicated for a particular screen area, and attribute values associated with the basic shape are overlapped interpolated the basic shape for each of the pixels (or sub-samples of the pixels).

When image defect removal techniques are established, coverage information indicating which sub-samples of a pixel are covered by a primitive may also be generated during the rasterization. Typically, this coverage information is given as a mask. The mask may correspond to a particular fragment of the primitive, and each element in the mask may correspond to a particular sub-sample of the pixel. For example, if a particular pixel contains 16 sub-samples, then the mask may contain 16 bits indicating whether each of the sub-samples in that pixel is covered by the basic form. In certain algorithms, it may be desirable to change the coverage information associated with a given fragment. However, conventional hardware may not be configured to update the coverage information generated during the rasterization in any manner. Therefore, there is a need to remedy these problems and / or other problems associated with the prior art.

OVERVIEW

A method, system and computer program product for controlling a scanning mask from a fragment shading unit are disclosed. The method comprises the steps of generating a fragment for each pixel which is at least partially covered by a basic form and the determination of coverage information for the fragment corresponding to the basic form. Then, for each fragment, the method includes the steps of generating a sample mask by a fragment shader unit, replacing the masking information for the fragment with the sample mask, and writing a result generated by the fragment shading unit into a memory based on the sample mask. The method may be implemented in a parallel processing unit configured to at least partially set up a graphics processing pipeline.

BRIEF DESCRIPTION OF THE DRAWINGS

1 shows a flowchart of a method for controlling a sampling mask from a Fragment shading program according to an embodiment;

2 shows a parallel processing unit according to an embodiment;

3A shows a general processing cluster of the parallel processing unit 2 according to an embodiment;

3B shows a partition unit of the parallel processing unit 2 according to an embodiment;

4 shows a data stream multiprocessor 3A according to an embodiment;

5 shows a system-on-chip with the parallel processing unit 2 according to an embodiment;

6 Figure 4 is a conceptual view of a graphics processing pipeline constructed by the parallel processing unit 2 is arranged according to an embodiment;

7A shows a basic form according to an embodiment;

7B shows the coverage information for a fragment according to an embodiment;

8th shows an operation for processing a basic form according to an embodiment; and

9 FIG. 10 illustrates a vivid system in which the various architectures and / or functions of the various previous embodiments may be implemented.

DETAILED DESCRIPTION

A graphics API is commonly used Microsoft ^® DirectX, which includes Direct3D API for creating three-dimensional graphics and the Direct2D API to produce two-dimensional graphics. Direct3D may provide a graphics generation target for storing color data for display of computer generated graphics. An "image forming destination" in D3D denotes a buffer (that is, the allocated area of memory) in which image data for a scene is stored. Multiple Scanning Image Errors (MSAA) can be set up using an imaging target that stores multiple color scans per pixel. The multiple color scans for a pixel are then merged to produce the final pixel color for a pixel. However, the resolution of an MSAA (that is, the number of samples per pixel) may be limited due to the size of the memory available in the graphics hardware.

Microsoft ^® Direct3G version 11.1 (hereafter referred to as D3G11) contains a new feature that is called targeted independent grid spacing (TIR). D3D11 TIR allows multiple raster scans to be used during image generation, with only a single color scan being stored in the rendering target. A pixel shader unit may be configured to process the coverage information associated with the plurality of raster scans to produce the single color sample stored in the imaging destination. D3D11 TIR allows a vector graphic drawn using Direct2D to handle GPU acceleration instead of being completely generated by a CPU. However, a disadvantage of D3D11 TIR is that depth and template checking must be disabled when MSAA is used with a non-multicolor color buffer.

Although the pixel shading unit obtains the coverage information for a basic shape generated during the rasterization, the pixel shading unit is merely configured to process the coverage information to produce a single color value for output to the imaging destination. The single color value may be based, at least in part, on a number of set bits in the coverage information. Although the pixel shading unit receives the coverage information as input, the coverage information generated during the rasterization is not modified. Instead, the coverage information is merely used to set the color value of the single sample output from the pixel shading unit and stored in the imaging target.

Another commonly used graphics API is ^OpenGL® , which also includes functions for creating three-dimensional and two-dimensional graphics. OpenGL ^® also implemented MSAA by generating coverage information during the screening of a basic form. The coverage information is supplied to a fragment shading unit. In OpenGL ^{® is} the fragment shader can write a value into an output array, gl_SampleMask, whereby the fragment shading unit is able to modify the coverage information generated during the grid division. As described in the ^OpenGL® specification, the coverage for the fragment transitions to the logical AND of the coverage information with the value written to the gl_SampleMask is. Setting a bit in the gl_SampleMask to zero (0) causes the corresponding sample to be considered uncovered for MSAA purposes. However, setting a bit in the gl_SampleMask to one (1) will never cause a scan that is not covered by the original primitive to be considered covered for MSAA purposes. Thus, although the value can be used, which is written in the gl_SampleMask output array, which is specified by OpenGL ^® to modify a resist mask, the value written to the gl_SampleMask output array value can not be used during overwrite the coverage information generated by the rasterization.

Neither D3D11 TIR nor the function, which is made possible by the OpenGL ^® -gl_SampleMask output array allows a fragment shader, the overwriting of coverage information for multiple scans of a pixel generated during the pitch as to completely control. In particular, the fragment shading unit may not change a particular sample that is to be reported as covered rather than uncovered. Certain algorithms that require this feature therefore can not be set up using conventional graphics acceleration hardware.

1 shows a flowchart of a method 100 for controlling a scanning mask from a fragment shader program according to an embodiment. In step 110 For example, a fragment is generated for each pixel that is at least partially covered by a primitive shape during a rasterization step of a graphics processing pipeline. The raster level describes a process of converting a basic graphic shape specified in a vector format (ie, over several vertices or vertices) into a raster format (ie, multiple pixels or fragments). The rasterizer generates a single fragment for each pixel covered by the primitive.

A processor, such as a GPU, can set up at least part of the graphics processing pipeline. In one embodiment, the rasterization stage of the graphics processing pipeline is implemented by a fixed function hardware unit configured to receive a basic form and output one or more fragments for processing by one or more further stages of the graphics processing pipeline. In another embodiment, the rasterization level of the graphics processing pipeline is established by a programmable data stream multiprocessor included in a GPU.

A basic shape may be defined as a collection of vertices, each vertex having a coordinate in three-dimensional space and one or more vertex attributes, such as color, one or more texture coordinates, a normal vector, and the like. The rasterization stage of the graphics processing pipeline may receive data defining a primitive form from a previous stage of the graphics processing pipeline established in the GPU or by software executed by a CPU. A fragment may include one or more interpolated attributes as well as coverage information related to multiple scans associated with a particular pixel. The data defining the basic shapes and the fragments can be stored in data structures.

In step 120 Coverage information is determined for each fragment corresponding to the basic shape during the rasterization stage of the graphics processing pipeline. The coverage information may be a mask indicating whether a scanning position associated with the pixel is covered by the basic shape. A scan position is determined to be occluded when a beam passes from a camera position passing through the scan position through a closed surface defined by the edges of the primitive. In other words, a sampling position is determined to be covered when the sampling position lying on a viewing plane is within a projected version of the basic shape on the viewing plane.

In one embodiment, a fixed function hardware unit may comprise a series of logic units, each logic unit configured to calculate a sample position in two-dimensional coordinates relative to a position for a pixel. Each logic unit may then compare the scan position coordinate with the projected vertices of the primitive to determine if that scan position is covered or uncovered. The coverage information for each of the samples may be collected in a mask.

In step 130 For each fragment corresponding to the basic shape, a scanning mask is generated by a fragment shading unit during a fragment shading stage of the graphics processing pipeline. The scan mask may correspond to the number of scan positions associated with a pixel. For example, if the coverage information comprises a 16-bit mask corresponding to the 16 sample positions, then the sample mask may also comprise a 16-bit mask, with each bit in the sample mask corresponding to a different sample position for the pixel.

In one embodiment, the fragment shading level is established by a programmable data stream multiprocessor included in a GPU. The data stream generating multiprocessor may be configured to execute a fragment shading unit (ie, a program adapted to process fragments). Another instance of the fragment shading unit (ie, a fragment shading thread) may be executed for each fragment that is generated during the rasterization stage of the graphics processing pipeline.

The fragment shader unit may include instructions executed by the GPU that cause the sample mask to be generated and stored in a memory of the GPU (eg, a register, DRAM, etc.). Different algorithms dictate how the sample mask is generated. For example, if an algorithm requires the use of conservative rasterization, all bits of the sample mask may be set if any sample position associated with the fragment is covered, as determined during the rasterization stage of the graphics processing pipeline. In another example, in an algorithm associated with path imaging, coverage information associated with a particular sample position may be copied to additional sample positions of the sample mask. In one embodiment, the value of the sampling mask is determined, at least in part, by the coverage information generated during the rasterization stage of the graphics processing pipeline. In another embodiment, the value of the sampling mask may be determined completely independently of the coverage information. For example, the sample mask may represent any position in a multi-sample color buffer into which the output of the fragment shading unit should be written.

In step 140 For each fragment that corresponds to the basic shape, the coverage information for the fragment that is generated during a rasterization step of the graphics processing pipeline is replaced with the scan mask. In one embodiment, the coverage information may be overwritten by the scanning mask. In another embodiment, the coverage information may be modified to indicate that the fragment is completely occluded (that is, all bits of the coverage information are set to 1), and a bitwise AND operation is used to resolve the merge modified coverage information with the scan mask.

In step 150 For example, for each fragment corresponding to the basic shape, a result generated during the fragmentation shading stage of the graphics processing pipeline is written to a memory based on the sampling mask. In one embodiment, the memory comprises a frame buffer containing a color buffer. The color buffer may refer to memory allocated to store one or more color values per pixel. The image block buffer may further comprise a depth buffer and / or a template buffer for storing according to depth values and / or template values associated with each sample position for each pixel of a surface to be generated. A resolution of the color buffer may be the same or different from a resolution of the depth buffer and the template buffer.

Further illustrative information will now be given regarding various optional architectures and features with which the previous platform may or may not be set up according to the wishes of the user. It should be noted, however, that the following information is presented for illustrative purposes and should not be construed as limiting in any way. Any following feature may optionally be introduced with or without the exclusion of other features described.

2 shows a parallel processing unit (PPU) 200 according to one embodiment. In one embodiment, the PPU 200 a multi-stranded processor configured in one or more integrated circuit devices. The PPU 200 is a processing-hiding architecture designed to handle a large number of strands in parallel. A thread (ie, a thread for execution) is an instantiation of a set of instructions formed by the PPU 200 to be executed. In one embodiment, the PPU 200 a graphics processing unit (GPU) adapted to set up a graphic imaging pipeline for processing three-dimensional (3D) graphics data to produce two-dimensional (2D image data for display on a display device, such as a liquid crystal display (LCD) device.) In other embodiments can the PPU 200 to perform calculations for general purposes. While a single illustrative parallel processor is provided herein for illustrative purposes, it is to be understood that such processor is provided herein for illustrative purposes only, and that any processor may be employed to supplement and / or replace it.

As in 2 shown includes the PPU 200 an input / output (I / O) unit 205 , a host interface unit 210 , a front-end unit 215 , a scheduler 220 , a work distribution unit 225 , a network node 230 , a cross connection unit (Xbar) 270 , one or more general processing clusters (GPCs) 250 and one or more partition units 280 , The PPU 200 can work with a host processor or other peripheral devices via a system bus 202 be connected. The PPU 200 may also be connected to a local memory which includes a number of memory devices 204 includes. In one embodiment, the local memory may include a number of dynamic random access memory (DRAM) memory devices.

The I / O unit 205 is configured to receive communication events (ie, instructions, data, etc.) from a host processor (not shown) over the system bus 202 to send and receive. The I / O unit 205 can with the host processor directly over the system bus 202 or communicate via one or more intervening devices, such as a memory bridge. In one embodiment, the I / O unit is directed 205 a Peripheral Component Connection Express (PCIe) interface for communication over a PCIe bus. In alternative embodiments, the I / O unit 205 set up other types of well-known interfaces for communicating with external devices.

The I / O unit 205 is with a host interface unit 210 coupled, the packets are decoded via the system bus 202 be received. In one embodiment, the packets represent commands that are formed, the PPU 200 to cause to perform various operations. The host interface unit 210 sends the decoded commands to various other units of the PPU 200 as indicated by the commands. For example, some commands may be to the front panel unit 215 be transmitted. Other commands may be to the network node 230 or other units of the PPU 200 , about one or more copy units, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the host interface unit 210 is trained to communicate events between and among various logical units of the PPU 200 forward.

In one embodiment, a program executed by the host processor decodes an instruction stream in a buffer that commits jobs to the PPU 200 for processing. A workload may comprise a series of commands and data to be processed by these commands. The buffer is an area in memory shared by both the host processor and the PPU 200 can be accessed. For example, the host interface unit 210 be trained on the buffer in a system memory connected to the system bus 202 is connected to access memory requests over the system bus 202 from the I / O unit 205 be sent. In one embodiment, the host processor writes the instruction stream into the buffer and then sends a pointer to the beginning of the instruction stream to the PPU 200 , The host interface unit 210 provides the front panel unit 215 with pointers to one or more command streams. The front side unit 215 manages the one or more streams by reading instructions from the streams and commands to the various units of the PPU 200 to get redirected.

The front side unit 215 is with a scheduler 220 connected to the various GPCs 250 configured to process tasks defined by the one or more streams. The scheduler 220 is trained to state information regarding the various tasks performed by the scheduler 220 be managed to monitor. The state can indicate which GPC 250 a task is assigned, whether the task is active or not active, a priority level assigned to the task, etc. The scheduler 220 manages the execution of multiple tasks in the one or more GPCs 250 ,

The scheduler 220 is with a work distribution unit 225 which is trained to perform tasks in the GPCs 250 issue. The work distribution unit 225 can be a set of scheduled tasks coming from the scheduler 220 be received, track. In one embodiment, the work distribution unit manages 225 a collection of pending tasks and a collection of active tasks for each of the GPCs 250 , The collection of pending tasks may include a number of sections (eg, 16 sections) that contain tasks assigned to be by some GPC 250 to be processed. The collection of active tasks may include a series of sections (for example, 4 sections) for tasks currently being performed by the GPCs 250 actively processed. If a GPC 250 Completing the execution of a task then this task becomes the accumulation of active tasks for the GPC 250 One of the other tasks from the collection of pending tasks is selected and will be used for execution in the GPC 250 scheduled. If an active task in the GPC 250 is left unprocessed, for example, when it is waiting for a data dependency to be resolved, then the active task can be retrieved from the GPC 250 taken out and back into the collection pending tasks are selected while another task is selected in the collection of pending tasks and for execution in the GPC 250 is scheduled.

The work distribution unit 225 communicates with the one or more GPCs 250 about an Xbar 270 , The Xbar 270 is a connection network that many of the units of PPU 200 with other units of PPU 200 combines. For example, the Xbar 270 be formed, the work distribution unit 225 with a special GPC 250 to pair. Although not explicitly shown, one or more other units are the PPU 200 with the host unit 210 connected. The other units can also use the Xbar 270 via a network node 230 be connected.

The tasks are performed by the scheduler 220 managed and sent to a GPC 250 through the work distribution unit 225 output. The GPC 250 is trained to process the task and produce results. The results may differ from other tasks within the GPC 250 be used to another GPC 250 about the Xbar 270 forwarded or in the memory 204 get saved. The results can be stored in memory 204 about the partition units 280 which is a memory interface for reading and writing data to / from memory 204 set up. In one embodiment, the PPU includes 200 a number U of partition units 280 which is equal to the number of separate and distinguishable memory devices 204 that with the PPU 200 are connected. A partition unit 280 will be described in more detail below in connection with 3B described.

In one embodiment, a host processor executes a driver kernel that establishes an application programming interface (API) that enables one or more applications executing in the host processor to perform operations in the PPU 200 to dispose of. An application may generate commands (ie, API calls) that cause the driver kernel to perform one or more tasks for execution by the PPU 200 to create. The driver kernel issues tasks to one or more streams from the PPU 200 to be processed. Each task may include one or more groups of associated strands, referred to herein as a strand group. A strand block may refer to multiple sets of threads containing instructions to perform the task. Strings in the same set of strands can exchange data about a shared memory. In one embodiment, a group of strands comprises 32 associated strands.

3A shows a GPC 250 the PPU 200 out 2 according to one embodiment. As in 3A is shown, each contains GPC 250 a number of hardware units for processing tasks. In one embodiment, each contains GPC 250 a pipeline manager 310 , a pre-raster operation unit (PROP) 315 , a grid unit 325 , a work distribution intersection connection unit (WDX) 380 , a storage management unit (MMU) 390 and one or more texture processing clusters (TPCs) 320 , It should be noted that the GPC 250 out 3A other hardware units instead of or in addition to those in 3A may have shown units.

In one embodiment, the operation of the GPC 250 through the pipeline manager 310 controlled. The pipeline manager 310 manages the configuration of the one or more TPCs 320 for processing tasks assigned to the GPC 250 are assigned. In one embodiment, the pipeline manager 310 at least one of the one or more TPCs 320 configure to set up at least part of a graphical imaging pipeline. For example, a TPC 320 configured to use a vertex shader in the Programmable Stream Multiprocessor (SM). 340 perform. The pipeline manager 310 can also be configured to receive packets from the work distribution unit 225 be obtained to appropriate logic units within the GPC 250 forward. For example, some packages may become hardware units with a set function in the PROP 315 and / or a grid unit 325 while other packets are forwarded to the TPCs 320 for processing by the basic form unit 335 or the SM 340 can be forwarded.

The PROP unit 315 is designed to receive data from the grid unit 325 and the TPCs 320 to a raster operation (ROP) unit in the partition unit 280 to forward, which is described in more detail below. The PROP unit 315 Further, it may be configured to perform optimizations for color mixing, to manage pixel data, to perform address translations, and the like.

The grid unit 325 contains a set of fixed function hardware units designed to perform various raster operations. In one embodiment, the grid unit comprises 325 a set-up unit, a coarse grid unit, a reject unit, a cutter unit, a fine grid unit, and a tile connection unit. The setup unit receives transformed vertices and creates plane equations associated with the geometric primitive defined by the vertices. The Level equations are transferred to the coarse rasterizer to generate coverage information (eg, a x, y coverage mask for a tile) for the primitive. The output of the coarse rasterizer unit may be transmitted to the rejection unit, in which fragments which are assigned to the basic form and do not pass a z-test, are discarded, and may be transmitted to a slicing unit, in which fragments which are outside a viewing area to be cut off. These fragments, which are still present after disposal and deposition, may be passed to a fine rasterizer that generates attributes for the pixel fragments based on the level equations created by the setup device. The output of the grid unit 380 includes fragments derived, for example, from a fragment shading unit present in a TPC 320 is set up to be processed.

Every TPC 320 who is in the GPC 250 includes an M-channel controller (MPC) 330 , a basic form unit 335 , a SM 340 and one or more texture units 345 , The MPC 330 controls the functioning of the TPC 320 , where are packets from the pipeline manager 310 to the appropriate units in the TPC 320 to get redirected. For example, packets associated with a vertex may become the primitive unit 335 which is configured to extract vertex attributes belonging to the vertex from the memory 204 pick. In contrast, packets belonging to a shader program may be part of the SM 340 be sent.

In one embodiment, the texture units are 345 formed, texture maps (for example, a 2D array of Texel) from the memory 204 and to scan the texture maps to produce sampled texture values for use in shader programs generated by the SM 340 be executed. The texture units 345 implement texture operations, such as filter operations using mip maps (ie texture maps with different levels of detail). In one embodiment, each TPC comprises 320 four (4) texture units 345 ,

The SM 340 includes a programmable data stream processor configured to perform tasks represented by a series of threads. Every SM 340 is multi-stranded and designed to execute multiple strands (for example 32 strands) from a particular group of strands simultaneously. In one embodiment, the SM implements 340 an SIMD (Single Command, Multiple Data) architecture in which each thread in a group of threads (ie, a thread group) is configured to process another record based on the same set of commands. All strands in the set of strands execute the same commands. In another embodiment, the SM implements 340 a SIMT (Single Instruction, Multiple Strings) architecture in which each strand in a group of strands is configured to process a different set of data based on the same set of instructions, but individual strands in the set of strands have the possibility to diverge during execution. In other words, when an instruction for the set of strands is issued for execution, some strands in the set of strands may be active, thereby executing the instruction, while other strands in the set of strands may be inactive, thus making a no-operation (NOP) instead of executing the command. The SM 340 Can in conjunction with 4 will be described in more detail below.

The MMU 390 provides an interface between the GPC 250 and the partition unit 280 ready. The MMU 390 can enable translation of virtual addresses into physical addresses, memory protection and distribution of memory requests. In one embodiment, the MMU 390 one or more translation look-by buffer (TLBs) to improve the translation of virtual addresses into physical addresses in the memory 204 ready.

3B shows a partition unit 280 the PPU 200 out 2 according to one embodiment. As in 3B shown includes the partition unit 280 a raster operation (ROP) unit 350 , a level two cache (L2) 360 , a storage interface 370 and an L2 cross connection unit (Xbar) 365 , The storage interface 370 is with the store 204 connected. The storage interface 270 can set up 16, 32, 64, 128-bit data buses or the like for high-speed data transfer. In one embodiment, the PPU includes 200 U interfaces 370 ie a memory interface 370 per partition unit 280 where each partition unit 280 with a corresponding memory device 204 connected is. For example, the PPU 200 with up to U memory devices 204 For example, a synchronous dynamic random access memory for double-data rate version 5 (GDDR5 SDRAM) graphics may be connected. In one embodiment, the memory interface implements 370 a DRAM interface and U equals 6.

In one embodiment, the PPU implements 200 a more level memory hierarchy. The memory 204 is arranged as SDRAM off-chip and is connected to the PPU 200 connected. dates from the store 204 can be picked up and in the L2 cache 360 stored on the chip and from the various GPCs 250 shared. As shown, each partition unit comprises 280 a part of the L2 cache 360 , the corresponding storage device 204 assigned. Lower level caches can be found in various units within the GPCs 250 be set up. For example, each of the SMs 340 set up a level one cache (L1). The L1 cache is a private store dedicated to a special SM 340 assigned. Data from the L2 cache 360 can be fetched and stored in each of the L1 caches for processing in the functional units of the SMs 340 get saved. The L2 cache 360 is with the memory interface 370 and the Xbar 270 connected.

The ROP unit 350 includes a ROP manager 355 , a color ROP (CROP) unit 352 and a Z-ROP (ZROP) unit 354 , The CROP unit 352 performs raster operations related to pixel color, such as color compression, pixel blending and the like. The ZROP unit 354 implements a depth check in conjunction with the grid unit 325 , The ZROP unit 354 receives a depth for a sample position associated with a pixel fragment from the discard unit of the rasterizer 325 , The ZROP unit 354 checks the depth versus a corresponding depth in a depth buffer for a sample position associated with the fragment. If the fragment passes the depth test for the sample position, then the ZROP unit updates 354 the depth buffer and sends a result of the depth test to the grid unit 325 , The ROP administrator 355 Controls the operation of the ROP unit 350 , It should be noted that the number of partition units 280 may be different compared to the number of GPCs 250 , and therefore any ROP unit can 350 with each of the GPCs 250 be connected. Therefore, the ROP administrator is following 355 Packages coming from the different GPCs 250 and determines which GPC 250 a result from the ROP unit 350 was generated, is to be forwarded. The CROP unit 352 and the ZROP unit 354 are with the L2 cache 360 over an L2-Xbar 365 connected.

4 shows the data stream multiprocessor 340 out 3A according to one embodiment. As in 4 is shown, the SM includes 340 an instruction cache 405 , one or more scheduler units 410 , a register file 420 , one or more processing cores 450 , one or more special function units (SFUs) 452 , one or more load / store units (LSUs) 454 , a connection network 480 and a shared memory / L1 cache 470 ,

As described above, the work distribution unit indicates 225 Tasks to execute in the GPCs 250 the PPU 200 out. The tasks become a special TPC 320 within a GPC 250 and if the task is associated with a shader, the task can be assigned to an SM 340 be assigned to. The scheduler 410 receives the tasks from the work distribution unit 225 and manages command dispatching for one or more groups on strands (ie, thread groups) associated with the SM 340 are assigned. The scheduler 410 schedules strands to execute in groups of parallel strands, each group being called a strand group. In one embodiment, each strand group contains 32 Strands. The scheduler 410 can manage several different thread groups that dispose thread groups for execution and then commands from the several different thread groups to the various functional units (ie cores 350 , SFUs 352 and LSUs 354 ) during each clock cycle.

In one embodiment, each scheduler unit comprises 410 one or more command output units 415 , Each output unit 415 is configured to send commands to one or more of the functional units. In the in 4 the embodiment shown comprises the scheduler 410 two output units 415 that allow two different commands from the same thread group to be issued during each clock cycle. In alternative embodiments, each scheduler may 410 a single output unit 415 or additional output units 415 exhibit.

Every SM 340 contains a register file 420 containing a group of registers for the functional units of the SM 340 provides. In one embodiment, the register file is 420 divided into each of the functional units such that each functional unit is a special part of the register file 420 assigned. In another embodiment, the register file is 420 between the different strand groups used by the SM 340 be executed, split. The register file 420 provides temporary storage for operands associated with the data paths of the functional units.

Every SM 340 includes L processing cores 450 , In an embodiment, the SM comprises 340 a large number (e.g., 192, etc.) of separate processing cores 450 , Every core 450 may comprise a fully pipelined single precision processing unit having a floating point arithmetic logic unit and an integer arithmetic logic unit. The core 450 Furthermore, a double-precision processing unit may be provided with a floating point Arithmetic logic unit. In one embodiment, the floating point arithmetic logic unit implements the IEEE 754-2008 standard for floating point arithmetic. Every SM 340 also includes M SFUs 452 performing special functions (for example, pixel merging operations, and the like) and N LSUs 454 , the load and store operations between the shared memory / L1 cache 470 and the register file 420 to implement. In an embodiment, the SM comprises 340 192 cores 450 , 32 SFUs 452 and 32 LSUs 454 ,

Every SM 340 contains a connection network 480 containing each of the functional units with the register file 420 and the shared memory / L1 cache 470 combines. In one embodiment, the interconnect network is 480 a cross connect unit that may be configured to include any of the functional units with any register in the register file 420 or the locations in the shared memory / L1 cache 470 connect to.

The shared memory / L1 cache 470 FIG. 10 is an on-chip memory array that, in one embodiment, may be a shared memory or L1 cache, or a combination of both, according to application requirements. For example, the shared memory / L1 cache 470 64 kB of storage capacity. The shared memory / L1 cache 470 may be configured as a 64 KB of shared memory or an L1 cache, or a combination of both, such as a 16 KB of L1 cache and 48 KB of shared memory.

The previously described PPU 200 can be configured to perform calculations in a very parallel manner much faster than conventional CPUs. The parallel calculation has advantages in graphics processing, data compression, biometric methods, data stream processing algorithms, and the like.

In one embodiment, the PPU includes 200 a graphical processing unit (GPU). The PPU 200 is configured to receive commands indicating shading programs for processing graphics data. Graphics data may be defined as a group of primitives, such as dots, lines, triangles, squares, triangular stripes, and the like. Typically, a primitive contains data indicating a number of vertices for the primitive shape (eg, in a model space coordinate system) as well as attributes associated with each vertex of the primitive shape. The PPU 200 may be configured to process the basic graphic shapes to produce an image block buffer (ie, pixel data for each of the pixels of the display).

An application writes model data for a scene (ie, a collection of vertices and attributes) to memory, such as system memory or memory 204 , The model data defines every object that can be visible on a display. The application then makes an API call to the driver kernel requesting that the model data be generated and displayed as an image. The driver kernel then reads the model data and writes instructions to the one or more streams to perform operations so that the model data is processed. The commands may correspond to different shader programs used in the SMs 340 the PPU 200 to be set up, which include a vertex shading unit and / or a wrap shading unit and / or a domain shading unit and / or a geometry shading unit and / or a pixel shading unit. For example, one or more of the SMs 340 be configured to execute a vertex shading program that processes a number of vertices defined by the model data. In one embodiment, the different SMs 340 be configured to run simultaneously different shading programs. For example, a first subset of the SMs 340 be configured to execute a vertex shader while a second subset of the SMs 340 may be configured to execute a pixel shader program. The first subgroup of SMs 340 Processes vertex data to produce processed vertex data and writes the processed vertex data into the L2 cache 360 and / or the memory 204 , After the processed vertex data is divided into rasters (ie transformed from the three-dimensional data into two-dimensional data in screen space) to generate fragment data, the second subset of the SMs 340 a pixel shader unit to generate processed fragment data which is then merged with other processed fragment data and stored in the image block buffer in memory 204 to be written. The vertex shader and the pixel shader may be executed concurrently, thereby processing different data from the same scene in the manner of a pipeline until all model data for the scene is stored in the frame buffer as an image. Subsequently, the content of the image block buffer is transmitted to a display controller for display on a display device.

The PPU 200 may be included in a desktop computer, a portable computer, a tablet computer, a smart phone (eg, a wireless handset), a personal digital assistant (PDA), a digital camera, an electronic handset, and the like. In one embodiment, the PPU 200 formed on a single semiconductor substrate. In another embodiment, the PPU 200 in a system-on-a-chip (SoC) along with one or more other logic units, such as a CPU of a reduced instruction set computer (RISC), a memory management unit (MMU), a digital-to-analog converter (DAC), and like.

In one embodiment, the PPU 200 to be included in a video card containing one or more memory devices 204 , such as GDDR5 SDRAM. The graphics card may be configured to interface with a PCIe slot on a skin board of a desktop computer having, for example, a northbridge chipset and a southbridge chipset. In yet another embodiment, the PPU 200 an integrated graphics processing unit (iGPU) included in the chipset (ie, north bridge) of the motherboard.

5 shows a system-on-chip (SoC) 500 with the PPU 200 out 2 according to one embodiment. As in 5 shown includes the SoC 500 a CPU 550 and a PPU 200 , Like previously described. The SoC 500 may also be a system bus 202 exhibit a communication between the various components of the SoC 500 allows. Memory requirements by the CPU 550 and the PPU 200 can be generated via a system MMU 590 be redirected by the several components of the SoC 500 is shared. The SoC 500 may further include a memory interface 595 have, with one or more storage devices 204 connected is. The storage interface 595 For example, you can set up a DRAM interface.

Although not explicitly shown, the SoC 500 other components in addition to those in 5 have shown components. For example, the SoC 500 several PPUs 200 (For example, four PPUs 200 ), a video encoder / decoder, and a broadband wireless transceiver and other components. In one embodiment, the SoC 500 with the memory 204 be contained in a housing-to-housing (PoP) configuration.

6 is a conceptual view of a graphics processing pipeline 600 that of the PPU 200 out 2 is arranged according to an embodiment. The graphics processing pipeline 600 Figure 3 is an abstract flowchart of the processing steps configured to generate 2D computer generated images from 3D geometric data. As is well known, pipeline architectures can more efficiently perform long processing time operations by dividing the operation into multiple stages with the output of each stage connected to the input of the next succeeding stage. Thus, the graphics processing pipeline receives 600 input data 601 that move from one stage to the next stage of the graphics processing pipeline 600 be transmitted to output data 602 to create. In one embodiment, the graphics processing pipeline 600 represent a graphics processing pipeline, which is defined by the OpenGL ^® API.

As in 6 shown includes the graphics processing pipeline 600 a pipeline architecture that includes a number of stages. The stages include, but are not limited to, a data merging stage 610 , a vertex shading level 620 , a basic form association stage 630 , a geometry shading level 640 , a viewport scaling, screening and cutting (VSCC) step 650 , a raster level 660 , a fragment shading level 670 and a raster operation level 680 , In one embodiment, the input data includes 601 Commands that configure the processing units to control the stages of the graphics processing pipeline 600 and the basic geometric shapes (e.g., points, lines, triangles, squares, triangular stripes or fans, etc.) to be processed by the stages are established. The output data 602 may comprise pixel data (ie, color data) which is copied to a frame buffer or other type of surface data structure in a memory.

The data union level 610 receives the input data 601 specifying vertex data for higher-order surfaces, primitives, or the like. The data union level 610 collects the vertex data in a temporary memory or queue, such as by receiving a command from the host processor containing a pointer to a buffer in memory and reading the vertex data from the buffer. The vertex data is then sent to the vertex shading stage 620 transferred for processing.

The vertex shading level 620 Processes vertex data by performing a group of operations (ie, a vertex shader or a vertex shader) once for each of the vertices. For example, vertices may be represented as a 4-coordinate vector (ie, <x, y, z, w>) associated with one or more vertex attributes ( color, texture coordinates, surface normals, etc.). The vertex shading level 620 can process properties such as position, color, texture coordinates, and the like. In other words, the vertex shading level 620 performs operations on the vertex coordinates or other vertex attributes associated with a vertex. Such operations usually involve lighting operations (ie, modifying color attributes for a vertex) and transform operations (ie, modifying the coordinate space for a vertex). For example, vertices may be specified using coordinates in an object coordinate space that are transformed by multiplying the coordinates by a matrix that converts the coordinates from the object coordinate space to a world space or a normalized device coordinate (NCD). Room transferred. The vertex shading level 620 generates transformed vertex data corresponding to the primitive union stage 630 be supplied.

The basic form association stage 630 collects vertices that come from the vertex shading level 620 and group the vertices in basic geometric shapes for processing by the geometry shading stage 640 , For example, the primitive merging stage 630 be formed all three consecutive vertices as a basic geometric shape (ie, a triangle) for transmission to the geometry shading stage 640 to copy. In some embodiments, special vertices may be reused for successive basic geometric shapes (eg, two consecutive triangles in a triangle strip may share two vertices). The Basic Shapes Unification Level 630 sends geometric primitives (ie a collection of associated vertices) to the geometry shading stage 640 ,

The geometry shading level 640 processes basic geometric shapes by performing a group of operations (ie, a geometry shader or program) on the basic geometric shapes. Tiling operations can generate one or more basic geometric shapes from any basic geometric shape. In other words, the geometry shading level 640 can divide each basic geometric shape into a finer grid of two or more geometric primitives to get from the rest of the graphics processing pipeline 600 to be processed. The geometry shading level 640 sends geometric primitives to the viewport SCC stage 650 ,

The viewport SCC stage 650 For the scaling of the field of view performs a separation and a truncation of the geometric basic forms. Each surface that is created is linked to an abstract camera position. The camera position represents a position of a viewer looking at the scene and defines a viewing cone that encloses the objects of the scene. The viewing cone may include a viewing plane, a back plane, and four cutting planes. Any geometric primitive lying entirely outside the viewing cone may be discarded (ie discarded) because the basic geometric shape does not contribute to the final generated scene. Any geometric primitive lying partially within the viewing cone and partially outside the viewing cone may be trimmed (ie transformed into a new basic geometric shape enclosed by the viewing cone.) In addition, geometric primitives may each be scaled based on the depth of the viewing cone All possibly visible basic geometric shapes then become the raster level 660 fed.

The grid level 660 converts the geometric 3D basic shapes into 2D fragments. The grid level 660 may be configured to use the vertices of the geometric primitives to set up a set of plane equations from which various attributes can be interpolated. The grid level 660 may further calculate a coverage mask for a plurality of pixels indicating whether one or more scan positions for the pixel intersect the geometric primitive. In one embodiment, a z-check may also be performed to determine if the geometric primitive is enclosed by other geometric primitives that have already been divided into a raster. The grid level 660 generates fragment data (ie, interpolated vertex attributes associated with a particular sample position for each covered pixel) corresponding to the fragment shading level 670 be transmitted.

The fragment shading level 670 Processes fragment data by executing a group of operations (ie, a fragment shader or a program) on each of the fragments. The fragment shading level 670 may generate pixel data (ie, color values) for the fragment, such as by performing lighting operations or scanning texture maps using interpolated texture coordinates for the fragment. The fragment shading level 670 generates pixel data corresponding to the raster operation level 680 be forwarded.

The raster operation level 680 may perform various operations on the pixel data, such as performing alpha checks, template checks, and may merge the pixel data with other pixel data corresponding to other pixels belonging to the pixel. If the raster operation level 680 has finished processing the pixel data (the output data 602 ), the pixel data may be written into an image forming target, such as a frame buffer, a color buffer, or the like.

It should be noted that one or more additional stages in the graphics processing pipeline 600 may be present in addition to or instead of the one or more stages described above. Various implementations of the abstract graphics processing pipeline may implement other stages. Further, in some embodiments, one or more of the previously described stages may be out of the graphics processing pipeline, such as the geometry shading stage 640 be omitted. Other types of graphics processing pipelines are also considered to be within the scope of the present disclosure. Furthermore, any stage of the graphics processing pipeline 600 by one or more special hardware units within a graphics processor, such as the PPU 200 , Other stages of the graphics processing pipeline 600 can by programmable hardware units, such as the SM 340 the PPU 200 be set up.

The graphics processing pipeline 600 can have an application that is powered by a host processor, such as a CPU 550 to be set up. In one embodiment, a device driver may implement an application programming interface (API) that defines various functions that may be used by an application to generate the graphical data for display. The device driver is a software program that contains several commands that govern the operation of the PPU 200 Taxes. The API provides an abstraction for a programmer that allows a programmer specialized graphics hardware, such as the PPU 200 so that it generates graphical data without the programmer having to use the special instruction set for the PPU 200 must apply. The application may include an API call to the device driver for the PPU 200 is passed on. The device driver interprets the API call and performs various operations to respond to the API call. In some cases, the device driver may perform operations by placing commands in the CPU 550 be executed. In other cases, the device driver may perform operations at least partially by performing operations in the PPU 200 be started, with an input / output interface between the CPU 550 and the PPU 200 is used. In one embodiment, the device driver is the graphics processing pipeline 600 using the hardware of the PPU 200 to set up.

There may be various programs in the PPU 200 be executed at the various stages of the graphics processing pipeline 600 to set up. For example, the device driver may have a kernel in the PPU 200 start at the vertex shading level 620 in a SM 340 (or multiple SMs 340 ). The device driver (or the initial kernel used by the PPU 200 is executed) can also other system cores in the PPU 200 start to other stages of the graphics processing pipeline 600 perform, such as the geometry shading level 640 and the fragment shading step 670 , Furthermore, some of the stages of the graphics processing pipeline 600 in a fixed hardware unit, such as a rasterizer unit or a data linker unit, in the PPU 200 is set up to be implemented. Note that results from a kernel may be processed by one or more intervening fixed-function hardware units before passing through a subsequent kernel in an SM 340 are processed.

Control of a scanning mask

7A shows a basic form 720 according to one embodiment. As in 7A is shown is the basic form 720 several pixels 710 superimposed. Every pixel 710 can be assigned to multiple sampling positions (indicated by the crosshairs). In one embodiment, each pixel is 710 Assigned 16 sample positions. In alternative embodiments, other numbers of sample positions may be specified for each pixel (eg, 4 sample positions, 64 sample positions, etc.). Furthermore, the sampling positions may be even relative to the boundaries of the pixel 710 be spaced. Alternatively, the scanning positions may be shifted. As in 7A is shown, covers the basic shape 720 at least partially (ie, intersects) five of the sixteen pixels (pixels 710 (5) . 710 (6) . 710 (7) . 710 (10) and 710 (11) ).

In one embodiment, the grid unit comprises 325 Hardware with defined function to set up the screen level 660 the graphics processing pipeline 600 , During grid division, the grid unit receives 325 Vertex data that defines each basic form. The vertex data may include three vertices along with associated vertex attributes. For example, each vertex of the basic shape 720 are given by a four-component vector having an x-coordinate, a y-coordinate, a z-coordinate and indicates a w coordinate representing a position of the vertex in homogeneous coordinates. Each vertex may be further associated with a color value, texture coordinates (eg, an s-coordinate and a c-coordinate), a normal vector, and the like.

The grid unit 325 can data for all three vertices of the basic shape 720 and can use the vertex data to construct edge equations for the primitive. The grid unit 325 uses the edge equations to determine which pixels 710 to cut the basic shape. For every cutting pixel 710 For example, the rasterizer may generate a fragment from a fragment shader unit during the fragment shading stage 670 the graphics processing pipeline 600 is to be processed. The fragment may include an interpolated z-value (depth) for the fragment, interpolated values for each of the vertex attributes, and the coverage information indicating which sample locations that belong to the pixel 710 belong, of the basic form 720 be covered.

7B shows the coverage information 700 for a fragment according to an embodiment. Although the cover information 700 for illustrative purposes is shown as a two-dimensional array, that is a relative position of the sample positions for a pixel 710 is generally the coverage information 700 an N-bit value, each bit of a particular sample position of the pixel 710 equivalent. The cover information 700 can during a raster stage 660 the graphics processing pipeline 600 and may alternatively be referred to as raster coverage information.

As in 7B Shown would be a fragment that is the pixel 710 (5) out 7A corresponds to the coverage information 700 contain. The cover information 700 contains 16 bits. In the cover information 700 indicates a value "0" that a sample position of the basic shape 720 is not covered, and a value "1" indicates that a sample position is of the basic shape 720 is covered. Because the basic form 720 four sample positions in the pixel 710 (5) is the cover information 700 given as 0b0000000001110001. The fragment containing the cover information 700 can contain in a memory, such as a register file 420 to be saved, which become a SM 340 which is adapted to perform a fragment shading when the output of the raster level 660 is used immediately, or the output of the raster level 660 can in the store 204 be stored for later processing.

8th FIG. 12 shows a process for controlling a scan mask from a fragment shader program according to one embodiment. FIG. As in 8th is shown, generates a raster unit (for example, raster unit 325 ) One or more fragments for a basic form, such as the basic form 720 , A fragment shader that is owned by one or more SMs 340 is executed, is configured to process the fragments. The data for the fragment will be sent to a special SM 340 forwarded, which is designed to process this fragment. The data includes the coverage information 700 that during the grid step 660 the graphics processing pipeline 600 was generated. In one embodiment, the coverage information becomes 700 also the ROP 350 adapted to mix the output of the fragment shading unit with values stored in the image block buffer to produce a final value for each pixel.

During the raster operation stage 680 the graphics processing pipeline 600 can the ROP 350 the coverage information 700 that during the grid step 660 the graphics processing pipeline 600 was replaced by the scan mask during the fragment shading stage 670 the graphics processing pipeline 600 was generated. In one embodiment, the ROP is 350 set up, the cover information 700 for a fragment to re-initialize to indicate that the sample positions associated with the corresponding pixel are completely covered. In other words, to the ROP 350 transmitted coverage information 700 is overwritten with 0xFF (ie all "1"). A bitwise AND operation is then performed to update the modified coverage information 700 with the sampling mask generated by the fragment shading unit. In fact, the sampling mask generated by the fragment shading unit becomes the ROP 350 and replaces the coverage information 700 that during the grid step 660 was generated. Any sample position in the pixel may be controlled by the fragment shader unit to be considered covered or uncovered. Importantly, any sample position from the fragment shading unit is independent of the coverage information 700 can be controlled. Thus, the fragment shading unit can describe the sample mask during shading to thereby understand the function of the ROP 350 during the raster operation stage 680 the graphics processing pipeline 600 to control.

It should be noted that the PPU described herein 200 is merely an illustrative architecture for establishing control of a scanning mask by a fragment shading unit. For example, in other embodiments, the raster level 660 the graphics processing pipeline 600 in a programmable unit, such as the SM 340 instead of a special hardware unit, such as the grid unit 325 to be set up. Other types of architectures that generate coverage information during rasterization of a primitive and then replace the coverage information with a scan mask generated during shading are also considered to be within the scope of the present disclosure.

In one embodiment, the PPU 200 communicatively connected to a host processor, such as a CPU. The host processor may be connected to a memory including a graphics application, an operating system, a device driver for the PPU 200 , and the like stores. The device driver can set up a graphical API, such as the OpenGL API. To set up the override coverage information function from the fragment shading unit, the device driver may also implement an extension to the graphical API. The graphics application may include a command that uses the graphical API extension to the PPU 200 to configure so that the scanning mask is controlled by the fragment shading unit.

For example, an API extension to the OpenGL ^® specification, which is referred to as NV_sample_mask_override_coverage, and defined by the device driver for the PPU 200 be set up. The extension allows the fragment shading unit to control whether the gl_SampleMask output array can enable samples that are not covered by the basic form, or that have failed the early depth / template checks to indicate that the sample is from the sample Basic form was not covered. The function can be activated by redecluding the gl_SampleMask output array with an override_coverage layout qualification in a command in the graphics application, as follows:
Layout (override_coverage) out int gl_SampleMask [];

Once the gl_SampleMask output array variable has been re-declared, then the fragment shader unit can override the coverage information by writing a value to the gl_SampleMask variable for each fragment. If the fragment shader does not explicitly write a value to the gl_SampleMask variable, then the sample mask is undefined and the coverage information is passed through the ROP 350 not modified.

However, if the fragment shader describes a particular bit in the gl_SampleMask output array with 0, then the corresponding sample position is treated as uncovered, or if the fragment shader describes a particular bit in the gl_SampleMask output array of 1, then the corresponding one Scan position treated as covered. The ROP 350 then replaces the coverage information with the scan mask specified in the gl_SampleMask output array. If the graphics application does not declare the gl_SampleMask output array using the override_coverage layout qualification, then the ROP becomes 350 configured to perform a bitwise AND operation on the coverage information and the value stored in the gl_SampleMask output array when the value is written to the gl_SampleMask output array while the fragment is shaded, such as previously specified by the ^OpenGL® specification.

In other embodiments, the NV_sample_mask_override_coverage extension to the OpenGL ^® API for architectures that from the PPU 200 differ, be set up by other device drivers. In still other embodiments, a similar function extension may be defined for other graphical APIs, such as the Direct3D API.

Note that the ability to replace the coverage information 700 for any fragment shading algorithm or application, and is not limited to a TIR application. In particular, providing the possibility that the cover information 700 is replaced by a scan mask generated by the fragment shading unit, that an application "turns on" samples that were not originally covered by the basic form. Further, note that a thread of a fragment shading unit, which is an instance of the fragment shading unit that is executed for a particular fragment, only affects the scans in a corresponding pixel. The strand of the fragment shading unit can not turn on samples in other pixels, and no new fragments can be generated. Further, if a hybrid image defect recovery is applied with more than a single pass of the fragment shader, the fragment shader unit strand may only turn on samples corresponding to that run.

As used herein, a fragment shader program string designates a particular instance of the fragment shader program that executes a set of fragment data pertaining to a single pixel covered by a particular primitive form. For example, 16 cores 450 a SM 340 be configured to execute 16 fragment shader programs in parallel, each core 450 associated with one of the 16 pixels of a target imaging surface. When a primitive is divided into a raster, any kernel associated with a pixel that does not intersect the primitive is disabled. For example, 16 cores 450 a SM 340 configured to execute a fragment shading unit, the 16 pixels 710 match that in 7A are shown. While shading may be only five cores 450 activated (and 11 cores are disabled) when the five fragments are processed, which are the basic form 720 belong. Each of the five active cores can execute a single fragment shader thread, the fragments of each of the five pixels 710 corresponds to that of the basic form 720 get cut.

In one embodiment, the graphics processing pipeline 600 include a depth test (ie, Z-test) as a way to weed out basic shapes that are completely covered by other basic shapes to reduce the number of fragments that are completely shaded. Typically, the description of the depth buffer is usually done after shading and, therefore, the modified coverage information representing the scan mask generated by the fragment shading unit can be used to write depth values into the depth buffer. However, it is still possible to perform an earlier conservative depth test (ie, Zcull) before shading (ie, before the fragment shading unit has generated a scan mask used to modify the coverage information). When an early z check is enabled, it is necessary to treat each pixel as fully covered when computing the depth range (z-scale) for a primitive shape. In other words, since the fragment shading unit may "turn on" samples which are not covered by the basic form during the rasterization, care should be taken to use a conservative value for the z-scale during the early-z test ensure that a fragment is not discarded before shading if an uncovered sample could be plain in the base form, based on the values stored in the depth buffer when the fragment shading unit changes that sample from uncovered to covered , Therefore, it is necessary not to use a z-pro section (ie, z-values at the intersection of triangle edge / pixel edge) or the original z-scale of the basic shape when performing an early-z check.

Path generation is an application in which control of a scanning mask by the fragment shading unit can be used. Path generation refers to a type of 2D graphics generation. Path creation specifies a scene as a sequence of outlines, regardless of the screen resolution, and calls the outlines as paths that can be filled or left as strokes (that is, unfilled). The paths can be drawn as consistent colors, linear or radial gradients or images. Path generation generates images that can be scaled independently of the screen resolution. An example of the use of a fragment shader to control a scan mask during path generation is to blur the coverage of a scan on a group of scans in the pixel, causing the group of scans to be treated as if it were a single scan position are.

Multi-scan color buffers are another application in which control of a scan mask by the fragment shader unit can be used. Image defect elimination refers to a variety of techniques for reducing image aberrations caused by the sampling of high frequency data at limited resolution. One technique, MSAA, refers to an implementation in which a fragment shading unit is executed once per pixel (for example, for a single sample position in the center of the pixel), but with depth and template values for each sample position in the pixel be calculated. In MSAA, a single color value is merged with the value in a color buffer based on the coverage information for a fragment. In another technique, a full scene (FSAA) or oversampling correction is an implementation in which an image is generated at a higher resolution and then down-sampled to produce the final image. A color value can be calculated for each sample position and combined with values stored in a multi-sample color buffer. After the entire scene is shaded, the color buffer can be filtered to produce a final color value for each pixel.

When multi-sample color buffers are used in an image generation algorithm, each section in the multi-sample color buffer corresponds to a particular sample position (or subset of sample positions) for a particular pixel. For example, the multi-sample color buffer may contain four sections per pixel, each of the four sections corresponding to a different sample position in the pixel. A color value may be used for each of the sample positions is covered by the basic form, generated and stored in the color buffer with the multiple samples. Therefore, the coverage information becomes 700 is used to determine which portions in the color buffer should be overwritten or blended with the color value output by the fragment shader unit. In conventional techniques, data in the multi-sample color buffer can only be written to portions of the multi-sample color buffer which are covered by the basic form. In contrast, when the scanning mask generated by the fragment shading unit is used, the coverage information 700 that during the grid step 660 to replace, then the multi-sample color buffer may be treated as a more general data structure. In particular, the fragment shading unit may be used to attribute a scanning mask indicating which portion (or portions) of the color buffer correspond to the color value output by the fragment shading unit. The multiscanned color buffer may then be used as an array at portions into which any group of indices selected by the fragment shader unit may be written. The multi-sample color buffer may then be filtered to produce a single value of each pixel in the generated image, or the multi-sample color buffer may be processed by another fragment shader in a second pass in which the data in the color buffer matches its color buffer Samples are processed in a manner determined by the program.

In one embodiment, a single color value is generated by the fragment shader unit for each fragment. The single color value may then overwrite or be mixed with the value stored in each section of the multi-sample color buffer indicated by the coverage information. In other words, another color may be stored for each scan position based on multiple fragments associated with multiple primitives that cover the scan positions for a pixel, even if a single color is created over the entire pixel for a particular fragment , In another embodiment, different color values may be generated for each particular sample position. For example, texture coordinates for each sample position may be generated during the rasterization. Multiple fragment shader threads are then executed, each fragment shader thread being associated with a particular sample position. Each fragment shader program string then samples a color value from a texture map based on the texture coordinates for that sample position. Finally, the resulting color values are stored in the corresponding section in the multiscanned color buffer.

There are many applications in which the ability to describe any portion in the multi-sample color buffer is advantageous. For example, such an application lies in image defect correction schemes in which the number of sections in the multi-scan color buffer is less than a number of scan locations associated with visibility (eg, depth and template checking). In other words, the resolution of the multi-sample color buffer is smaller than a resolution of the sample positions. For example, a pixel having 16 sample positions may be linked for visibility, but a multi-sample color buffer contains only two or four sections for storing color values for each pixel. A multi-sample color buffer having a number of portions equal to the number of sample positions provided for the purpose of visibility may require too much memory. However, a multi-scan, better-managed color buffer can be set up to store multiple color values for each pixel while still maintaining visibility information at higher resolutions. The plurality of color values stored in the color buffer may then be merged based on the higher resolution visibility information.

By decoupling the output color value from the visibility-related sample position, it is possible to reduce the number of sections for representing arbitrary sample positions in, for example, the depth buffer. One possible implementation of a lossy algorithm would be to implement a multi-sample color buffer with two sections and generate a final color value based on a weighted average of the color values stored in the two sections. The weighting factors may be determined based on the visibility information (i.e., scanning mask) generated by the fragment shading unit.

Another use is to establish a transparency independent of the order using a multi-sample color buffer, where an algorithm stores an unsorted list of semitransparent colors and depths per pixel. The algorithm then sorts and merges the semitransparent colors in a downstream processing pass. The Fragment Shading Unit maintains a per-pixel index that counts the number of semi-transparent fragments associated with the pixel. The fragment shading unit may then store the fragment color and depth at the sample associated with the index by setting the appropriate bit in the sample mask (ie, the color sample and depth sample are not stored in the sample position based on the coverage, but in sequence the semitransparent fragments corresponding to this particular pixel). If the index number exceeds the number of samples, the mask can be set to zero, and the fragment shader unit can resort to a slower global list of fragments to store the remaining color / depth combinations associated with the pixel.

Yet another use is to establish a limited form of conservative rasterization. In a conservative rasterization, the coverage information may be generated such that, if any sample is covered by the basic form, then all samples will be treated as being covered by the basic form. However, when a conservative rasterization is established, depth and template checks are typically performed based on the pixel being "fully covered", which may result in certain inaccuracies in the algorithm. Instead, an algorithm may establish a conservative rasterization by performing an early and / or template test based on exact coverage information generated by the rasterizer and then adjusting the scan mask to indicate that the entire pixel is "masked" if any scan position for a fragment is "masked". Algorithms for voxel formation and collision detection may benefit from a "template-then-coverage" application of a conservative rasterization.

The applications described above provide examples of specific algorithms that may use control of a scanning mask provided by the fragment shading unit. However, a variety of applications and applications of the concept described herein are considered to be within the scope of the present disclosure.

9 shows a vivid system 900 in which the various architectures and / or functions of the various preceding embodiments can be established. As shown, is a system 900 provided with at least one central processor 901 that with a communication bus 902 connected is. The communication bus 902 may be established using any suitable protocol, such as PCI (Peripheral Component Connection), PCI Express, AGP (Accelerated Graphics Port), HyperTransport, or other bus or point-to-point communication protocol (s). The system 900 also has a main memory 904 on. A control logic (software) and data are in main memory 904 which may take the form of a random access memory (RAM).

The system 900 also includes input devices 912 , a graphics processor 906 and an ad 908 That is, a conventional CRT (Cathode Ray Tube), an LCD (Liquid Crystal Display), an LED (Light Emitting Diode) display, a plasma display, or the like. A user input may be from the input devices 912 For example, keyboard, mouse, touch-sensitive pad, microphone and the like can be received. In one embodiment, the graphics processor 906 have multiple shading modules, a raster module, etc. Each of the foregoing modules may be arranged in a single semiconductor platform to form a graphics processing unit (GPU).

In the present specification, a single semiconductor platform refers to a single semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with enhanced connectivity that simulate on-chip functionality, and substantial improvements over implementation using a conventional central processing unit (CPU) and a bus. Of course, the various modules can also be arranged separately or be provided in various combinations of semiconductor platforms according to the wishes of the user.

The system 900 can also have a secondary memory 910 exhibit. The secondary storage 910 For example, a hard disk drive and / or a removable storage drive that includes a floppy disk drive, a magnetic tape drive, a compact diskette drive, a digital versatile floppy disk (DVD) drive, a recording device, a universal serial bus (USB) flash memory. The removable storage drive reads from and / or stores in a well-known manner from a non-stationary storage unit.

Computer programs or computer control logic algorithms may reside in main memory 904 and / or the secondary memory 910 be saved. Such computer programs put the system in execution 900 in a position, to perform various functions. The memory 904 , the memory 910 and / or any other memory are possible examples of computer-readable media.

In one embodiment, the architecture and / or function of the various preceding figures may be related to the central processor 901 , the graphic processor 906 an integrated circuit (not shown) that incorporates at least a portion of the characteristics of both the central processor 901 as well as the graphic processor 906 has been designed to operate a chipset (ie a group of integrated circuits designed to operate and be sold as a unit for performing associated functions, etc.) and / or another integrated circuit.

Furthermore, the architecture and / or functions of the various preceding figures may be implemented within an application specific system and / or other desired system in the context of a general computer system, a printed circuit board system, a game console system designed for entertainment purposes. For example, the system can 900 take the form of a desktop computer, a portable computer, a server computer, a workstation, game consoles, an embedded system, and / or any other type of logic. In addition, that system 900 may take the form of various other devices including, but not limited to, a personal digital assistant (PDA) device, a mobile device device, a television, etc.

Although not shown, the system may 900 to a network (e.g., a telecommunications network, a local area network (LAN), a wireless network, a wide area network (WAN), such as the Internet, a device-to-device network, a cable network, or the like) for communication purposes.

Although various embodiments have been described above, it should be understood that these are given by way of example only and not by way of limitation. Therefore, the breadth and scope of a preferred embodiment should not be limited by any of the previously described illustrative embodiments, but should be defined only in accordance with the following claims and their equivalents.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited non-patent literature

• IEEE 754-2008 standard [0059]

Claims (20)

A method with: Generating a fragment for each pixel that is at least partially covered by a basic shape; Determining coverage information for each fragment that corresponds to the basic form; and for each fragment: Generating a scanning mask by a fragment shading unit, Replacing the coverage information for the fragment with the sampling mask, and Writing, based on the scanning mask, a result generated by the fragment shading unit into a memory. The method of claim 1, wherein a fragment comprises a data structure having one or more interpolated attributes, and coverage information relating to a plurality of samples belonging to a particular pixel. The method of claim 1, wherein the basic form comprises a data structure containing a collection of vertices, each vertex in the collection of vertices containing a coordinate in my three-dimensional space and one or more vertex attributes. The method of claim 1, wherein generating the fragment and determining the coverage information are performed during a rasterization step of a graphics processing pipeline. The method of claim 4, wherein the graphics processing pipeline is at least partially established by a parallel processing unit including a plurality of programmable data stream multiprocessors (SM), each SM configured to execute a plurality of fragment shading strands in parallel. The method of claim 5, wherein each fragment shading string corresponds to another fragment generated during the rasterization stage of the graphics processing pipeline. The method of claim 5, wherein generating the scan mask occurs during a fragment shading stage of the graphics processing pipeline and replacing the coverage information by the scan mask during a raster operation stage of the graphics processing pipeline. The method of claim 7, wherein the parallel processing unit includes a rasterizer configured to at least partially establish the rasterization level of the graphics processing pipeline, and a rasterizer configured to at least partially establish the rasterizer stage of the graphics processing pipeline. The method of claim 1, wherein the results are written to a multi-sample color buffer. The method of claim 1, wherein the coverage information comprises an N-bit mask, each bit in the N-bit mask corresponding to a different sample location associated with a pixel associated with the fragment. The method of claim 10, wherein the sampling mask comprises N bits, each bit of the sampling mask corresponding to a different sampling position. The method of claim 1, wherein the fragment shading unit receives the coverage information. A non-transitory computer-readable storage medium that stores instructions that, when executed by a processor, cause the processor to perform steps with: Generating a fragment for each pixel that is at least partially covered by a basic shape; Determining coverage information for each fragment that corresponds to the basic form; and for each fragment: Generating a scanning mask by a fragment shading unit, Replacing the coverage information for the fragment with the sampling mask, and Writing, based on the scanning mask, a result generated by the fragment shading unit into a memory. The non-transitory computer-readable storage medium of claim 13, wherein a fragment comprises a data structure having one or more interpolated attributes and coverage information relating to a plurality of samples associated with a particular pixel, and wherein the basic form comprises a data structure containing a collection of vertices where each vertex in the collection of vertices contains a coordinate in a three-dimensional space as well as one or more vertex attributes. The non-transitory computer readable storage medium of claim 13, wherein the processor comprises a parallel processing unit including a plurality of programmable data stream multiprocessors (SM), each SM configured to execute a plurality of fragment shading strands in parallel, and generating the fragment and determining coverage information during a raster stage of a graphics processing pipeline be executed, which is at least partially established by the parallel processing unit. The non-transitory computer-readable storage medium of claim 13, wherein the coverage information comprises an N-bit mask, each bit in the N-bit mask corresponding to a different sample location associated with a pixel corresponding to the fragment, and wherein the sample mask is N bits wherein each bit of the sampling mask corresponds to the different sampling positions. A system with: a parallel processing unit configured to at least partially establish a graphics processing pipeline, the parallel processing unit configured to generate basic shapes by: Generating a fragment for each pixel that is at least partially covered by a basic shape, Determining a coverage information for each fragment corresponding to the basic form, and for each fragment: Generation of a scanning mask by a fragment shading unit, Replacing the coverage information for the fragment with the sampling mask, and Writing a result generated by the fragment shading unit into a memory based on the sampling mask. The system of claim 17, wherein generating the fragment and determining coverage information is performed during a rasterization step of the graphics processing pipeline, wherein the generation of the scan mask occurs during a fragment shading stage of the graphics processing pipeline, and wherein the replacement of the coverage information by the sampling mask during a raster operation stage the graphics processing pipeline. The system of claim 17, further comprising: a memory for storing a graphical application and a device driver; and a host processor coupled to the memory and the parallel processing unit, the host processor configured to execute the graphical application and the device driver, wherein the device driver implements, at a graphical API, an extension used by the graphical application to cause the parallel processing unit to replace the coverage information for the fragment with the scan mask. The system of claim 17, wherein the parallel processing unit comprises a plurality of programmable data stream multiprocessors (SM), each SM configured to execute a plurality of fragment shading strands in parallel.

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