DE102015109796A1 - LED chip - Google Patents

Abstract

A light-emitting diode chip is specified, comprising - an active zone (2) which has been epitaxially grown on a first semiconductor layer (11), comprising - at least one quantum well layer (20), wherein - the active zone (2) is compressively clamped.

Description

An object to be solved is to specify a light-emitting diode chip with shortened switching times.

A light-emitting diode chip is specified. The LED chip is intended to emit electromagnetic radiation during operation. In particular, the wavelength of the electromagnetic radiation may be in the red and / or infrared range of the electromagnetic spectrum. The peak wavelength of the electromagnetic radiation may be at least 600 nm and at most 1000 nm. A "peak wavelength" here and hereinafter is the wavelength at which a spectrum of the electromagnetic radiation emitted during operation has a maximum, in particular a global maximum.

According to at least one embodiment of the light-emitting diode chip, this comprises a first semiconductor layer. On the first semiconductor layer, an active zone is epitaxially grown. For example, epitaxial growth is by molecular beam epitaxy (MBE) or metal organic vapor phase epitaxy (MOVPE). The active zone can emit the electromagnetic radiation during operation.

The LED chip has a main plane of extension in which it extends in lateral directions. Perpendicular to the lateral direction, in a stacking direction, the LED chip has a thickness. The thickness of the LED chip is small compared to the maximum extent of the LED chip along the lateral directions.

Here and below, a "thickness" of a layer always denotes its maximum extent in the stacking direction.

The active zone comprises at least one quantum well layer. The active zone may further comprise at least two quantum well layers and at least one barrier layer arranged between the at least two quantum well layers. In particular, the active zone may comprise a plurality of barrier layers and a plurality of quantum well layers, which follow one another in the stacking direction, for example. In this case, a barrier layer may each be surrounded by two quantum well layers and / or a quantum well layer may each be surrounded by two barrier layers.

A quantum well layer can be characterized in particular by the fact that charge carriers, in particular electrons, can undergo quantization of their energy eigenstates by confinement. The inclusion can be done for example by means of a barrier layer. In particular, a plurality of barrier layers may be present, wherein two of the barrier layers may adjoin one of the quantum well layers on both sides. In addition, a first and / or a second intermediate layer may be present, each of which may adjoin the quantum well layer. The charge carriers can also be enclosed by means of the first and / or second intermediate layer. Within the quantum well layer, the freedom of movement of the charge carriers may be limited in at least one spatial dimension.

The first semiconductor layer and the at least one quantum well layer may each be formed with or consist of a (compound) semiconductor material. In particular, the respective material of the first semiconductor layer and the quantum well layer has a crystal structure.

Furthermore, the optionally present barrier layer can be formed with or consist of a (connecting) semiconductor material. In particular, the material of the barrier layer may have a crystal structure. The material of the quantum well layer may have a smaller energy bandgap than the material of the barrier layer. It is also possible that the material of the first semiconductor layer has a smaller energy band gap than the material of the quantum well layer and / or optionally the barrier layer. Furthermore, the first and the second intermediate layer can be formed from or consist of a (connecting) semiconductor material.

The light-emitting diode chip can furthermore have a second semiconductor layer, which follows the active zone in the stacking direction and is arranged on a side of the active zone which faces away from the first semiconductor layer. The second semiconductor layer may also comprise or consist of a (compound) semiconductor material. By way of example, the first semiconductor layer is a p-type semiconductor layer and the second semiconductor layer is an n-type semiconductor layer.

The first intermediate layer can be arranged between the first semiconductor layer and the active zone. Furthermore, the second intermediate layer can be arranged between the second semiconductor layer and the active zone. In particular, the first intermediate layer and / or the second intermediate layer may each directly adjoin a quantum well layer. The active zone may be grown directly on the first intermediate layer. For example, it is possible for a quantum well layer to be surrounded either by two barrier layers or by a barrier layer and the first or second intermediate layer.

In accordance with at least one embodiment of the light-emitting diode chip, the active zone is compressively clamped. In particular, the at least one quantum well layer can be compressed in a compressive manner.

A layer, such as, for example, the quantum well layer, is considered to be strained in particular if, in particular epitaxial deposition of the material of said layer on a reference layer, a parallel lattice constant of the layer running along at least one of the lateral directions of the natural lattice constant of the layer is different. In the case of the quantum well layer, the reference layer may in particular be the substrate. Alternatively or additionally, it is possible that the reference layer is the barrier layer or the first intermediate layer. In particular, the parallel lattice constant of the layer may correspond to the lattice constant of the reference layer. With a compressive strain of the layer, the parallel lattice constant of the layer can be reduced compared to the natural lattice constant of the material of the layer. Furthermore, it is possible that with a compressive strain, a vertical lattice constant of the layer running along the stacking direction is increased in comparison to the natural lattice constant of the material layer.

The stress of a layer can be described with the stress coefficient. The strain coefficient of the layer is obtained from the quotient of the difference between the natural lattice constant of the reference layer a ₂ and the natural lattice constant of the layer a ₁ and the natural lattice constant of the grown layer described by the formula (a ₁ -a ₂ ) / a ₁ . In a compressive bracing results in a positive stress coefficient, with a tensile stress a negative stress coefficient.

The compressive strain of the quantum well layer can be demonstrated by the fact that the crystal structure of the material of the quantum well layer at least in places does not have the natural lattice constant of the material of the quantum well layer. In particular, the lattice constant of the material of the quantum well layer may at least in places have assumed the lattice constant of the material of the barrier layer or of the first intermediate layer. It is possible that the optionally present barrier layer and / or the optionally present first intermediate layer are also braced.

Furthermore, a strain of a layer sequence, such as the active zone, can be described by an average strain of the layer sequence. The average strain of a layer sequence having a plurality of layers is given by the weighted arithmetic mean of the stress coefficients of the layers. The weighting takes place with respect to the respective thickness of the layers. The mean stress of the active zone is thus the weighted arithmetic mean of the stress coefficients of the at least one quantum well layer contained in the active zone and the optionally present barrier layer.

The strain of the active zone can be determined, for example, by bending the layers, in particular the quantum well layer and the optionally present barrier layer, of the active zone. In a compressive strain, the active zone is curved in particular convex. In the case of a tensile stress, a concave curvature of the active zone may be present. Here, the terms "convex" and "concave" refer to a substrate on which the first semiconductor layer is grown and which is arranged in the stacking direction in front of the first semiconductor layer.

According to at least one embodiment of the light-emitting diode chip, the latter comprises an active zone which has been epitaxially grown on a first semiconductor layer and has at least one quantum well layer, wherein the active zone is clamped in a compressive manner.

In accordance with at least one embodiment of the light-emitting diode chip, the active zone comprises at least two quantum well layers and at least one barrier layer arranged between the at least two quantum well layers. The active zone may in particular comprise a quantum well structure.

The idea behind the light-emitting diode chip is to shorten the switching times by changing the crystal structure within the epitaxially grown layers. It has surprisingly been found that a compressive strain has the desired reduction of the switching times result. The switching times of the optoelectronic semiconductor component may in particular be the rise time and the fall time of a switching pulse of the optoelectronic semiconductor component.

It is possible that the compressive strain of the quantum well layer leads to a bending of the energy band structures in the area of the quantum well layer. This can facilitate induction of electrons into the quantum well layer and thus allow faster switching times. However, due to the bowing of the band structure, it is possible that the induction of holes having a higher effective mass than the electrons into the quantum well layer is degraded. This For example, it can lead to a reduced luminous efficacy compared to a light-emitting diode chip in which the active zone is not or only slightly compressed clamped.

In accordance with at least one embodiment of the light-emitting diode chip, the first semiconductor layer is epitaxially grown on a substrate. The substrate may comprise, for example, germanium, gallium arsenide and / or silicon, or consist of one of these materials. The mean strain of the active zone relative to the substrate is at least 600 ppm (ppm: parts per million, in English "parts per million"), preferably at least 1000 ppm, and more preferably at least 2000 ppm.

In accordance with at least one embodiment of the light-emitting diode chip, the at least one quantum well layer is clamped in a pseudomorphic compressive manner. A layer is pseudomorphically strained if the strain of the layer is not degraded or only to a small extent in the form of dislocations and / or cracks in the layer. In particular, the at least one quantum well layer has a thickness that is less than a critical layer thickness of the quantum well layer. The "critical layer thickness" of a layer here and in the following is a material-specific upper limit for pseudomorphic growth of the layer. In particular, the critical layer thickness of the quantum well layer is dependent on the difference between the natural lattice constant of the material of the quantum well layer and optionally the lattice constant of the material of the barrier layer and / or the first intermediate layer.

In accordance with at least one embodiment of the light-emitting diode chips, the stress coefficient of the quantum well layers is at least 7500 ppm, preferably at least 15000 ppm, greater than the stress-strain coefficient of the barrier layer. For example, the amount of the strain coefficient of the quantum well layers with respect to the material of the substrate ( 10 ) averages at least 5,000 ppm and at most 25,000 ppm.

In accordance with at least one embodiment of the light-emitting diode chips, the quantum well layers are clamped pseudomorphically compressively and the stress coefficient of the quantum well layers is in each case at least 7500 ppm, preferably at least 15000 ppm, greater than the stress coefficient of the barrier layer.

In accordance with at least one embodiment of the light-emitting diode chip, it emits an electromagnetic radiation with a peak wavelength of at least 750 nm, preferably at least 850 nm, and at most 1000 nm, preferably at most 940 nm. In other words, the LED chip emits electromagnetic radiation in the infrared Area of the electromagnetic spectrum. In particular, the LED chip can emit broadband radiation. In other words, a half-width of the intensity distribution of the electromagnetic radiation as a function of the wavelength may be at least 20 nm, preferably at least 50 nm.

In accordance with at least one embodiment of the light-emitting diode chip, the at least one quantum well layer in each case has a thickness of at least 2 nm, preferably at least 3 nm, and at most 6 nm, preferably at most 5 nm. In particular, the thickness of the at least one quantum well layer is less than the critical layer thickness of the quantum well layer. Further, it is possible that the thickness of each barrier layer is at least 3 times the thickness of the quantum well layer.

In accordance with at least one embodiment of the light-emitting diode chip, the at least one quantum well layer is based on gallium arsenide (GaAs). In other words, the quantum well layer comprises gallium and arsenic. Here, at least 5% and at most 44% of the gallium atoms have been replaced by indium atoms and / or aluminum atoms. In other words, the quantum well layer may be formed of or consist of In _x Al _y Ga _1-xy As where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and x + y ≦ 1.

The gallium atoms and / or the arsenic atoms within the quantum well layer may thus have been replaced by heavier and thus in particular larger atoms, such as, for example, indium atoms. Such replacement of the lighter atoms results in an increase in the natural lattice constant of the material of the quantum well layers as compared to a material in which fewer atoms are replaced. This facilitates the provision of compressively strained quantum well layers.

In accordance with at least one embodiment of the light-emitting diode chip, the at least one quantum well layer is formed with In _x Ga _1-x As. In this case, 0.08 ≦ x ≦ 1, preferably 0.16 ≦ x ≦ 1. The quantum well layer thus has a high indium doping. The lattice constant, in particular the natural lattice constant, of In _x Ga _1-x As grows in particular with increasing indium content x.

The at least one quantum well layer may in particular have a thickness which is at most 90%, preferably at most 80% and particularly preferably at most 70%, of a thickness of a quantum well layer of an alternative light-emitting diode chip which generates electromagnetic radiation with a peak Wavelength of at least 1000 nm emitted is.

An increase in the indium concentration in the quantum well layer can lead to a reduction of the energy band gap in the quantum well layer. This would result in an increase in the emission wavelength of the LED chip. Such an increase in the emission wavelength can be avoided by reducing the thickness of the quantum well layers. As a result, the electromagnetic radiation emitted during operation of the light-emitting diode chip can furthermore have a peak wavelength of less than 1000 nm.

In accordance with at least one embodiment of the light-emitting diode chip, the barrier layer is clamped pseudomorphically tensilely. The strain coefficient of the barrier layer with respect to the substrate is at least at least -10000 ppm and at most -500 ppm. Preferably, the strain coefficient of the barrier layer with respect to the substrate is at most -2000 ppm, more preferably at most -3000 ppm.

By means of a pseudomorphic tensile stressing of the barrier layer, it is possible in particular to provide highly compressively strained quantum well layers, wherein high compressive strain is partially compensated by the tensile strain. This makes it possible to reduce the mean stress of the active zone in comparison to the strain of the quantum well layers and thus to avoid bending of the active zone, for example. Furthermore, the compensation of the stress enables pseudomorphic growth of a plurality of quantum well layers and prevents the formation of dislocations in the active zone.

In accordance with at least one embodiment of the light-emitting diode chip, the barrier layer is formed with Al _y Ga _1-y As _b P _1-b , where 0.09 ≦ b ≦ 1, preferably 0.18 ≦ b ≦ 1, and 0 ≦ y ≦ 1 Increasing the phosphorus concentration b in the barrier layer leads to a reduction of the lattice constant, in particular of the natural lattice constant, of the material of the barrier layer and thus to a tensile strain of the barrier layer.

According to at least one embodiment of the light-emitting diode chip, an intensity signal during a switching pulse has a rise time of at most 10 ns, preferably at most 6 ns, and / or a fall time of at most 12 ns, preferably at most 7 ns. A switching pulse may be a predefinable time duration between a turn-on operation and a turn-off operation of the optoelectronic semiconductor device. In particular, the intensity signal is the intensity of the electromagnetic radiation emitted during the switching pulse during operation of the light-emitting diode chip as a function of time. In particular, the rise time may be the amount of time required to turn on the light emitting diode chip to increase the intensity signal from 10% of a maximum intensity to 90% of the maximum intensity. Further, the fall time may be the amount of time required to turn off the light emitting diode chip to reduce the intensity signal from 90% of the maximum intensity to 10% of the maximum intensity. The rise time or the fall time may in particular be the width or steepness of the rising or falling edge of the intensity signal of a switching pulse. A switching pulse of the LED chip thus has short switching times.

Short switching times of light-emitting diode chips are particularly advantageous in applications in the field of time-of-flight measurements, for example for game consoles, cameras, mobile phones, distance measurements and / or autofocus measurements.

In accordance with at least one embodiment of the light-emitting diode chip, it is free of a resonator. The light-emitting diode chip is thus in particular not a laser diode chip. A resonator is in particular an arrangement of at least two mirrors, between which at least one mode of the electromagnetic field, in particular in the visible region of the electromagnetic spectrum, can be stored, in particular as a standing wave.

In the following, the light-emitting diode chip described here will be explained in more detail on the basis of exemplary embodiments and the associated figures.

The 1 shows an embodiment of a light-emitting diode chip described here.

The 2A and 2 B show exemplary embodiments of a crystal structure of a light-emitting diode chip described here.

The 3 shows an intensity signal of a switching pulse of an embodiment of a light-emitting diode chip described here.

The 4 shows rise times or fall times.

The same, similar or equivalent elements are provided in the figures with the same reference numerals. The figures and the proportions of the elements shown in the figures with each other are not to be considered to scale. Rather, individual elements can be used for better representability and / or be shown exaggerated for better understanding.

Based on the schematic sectional view of 1 an embodiment of a light-emitting diode chip described here is explained in more detail. The light-emitting diode chip comprises a first semiconductor layer 11 , a first intermediate layer 13 , an active zone 2 , a second intermediate layer 14 and a second semiconductor layer 12 , which are arranged in the order just given in a stacking direction z on top of each other. The active zone 2 adjoins directly to the first intermediate layer 13 and to the second intermediate layer 14 at.

The active zone 2 includes a plurality of quantum well layers 20 and a variety of barrier layers 21 , each between two quantum well layers 20 are arranged. Each quantum well layer 20 has a thickness in a stacking direction 20d on.

At one of the active zone 2 remote side of the first semiconductor layer 11 is a substrate 10 arranged on which the first semiconductor layer 11 grew up epitaxially. For example, the substrate is formed with germanium, silicon and / or gallium arsenide. Alternatively to that in the 1 In the embodiment shown, it is possible for the substrate 10 has been replaced in a manufacturing process and the LED chip no substrate 10 having.

Based on the schematic representations of 2A and 2 B an operation of a light-emitting diode chip described here is explained in more detail. The 2A shows the crystal structure of a layer 31 and a reference layer 32 in the unadjusted and thus unstrained condition. In the 2 B is the crystal structure of the layer 31 and the reference layer 32 shown in the adjusted and thus strained state.

In the unstressed state, as in the 2A shown, assigns the layer 31 a first lattice constant a ₁ , which is the natural lattice constant of the material of the layer 31 can act. The reference layer 32 has in the unstressed state a second lattice constant a ₂ , which is smaller than the first lattice constant a ₁ in the case shown. The second lattice constant a ₂ can be the natural lattice constant of the material of the reference layer 32 be. Alternatively, it is possible that the second lattice constant a _{2 is} not the natural lattice constant of the material of the reference layer 32 corresponds, but the crystal structure of the reference layer 32 itself is tense.

In the in the 2 B shown strained state has the reference layer 32 furthermore the second lattice constant a ₂ . The layer 31 However, due to the pseudomorphic strain, it now has a parallel lattice constant a _p and a vertical lattice constant a _s . The vertical lattice constant a _s extends along the stacking direction z, while the parallel lattice constant a _p extends perpendicular to the stacking direction z, along one of the lateral directions. The parallel lattice constant a _p essentially corresponds to the second lattice constant a ₂ and is thus smaller than the first lattice constant a ₁ , while the vertical lattice constant a _{s is} greater than the first lattice constant a ₁ and the second lattice constant a ₂ .

The parallel lattice constant a _p has adapted to the second lattice constant a ₂ . In particular, the parallel lattice constant a _p corresponds to the second lattice constant a ₂ . The crystal structure of the layer 31 was thus compressed in lateral directions and the layer 31 is clamped compressively. Below the critical layer thickness of the layer 31 This compression can be compensated in the lateral direction by increasing the vertical lattice constant A _s .

In the in the 2A and 2 B shown layer 31 For example, it may be one of the quantum well layers 20 act. The reference layer 32 can then be the first intermediate layer 13 or to the quantum well layer 20 adjacent barrier layer 21 be.

That in connection with the 2A and 2 B explained principle of compressive strain at different lattice constants a ₁ , a ₂ , a _s , a _p can also mutatis mutandis, on a tensile strain, such as in the case of the barrier layers 21 as a layer 31 and the quantum well layer 20 as reference layer 32 , be applied. In other words, if the layer 31 in the unstressed state has a first lattice constant a ₁ , which is smaller than the second lattice constant a _{2 of} the reference layer 32 , arises when growing up on the reference layer 32 a tensioned layer 31 , In tensil stressed state, the layer 31 a parallel lattice constant a _p , which is greater than the vertical lattice constant a _s .

The 3 shows a sketched intensity signal of a switching pulse of a light-emitting diode chip described here. The intensity signal shows the intensity I of the electromagnetic radiation emitted by the light-emitting diode chip during operation of a switching pulse normalized to the maximum intensity signal I _m as a function of the time t. At the time t = 0, the LED chip is turned on. After switching on the intensity signal I increases as a function of time, then remains at the maximum value I _m and then drops again. The rise time t _r here is the time required for an increase of the intensity signal of I from 10% of the maximum intensity signal I _m to 90% of the maximum intensity signal I _m . Furthermore, the fall time t _{f is} the time required for a fall of the intensity signal I from 90% of the maximum intensity signal I _m to 10% of the maximum intensity signal I _m .

The 4 shows switching times for different embodiments of a light-emitting diode chip described here. Here, the rise time t _r and the fall time t _{f are shown} for different measurements M1, M2, M3, M4. The light-emitting diode chip associated with each of the measurements comprises eleven barrier layers each 21 ,

The quantum well layers 20 the first measurement M1 are tensile tensed. In particular, the active zone 2 of the LED chip of the first measurement M1 compared to the substrate 10 an average strain of -1500 ppm. The quantum well layers 20 of the second measurement M2 are unstrained within the scope of the measurement inaccuracies. In particular, the active zone 2 of the LED chip of the second measurement M2 compared to the substrate 10 an average tension of 50 ppm. The quantum well layers 20 of the third measurement M3 have a low compressive strain. The active zone 2 of the LED chip of the third measurement M3 has compared to the substrate 10 an average tension of 700 ppm. The quantum well layers 20 of the fourth measurement M4 have a high compressive strain. The active zone 2 of the LED chip of the fourth measurement M4 has compared to the substrate 10 an average strain of 1200 ppm.

In addition, the barrier layers 21 the LED chips of the third measurement M3 and the fourth measurement M4 are each higher than the barrier layers 21 the LED chips of the first measurement M1 and the second measurement M2 doped. For example, the barrier layers 21 each doped with a p-type dopant.

The light-emitting diode chip of the first measurement M1 has a rise time t _r of 10.7 ns. The fall time t _{f of} the first measurement M1 is 13.2 ns. The light-emitting diode chip of the second measurement M2 has a rise time t _r of 9.8 ns and a fall time t _f of 11.7 ns. The LED chip of the third measurement M3 has a rise time t _r of 6.9 ns and a fall time t _f of 4.4 ns. The LED chip of the fourth measurement M4 has a rise time t _r of 6.2 ns and a fall time t _f of 4.4 ns.

Due to the compressive strain of the quantum well layers 20 The light-emitting diode chips of the third measurement M3 and the fourth measurement M4 are thus the switching times, in particular the rise time t _r and the fall time t _f , reduced. In addition, increasing the compressive strain in the quantum well layers 20 of the LED chip of the fourth measurement M4 in comparison to the less strongly strained quantum well layers 20 the third measurement M3 to a further reduction of the rise time t _r .

The invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

10

 substratum

11

 first semiconductor layer

12

 second semiconductor layer

13

 first intermediate layer

14

 second intermediate layer

2

 active zone

20

 Quantum well layer

20d

 Thickness of the quantum well layer

21

 barrier layer

31

 (strained) layer

32

 reference layer

a ₁

 first lattice constant

a ₂

 second lattice constant

a _s

 vertical lattice constant

a _p

 parallel lattice constant

_r

 rise time

t _f

 Fall time

I _m

 maximum intensity signal

I

 intensity signal

M1

 first measurement

M2

 second measurement

M3

 third measurement

M4

 fourth measurement

z

 stacking direction

Claims (12)

LED chip comprising - one on a first semiconductor layer ( 11 ) epitaxially grown active zone ( 2 ) with - at least one quantum well layer ( 20 ), where - the active zone ( 2 ) is clamped compressively. A light-emitting diode chip according to the preceding claim, in which the active zone ( 2 ) at least two quantum well layers ( 20 ) and at least one between the at least two quantum well layers ( 20 ) arranged barrier layer ( 21 ). Light-emitting diode chip according to one of the preceding claims, in which the first semiconductor layer ( 11 ) epitaxially on a substrate ( 10 ) and an average strain of the active zone ( 2 ) relative to the substrate ( 10 ) is at least 600 ppm, preferably at least 1000 ppm and more preferably at least 2000 ppm. A light-emitting diode chip according to one of the preceding claims, in which - the quantum well layers ( 20 ) are clamped pseudomorphically compressively and - the strain coefficient of the quantum well layers ( 20 ) in each case by at least 7500 ppm, preferably at least 15000 ppm, greater than the stressing coefficient of the barrier layer ( 21 ). A light-emitting diode chip according to one of the preceding claims, which in operation emits electromagnetic radiation having a peak wavelength of at least 750 nm, preferably at least 850 nm, and at most 1000 nm, preferably at most 940 nm. Light-emitting diode chip according to one of the preceding claims, in which the at least one quantum well layer ( 20 ) a thickness ( 20d ) of at least 2 nm, preferably at least 3 nm, and at most 6 nm, preferably at most 5 nm. Light-emitting diode chip according to one of the preceding claims, in which the at least one quantum well layer ( 20 ) based on GaAs, wherein at least 5% and at most 44% of the gallium atoms have been replaced by indium and / or aluminum atoms. Light-emitting diode chip according to one of the preceding claims, in which the at least one quantum well layer ( 20 ) are formed with In _x Ga _1-x As, wherein 0.08 ≦ x ≦ 1, preferably 0.16 ≦ x ≦ 1. Light-emitting diode chip according to one of the preceding claims, in which the barrier layer ( 21 ) pseudomorph tensil is braced and the strain coefficient of the barrier layer ( 21 ) with respect to the substrate ( 10 ) is at least -10000 ppm and at most -500 ppm. Light-emitting diode chip according to one of the preceding claims, in which the barrier layer ( 21 ) with Al _y Ga _1-y As _b P _1-b , where b ≥ 0.09, preferably b ≥ 0.18. A light-emitting diode chip according to one of the preceding claims, wherein an intensity signal during a switching pulse has a rise time (t _r ) of at most 10 ns and / or a fall time (t _f ) of at most 12 ns. Light-emitting diode chip according to one of the preceding claims, which is free of a resonator.

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