DE102015107182A1 - Fin Field Effect Transistor (FinFET) device and method of making the same - Google Patents

Abstract

A fin field effect transistor (FinFET) device structure and a method of forming the FinFET device structure are provided. The FinFET device structure includes a substrate and a fin structure extending over the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height, wherein the first height is greater than the second height, and the fin sidewall spacers are configured to regulate a volume and the first height of the epitaxial structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to the following co-pending and commonly assigned application U.S. Pat. Serial no. No. 14 / 517,209, filed October 17, 2014, entitled "Fin field effect transistor (FinFET) device and method for forming the same" (Applicant's Serial No. TSMC 2014-0685).

GENERAL PRIOR ART

Semiconductor devices are used in a variety of electronic applications such. As workstations, mobile phones, digital cameras and other electronic devices used. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconducting layers of material over a semiconductor substrate, and patterning these dissimilar material layers using lithography to form thereon components and elements of circuits. Many integrated circuits are typically fabricated on a single semiconductor wafer and the individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are usually packaged separately in multi-chip modules or other package types.

As the semiconductor industry has progressed toward the nanometer technology process nodes in efforts to achieve higher device density, higher performance, and lower cost, the challenges of both manufacturing and design problems have been the development of three-dimensional designs, such as silicon nanoprocessing. B. the fin field effect transistor (FinFET), had the consequence. FinFETs are made with a thin vertical "fin" (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. Above the fin, a gate is provided. Advantages of the FinFET may include limiting the short channel effect and higher current flow.

Although the present FinFET devices and the methods of fabricating FinFET devices have generally been adequate for their intended purpose, they have not been fully satisfactory in every way.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is noted that in accordance with the usual practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of exposition.

1 FIG. 12 is a perspective view of a fin field effect transistor (FinFET) device structure according to some embodiments of the disclosure. FIG.

The 2A - 2F 12 show side views of various shaping stages of a fin field effect transistor (FinFET) device structure according to some embodiments of the disclosure.

2G is an enlarged view of a region A of 2F according to some embodiments of the disclosure.

The 3A - 3B 12 show side views of various shaping stages of a fin field effect transistor (FinFET) device structure according to some embodiments of the disclosure.

3C is an enlarged view of a region B of 3B according to some embodiments of the disclosure.

The 4A - 4D 12 show side views of various shaping stages of a fin field effect transistor (FinFET) device structure according to some embodiments of the disclosure.

4E is an enlarged view of a region C of 4D according to some embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Hereinafter, specific examples of components and arrangements will be described to simplify the present disclosure. Of course, these are just examples, and they are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are in direct contact can be formed, and it may also include embodiments in which additional features may be formed between the first and second feature such that the first and second feature can not contact directly. Additionally, reference numerals and / or characters may be repeated in the various examples in the present disclosure. This repetition is for convenience and clarity and, by itself, does not suggest any relationship between the various embodiments and / or configurations discussed.

Some variants of the embodiments will be described. In the various views and illustrative embodiments, like reference numerals are used throughout to identify similar elements. It is understood that additional operations may be provided before, during, and after the process, and that for other embodiments of the process, some of the operations described may be substituted or omitted.

Embodiments are provided for forming a fin field effect transistor (FinFET) device structure. 1 shows a perspective view of a fin field effect transistor (FinFET) device structure 10 according to some embodiments of the disclosure. The FinFET device structure 10 includes an n-channel FinFET device structure (NMOS) 15 and a p-channel FinFET device structure (PMOS) 25 ,

The FinFET device structure 10 includes a substrate 102 , The substrate 102 may consist of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 other element semiconductor materials, such as. B. germanium. In some embodiments, the substrate is 102 from a compound semiconductor, such as. As silicon carbide, gallium arsenide, indium arsenide or indium phosphide. In some embodiments, the substrate is 102 from an alloy semiconductor, such as. Silicon germanium, silicon germanium carbide, gallium arsenide phosphide or gallium indium phosphide. In some embodiments, the substrate 102 an epitaxial layer. For example, the substrate 102 have an epitaxial layer, which rests on a semiconductor body.

The FinFET device structure 100 also has one or more fin structures 104 (eg, Si fins) extending from the substrate 102 extend out. Optionally, the fin structure 104 Germanium (Ge). The fin structure 104 can be determined using suitable processes, such. As photolithography and etching processes are formed. In some embodiments, the fin structure becomes 104 from the substrate 102 etched using dry etching or plasma processes.

In some other embodiments, the fin structure may 104 be formed by a double structuring lithography (DPL) process. DPL is a method of creating a pattern on a substrate by dividing the pattern into two nested structures. The DPL allows for increased density of features (eg, fins).

It becomes an isolation structure 108 , such as For example, a trench isolation (shallow trench isolation, STI) is formed around the fin structure 104 to enclose. In some embodiments, a lower part of the fin structure becomes 104 from the isolation structure 108 enclosed, and an upper part of the fin structure 104 protrudes from the isolation structure 108 out, like in 1 is shown. In other words, part of the fin structure 104 in the isolation structure 108 embedded. The isolation structure 108 prevents electrical interference or crosstalk.

The FinFET device structure 100 further includes a gate stack structure including a gate electrode 110 and a gate dielectric layer (not shown). The gate stack structure is over a middle part of the fin structure 104 educated. In some other embodiments, over the fin structure 104 formed a plurality of gate stack structures.

In some other embodiments, the gate stack structure is a dummy gate stack, which is later replaced by a metal gate (MG) after the high heat conversion processes have been performed.

The gate dielectric layer (not shown) may include dielectric materials, such as silicon dioxide. As silicon oxide, silicon nitride, silicon oxynitride, dielectric material (s) having a high dielectric constant (high-k) or combinations thereof, have. Examples of high dielectric constant dielectric materials include hafnium oxide, zirconia, alumina, hafnia-alumina alloy, hafnium-silicon oxide, hafnium-silicon oxynitride, hafnium-tantalum oxide, hafnium-titanium oxide, hafnium-zirconium oxide , the like or combinations thereof.

The gate electrode 110 may comprise polysilicon or metal. The metal includes tantalum nitride (TaN), nickel-silicon (NiSi), cobalt-silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zircon (Zr ), Platinum (Pt) or other usable materials. The gate electrode 110 can be in a gate-load process (or gate exchange process) are formed. In some embodiments, the gate stack structure includes additional layers, such as. B. interfacial layers, cover layers, diffusion / barrier layers or other useful layers on.

The gate stack structure is formed by a deposition process, a photolithography process and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), organometallic CVD (MOCVD), remote plasma CVD (RPCVD), plasma assisted CVD (PECVD), Plating, other suitable methods and / or combinations thereof. Photolithographic processes include photoresist coating (e.g., spin coating), mild annealing, mask alignment, exposure, post-exposure annealing, photoresist development, rinsing, and drying (eg, baking). The etching process includes a dry etching process or a wet etching process. Alternatively, the photolithography process by other suitable methods, such as. As maskless lithography, electron beam writing and ion beam writing, realized or replaced.

The 2A - 2F 12 show side views of various shaping stages of a fin field effect transistor (FinFET) device structure according to some embodiments of the disclosure. The 2A - 2F show side views taken along the arrow 1 from 1 are included, the arrow 1 parallel to the X axis.

With reference to 2A will be on the gate electrode 110 a first hard mask layer 112 formed, and on the first hard mask layer 112 becomes a second hardmask layer 114 educated. In some embodiments, the first hard mask layer is 112 of silicon oxide, silicon nitride, silicon oxynitride or other usable materials. In some embodiments, the second hard mask layer is 114 of silicon oxide, silicon nitride, silicon oxynitride or other usable materials.

On the opposite side walls of the gate electrode 110 become gate sidewall spacers 115 formed, and on the opposite side walls of the fin structure 104 become fin sidewall spacers 105 educated. After that, on the gate sidewall spacers 115 a floor antireflection coating (BARC) layer 202 educated. The BARC layer 202 is used under a photoresist layer to transfer the structure onto the hardmask layers 112 . 114 during a structuring process. When an Implantation Process on an N-Channel FinFET Device Structure (NMOS) 15 then, in some embodiments, the BRAC 202 and a photoresist (not shown) standing on the BRAC 202 is formed on the gate electrode 110 generated to the gate electrode 110 in the p-channel FinFET device structure (PMOS) 25 cover.

Thereafter, the (not shown) photoresist and the BRAC 202 according to some embodiments of the disclosure, eliminates by an etching process, as in 2 B is shown. The etching process may be a dry etching process or a wet etching process. In some embodiments, a first dry etch process is performed at a pressure in a range of about 3 millitorr to about 50 millitorr. In some embodiments, the gas used in the first dry etching process includes methane (CH ₄ ), nitrogen (N ₂ ), helium (He), oxygen (O ₂ ), or combinations thereof. In some embodiments, the first dry etching process is performed at a power in a range of about 50 watts to about 1000 watts. In some embodiments, the first dry etching process is performed at a temperature in a range of about 20 ° C to about 80 ° C.

After the BRAC 202 is eliminated, part of the gate sidewall spacers, in accordance with some embodiments of the disclosure 115 and part of the fin sidewall spacer 105 eliminated, as in 2C is shown. More specifically, it becomes a header of the gate sidewall spacers 115 eliminated the second hardmask layer 114 expose. A headboard of fin sidewall spacers 105 is eliminated to the fin structure 104 expose.

In some embodiments, when the gate sidewall spacers 115 and the fin sidewall spacer 105 made of silicon nitride, a second etching process is performed to remove the silicon nitride. In some embodiments, the second etching process is a second dry etching process performed at a pressure in a range of about 3 millitorr to about 50 millitorr. In some embodiments, the gas used in the second dry etch process comprises fluoromethane (CH ₃ F), difluoromethane (CH ₂ F ₂ ), methane (CH ₄ ), argon (Ar), hydrogen bromide (HBr), nitrogen (N ₂ ), Helium (He), oxygen (O ₂ ) or combinations thereof. In some embodiments, the second dry etching process is performed at a power in a range of about 50 watts to about 1000 watts. In some embodiments, the second dry etching process is performed at a temperature in a range of about 20 ° C to about 70 ° C.

After the second dry etching process, each of the fin sidewall spacers 105 a first height H ₁ . In some embodiments, the first is Height H ₁ in a range of about 0.1 nm to about 100 nm.

After the part of the gate sidewall spacer 115 and the part of the fin sidewall spacer 105 are eliminated, part of the remaining fin sidewall spacers, in accordance with some embodiments of the disclosure 105 eliminated, as in 2D is shown. The upper parts of the fin sidewall spacer 105 are eliminated by a third etching process. The third etching process may be a dry etching process or a wet etching process.

In some embodiments, the third etching process is a third dry etching process performed at a pressure in a range of about 3 millitorr to about 50 millitorr. In some embodiments, the gas used in the third dry etching process includes fluoromethane (CH ₃ F), difluoromethane (CH ₂ F ₂ ), methane (CH ₄ ), argon (Ar), hydrogen bromide (HBr), nitrogen (N ₂ ), Helium (He) or oxygen (O ₂ ) or combinations thereof. In some embodiments, the third dry etching process is performed at a power in a range of about 50 watts to about 1000 watts. In some embodiments, the third dry etching process is performed at a temperature in a range of about 20 ° C to about 70 ° C.

After the third dry etching process, the height of the fin sidewall spacer is 105 has been reduced from a first height H ₁ to a second height H ₂ . In some embodiments, the second height H ₂ is in a range of about 0.1 nm to about 90 nm.

It should be noted that the second height H _{2 of} the fin sidewall spacer 105 critical for an epitaxial structure (such as the epitaxial structure 210 in 2E -2) is. The height and volume of the epitaxial structure are determined by the second height H _{2 of} the fin sidewall spacers 105 affected. In other words, the fin sidewall spacer 105 are designed, the height and the volume of the epitaxial structure 210 to regulate.

After the third dry etching process, according to some embodiments of the disclosure, a part of the fin structure becomes 104 eliminated, as in 2E is shown. The fin structure 104 is by an etching process, such. As a dry etching or wet etching process eliminated.

As in 2E is shown, there is a top surface of the remaining fin structure 104 on a plane with a top surface of the isolation structure 108 , By eliminating part of the fin structure 104 , over the isolation structure 108 lies, becomes a ditch 204a educated. The side walls of the trench 204a are vertically parallel to each other. In some embodiments, an angle θ _{1 is} between the sidewall of the trench 204a and a top surface of the fin structure 104 about 90 degrees.

After the part of the fin structure 104 is eliminated, in accordance with some embodiments of the disclosure in the trenches 204a an epitaxial structure 210 trained as in 2F is shown.

The epitaxial structure 210 has a source / drain epitaxial structure. In some embodiments, the source / drain epitaxial structures comprise epitaxial growth silicon (Epi-Si) when an n-channel FET (NFET) device is required. Alternatively, if a p-channel FET (PFET) device is required, then the source / drain epitaxial structures have an epitaxially growing silicon germanium (SiGe).

2G is an enlarged view of a region A of 2F according to some embodiments of the disclosure. As in 2G is shown, has the epitaxial structure 210 a rhombus-like upper part and a columnar lower part. The rhomboid-like upper part of the epitaxial structure 210 has four facets 210A . 210B . 210C and 210D on. Every facet has a crystallographic orientation ( 111 ). The columnar lower part of the epitaxial structure 210 has a bottom surface and sidewalls that connect to the bottom surface. An angle θ ₁ between the bottom surface and the side walls is about 90 degrees. In addition, the bottom surface of the columnar lower portion of the epitaxial structure is located 210 essentially in a plane with the top surface of the insulation structure 108 ,

As in 2G has the epitaxial structure 210 a height H _t1 and a width W ₁ . In some embodiments, the height H _{t1 is} in a range of about 10 nm to about 300 nm. If the height H _{t1 is} too large, then the electrical resistance becomes lower. If the height H _{t1 is} too small, then the electrical resistance increases so that it affects the device speed. In some embodiments, the width W _{1 is} in a range of about 10 nm to about 100 nm. If the width W _{1 is} too large, then the epitaxial structure 210 pass into the neighboring and cause a short circuit. If the width W _{1 is} too small, then a contact window for contacting the epitaxial structure 210 too narrow, and consequently the circuit effect can be interrupted.

In addition, there is a ratio (H _t1 / H ₂ ) of the height H _{t1 of} the epitaxial structure 210 to the height H _{2 of} the fin sidewall spacer 105 in a range of about 1.5 to about 10. If the ratio is too small, then the fin sidewall can not effectively support the Be EPI high and create an EPI structure short.

The 3A - 3B 12 show side views of various shaping stages of a fin field effect transistor (FinFET) device structure according to some embodiments of the disclosure.

As in 3A is shown, there is a top surface of the remaining fin structure 104 lower than a top surface of the insulation structure in some embodiments 108 , By eliminating part of the fin structure 104 that under the isolation structure 108 lies, becomes a ditch 204b educated. In some other embodiments, an angle θ _{2 is} between the sidewall of the trench 204b and a top surface of the fin structure 104 about 90 degrees. The ditch 204b extends from a top surface of the isolation structure 108 to a depth D1 in a range of about 0.1 nm to about 50 nm.

After the part of the fin structure 104 is eliminated, in accordance with some embodiments of the disclosure in the trenches 204b an epitaxial structure 212 trained as in 3B is shown. The epitaxial structure 212 has a source / drain epitaxial structure. In some embodiments, the source / drain epitaxial structures comprise epitaxial growth silicon (Epi-Si) when an n-channel FET (NFET) device is required. Alternatively, if a p-channel FET (PFET) device is required, then the source / drain epitaxial structures have an epitaxially growing silicon germanium (SiGe).

3C is an enlarged view of a region B of 3B according to some embodiments of the disclosure. As in 3C is shown, has the epitaxial structure 212 a rhombus-like upper part and a columnar lower part. The rhomboid-like upper part of the epitaxial structure 212 has four facets 212A . 212B . 212C and 212D on. Every facet has a crystallographic orientation ( 111 ). The columnar lower part of the epitaxial structure 212 has a bottom surface and sidewalls that connect to the bottom surface. An angle θ ₂ between the bottom surface and the sidewalls is approximately 90 degrees. In addition, the bottom surface of the columnar lower portion of the epitaxial structure is located 212 deeper than a top surface of the insulation structure 108 ,

As in 3C has the epitaxial structure 212 a height H _t2 and a width W ₂ . The height H _t1 is smaller than the height H _{t2 ,} and the width W ₁ is greater than the width W ₂ . In some embodiments, the height H _{t2 is} in a range of about 15 nm to about 150 nm. In some embodiments, the width W _{2 is} in a range of about 10 nm to about 100 nm.

The epitaxial structures 210 and an epitaxial structure 212 have independently a single element semiconductor material, such as. As germanium (Ge) or silicon (Si), or compound semiconductor materials, such as. Gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or a semiconductor alloy, such as. Silicon germanium (SiGe), gallium arsenide phosphide (GaAsP).

The epitaxial structures 210 and 212 are formed by an epi process. The epi process may include a selective epitaxial growth (SEG) process, CVD deposition techniques (eg, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other applicable Epi processes.

The epitaxial structures 210 and 212 can be doped in situ or left undoped during the epi process. For example, the epitaxially grown SiGe epitaxial structure may be doped with boron, and the epitaxially grown Si epitaxial structure may be doped with carbon to form an Si: C epitaxial structure with phosphorus to form an Si: P epitaxial structure, or both with carbon as well as phosphorus to form a SiCP epitaxial structure. The doping may be performed by an ion implantation process, plasma immersion ion implantation (PIII) process, a gas and / or solid source diffusion process, or other suitable process. The epitaxial structures 210 and 212 can also heat treatment processes, such. As a rapid thermal annealing process.

Become the epitaxial structures 210 and 212 not doped in situ, a second implantation process (eg, a joint implantation process) is performed to form the epitaxial structures 210 and 212 to dope.

The fin structure 104 has a channel region (not shown) from the gate electrode 110 enclosed or wrapped. The lattice constants of the epitaxial structure 210 and 212 differ from that of the substrate 102 , the channel region is deformed or distorted to allow the carrier mobility of the FinFET device structure and to increase the performance of the FinFET device structure.

It should be noted that the volume and the heights H _t1, H _t2 of the epitaxial structure 210 and 212 by adjusting the height H _{2 of} the fin sidewall spacers 105 and / or the depth D _{1 are} regulated. Once the volume and heights H _t1 , H _{t2 of} the epitaxial structure 210 and 212 are properly controlled, a further improvement in the performance of the FinFET device structure is achieved. To the For example, the device mobility (Id_Sat) will increase as the FinFET device structure is improved.

The 4A - 4D 12 show side views of various shaping stages of a fin field effect transistor (FinFET) device structure according to some embodiments of the disclosure. 4E is an enlarged view of the area C of 4D according to some embodiments of the disclosure. The 4A - 4D show side views taken along the arrow 1 from 1 are included, the arrow 1 parallel to the X axis.

With reference to 4A become the gate sidewall spacers 115 on the opposite side walls of the gate electrode 110 and the fin sidewall spacer 105 on the opposite side walls of the fin structure 104 educated.

Thereafter, in accordance with some embodiments of the disclosure, the fin sidewall spacers become 105 completely eliminated, as in 4B is shown. As a result, the top surface and part of the side walls are the fin structure 104 exposed. On the fin structure 104 are not fin sidewall spacers 105 educated.

After the fin sidewall spacer 105 are completely eliminated, becomes a part of the fin structure according to some embodiments of the disclosure 104 eliminated, as in 4C is shown. The result is by eliminating part of the fin structure 104 a ditch 304 educated.

The ditch 304 has a depth D ₂ , which is below the isolation structure 108 is. In some embodiments, the depth D _{2 is} in a range of about 0.1 nm to about 50 nm. In some embodiments, an angle θ _{2 is} between the sidewall of the trench 304 and a top surface of the fin structure 104 about 90 degrees.

After the part of the fin structure 104 is eliminated, in accordance with some embodiments of the disclosure in the trench 304 and on the fin structure 104 an epitaxial structure 214 trained as in 4D is shown.

The epitaxial structures 214 has a single-element semiconductor material, such as. As germanium (Ge) or silicon (Si), or compound semiconductor materials, such as. Gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or a semiconductor alloy, such as. Silicon germanium (SiGe), gallium arsenide phosphide (GaAsP).

The epitaxial structures 214 is formed by an epi process. The epi process may include a selective epitaxial growth (SEG) process, CVD deposition techniques (eg, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other applicable Epi processes.

Similar to the epitaxial structures 210 and 212 has the epitaxial structure 214 a rhombus-like upper part and a columnar lower part. The rhomboid-like upper part of the epitaxial structure 214 has four facets 214A . 214B . 214C and 214D on. Every facet has a crystallographic orientation ( 111 ).

It should be noted that in comparison with 2G and 3C no fin sidewall spacers are formed on the epitaxial structure 214 in 4E adjoin. Therefore, the volume and height of the epitaxial structure become 214 regulated by the depth of the (in 4 shown) trench 304 is adjusted. Since there are no fin sidewall spacers showing the growth of the epitaxial structure 214 obstruct, the epitaxial structure tends 214 in addition to growth in the direction of the X-axis. Therefore, the width W _{3 of} the epitaxial structure 214 larger than the width W _{4 of} the fin structure 104 ,

The epitaxial structure 214 has a height H _t3 and a width W ₃ . The height H _{t3 of} the epitaxial structure 214 is smaller than the height H _{t2 of} the epitaxial structure 212 , and the width W _{2 of} the epitaxial structure 212 is greater than the width W _{3 of} the epitaxial structure 214 , In addition, height H is _{t3 of} the epitaxial structure 214 smaller than the height H _{t1 of} the epitaxial structure 210 , and the width W _{1 of} the epitaxial structure 210 is greater than the width W _{3 of} the epitaxial structure 214 ,

With renewed reference to 4D is a distance S between two adjacent epitaxial structures 214 in a range of about 0.1 nm to about 100 nm. In some embodiments, the width W _{3 of} the epitaxial structure is 214 in a range of about 10 nm to about 100 nm. In some embodiments, the height H _{t3 of} the epitaxial structure is 214 in a range of about 10 nm to about 300 nm. In some embodiments, the ratio (H _t3 / W ₃ ) is the height to the width of the epitaxial structure 214 in a range of about 0.1 to about 10.

Thereafter, it may be proceeded to subject the FinFET structure to further processes to form other structures or devices. In some embodiments, the metallization includes vertical connections, such as. As conventional vias or contacts, as well as horizontal connections, such. B. metal interconnects. The various connection features can be realized by various conductive materials, including copper, tungsten and / or silicide.

Embodiments are provided for forming a fin field effect transistor (FinFET) device structure. The FinFET device structure includes a fin structure extending over the substrate and an epitaxial structure formed on the fin structure. Adjacent to the epitaxial structure, in some embodiments, the fin sidewall spacers are formed. The fin sidewall spacers are designed to regulate a volume and the height of the epitaxial structure. In some other embodiments, there are no sidewall spacers adjacent to the epitaxial structure, the volume and height of the epitaxial structure are regulated by adjusting the depth of a trench formed by resetting a top portion of the fin structure. Once the volume and height of the epitaxial structure are controlled, a further improvement in the performance of the FinFET device structure is achieved.

In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate and a fin structure extending over the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent the epitaxial structure. The sidewall spacers have a second height, wherein the first height is greater than the second height, and the fin sidewall spacers are configured to regulate a volume and the first height of the epitaxial structure.

In some embodiments, a fin field effect transistor (FinFET) device structure is provided. The FinFET structure includes a substrate and a fin structure extending over the substrate. The FinFET structure also includes an isolation structure formed on the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes a first epitaxial structure formed on the fin structure, wherein an interface between the first epitaxial structure and the fin structure is below a top surface of the isolation structure, and wherein no fin sidewall spacers adjacent to the first epitaxial structure are formed ,

In some embodiments, a method of forming a fin field effect transistor (FinFET) device structure is provided. The method includes providing a substrate and forming a fin structure over the substrate. The method also includes forming a gate stack structure over a central portion of the fin structure and forming gate sidewall spacers on a top surface and sidewalls of the gate stack structure, and forming fin sidewall spacers on a top surface and sidewalls of the fin structure , The method further includes eliminating a head portion of the gate sidewall spacers and a head portion of the fin sidewall spacers to expose a top portion of the gate stack structure and a top portion of the fin structure. The method includes eliminating a portion of the fin sidewall spacers, the fin sidewall spacers having a second height. The method further includes resetting a portion of the fin structure to form a trench. The method also includes growing an epitaxial structure from the trench, and the epitaxial structure is formed over the fin structure, and the epitaxial structure has a first height, wherein the first height is greater than the second height.

In the foregoing, features of various embodiments are briefly presented so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or achieve the same benefits of the embodiments set forth herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may carry out various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

Fin field effect transistor (FinFET) device structure with: a substrate; a fin structure extending over the substrate; an epitaxial structure formed on the fin structure, the epitaxial structure having a first height; Fin sidewall spacers formed adjacent the epitaxial structure, wherein the sidewall spacers have a second height and the first height is greater than the second height, and wherein the fin sidewall spacers are configured to regulate a volume and the first height of the epitaxial structure. The fin field effect transistor (FinFET) device structure of claim 1, further comprising: a gate stack structure formed over a middle part of the fin structure, wherein the epitaxial structure is formed adjacent to the middle part of the fin structure. The fin field effect transistor (FinFET) device structure of claim 1 or 2, wherein the second height is in a range of about 0.1 nm to about 100 nm Fin field effect transistor (FinFET) device structure according to one of the preceding claims, further comprising: an insulation structure, wherein the fin structure is embedded in the isolation structure. A fin field effect transistor (FinFET) device structure according to claim 4, wherein a bottom surface of the epitaxial structure lies in a plane with the top surface of the insulating structure. Fin-field effect transistor (FinFET) device structure according to claim 4, wherein a bottom surface of the epitaxial structure is lower than a top surface of the insulating structure. The fin field effect transistor (FinFET) device structure of claim 6, wherein the epitaxial structure extends from a top surface of the isolation structure to a depth in a range of about 0.1 nm to about 50 nm. Fin-field effect transistor (FinFET) device structure according to one of the preceding claims, wherein the epitaxial structure comprises a source / drain structure. A fin field effect transistor (FinFET) device structure as claimed in any one of the preceding claims, wherein the epitaxial structure has a rhombus-like upper portion and a columnar lower portion and wherein the columnar lower portion has a bottom surface and sidewalls adjoining the bottom surface and wherein an angle between floor area and side walls is about 90 degrees. Fin field effect transistor (FinFET) device structure with: a substrate; a fin structure extending over the substrate; an insulating structure formed on the substrate, the fin structure being embedded in the insulating structure; and a first epitaxial structure formed on the fin structure, wherein an interface of the first epitaxial structure and the fin structure is below a top surface of the isolation structure, and wherein no fin sidewall spacers are formed adjacent to the first epitaxial structure. The fin field effect transistor (FinFET) device structure of claim 10, wherein the first epitaxial structure extends from a top surface of the isolation structure to a depth in a range of about 0.1 nm to about 50 nm. Fin field effect transistor (FinFET) device structure according to claim 10 or 11, further comprising: a gate stack structure formed over a middle part of the fin structure; and Gate sidewall spacers formed adjacent to the gate stack structure. Fin field effect transistor (FinFET) device structure according to any one of claims 10 to 12, further comprising: a second epitaxial structure adjacent to the first epitaxial structure, wherein a distance between the first epitaxial structure and the second epitaxial structure is in a range of about 0.1 nm to about 100 nm. The fin field effect transistor (FinFET) device structure according to any one of claims 10 to 13, wherein the epitaxial structure has a rhombus-like upper part and a columnar lower part, and wherein the columnar lower part has a bottom surface and sidewalls adjoining the bottom surface, and wherein Angle between the floor surface and the side walls is about 90 degrees. The fin field effect transistor (FinFET) device structure of any one of claims 10 to 14, wherein the fin structure has a first width, the first epitaxial structure having a second width, and wherein the second width is greater than the first width. A method of forming a fin field effect transistor (FinFET) device structure, comprising: providing a substrate; Forming a fin structure over the substrate; Forming a gate stack structure over a middle part of the fin structure; Forming gate sidewall spacers on a top surface and sidewalls of the gate stack structure, and forming fin sidewall spacers on a top surface and sidewalls of the fin structure; Eliminating a head portion of the gate sidewall spacers and a head portion of the fin sidewall spacers to expose a head portion of the gate stack structure and a top portion of the fin structure; Eliminating a portion of the fin sidewall spacers, the fin sidewall spacers having a second height; Canceling a part of the fin structure to form a trench; and epitaxially growing an epitaxial structure from the trench, wherein the epitaxial structure is formed over the fin structure and the epitaxial structure has a first height and the first height is greater than the second height. The method of forming the FinFET device structure of claim 16, wherein forming the gate stack structure over the middle portion of the fin structure comprises: Forming a gate electrode on the fin structure; Forming a first hardmask layer on the gate electrode; and Forming a second hard mask layer on the first hard mask layer. The method of forming the FinFET device structure of claim 16 or 17, further comprising: Forming an insulation structure on the substrate, wherein a bottom surface of the epitaxial structure lies on a plane with or below a top surface of the insulation structure. The method of forming the FinFET device structure according to any one of claims 16 to 18, wherein removing a part of the fin structure for forming the recess between the fin sidewall spacers further comprises: Eliminating the part of the fin structure until a top surface of the fin structure lies on a plane with or below a top surface of the insulation structure. A method of forming the FinFET device structure of any one of claims 16 to 19, further comprising prior to epitaxial epitaxial growth of the epitaxial structure: Eliminating the entire fin sidewall spacer; and Removing a part of the fin structure until a top surface of the fin structure is below a top surface of the insulation structure.

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