DE102015003082B4 - MOS transistor with an improved on-resistance - Google Patents

Abstract

MOS transistor in a substrate (sub) or a doped well (well) with a second conductivity type, which have a surface (OBS), the transistor having a second highly doped drain contact region (DD +) of a first conductivity type that extends to the surface (OBS), and wherein the transistor has a first highly doped source contact region (DS +) of the first conductivity type, which is spaced from the second drain contact region (DD +) by a channel region (CHN) and extends to the surface (OBS), and - the surface (OBS) of the substrate (Sub) and / or the well (well) being covered with an electrically insulating dielectric (GOX, IOX2) in the area of the channel region (CHN) and - being along at least one first straight or curved connecting line (B-B ') between the first source contact region (Ds +) and the second drain contact region (DD +) this first connecting line intersects at least one highly doped bulk contact region (BCA) which has the second conductivity type and is directly adjacent to the highly doped source contact region (Ds +) and extends to the surface (OBS), and - along at least one second straight or curved connecting line (A-A ') between the first source contact region (Ds + ) and the second drain contact area (DD +), this second connecting line, this at least one highly doped bulk contact area (BCA), which has the second conductivity type, does not intersect, characterized in that along at least the first straight or curved connecting line (B-B ') between the first source contact area (Ds +) and the second drain contact area (DD +) this first connecting line intersects at least the highly doped bulk contact area (BCA) and additionally a highly doped LDD area (LDD) intersects the first Has conductivity type and the highly doped bulk contact area (BCA) is directly adjacent, and that the highly doped bulk contact area (BCA) between the LDD area (LDD) and the adjacent highly doped source contact area (Ds +) and- that the highly doped bulk contact area (BCA) has a contact area (BF) with the LDD area (LDD) and- that said LDD implantation area (LDD ) to the highly doped drain contact area (DD +) or another bulk contact area (BCA), which in particular can be adjacent to the highly doped drain contact area (DD +), or another LDD area that is defined by the first connecting line (B- B ') is cut, is not adjacent - that this contact surface (BF) - lies in the drain direction beyond the source-side edge (SSSK) of a source-side spacer (SP1) or - in the drain direction beyond a source side poly edge (SPK) or on the source-side poly edge (SPK)

Description

introduction

• 1 zeigt einen relevanten beispielhaften MOS-Transistor entsprechend dem Stand der Technik in schematischer Weise von oben skizziert. Die Figur zeigt zwei Schnittlinie A-A' und B-B', die in den beiden nachfolgenden Figuren dargestellt sind.
• 2 zeigt einen beispielhaften schematisierten Schnitt durch den Transistor der 1 entlang der in der 1 skizzierten Line A-A'.
• 3 zeigt einen beispielhaften schematisierten Schnitt durch den Transistor der 1 entlang der in der 1 skizzierten Line B-B'.
• 4 zeigt einen beispielhaften schematisierten Schnitt durch den Transistor der 1 entlang der in der 1 skizzierten Line A-A', wobei die Oberfläche (OBS) des Substrates (Sub) in Sinne dieser Offenbarung durch eine fett markierte Linie hervorgehoben ist.
• 5 zeigt einen relevanten beispielhaften MOS-Transistor entsprechend dem Stand der Technik in schematischer Weise von oben skizziert mit skizzierten Strompfaden.

The invention relates to a MOS transistor, which is preferably produced in a shallow trench technology. First, the prior art is based on the 1 to 4th explained in order to derive the task to be solved.

• 1 shows a relevant exemplary MOS transistor according to the prior art in a schematic manner outlined from above. The figure shows two section lines AA 'and B-B', which are shown in the two following figures.
• 2 FIG. 11 shows an exemplary schematic section through the transistor of FIG 1 along the in the 1 sketched line A-A '.
• 3 FIG. 11 shows an exemplary schematic section through the transistor of FIG 1 along the in the 1 sketched line B-B '.
• 4th FIG. 11 shows an exemplary schematic section through the transistor of FIG 1 along the in the 1 sketched line A-A ', the surface ( OBS) of the substrate ( Sub ) in the sense of this disclosure is highlighted by a bold line.
• 5 shows a relevant exemplary MOS transistor according to the prior art in a schematic manner sketched from above with sketched current paths.

As the functions of the various structures become clearer in the sectional images, the 2 and 3 described and then the 1 which was only listed first to clarify the different cutting positions (A-A ', B-B').

2 shows the exemplary, sketched section through a transistor of the prior art. This is in a semiconducting, typically monocrystalline substrate ( Sub ) manufactured. Production in a p-doped substrate is particularly preferred ( Sub ) when used in a CMOS process. With this substrate ( Sub ) it is thus typically a semiconducting, single-crystalline, weakly doped substrate ( Sub ) of a first line type. In the case of CMOS technology, it is preferably a weakly p-doped substrate ( Sub ). The substrate ( Sub ) is possibly set to a defined potential through a substrate contact in such a way that the resulting PN junction between the well ( Well ) and the substrate ( Sub ) Is blocked. It should be pointed out here that it is irrelevant for the invention whether the tub described ( Well ) and the substrate ( Sub ) actually form a PN junction.

In this substrate ( Sub ) is typically a tub ( Well ) of a second conduction type, this second conduction type preferably being opposite to the first conduction type. The tub ( Well ) preferably extends from within the substrate ( Sub ) to the surface ( OBS) of the substrate. Is the substrate ( Sub ) p-doped, this tub is ( Well ) thus typically n-doped. Is the substrate ( Sub ) n-doped, this tub is ( Well ) typically p-doped. In the case of CMOS technology, this tub is ( Well ) preferably n-doped. Should in the case of a p-doped substrate ( Sub ) an N-channel MOS transistor can be implemented, this tub ( Well ) can also be omitted. Typically, however, an N-channel MOS transistor also has a p-doped well ( Well ). Should in the case of an n-doped substrate ( Sub ) a P-channel MOS transistor can be realized, this tub ( Well ) can also be omitted. Preferably the tub ( Well ) but trained. The tub ( Well ) contain further wells (Well _i ), which are typically one of the conductivity type of this first well ( Well ) have different and / or the same conduction type and possibly also differ in the doping. In the following, a single tub ( Well ) went out. The tub ( Well ) is possibly set to a defined potential through a tub contact in such a way that the resulting PN transition between tub ( Well ) and substrate ( Sub ) Is blocked. This is familiar to the person skilled in the art and is therefore not explained further here.

The MOS transistor according to the prior art is typically electrically isolated from other electronic components in the substrate ( Sub ) isolated. A particularly preferred lateral insulation is, for example, a shallow trench insulation ( STI ). Of course, other forms of insulation are also possible, such as LOCOS insulation with a field oxide.

In the tub ( Well ) are two highly doped contact areas, a first highly doped source contact area ( D _S + ) and a second highly doped drain contact area ( D _D + ), which work as a drain or source contact depending on the polarity of the electrical connection. These extend from inside the tub ( Well ) to the surface ( OBS ) of the substrate ( Sub ) in the vertical direction. In the lateral direction these are through the canal ( CHN ) Cut. The highly doped contact areas ( D _S + , D _D + ) are each through the PN junction between the respective highly doped contact area ( D _S + , D _D + ) and the tub ( Well ) preferably isolated. At this point it should be noted that manifold transistor structures are known, which differ in the shape and doping of the drain and source contact areas ( D _D + , D _S + ) differ. In this respect it can be, for example, that the highly doped drain contact area ( D _D + ) of the drain contact is doped and shaped differently than the highly doped source contact area ( D _s + ) of the source contact. In the example of the 1 to 4th the contacts are shown arbitrarily symmetrically to simplify the illustration. With regard to the modification according to the invention presented later, this is of no importance. In the 2 the second, right, highly doped contact area ( D _D + ) is called the drain or drain contact area and the first, left, highly doped contact area ( D _s + ) as the source or source contact area. The conductivity type of these highly doped contact areas ( D _D + , D _S + ) is the line type of the tub ( Well ), in which these highly doped contact areas lie, typically opposite. In the exemplary case of an N-channel transistor in a P-well ( Well ) or in a p-doped substrate ( Sub ) are these highly doped contact areas ( D _D + , D _S + ) therefore preferably highly n-doped. In the exemplary case of a P-channel transistor in an N-well ( Well ) or in an n-doped substrate ( Sub ) are these highly endowed contact areas ( D _D + , D _S + ) therefore preferably highly p-doped.

A gate oxide ( GOX ) or another suitable electrically insulating dielectric with the same function for electrically insulating the gate control electrode ( PLY ) of the MOS transistor opposite the channel ( CHN ) below the control electrode in the substrate ( Sub ) or in the tub ( Well ) is on the surface ( OBS ) of the substrate ( Sub ) educated. The gate oxide ( GOX ) in the area between the two highly doped contact areas ( D _D + , D _S + ) above the tub ( Well ) extending to the surface ( OBS ) of the substrate ( Sub ) extends.

This gate oxide ( GOX ) isolates the gate control electrode ( PLY ) of the transistor, for example in the form of the polysilicon gate ( PLY ) is formed by the channel that is under the gate oxide ( GOX ) in the tub ( Well ) between the two highly doped contact areas ( D _D + , D _S + ) lies.

In the exemplary transistor, the gate control electrode ( PLY ) of the transistor, the gate ( PLY ) by two non-conductive spacers, typically made of silicon oxides or silicon nitride ( SP1 , SP2 ) laterally isolated. In the same function are u. U. other insulating layers ( IOX2 ) on the control electrode ( PLY ) of the transistor.

The already mentioned polycrystalline polysilicon gate, the control electrode ( PLY ) of the transistor, is also preferably made of poly-crystalline silicon. This poly-silicon gate ( PLY ) is preferably provided with a doping of a fourth conductivity type, which is identical to either the first or the second conductivity type, for setting the threshold voltage and the behavior of the transistor. The dopant concentration can differ. The polysilicon gate, the control electrode ( PLY ) of the transistor, is through the first gate oxide ( GOX ) from the channel ( CHN ) in the substrate ( Sub ) or in the tub ( Well ) electrically isolated.

The side flanks of the gate package, consisting of the spacer ( SP1 , SP2 ) and the polysilicon gate ( PLY ) and the gate oxide ( GOX ) are for example by further insulation, for example SiN ( SiN ), electrically isolated.

Finally, a typical prior art transistor has a drain contact ( CD ) on. The drain contact ( CD ) makes the electrical contact to the highly doped drain contact area ( D _D + ), which is assigned to the drain and takes over the function of such a drain area in the further interconnection of the transistor with other electronic components.

Likewise, the transistor from the prior art has a source contact ( C_S ) on. The source contact ( C_S ) makes the electrical contact to the highly doped source contact area ( D _s + ), which is assigned to the source and takes over the function of a source region in the further interconnection of the transistor with other electronic components.

The gate contact ( C_G ) is the actual control contact of the transistor. The gate contact ( C_G ) makes the electrical contact to the polysilicon gate, the gate control electrode ( PLY ) of the transistor, in this exemplary case.

The previously described functional elements of a transistor from the prior art except for the first source contact area ( D _s + ) can be found both in the section along the line AA ' 1 who is in 2 is shown as a sectional view, as well as in the section along the line BB ' 1 who is in 3 is shown as a sectional view.

3 differs only in the bulk contact area ( BCA ), which is the source contact area ( D _s + ) electrically limited at its edges. Preferably, the bulk contact area ( BCA ) has a conductivity type that corresponds to the conductivity type of the adjacent source contact area ( D _s + ) is opposite. In the case of an N-channel transistor, the bulk contact areas ( BCA ) So preferably highly p-doped. In the case of a P-channel transistor, these are preferably high n- endowed. This means that the respective source contact area ( D _s + ) unable to reach the bulk contact area ( BCA ) Load carriers in the channel ( CHN ) to inject. This will open the channel under the control electrode ( PLY ) of the transistor in the area of the bulk contact areas ( BCA ) from the highly doped source contact area ( D _s + ) separated and a highly doped source contact ( C_S ) can by means of the associated highly doped source contact area ( D _S + ) no longer inject charge carriers into the channel. The bulk contact area ( BCA ) does not extend over the entire width of the MOS transistor or the source contact area ( D _S + ), since otherwise this source contact area ( D _s + ) yes no more charge carriers could inject into the channel. Rather, the bulk contact area ( BCA ) advantageously only on the sides or, if necessary, also at regular or irregular intervals within the source contact area ( D _S + ) designed so as not to significantly reduce the injection of charge carriers into the channel. The bulk contact area ( BCA ) thus limits the current emission through the source contact area ( D _s + ) in a lateral extension perpendicular to the initial current density vector. If the transistor is not to be operated symmetrically, an implantation in the form of a bulk contact area ( BCA ) at the respective edge of the source contact area ( D _s + ) sufficient.

5 illustrates the distribution of the current density in the switched-on state in such a transistor from the prior art in a sketchy manner. The hatched areas with little or no current density arise. The prior art transistor does not use the full width of its channel near the source contact areas ( D _s + ) out. This leads to an increased switch-on resistance (R _on ).

From the document forming the generic prior art US 2007/0 249 124 A1 a DMOS transistor is known whose on-resistance is increased.

Compared to the transistor according to the invention explained later, it requires an additional lithography step. The pamphlet found in this US 2007/0 249 124 A1 The transistor described requires an additional process sequence for its production compared to the claimed disclosure, which is usually not included in a conventional CMOS process sequence. This is a decisive disadvantage of the technical teaching of the US 2007/0 249 124 A1 . Inside the in the US 2007/0 249 124 A1 This additional so-called body implantation (reference symbols p +, 61 and 25th the US 2007/0 249 124 A1 ) into the already opened contact hole opening (reference numeral 37c of the US 2007/0 249 124 A1 ). Through this to manufacture the transistor according to the US 2007/0 249 124 A1 The process control used is a transistor according to the technical teaching of US 2007/0 249 124 A1 the change in doping in the area of the source-side contact hole (reference symbol 37c in 25th the US 2007/0 249 124 A1 ). This leads to the said increased on-resistance.

From the pamphlet US 2014/0 252 472 A1 a transistor on an SOI substrate is known. Such soi structures can in principle with transistor structures such as the US 2007/0 249 124 A1 be combined.

From the pamphlet DE 103 50 137 A1 a transistor with source and drain structures arranged offset is known.

Object of the invention

It is therefore the object of the invention to ensure an improved current density distribution in the switched-on state without the advantages of suppressing parasitic effects such as snap-back by the bulk contact areas ( BCA ) to give up. The number of lithography steps should not be increased here.

This object is achieved by a device according to claim 1.

Description of the invention

The idea according to the invention is based on a modification of the conductivity within the duct connection area directly at the bulk contact areas ( BCA ).

The LDD implantation area according to the invention serves this purpose ( LDD ). Such an LDD implantation area ( LDD ) is therefore applied to the bulk contact area ( BCA ) in the direction of the drain contact area ( D _D + ) placed. The LDD implantation area according to the invention ( LDD ) is preferably of the same conductivity type as the highly doped first source contact area ( D _s + ) and of the opposite conductivity type to the associated bulk contact area ( BCA ) belonging to the LDD area ( LDD ) on one side or at least on the side facing the drain contact area ( D _D + ) is affected. This will open the channel under the control electrode ( PLY ) of the transistor, which in the area of the section line BB 'through the implantation of the bulk contact area ( BCA ) from the highly doped source contact area ( D _s + ) is separated from the injection area ( INJ ) of the highly doped source channel area serving as the source ( D _S + ) then connected again with low resistance when the LDD Implantation to a very high doping level in the LDD implantation area ( LDD ) and this area is therefore particularly low-resistance. This reduces the current flow under the control electrode ( PLY ) on the source side of the transistor along the width already homogenized over a shorter distance to the drain and the switch-on resistance of the transistor (R _on ) drops compared to a transistor according to the prior art. The current flow therefore now also includes the in 5 areas of the canal marked as weakly energized by hatching ( CHN ). Since this is only in the area of the bulk contact area ( BCA ) is an additional benefit, the LDD implantation area needs ( LDD ) do not necessarily extend over the entire width of the source-side highly doped source contact area ( D _s + ) to extend. The LDD implantation area ( LDD ) can therefore, like the bulk contact area ( BCA ), even only at the points of the source contact area ( D _s + ) where the current density distribution in the direction of the drain contact area ( D _D + ) after focusing the injection in this direction should be pulled back in width. The bulk contact area ( BCA ) thus limits the current emission through the source contact area ( D _s + ) in a lateral extension perpendicular to the initial current density vector. If the transistor is not to be operated symmetrically, an LDD implantation on the source contact area ( D _s + ) sufficient. The bulk contact area ( BCA ) thus prevents the ability of the source contact ( D _s + ) for injecting the charge carriers typically at its edges, while the LDD implantation area ( LDD ) the current density is optimally distributed in width within the transistor.

Figure list

• 6th 6th shows a relevant exemplary MOS transistor according to the invention in a schematic manner outlined from above.
• 7th shows an exemplary schematic section through the transistor according to the invention in FIG 6th along the in the 6th sketched line A-A '.
• 8th shows an exemplary schematic section through the transistor according to the invention in FIG 6th along the in the 6th sketched line B-B '.
• 9 shows an exemplary MOS transistor according to the invention in a schematic manner sketched from above with sketched current paths.

The 6th essentially corresponds to 1 . It differs in the drawn LDD implantation ( LDD ). As in 1 the two relevant cutting lines (A-A ', B-B') are shown again. These are in the two 7th and 8th shown roughly schematically.

7th corresponds to the 2 . In this section (A-A '), the transistor according to the invention typically does not differ from the prior art or only differs from the prior art due to the LDD implantation according to the invention (LLDI).

8th shows an exemplary form of the LDD area ( LDD ), the now injection of charge carriers from the highly doped first source contact area ( D _S + ) in the area of the cut (B-B '), since the bulk connection doping ( BCA ) already ends in front of the channel (e.g. in the area of the spacer) and thus an electrical connection via the LDD area on the channel side ( LDD ) and source channel area ( D _s + ) to source contact ( C_S ) given is.

In this example, the LDD area is ( LDD ) immediately behind the bulk contact area ( BCA ) in the direction of the drain contact area ( D _D + ). This is not absolutely necessary and is therefore only an example here.

6th shows an exemplary location of the LDD area ( LDD ) in the connecting line between the bulk contact areas ( BCA ).

In 9 is the deformation of the current density path through the relatively highly doped and therefore very well conductive LDD area ( LDD ) outlined. In the 5 Areas marked with hatched areas through which there is no flow are now also detected by the current flow, thereby activating additional current-carrying areas. Thus, the on-resistance (R _on ) drops in the linear operating range of the transistor and the current also increases in the saturation range.

The MOS transistor according to the invention is thus a MOS transistor which is manufactured in a substrate or a doped well with a second conductivity type. The substrate and the structures made in it have a surface ( OBS ). In the context of this disclosure, the surface of the substrate is understood to be the interface between the monocrystalline area of the component and other, for example polycrystalline or amorphous areas. In this respect, the MOS transistor also has components above the surface defined in this way ( OBS ), for example the mostly polycrystalline control electrode ( PLY ) of the transistor.

The MOS transistor according to the invention has a second highly doped drain contact area ( D _D + ) from the first type of conduction to the surface (OBS ) is sufficient, as well as a first highly doped source contact area ( D _s + ) of the first conductivity type, which is from the second drain contact area ( D _D + ) through a duct area ( CHN ) and also to the surface ( OBS ) enough. It is in the area of the canal ( CHN ) the surface ( OBS ) of the substrate ( Sub ) and / or the tub ( Well ) with an electrically insulating dielectric ( GOX , IOX2 , SP1 , SP2 ) covered. At least one first straight or curved connecting line (B-B ') between the second drain contact area ( D _D + ) and the first source contact area ( D _s + ) can be constructed. Along this at least one first straight or curved, crossing-free connecting line (B-B ') between the second drain contact area ( D _D + ) and the first source contact area ( D _s + ) this first connecting line (B-B ') intersects at least one highly doped bulk contact area ( BCA ). This highly doped bulk contact area ( BCA ) has a second conductivity type which is opposite to the first conductivity type. It is the highly doped first source contact area ( D _s + ) usually directly adjacent and extends to the surface ( OBS ). Furthermore, at least one second straight or curved, crossing-free connecting line (A-A ') can be created between the second drain contact area ( D _D + ) and the first source contact area (DS +). This second straight or curved connecting line (A-A ') now intersects between the second drain contact area ( D _D + ) and the first source contact area ( D _s + ) this at least one highly doped bulk contact area ( BCA ), which has a second conductivity type which corresponds to the first conductivity type of the source contact region ( D _s + ) is opposite, not.

The MOS transistor according to the invention differs from the prior art in that along at least the first straight or curved connecting line (B-B ') between the second drain contact region ( D _D + ) and the first source contact area ( D _s + ) this first connecting line (B-B ') at least the highly doped bulk contact area ( BCA ) and, compared to the state of the art, also a highly doped LDD area ( LDD ), which now has a first conductivity type corresponding to that of the first source contact area ( D _s + ) and the highly doped bulk contact area ( BCA ) is directly adjacent and electrically connected to the source contact area ( D _S + ) is connected, in particular this is directly adjacent. Thus, according to the invention, the bulk contact area ( BCA ) typically but not necessarily between the LDD area ( LDD ) and the adjacent highly doped source contact area ( D _s + ) The LDD area ( LDD ) is preferably not in any other LDD area ( LDD ) which is intersected by the first connecting line (B-B ').

It can be the case that along at least this second straight or curved, intersection-free connecting line (A-A ') between the second drain contact area ( D _D + ) and the first source contact area ( D _s + ) this second connecting line (A-A ') this at least one LDD area ( LDD ), which has a first conductivity type, does not intersect. In 6th there is shown a case where the connecting line intersects.

Advantages of the invention

The switch-on resistance (R _on ) of the transistor according to the invention is now lower than the switch-on resistance of a transistor from the prior art, since the entire width of the transistor is better utilized.

List of reference symbols

A.

arbitrary starting point of the second connecting line from a first highly doped source contact area ( D _s + ) to a second highly doped drain contact area ( D _D + ).

A '

arbitrary end point of the second connecting line from a first highly doped source contact area ( D _s + ) to a second highly doped drain contact area ( D _D + ).

B.

arbitrary starting point of the first connection line from a first highly doped source contact area ( D _S + ) to a second highly doped drain contact area ( D _D + ).

B '

arbitrary end point of the first connecting line from a first highly doped source contact area ( D _s + ) to a second highly doped drain contact area ( D _D + ).

BCA

Bulk contact area. One highly doped bulk contact area each delimits the highly doped source contact area ( D _s + ) on both edges. It is of the opposite conductivity type as the respective highly doped source contact area ( D _S + ). In this way the possibly developable channel ( CHN ) under the gate control electrode ( PLY ) from the highly doped source contact area ( D _s + ) separated and a highly doped source contact ( C_S ) can by means of the associated highly doped source contact area ( D _s + ) no more load carriers in the channel ( CHN ) in the area of the bulk contact area ( BCA ) inject. Therefore the bulk contact area does not extend over the entire width of the source contact area ( D _S + ). Rather, the bulk contact area is typically only on the sides of the source contact area ( D _s + ) designed to inject the current density distribution in the direction of the drain contact area ( D _D + ) to focus. The current density in the injection area cannot. The bulk contact area ( BCA ) thus limits the current emission through the source contact area ( D _s + ) in a lateral extension perpendicular to the initial current density vector. If the transistor is not to be operated symmetrically, implantation of the bulk contact areas ( BCA ) at the edges of the source contact area ( D _s + ) sufficient. The bulk contact area ( BCA ) thus prevents the ability of the source contact area ( D _s + ) for injecting the charge carriers in its area, typically at its edges.

BF

Contact area between bulk contact area ( BCA ) and LDD area ( LDD ) (please refer 8th )

C_B

Bulk contact. The bulk contact typically provides electrical contact to the tub ( Well ) or the substrate ( Sub ) here. In the case of the invention, this is used for limiting the current injection for through the source contact area ( D _s + ) used. If there is no electrical connection between the bulk contact area and the substrate ( Sub ) or the tub ( Well ) arises in a transistor according to the invention, in embodiments of the invention only one contact to the bulk contact area ( BCA ) getting produced. The advantage of this type of wells or substrate contact is a particularly compact design.

CD

Drain contact. The drain contact provides the electrical contact to the highly doped contact area ( D _D + ), which is assigned to the drain and takes over its function in the further interconnection of the transistor with other electronic components.

C_G

Gate contact. The gate contact provides the electrical contact to the polysilicon gate ( PLY ), the gate control electrode ( PLY ) of the transistor, in this exemplary case.

C_S

Source contact. The source contact makes the electrical contact to the highly doped source contact area ( D _s + ), which is assigned to the source and takes over its function in the further interconnection of the transistor with other electronic components.

CHN

Canal area. The channel region lies between the highly doped source contact region ( D _s + ) and the highly doped drain contact area ( D _D + ). With a suitable bias voltage, the gate control electrode ( PLY ) of the transistor the conductive channel of the transistor.

D _D +

second highly doped drain contact region which then forms the drain of the transistor according to the invention or a transistor from the prior art without the modification according to the invention. The conductivity type of this highly doped drain contact area is that of the well ( Well ), in which this highly doped drain contact area lies, opposite. In the exemplary case of an N-channel transistor in a P-well ( Well ) or in a p-doped substrate ( Sub ) this highly doped drain contact area is therefore highly n-doped. In the exemplary case of a P-channel transistor in an N-well ( Well ) or in an n-doped substrate ( Sub ) this highly doped drain contact area is therefore highly p-doped.

D _S +

first highly doped source contact region which then forms the source of the transistor according to the invention or of a transistor from the prior art without the modification according to the invention. The conductivity type of this highly doped source contact area is that of the well ( Well ), in which this highly doped source contact area lies, opposite. In the exemplary case of an N-channel transistor in a P-well ( Well ) or in a p-doped substrate ( Sub ) this highly doped source contact area is therefore highly n-doped. In the exemplary case of a P-channel transistor in an N-well ( Well ) or in an n-doped substrate ( Sub ) this highly doped source contact area is therefore highly p-doped.

GOX

Gate oxide or other dielectric with the same function for electrical insulation of the gate control electrode ( PLY ) of the transistor opposite the channel ( CHN ) below the control electrode ( PLY ) in the substrate ( Sub ) or in the tub ( Well ).

INJ

Injection area of the source contact area ( D _S + ). The width over which the source contact area ( D _s + ) into the channel ( CHN ) Can inject charge carriers is through one or more bulk contact areas ( BCA ) to the injection area of the source contact area ( D _s + ) limited. This is preferably done in such a way that the two ends of the injection area are not aligned with the two edges of the channel that are parallel to the direction of flow, but rather lie between these two. The source contact area ( D _s + ) is therefore only able to transfer charge carriers into the channel ( CHN ) to inject. Due to the adjacent bulk contact areas ( BCA ) its length and position is determined.

IOX2

insulating oxide or other dielectric with the same function for electrical insulation of the gate control electrode ( PLY ) of the transistor opposite the channel ( CHN ) below the gate control electrode ( PLY ) of the transistor in the substrate ( Sub ) or in the tub ( Well ) and towards the contact areas ( D _D + , D _S + ).

LDD

LDD implantation area according to the invention. The LDD implantation area is tangent on one side in the direction of the drain contact area ( D _D + ) a bulk contact area ( BCA ), which in turn is the highly doped source contact area ( D _s + ) in an edge area of this source contact area ( D _S + ) limited. The inventive LDD implantation area is of the same conductivity type as the respective highly doped source contact area ( D _s + ) and of the opposite conductivity type to the associated bulk contact area ( BCA ) which is limited or affected on one side by the respective LDD area. As a result, the channel that can possibly be formed, which is under the gate control electrode ( PLY ) of the transistor due to the implantation of the bulk contact area ( BCA ) from the highly doped source contact area ( D _s + ) in the area of the bulk contact area ( BCA ) is separated from the injection area ( INJ ) of the highly doped source contact area serving as the source ( D _s + ) then connected again with low resistance when the LDD implantation leads to very high doping in the LDD area and this area is therefore particularly low-resistance. This will reduce the current flow under the gate control contact ( PLY ) of the transistor and the switch-on resistance of the transistor (R _on ) drops compared to a transistor according to the prior art. Since this is only in the area of the bulk contact area ( BCA ) is desired, can the LDD implantation area also possibly not over the entire width of the source contact area ( D _s + ) extend across the canal. The LDD implantation area, like the bulk contact area, can therefore only be used at the points of the source contact area ( D _s + ), where the bulk contact area is located, in order to increase the current density distribution in the direction of the drain contact area ( D _D + ) after focusing the injection in this direction again in width. The bulk contact area ( BCA ) thus limits the current emission through the source contact area ( D _s + ) in a lateral extension perpendicular to the initial current density vector. If the transistor is not to be operated symmetrically, an LDD implantation on the source-side contact area ( D _s + ) sufficient. If the transistor is to be operated with reverse polarity with regard to drain and source, further bulk contact areas must also be on the drain side ( BCA ) and a corresponding LDD implantation area can be provided. The bulk contact area ( BCA ) thus prevents the ability of the source contact area ( D _S + ) for injecting the charge carriers typically at their edges.

OBS

Surface of the substrate ( Sub ). This also refers to the surface in the areas where the tub ( Well ) and / or the highly doped contacts (D +) extend to the surface. What is meant by the surface in the sense of this disclosure is in 4th outlined. There the surface is shown as a bold line in the drawing of the 2 registered. This definition applies correspondingly to all other drawings in this disclosure. In principle, in the sense of this disclosure, the surface is the planar structure up to which the monocrystalline structure of the substrate crystal can be assumed to still exist. Doped areas are therefore below the surface of the substrate ( Sub ), while oxidized areas are above.

OX

insulating layer. The insulating layer insulates the substrate or the tub ( Well / Sub ) of the transistor electrically compared to the base substrate ( Sub2 ) if the transistor is manufactured using SOI technology.

SP1

source-side insulating spacer, typically made of silicon oxide or silicon nitride.

PLY

Poly-silicon gate, which is preferably made of poly-crystalline silicon. In order to set the threshold voltage and the behavior of the transistor, the polysilicon gate can be provided with a doping of a fourth conductivity type which is identical to either the first or the second conductivity type. The second poly-silicon gate is replaced by the first gate oxide ( GOX ) from the channel ( CHN ) in the substrate (Sub ) or in the tub ( Well ) electrically isolated. It serves as the gate control electrode of the transistor.

SP2

insulating spacer on the drain side, typically made of silicon oxide or silicon nitride.

SPK

source-side poly edge (PK) S ₁ first intersection point between the first perpendicular (E-E ') and the third connecting line (C-C').

S ₂

second intersection between the second vertical line (F-F ') and the third connecting line (C-C').

S ₃

third point of intersection between the third perpendicular (G-G ') and the third connecting line (C-C').

S _d

Point located within the highly doped source contact area ( D _s + ) to which the bulk contact area ( BCA ), which intersects the first perpendicular (E-E '), is adjacent and lies on the third connecting line (C-C'). In many, but not all applications, this point can be used as the focus of the highly doped source contact area ( D _s + ) are accepted.

SiN

The side flanks of the gate package, consisting of the spacer areas ( SP1 , SP2 ) and the polysilicon gate ( PLY ) and the gate oxide ( GOX ) and the insulating oxide ( IOX2 ) are through further insulation, for example SiN , electrically isolated.

SOI

Silicon On Insulator. It is a semiconductor technology in which the well (Well2), in which the transistor is manufactured, is placed on an electrically insulating layer ( OX ) lies.

SSSK

source-side edge ( SSSK ) of the source-side spacer ( SP1 )

STI

Shallow trench isolation for isolating the transistor from other circuit elements of the integrated circuit in the lateral direction. Of course, other forms of insulation are also possible, such as LOCOS insulation with a field oxide.

Sub

semiconducting, monocrystalline, weakly doped substrate of a first conductivity type. In the case of CMOS technology, it is preferably a weakly p-doped substrate.

Sub2

typically semiconducting, monocrystalline, lightly doped back side carrier substrate that the circuits that are in the actual substrate ( Sub ) or in the tub ( Well ) are made, mechanically bears. Typically it is a monocrystalline, semiconducting substrate that has a defined doping and crystal orientation.

Well

in the substrate ( Sub ) formed well of a second conduction type, which is preferably opposite to the first conduction type. Is the substrate ( Sub ) p-doped, this tub is n-doped. Is the substrate ( Sub ) n-doped, this tub is p-doped. In the case of CMOS technology, this well is preferably weakly n-doped. Should in the case of a p-doped substrate ( Sub ) an N-channel MOS transistor can be realized, this tub can be omitted. Should in the case of an n-doped substrate ( Sub ) a P-channel MOS transistor can be realized, this tub can also be omitted. However, the tub is preferably formed. The well can also contain further wells, have a conduction type that is different and / or the same from this first well, and possibly also differ in terms of doping. This is familiar to the person skilled in the art and is therefore not considered further here.

Well / Sub2

Substrate or well of the transistor if it is manufactured using SOI technology. The substrate or the well of the transistor in such an SOI technology is preferably isolated from other components on the same substrate by means of isolation techniques (e.g. STI ) laterally isolated.

Claims (4)

MOS transistor in a substrate (sub) or a doped well (well) with a second conductivity type, which have a surface (OBS), the transistor having a second highly doped drain contact region (DD +) of a first conductivity type that extends to the surface (OBS), and wherein the transistor has a first highly doped source contact region (DS +) of the first conductivity type, which is spaced from the second drain contact region (DD +) by a channel region (CHN) and extends to the surface (OBS), and - where in the area of the channel area (CHN) the surface (OBS) of the substrate (Sub) and / or the well (well) is covered with an electrically insulating dielectric (GOX, IOX2) and - wherein along at least one first straight or curved connecting line (B-B ') between the first source contact region (D _s +) and the second drain contact region (D _D +) this first connecting line has at least one highly doped bulk contact region (BCA) intersects, which has the second conductivity type and is directly adjacent to the highly doped source contact region (D _s +) and extends to the surface (OBS), and - along at least one second straight or curved connecting line (A-A ') between the first Source contact region (D _s +) and the second drain contact region (D _D +) this second connecting line does not intersect this at least one highly doped bulk contact region (BCA), which has the second conductivity type, characterized in that - longitudinally at least the first straight or curved connecting line (B-B ') between the first source contact region (D _s +) and the second drain contact region (D _D +), this first connecting line at least the ho ch doped bulk contact area (BCA) and also intersects a highly doped LDD area (LDD) that has the first conductivity type and is directly adjacent to the highly doped bulk contact area (BCA), and that the highly doped bulk contact area (BCA) between the LDD region (LDD) and the adjacent highly doped source contact region (D _s +) and - that the highly doped bulk contact region (BCA) has a contact surface (BF) with the LDD region (LDD) and - That said LDD implantation area (LDD) to the highly doped drain contact area (D _D +) or another bulk contact area (BCA), which in particular can be adjacent to the highly doped drain contact area (D _D +), or a is not adjacent to another LDD region intersected by the first connecting line (B-B '). - that this contact surface (BF) - lies in the drain direction beyond the source-side edge (SSSK) of a source-side spacer (SP1) or - in the drain direction beyond a source-side poly edge (SPK) or at the source side poly edge (SPK) lies MOS transistor after Claim 1 - wherein along at least the second straight or curved connecting line (A-A ') between the first source contact region (D _S +) and the second drain contact region (D _D +) this second connecting line (A-A') has this at least one LDD region (LDD) having the first conductivity type does not intersect. MOS transistor after Claim 1 or 2 - wherein the transistor is manufactured on an SOI substrate and the substrate (Sub) or the well (well) of the transistor is electrically connected via a bulk contact (C_B) and - wherein the bulk contact (C_B) with a highly doped Bulk contact area (BCA) is electrically connected and - wherein the highly doped bulk contact area (BCA) is at an edge of the source contact area (D _s +) and - wherein the highly doped bulk contact area (BCA) also has an edge that is flush with one edge of the channel (CHN). MOS transistor according to one of the preceding Claims 1 to 3 - The transistor is manufactured on an SOI substrate and the substrate (sub) or the well (well) of the transistor is electrically connected via a bulk contact (C_B) and - the bulk contact (C_B) with a high doped bulk contact area (BCA) is electrically connected and - wherein the highly doped bulk contact area (BCA) is at an edge of the source contact area (D _S +) and adjacent to this source contact area (D _S +) and - wherein the highly doped bulk contact region (BCA) also has an edge which is aligned with an edge of the channel (CHN) and - the highly doped bulk contact region (BCA) having the width of an injection region (INJ) of the source contact region (D _S +) limited on at least one side so that the end of the injection area (INJ) does not align with the edges of the channel (CHN), which are parallel to the direction of flow in the channel (CHN), and lies between them.

Images