DE102014223441B4 - Error detection for electrical networks - Google Patents

Abstract

Embodiments of the present invention provide a device for fault detection in an AC electrical network. The device comprises a dq transformation device which is designed to generate a q component for at least one phase using a single-phase transformation. Furthermore, an evaluation unit which is designed to detect a voltage deviation in the electrical AC voltage network as a function of the q component and to output an error signal if there is a voltage deviation.

Description

Embodiments of the present invention relate to a device for fault detection in an electrical alternating voltage network. Further exemplary embodiments relate to a method for error detection in an electrical alternating voltage network.

The present invention thus describes a concept for the detection of faults in electrical networks. The concept can z. B. in inverter-coupled energy supply systems such as solar inverters, wind turbines or combined heat and power plants (CHP) can be used to detect network errors. Furthermore, the concept of dynamic voltage maintenance can be used (eg fault ride-through). The concept is characterized by high dynamics, and can be used for power and voltage dips.

Mains services for voltage maintenance (voltage dip) in electrical networks (eg TransmissionCode) are specified in the BDEW guideline (see reference [1]) and VDE-AR-N 4105 (see reference [2]). In power converters in the medium voltage, the voltage support in a voltage dip by feeding reactive power to the state of the art. There are approaches to transfer this behavior to the low voltage. Amendments to reference [2] will be discussed in expert panels.

The voltage dip occurs unpredictably and, depending on the network condition and error removal, results in large short-circuit currents. So that the entire generation power does not have to be separated directly from the faulty network section, an attempt is made to "drive through" the error. Both the detection of the error and corresponding measures must therefore take place as quickly as possible.

The task of error detection is to display a network error as quickly as possible and, if necessary, also to determine the type of error (eg symmetrical or asymmetrical). As symmetrical errors network errors are called, which occur simultaneously on all phases. Unbalanced errors affect one or more phases. As a network error voltage dips are understood in this document, the z. B. may arise as a result of short circuits or ground faults. It is Z. B. for the dynamic voltage maintenance in addition to the pure detection of the error just as important to detect the depth of the voltage drop as quickly as possible (final value).

In contrast to, for example, synchronous generators, modern power electronics in power converters can not withstand short-term overcurrents without destruction. Therefore, overcurrent protection by comparators is usually implemented on the hardware side. Such a protective circuit is used in many devices, for example, with modern power electronics even in the detection of a network failure to support in order to protect the power converter. If one is able to do without comparators on account of the topology and a quick fault detection during the voltage dip, costs can be reduced in larger series, with the same degree of safety. In addition, can be dispensed with a subsequent unlocking the power electronics, which increases the responsiveness to the situation.

mit dem wählbarem Parameter T_end. Der übliche Effektivwert wird über eine volle Periode ermittelt, womit sich bei 50 Hz T_end = 20 ms ergibt. Somit benötigt eine volle Bestimmung des Effektivwertes eine gesamte Netzperiode.A simple and intuitive method for error detection is the calculation and monitoring of the moving effective value of the mains voltage:

with the selectable parameter T _end . The usual rms value is determined over a full period, giving T _end = 20 ms at 50 Hz. Thus, a full determination of the RMS value requires an entire network period.

The half-wave rms value (the idea and the term half-cycle rms value are taken from the FGW TR3) is calculated over half a grid period (T _end = 10 ms) and is thus twice as fast. The error evaluation can then z. B. via a threshold comparison with or without hysteresis.

The implementation of the half-wave rms value is simple and very robust (averaging eliminates high-frequency components such as harmonics and noise). Symmetrical and unbalanced errors are recognized equally well. However, the dynamics of the process is relatively low, resulting in a longer reaction time.

The WO 2014/162 156 A describes an error detection in an electrical machine in which the measured voltage and current values are transformed by Clarke transformations. Based on the transformed values, an instantaneous power value is determined. An error is detected based on a harmonic analysis of the current power value in a dq0 reference frame.

Object of the present invention is a rapid detection of symmetrical and unbalanced errors. If the error edges are sufficiently steep, the detection should only be one sampling step need. The concept for error detection should be cost-effective and have high dynamics. Furthermore, the robustness of the method should be adjustable with respect to the dynamics with additional degrees of freedom.

This object is achieved by a device according to claim 1, a method according to claim 19, and a computer program according to claim 20.

Embodiments of the present invention provide a device for fault detection in an AC electrical network. The device comprises a dq transformation device which is designed to generate a q component for at least one phase using a single-phase transformation. Furthermore, an evaluation unit which is designed to detect a voltage deviation in the electrical AC voltage network as a function of the q-component and to output an error signal if there is a sufficiently large voltage deviation. A phase retarder is provided on at least one of the phases, the phase retarder being designed to detect a respective input signal of the respective phase and to output a respective signal which is delayed by a phase angle of 90 ° with respect to the respective input signal. Furthermore, the dq transformation device is designed to receive the respective input signal and the respective delayed signal. By the phase retarder, the delayed signal of the same phase is generated from the input signal of a phase of the electrical alternating voltage network. The input signal and the delayed signal are used to perform a dq transformation, also referred to as a park transform.

The idea of sdq monitoring (single-phase dq monitoring) is to use the extremely fast response in the q component of the line voltage to a voltage dip. In order to be able to extend the process to all voltage errors, a separate sdq transformation (single-phase dq transformation) is carried out for each phase. Of the six indicator voltages thus obtained in a three-phase electrical network (three d-components and three q-components), only the three q-components are used to detect an error by means of a threshold comparison. Thus, the type of fault (symmetric or unbalanced) can be accurately detected.

In a preferred embodiment, the electrical AC voltage network is designed as a multi-phase electrical network. Electrical alternating voltage grids are designed, among other things, for the more efficient energy transfer in multi-phase. Furthermore, for example, drives such as electric motors can be started or started more reliably with a multi-phase electrical network.

In a further preferred embodiment, the phase retarder is designed as a generalized second order integrator (SOGI). By a generalized second-order integrator, a delayed signal with a phase shift of 90 ° to the respective input signal can be generated for each of the phases.

In a preferred embodiment, the generalized second order integrator is time discrete. In a discrete-time circuit configuration, the signals can be processed digitally, for example by means of a digital signal processor. Digital signal processors are often more cost effective in complex circuit design than the construction of an analog or discrete circuit.

In a preferred embodiment, the generalized second-order integrator is formed continuous-time. A continuous-time circuit design can be done with analog circuit elements. This reduces the programming effort for a phase retarder. In addition, a robust construction of the circuit is possible.

In a further preferred embodiment, the device additionally comprises a Clarke transformation device, which is designed to generate α components and β components from a three-phase electrical network. A Clarke transformation in the Clarke Transformer converts the three-phase quantities (current, voltage) of an electrical network of a three-phase machine into a simpler two-axis coordinate system with the axes α and β. The α-component shows the real part in the complex plane, while the β-component shows the imaginary part.

In a preferred embodiment, the device additionally includes a phase locked loop (PLL) configured to receive the α component and the β component from the Clark transform means and a sinusoidal signal tuned to the α component and the β component and to generate a cosine signal phase-shifted by 90 ° with respect to the sine signal. For the dq transformation, a sinusoidal signal generated from the α component and β component and a cosine signal phase-shifted by 90 ° with respect to the sine signal are required. The sine signal and the cosine signal can be generated by the phase locked loop. The phase shift between the sine signal and The cosine signal can have a tolerance of about ± 5 °.

In a further preferred embodiment, a first signal delay is designed to generate a sinusoidal signal delayed by 120 ° with respect to the sine signal and a cosine signal delayed by 120 ° with respect to the cosine signal. Furthermore, a second signal delay is designed to generate a sinusoidal signal delayed by 240 ° with respect to the sine signal and a cosine signal delayed by 240 ° with respect to the cosine signal. The sine and cosine signals delayed by the first and second signal delays are also needed for the dq transformation. The phase shift between the sinusoidal signal delayed by 120 ° or by 240 ° to the cosine signal delayed by 120 ° or by 240 ° can likewise have a tolerance of approximately ± 5 °. A balanced three-phase system (120 °) with the amplitude A can be generated in different ways, eg. Sin (ωt + 120 °) etc.

In a preferred embodiment, the apparatus comprises three phase-locked loops, each of the phase-locked loops being configured to receive the α-component and the β-component from the Clark transformation device and for each of the phases to be input to the α-component and the β-component. Component to generate tuned sinusoidal signal and a relation to the sine signal phase-shifted by 90 ° cosine signal, each of the three phase locked loops generates the respective sine signal and the respective cosine signal of another phase. Furthermore, a phase-locked loop of the α-component and the β-component for each of the phases can generate a sinusoidal signal tuned to the α-component and the β-component and a cosine signal phase-shifted by 90 ° with respect to the sinusoidal signal. By generating the sine signal and the cosine signal for each of the phases in an electrical network, the signal delayers delaying the sine signal and the cosine signal can be dispensed with in addition. The phase shift between each of the sinusoidal signals and the cosine signal phase-shifted to 90 ° can in turn have a tolerance of about ± 5 °.

In a further preferred embodiment, the q-component comprises a q-voltage. The q-voltage can be monitored inexpensively to a threshold value by simple means such as a comparator.

In a preferred embodiment, the dq transformation device is formed with an input signal, a delayed signal which is tuned to the input signal, as well as with a sine signal sin (ωt) and a cosine signal cos (ωt) which are phase-shifted by 90 ° with respect to the sine signal is to perform a park transformation for each of the phases, using the park transformation through the equation u _q = cos (ωt) u _r + sin (ωt) u _i is defined. The parameters u _r and u _i are outputs of a 90 ° shift device (Clark transform device). The 90 ° phase shift between the sinusoidal signals and the cosine signals can have a tolerance of about ± 5 °. The park transformation generates the q-component or the q-voltage. Depending on the value of the q-voltage, conclusions can be drawn about the condition of the electrical alternating voltage network and thus about possible faults in the electrical alternating voltage network.

In a preferred embodiment, the evaluation device is designed to compare the q-component with at least one threshold value and to output an error signal if the threshold value is exceeded or undershot. A threshold defines a value for the q component. Until this threshold value is reached, it can be assumed that there is no fault in the electrical alternating voltage network and the electrical alternating voltage network is thus faultless. When exceeding or falling below the threshold value, it can be assumed that the electrical AC voltage network has an error.

In a further preferred embodiment, the evaluation device is designed to output an error signal if the q component exceeds or falls below the threshold value in at least one of the phases in the electrical alternating voltage network. By issuing an error signal, measures can be taken, for example, to protect the components present in the electrical alternating voltage network. Furthermore, measures can also be taken to isolate the component causing the fault. Furthermore, persons can be informed about the state of the electrical alternating voltage network.

In a preferred embodiment, the evaluation device is designed to determine whether a symmetrical or an asymmetrical network fault is present or if the evaluation device is designed to determine a final value of the voltage deviation. Furthermore, the evaluation device is designed to output an error signal, which depends on the type of error. By the fastest possible determination of the type of error or the final value of the voltage deviation, which is caused by the error can For example, a possible source of error can be determined quickly. As a result, measures for protecting further components in the electrical alternating voltage network can again be taken very quickly. Also can be prevented by a fast and precise error determination further damage to the component causing the error. This reduces the consequential costs of the error.

In a further preferred embodiment of the apparatus for a nominal frequency of 50 is formed 60 or 16 _^2/3 Hz. Furthermore, the device can be designed to be adaptive to frequency. The device may be designed with its components at a specific nominal frequency in order to be operated at corresponding frequencies and to output an error signal in the event of deviations from the nominal frequency which exceeds a certain tolerance. For example, an error signal may be output if the device detects a frequency deviation from the nominal frequency greater than ± 1% or ± 5%. By adapting the device to a specific nominal frequency, a simple circuit construction with lower-cost components is possible. Frequency-adaptive circuitry allows use of the device in various electrical networks or in networks of fluctuating network frequency. In embodiments, it is also possible to operate the device adapted to the nominal frequency, for example, by preselecting the nominal frequency.

Embodiments of the present invention will be explained with reference to the accompanying figures. Show it:

1 a schematic representation of a first embodiment of a device according to the invention;

2 a schematic representation of another embodiment of the device according to the invention;

3 a simulation scheme of an embodiment;

4 a schematic representation of a generalized second order integrator integrator (SOGI);

5 a schematic representation of a filter in which the SOGI is integrable;

6 a Bode diagram of the SOGI filter;

7a the voltage curve of a symmetrical fault in a three-phase electrical network;

7b a network monitor with a dual generalized second order integrator (DSOGI);

7c a half-period RMS network monitoring;

7d the voltage curve of the symmetrical fault in a three-phase electrical network as in 7a shown;

7e a network monitoring with a dq monitoring;

7f a network monitoring with a single-phase dq monitoring according to the invention;

8a the voltage curve of an unbalanced fault in a three-phase electrical network;

8b a network monitor with a dual generalized second order integrator (DSOGI);

8c a half-period RMS network monitoring;

8d the voltage curve of the unbalanced fault in a three-phase electrical network as in 8a shown;

8e a network monitoring with a dq monitoring;

8f a network monitoring with a single-phase dq monitoring according to the invention;

In the following description of the embodiments of the invention, the same or equivalent elements in the figures are given the same reference numerals, so that their description in the different embodiments is interchangeable.

1 shows a schematic representation of a device 10 for fault detection in an electrical alternating voltage network. The electrical alternating voltage network can comprise several phases. Preferably, the multiphase electrical network comprises as in 1 shown three phases. The device 10 but can also be designed to detect faults in an electrical network with one, two, four, five or more phases. In the case of several phases, the phases can have a phase angle of the same size relative to each other. That is, the value of the phase angle is 360 ° divided by the number of phases of the electric network. For a three-phase electrical network, the phase angle between the three phases is 120 ° each.

An alternating voltage network is an electrical network which outputs an alternating voltage to an electrical consumer (eg motor, heating, lighting, etc.). As an alternating voltage network, an alternating current network or, generally speaking, an electrical network with an electrical alternating quantity can also be designated.

An error can be a deviation from the normal voltage value. In this case, the voltage may assume a value above the normal voltage value or a value below the normal voltage value. For example, a normal voltage value may correspond to the rms value of 230V. Depending on network normalization, a deviation of ± 10% can be considered as a line voltage tolerance, ie. H. no error is output if the voltage value is within the mains voltage tolerance. The presence of an error can be assumed, for example, if the rms value of the voltage value is exceeded by 15% or 15%.

The device comprises a dq transformation device which is designed to generate a q component for at least one of the phases using a single-phase transformation. The in the 1 The device shown has three dq transformation devices 12a . 12b . 12c on, with each of the dq transformation facilities 12a . 12b . 12c one of the three phases transformed. The dq transformation facilities 12a . 12b . 12c are trained to perform a park transformation. In this case, the quantities (current or voltage) of an electrical network are converted into a two-axis coordinate system with the components d and q. The d and q components can rotate in the stationary case with the rotor of a three-phase machine. The value pair d and q represents time-constant quantities. The value d can indicate the magnetic flux density of the magnetic field strength. The value q may be an expression for the torque generated by the rotor.

The q component includes, for example, the value of an analog electrical voltage or an analog electrical current. Preferably, the q-component is a q-voltage. The q component can also be a digital signal instead of an analog signal and thus be present as a bit combination. A bit combination and thus a digital value can simply be stored in a digital memory, for example a RAM or on a hard disk. Further, a digital value may be processed by, for example, an algorithm in a digital computer or processor.

In the dq transformation or the parking transformation, an input signal SRA, SRB, SRC with the symbol u _r and a delayed by 90 ° signal SIA, SIB, SIC with the symbol u _i , the input signal SRA, SRB, SRC is tuned, used for transformation. The delay between the input signal SRA, SRB, SRC and the delayed signal SIA, SIB, SIC should be a phase shift between the signals of preferably 90 ° ± 5 ° (tolerance ≤ ± 5 °). Further, a sinusoidal signal sin (ωt) and a cosine signal cos (ωt) with the cosine signal cos (ωt) phase-shifted from the sinusoidal signal sin (ωt) by 90 ° are required for the dq transformation. The dq transformation is performed for each of the phases of the AC electrical network. The dq transformation is through the equation u _q = cos (ωt) u _r + sin (ωt) u _i Are defined.

The q-component SQA, SQB, SQC with the symbol u _q is dependent on the input signal u _r (SRA, SRB, SRC), which shows the voltage profile of the monitored phases of the AC electrical network and the delayed signal u _i (FIG. SIA, SIB, SIC), which has a delayed by 90 ° ± 5 ° waveform with respect to the input signal u _r (SRA, SRB, SRC). Thus, the q-component SQA, SQB, SQC is directly dependent on the value of the input signal SRA, SRB, SRC or the delayed signal SIA, SIB, SIC of the monitored phases of the AC electrical network. By the three parallel dq transformation facilities 12a . 12b . 12c , which individually transform each of the monitored phases, the input signals SRA, SRB, SRC and the delayed signals SIA, SIB, SIC of the three phases are individually monitored.

The input signals SRA, SRB and SRC correspond to the input voltages with the symbol u _r , where each signal designates the input signal of one of the three phases A, B, C. The signals SIA, SIB and SIC correspond to the delayed signal with the symbol u _i , where again each signal denotes the input signal of one of the three phases. The signals Si1, Si2 and Si3 correspond to the sine signal with the symbol sin (ωt), wherein the signal Si2 has a phase shift of 120 ° with respect to the signal Si1 and the signal Si3 has a delay of 240 ° with respect to the signal Si1. The signals C1, Co2 and Co3 correspond to the cosine signal with the symbol cos (ωt), wherein the signal Co2 has a phase shift of 120 ° with respect to the signal Co1 and the signal Co3 has a delay of 240 ° with respect to the signal Co1. The signals SQA, SQB and SQC correspond to the q-component with the symbol u _q , where each signal SQA, SQB, SQC designates the q-component of one of the three phases.

Furthermore, the device comprises an evaluation unit 14 , which is designed to detect a voltage deviation in the AC electrical network depending on the q-component SQA, SQB, SQC. The evaluation unit can be constructed as part of an electronic circuit with electrical components or be part of a program code, for example within a signal processor. The evaluation unit receives the signals of the q-component SQA, SQB, SQC, for example at an interface between the dq transformation device 12a . 12b . 12c and the evaluation unit 14 , For example, in a discrete circuit construction with electrical components, the evaluation unit 14 with each of the dq transformation facilities 12a . 12b . 12c electrically connected.

The evaluation unit 14 detects the value of the q components SQA, SQB, SQC of each of the dq transformers 12a . 12b . 12c , The value of the q-component SQA, SQB, SQC can be sent to the evaluation unit 14 be transmitted as a digital or analog electrical signal. The electrical signal may have a variable current or voltage magnitude.

The evaluation unit 14 is further configured to output an error signal FS if there is an error or a voltage deviation in the electrical alternating voltage network. The error signal FS can be output at an interface to a further unit, which can take a measure, for example, in the case of an error signal. The evaluation unit 14 can also be designed, for example, depending on the error signal FS to take action itself. Measures can be taken, for example, to limit the error or to remedy the error by switching on, switching off or bridging areas that cause errors or are affected by errors.

To detect whether an error is present, the evaluation 14 be configured to compare the q-component SQA, SQB, SQC with at least one threshold and output an error signal FS when the threshold is exceeded or fallen below. The threshold defines a value that, when reached, assumes that an error condition has been reached. For example, the q-component may have a value of 5 volts in the normal state. A threshold can be set at 4 volts. If the value of the signal SQA, SQB or SQB is less than or equal to 4 volts, an error signal FS is output. If signal SQA, SQB or SQB again exceeds the threshold of 4 volts, the error signal can be reset. It is also possible for a threshold value to be set at 6 volts, for example, and an error signal FS to be output when the threshold value is exceeded. Furthermore, it is possible to output an error signal FS both when a threshold value (4 V, 6 V) is undershot and exceeded. Achieving the fault condition means that an error has occurred in the AC electrical network. The threshold values can also be provided with a switching hysteresis.

The evaluation device 14 can be configured to output an error signal FS, if in the electrical AC voltage network at least one of the phases, the signal of the q-components SQA, SQB, SQC exceeds or falls below the threshold. The output of the error signal FS indicates that an error has occurred in the AC electrical network. Thus, the taking of measures for correcting the error or for the isolation of individual components present in the electrical alternating voltage network can be initiated. Rapid action can help minimize the extent of damage done to a fault.

The evaluation device 14 may be configured to determine whether there is a symmetric or an unbalanced network error. By determining the nature of the error, possible measures can be checked or eliminated, for example, to remedy the error, in which case rapid action can help to minimize the extent of damage caused by the voltage error.

The evaluation device 14 may also be designed to determine a final value of the voltage deviation. By determining the end value of the voltage drop, it is possible, for example, to prevent components of the electrical alternating voltage network from being isolated, although no damage is to be expected for the corresponding components and furthermore no risk of damage from the corresponding components. Further, by determining the final value, components can be isolated even before the voltage dip reaches a value at which these components could be damaged.

The evaluation device 14 can be configured to output an error signal FS, which depends on the nature of the error. The output of an error signal FS, which describes the error as precisely as possible or is attributable to an error, supports the rapid adoption of measures for correcting the error. The error signal FS can be transmitted to a network monitor. The network monitoring or the evaluation device can, if a certain value of the error signal, depending on the value of the error signal FS, certain measures for troubleshooting or for error or damage limitation cause. For example, by switching contactors or relays, which are operated electrically or pneumatically, certain circuit areas or components are switched on or off.

2 shows a schematic representation of another embodiment of the device according to the invention. In addition, in the 2 opposite in the 1 shown further components for generating the signals required for the dq transformation shown.

The input signals SRA, SRB, SRC of the dq transformation facilities 12a . 12b . 12c are connected to the three phases A, B, C, which pass through the device 10 be monitored. The delayed by 90 ° signals SIA, SIB, SIC by a phase retarder 16a . 16b . 16c generated. Phase retarders can be designed, for example, as a generalized second-order integrator (SOGI). A generalized second order integrator will be discussed later with reference to FIGS 4 and 5 described.

At each of the phases A, B, C, one of the phase retarders 16a . 16b . 16c be provided, wherein the phase retarder 16a . 16b . 16c is designed to detect a respective input signal SRA, SRB, SRC of the respective phase PA, PB, PC and to output a respective signal SIA, SIB, SIC delayed from the input signal SRA, SRB, SRC by a phase angle of 90 °. The dq transformation facility 12a . 12b . 12c may be configured to receive the respective input signal SRA, SRB, SRC and the respective delayed signal SIA, SIB, SIC of the phase A, B, C.

There is also a Clarke transformation facility 18 connected to the three phases A, B, C. The Clarke transformation facility 18 is designed to produce α-components and β-components from a three-phase electrical network. The quantities (current or voltage) of the three phases are converted into a two-axis coordinate system with the axes α and β. The three phase currents or voltages are mapped from the rectangular coordinate system into two equivalent currents or voltages with a real part α and an imaginary part β.

The Clarke transformation facility 18 can with a phase locked loop (PLL) 20 be connected to the α components and β components of the Clarke transformation device 18 as the αβ component signal AB from the Clarke Transformer 18 to the phase locked loop 20 transferred to. The phase locked loop 20 is formed, the α component and the β component and the αβ component signal AB from the Clark transformation device 18 and to generate a sine signal tuned to the α component and the β component and a cosine signal phase-shifted by 90 ° with respect to the sine signal. The delay between the sine signal and the delayed cosine signal should correspond to a phase angle of preferably 90 ° ± 5 ° (tolerance ≤ ± 5 °). At the output of the phase locked loop 20 the sine signal and the cosine signal are output. The phase locked loop 20 may be an electronic circuit in which the frequency of a variable oscillator is influenced via a closed loop so that the phase deviation between an external reference signal and the oscillator or a signal derived therefrom is as constant as possible.

The output of the phase locked loop 20 can with the input of the dq transformation device 12a be connected so that the sine signal and the co-sinusoidal signal to the dq transformation means 12a can be transmitted.

Furthermore, between the output of the phase locked loop 20 and the input of the dq transformation device 12b a first signal retarder 22a be switched. The first signal retarder 22a is configured to delay the sine signal Si1 by 120 °, for example, and to generate a delayed sine signal Si2. The delayed sinusoidal signal Si2 can be sent to the dq transformation device 12b be transmitted. The first signal retarder 22a Furthermore, it is configured to generate a cosinusoid signal Co2 delayed by 120 °, for example, from the cosinusoidal signal Co1, wherein the cosinusoidal signal Co2 is likewise sent to the dq transformation device 12b can be transferred.

Next can be between the output of the phase locked loop 20 and the input of the dq transformation device 12c a second signal retarder 22b be switched. The second signal retarder 22b is configured to delay the sine signal Si1 for example by 240 ° and to generate a delayed sine signal Si3. The delayed sine signal Si3 can be sent to the dq transformation device 12c be transmitted. The second signal retarder 22b It is further configured to generate a cosinusoid signal Co3 delayed by 240 °, for example, from the cosinusoidal signal Co1, the cosinusoidal signal Co2 also being sent to the dq transformation device 12c can be transferred.

In embodiments, the device may also include three phase locked loops, or a phase locked loop for each of the phases A, B, C. Each of the phase locked loops is formed, the α component and the β component, from the Clark transform means 18 and to generate for each of the phases A, B, C a sine wave signal tuned to the α component and the β component and a cosine signal phase-shifted by 90 ° with respect to the sine wave signal. In the case of a plurality of phase locked loops, each of the three phase locked loops, for example, can be designed to generate the respective sine signal and the respective cosine signal of another phase.

In embodiments, the device may include a phase locked loop that is configured, the α component, and the β component of the Clark transform device 18 and to generate for each of the phases A, B, C a sine signal tuned to the α component and the β component and a cosine signal phase-shifted by 90 ° with respect to the sine signal. The phase locked loop is thus formed, the sine signal Si1 and the cosine signal Co1 to the dq transformation means 12a , the sine signal Si2 and the cosine signal Co2 to the dq transformation device 12b and the sine signal Si3 and the cosine signal Co3 to the dq transformation means 12c issue.

In embodiments, the apparatus for a nominal frequency of 50, 60 formed or 16 _^2/3 Hz. Thus, electrical networks with frequencies which are typical especially in Europe or the US in the public power supply, as well as electrical networks, which are common, for example, in rail transport systems are monitored. The adaptation to electrical networks with different frequencies can be achieved by the use of different components or by parameterization, for example, the phase locked loop 20 , the phase retarder 16a . 16b . 16c or the signal retarder 22a . 22b respectively. In embodiments, the device is designed to be adaptive to frequency, ie the device can be operated at different nominal frequencies without having to exchange components or to change the parameterization.

3 shows a simulation scheme (block diagram) of the method for fault detection in an electrical alternating voltage network. The simulation scheme (block diagram) shows the sdq procedure for three phases. The sine signal and the cosine signal are in the simulation scheme with a common connection to the dq transformers 12a . 12b . 12c transfer. Furthermore, in the simulation scheme, the input signal SRA, SRB, SRC, which indicates the voltage profile of the monitored phases A, B, C of the AC electrical network, and the delayed signal SIA, SIB, SIC with a common connection to the dq transformation means 12a . 12b . 12c transfer.

The evaluation of the voltages SQA takes place in the evaluation unit 14a , The evaluation of the voltages SQB takes place in the evaluation unit 14b and the evaluation of the voltages SQC takes place in the evaluation unit 14c , The evaluation units 14a . 14b . 14c can output an error signal FS.

Known dq transformations are defined for three-phase systems. For single-phase systems, therefore, the dq transformation must be modified. To do this, one must generate a signal offset by 90 ° per phase, which is initially simply represented as a time delay in the block diagram (see, for example, references [3] and [4]). Thus, one obtains the αβ components of each phase, which can then be converted into the dq components by using the network angle (phase shift, phase difference) of each phase for transformation. The network angle is the phase shift between the individual phases. In a three-phase electrical network, the network angle is 120 ° each.

The single-phase dq transformation itself then results from the following equations (see, for example, the reference [3]) u _d = sin (ωt) u _r - cos (ωt) u _i u _q = cos (ωt) u _r + sin (ωt) u _i , where the network angle θ _network = ωt from the phase locked loop 20 (PLL) and the voltages u _r , u _i (input signals SRA, SRB, SRC (u _r ), delayed signal SIA, SIB, SIC (u _i )) from the artificial phase shift of the respective phase A, B, C ( of the original system) by 90 °.

The 90 ° phase shift with the phase retarders 16a . 16b . 16c and the network angles of the individual phases with the signal delays 22a . 22b can be realized in different ways. In the simplest case this may be as in 3 represented by time delays, for example by a tuned integrator or a First In First Out Register.

To increase the robustness, the phase shift can also be realized by means of SOGI low pass (G ₂ (s)), which attenuates higher frequencies than the mains frequency. As a result z. B. harmonics better suppressed, the dynamics of the process is degraded, however, since high frequencies occur in the voltage jump of the error.

The network angles of the phase locked loop 20 (PLL) can via a phase locked loop 20 (PLL) with phase shift or 3 single-phase phase locked loops (PLLs) can be realized.

The robustness of the sdq method has already been taken up and will be shown here again. The method has a degree of freedom with which the robustness and thus also the dynamics can be adjusted. Essential actuators for this are the realization of the 90 ° phase shifts and the gain factor k of the SOGI structure.

Since the line frequency is tracked out of the phase locked loop, the method is robust against small frequency changes (eg between 49.8 Hz and 50.2 Hz). It does not matter if the frequency changes are slow or erratic. Even with a SOGI structure, which is fixed in a frequency-locked manner to 50 Hz, a detuning of the method due to a frequency deviating from 50 Hz can not be determined.

An adaptation of the procedure to other frequencies such as 16 _^2/3 Hz (rail systems) or 60 Hz (USA) is possible and easy to implement.

In embodiments, the entire method may be frequency adaptive, but this leads to a more complex system.

Harmonics in the original system of the mains voltage lead to oscillations in the indicator voltages (u _d , u _q ) of the sdq method, whereby an evaluation over a threshold value is made more difficult. As soon as the vibrations exceed the hysteresis band of the evaluation, reliable detection is no longer possible. If the 90 ° phase shift is generated by SOGI structures, the robustness to harmonics can be significantly increased.

The measurement noise tends to have a very low influence on the method since the measurement noise is usually very high-frequency. Harmonics are significantly more dominant in terms of measurement noise in influencing the indicator voltages.

In embodiments in real systems, it may, for. B. by the network impedance (eg., By the block transformer) to long and extremely strong oscillations of the mains voltage at the beginning and end of error come. An empty measurement on a 6-MVA test container showed z. B. such extreme behavior very clearly. In principle, this poses no problem for the sdq method. However, in the case of very long oscillations, it can lead to a network fault being recognized several times and appearing to have been clarified.

The dq transformation is actually three-phase. The dq transformation is a purely algebraic calculation both in the single-phase and in the three-phase case.

The implementation of the circuit can, as described here, be continuous-time. However, a discrete-time implementation of the SOGI structure is also possible. This requires a certain additional effort. Guidance on discrete-time implementation can be found in special literature (see, for example, reference [5]).

The big advantage of the method is the extremely fast detection of symmetrical and unbalanced errors, which requires only one scanning step with sufficiently steep error edges. Furthermore, there are degrees of freedom to adjust the robustness of the method to the dynamics.

Compared to certain known systems, sdq error detection can have lower robustness and high complexity. For the implementation of the SOGI structure on digital systems exist efficient and established possibilities.

Known procedures similar to the sdq method are so-called delayed signal cancellation or the T / 4 method (see reference [6] and [7]). These are not based on the single-phase dq transformation, but on the splitting into symmetrical components. Embodiments of the invention, however, have greater dynamics than these systems, since no splitting into symmetrical components is performed and unbalanced errors are detected. Common to the methods is also the artificial phase shift of the input signals by 90 ° (T / 4).

According to references [6] and [7], the signals in the αβ system are shifted by 90 ° and then split into symmetrical components for evaluation.

mit der wählbaren Dämpfung k und der Frequenz ω. (ω = 2πf).In 4 and 5 is the construction of a SOGI structure (SOGI = Second Order Generalized Integrators, generalized second-order integrator) shown on a simulation diagram. In embodiments, the phase retarder is designed as a second-order integrator. The second-order integrator can be designed to be time-discrete or continuous-time. In principle, the structure SOGI_BP is in 5 depending on the output or input to a low or band pass. The transfer functions are:

with the selectable damping k and the frequency ω. (ω = 2πf).

K = v results in a critical damping. The value is used as default. The structure can be designed to be frequency-adaptive by tracking the network frequency ω from the phase-locked loop (PLL). In embodiments, the nominal frequency ω = ω ₀ = 2π 50 ^rad / _{s is} used.

6 shows the Bode diagrams of the SOGI structures. Out 6 It can be seen that the structure is perfectly suitable for generating orthogonal signals, since at the frequency ωw there is a phase shift of exactly 90 ° between G ₁ and G ₂ and thus between the outputs v and v '. Higher frequencies, however, are attenuated.

In references [4] and [8], the described structure is used to detect network errors. Two SOGI bandpasses are combined to form a DSOGI structure (dual second order generalized integrators, double-generalized second-order integrator). By means of the DSOGI structure, positive and negative sequences of the mains voltage can be formed. For each sequence, a dq transformation is then carried out, the components of which then act as indicator voltages (u _d , u _q ).

The d component of the positive sequence indicates a symmetric error. The d-component of the negative sequence indicates an unbalanced error. The two voltages can be evaluated via threshold comparisons.

The DSOGI method is based on the splitting of the mains voltage into symmetrical components. In each case for positive and negative sequences, a dq transformation is carried out, the 4 components (d +, d-, q +, q-) are monitored. Basis of the method are so-called generalized integrators (SOGI). This structure can be used for many purposes, e.g. As for the decomposition of unbalanced signals into symmetrical components, as a phase-locked loop (PLL) or for power control. The structure of the SOGI is also excellent for generating orthogonal signals (see reference [4] and reference [5]) and is also used in embodiments of the invention.

7a shows the mains voltage with a symmetrical error with 5% residual voltage. The voltages U _L1 , U _L2 , U _L3 can correspond to the phases A, B and C. As in 7b In the case of a symmetrical error, an asymmetrical error is first detected (see also Reference [8]). This makes symmetric error detection relatively slow and initially inaccurate. For unbalanced errors, fault detection based on the d-component works very well. The process is characterized by great robustness; but it is complex. 7c shows fault detection with half-period RMS monitoring.

7d also shows the mains voltage with a symmetrical error with 5% residual voltage. When dq monitoring, as in the 7e shown, the three-phase dq transformation (park transformation) of the mains voltages is used for error detection. The thus obtained dq components of the mains voltages can then be used directly via a threshold comparison for error detection.

The dq method is simpler compared to the previous ones. Thereby an extremely fast detection takes place for symmetrical errors. This is due to the fact that the computation of the dq components initially occurs purely algebraically and the network angle and the network frequency from the phase-locked loop (PLL) remain constant at first.

7f shows the indicator voltage and the error detection in one embodiment of the inventive single-phase dq monitoring in a symmetric error. The voltages U _{q, L1,} U _{q, L2,} U _{q, L3} possibility the indicator voltages SQA, SQR, SQC of the phases A, B and C are assigned. The detection of an error can be extremely fast due to the rapidly changing indicator voltages U _q , L ₁ , U _q, L ₂ , U _q, L ₃ . Also, the return of the mains voltage and thus the normal state can be detected quickly. An error signal can be output dependent from the edge or the voltage value, which has the mains voltages U _L1 , U _L2 , U _L3 or indicator voltages U _{q, L1} , U _{q, L2} , U _{q, L3} . The time from which the error signals F _L1 , F _L2 , F _L3 indicate a valid signal after a faulty voltage value of the mains voltage U _L1 , U _L2 , U _L3 , may be dependent on the time and thus the phase position of the voltage at which the mains voltages U _L1 , U _L2 , U _{L3 is} reinstated. In this case, the error signals F _L1 , F _L2 , F _L3 , be connected to each other by a logical AND, ie only if the error signals F _L1 , F _L2 , F _L3 all phases indicate no error and thus a valid signal, the electric AC mains as faultless and thus viewed in normal condition.

8a shows the mains voltage with an unbalanced fault with 5% residual voltage (short circuit U _L1 -N.) The voltages U _L1 , U _L2 , U _L3 can again correspond to the phases A, B and C.

As in 8b In the case of asymmetrical errors, error detection based on the d-component works very well. However, the elimination of the fault and thus the return of the normal state of the voltage is detected only with a certain delay. The process is complex, but has a certain robustness. 8c shows fault detection with half-period RMS monitoring.

8d also shows the mains voltage with an unbalanced error with 5% residual voltage. For unbalanced errors, a two-frequency negative sequence (eg 100 Hz) occurs in the evaluation with the three-phase dq transformation, which, as in 8e shown, leads to a strong oscillation in the indicator voltages (U _d and U _q ). A secure evaluation is thus no longer immediately possible. One possible solution would be z. Example, the determination of the positive sequence of the indicator voltage via a notch filter, a decoupling network or a Fourier analysis. The measures, however, worsen the dynamics of the process and significantly increase the effort.

8f shows the indicator voltage and the error detection in one embodiment of the inventive single-phase dq monitoring in a single-ended error. The voltages U _{q, L1,} U _{q, L2,} U _{q, L3} possibility the indicator voltages SQA, SQR, SQC of the phases A, B and C are assigned. Again, the detection of an error due to the rapidly changing indicator voltage Uq can be extremely fast. The return of the mains voltage and thus the normal state can also be detected extremely quickly.

The sdq method allows in embodiments an extremely fast error detection. The functionality of the method was validated in simulations and in laboratory measurements for different types of defects, whereby positive properties could be shown. By dispensing with sequence separation into symmetrical components, an increase in dynamics can be achieved in comparison with known methods. In embodiments, a hardware circuit for safety circuit overcurrent in case of network errors can be dispensed with.

• • Windkraftanlagen
• • Solarwechselrichter
• • BHKWs
• • Batteriestromrichter

The concept can basically be used in all converters that are connected to an electrical network. This includes not only a network, but also island networks, such as. UPS, etc. These include above all:

• • Wind turbines
• • solar inverter
• • CHPs
• • Battery inverter

The mains frequency of 50 Hz is assumed by way of example in exemplary embodiments. Other line frequencies are covered by the described methods, such as the sdq method.

Although some aspects have been described in the context of a device, it will be understood that these aspects also constitute a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or feature of a method step. Similarly, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device. Some or all of the method steps may be performed using a hardware device, such as a microprocessor , a programmable computer or an electronic circuit. In some embodiments, some or more of the most important method steps may be performed by such an apparatus.

Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software. The implementation may be performed using a digital storage medium, such as a floppy disk, a DVD, a BIu-ray disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or FLASH memory, a hard disk, or other magnetic disk or optical memory are stored on the electronically readable control signals that are connected to a programmable computer system can cooperate or cooperate in such a way that the respective procedure is carried out. Therefore, the digital storage medium can be computer readable.

Thus, some embodiments according to the invention include a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the methods described herein is performed.

In general, embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is operable to perform one of the methods when the computer program product runs on a computer.

The program code can also be stored, for example, on a machine-readable carrier.

Other embodiments include the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine-readable medium.

In other words, an embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer. The data medium, the digital storage medium or the recorded medium are usually tangible or non-volatile.

A further embodiment of the inventive method is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program is recorded for carrying out one of the methods described herein.

A further embodiment of the method according to the invention is thus a data stream or a sequence of signals, which represent the computer program for performing one of the methods described herein. The data stream or the sequence of signals may be configured, for example, to be transferred via a data communication connection, for example via the Internet.

Another embodiment includes a processing device, such as a computer or a programmable logic device, that is configured or adapted to perform one of the methods described herein.

Another embodiment includes a computer on which the computer program is installed to perform one of the methods described herein.

Another embodiment according to the invention comprises a device or system configured to transmit a computer program for performing at least one of the methods described herein to a receiver. The transmission may be, for example, electronic or optical. The receiver may be, for example, a computer, a mobile device, a storage device or a similar device. For example, the device or system may include a file server for transmitting the computer program to the receiver.

In some embodiments, a programmable logic device (eg, a field programmable gate array (an FPGA) may be used to perform some or all of the functionality of the methods described herein.) In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. In general, in some embodiments, the methods are performed by any hardware device, such as a general purpose hardware such as a computer processor (CPU), or hardware specific to the method, such as an ASIC.

The embodiments described above are merely illustrative of the principles of the present invention. It will be understood that modifications and variations of the arrangements and details described herein will be apparent to others of ordinary skill in the art. Therefore, it is intended that the invention be limited only by the scope of the appended claims and not by the specific details presented in the description and explanation of the embodiments herein.

LIST OF REFERENCE NUMBERS

10

Device for error detection

12

dq transformation means

14

evaluation

16

retarders

18

Clarke transformation means

20

Phase-locked loop

22

Signalverzögerer

A

Phase A

B

Phase B

C

Phase C

SRA

Input signal (Ur) of phase A

SRB

Input signal (Ur) of phase B

SRC

Input signal (Ur) of phase C

SIA

delayed signal (Ui) of phase A

SIB

delayed signal (Ui) of phase B

SIC

delayed signal (Ui) of phase C

Si1

sinewave

Si2

Sine signal with 120 ° delay

Si3

Sine signal with 240 ° delay

Co1

cosine

Co2

Cosine signal with 120 ° delay

Co3

Cosine signal with 240 ° delay

SQA

Q component (Uq) of phase A

SQR

Q component (Uq) of phase B

SQC

Q component (Uq) of phase C

FROM

αβ-component signal

FS

error signal

references

• [1] BDEW, Technical Guideline: "Generation Plants on Medium-Voltage Grid", 2008 URL: http://www.bdew.de/internet.nsf/id/DE_NetzCodes-und-Richtlinien
• [2] VDE application regulation "VDE-AR-N 4105: 2011-08 Generation plants on the low-voltage network, Minimum technical requirements for connection and parallel operation of generation plants in the low-voltage network", 2011 URL: http://www.bdew.de/internet.nsf/ id / DE_NetzCodes and guidelines
• [3] Gonzalez, M .; Cardenas, V .; Pazos, F., "DQ Transformation Development for Single-Phase Systems to Compensate Harmonic Distortion and Reactive Power," Power Electronics Congress, 2004. CIEP 2004. 9th IEEE International. vol., no., pp. 177, 182, 17-22 Oct. 2004 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1437575&isnumber=309 57
• [4] Rodriguez, P .; Teodorescu, R .; Candela, I .; Timbus, A. V .; Liserre, M .; Blaabjetg, F., "New Positive-sequence Voltage Detector for Grid Synchronization of Power Converters Under Faulty Grid Conditions," Power Electronics Specialists Conference, 2006. PESC'06. 37th IEEE. vol., no., pp. 1, 7, 18-22 June 2006 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1712059&isnumber=360 90
• [5] Rodriguez, F. J .; Bueno, E .; Aredes, M .; Rolim, L. G B; Neves, F.A.S. Cavalcanti, M.C., "Discrete-time implementation of second order generalized integrators for grid converters," Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE, vol., No., Pp. 176, 181, 10-13 Nov. 2008 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4757948&isnumber=475 7911
• [6] Benz, C.H .; Franke, W.-T .; Fuchs, F.W., "Low voltage ride through capability of a 5kW grid-tied solar inverter," Power Electronics and Motion Control Conference (EPE / PEMC), 2010 14th International, vol., No., Pp. T12-13, T12-20, 6-8 Sept. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5606829&isnumber=560 6503
• [7] Alepuz, S .; Busquets, S .; Bordonau, J .; Pontt, J .; Sllva, C .; Rodriguez, J., "On-line Symmetrical Components Separation Method for Synchronization and Control In Three-Phase Distributed Power Generation Systems", "Power Electronics and Applications, 2007 European Conference on, vol., No., Pp. 1, 1 o, 2-5 Sept. 2007 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4417343&isnumber=441 7197
• [8] Wessels, C., "Traversing Network Faults in Wind Turbines with FACTS," Dissertation, Uni Kiel, 2012 Saccomando, G .; Svensson, J., "Transient operation of grid-connected voltage soSRCe converter under unbalanced voltage conditions," Industry Applications Conference, 2001. Thirty-Sixth IAS Annual Meeting. Conference Record of the 2001 IEEE, vol. 4, no., Pp. 2419, 2424 vol. 4, Sept. 30 2001-Oct. 4 2001 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=955960&isnumber=2067 5

Claims (20)

Device for error detection ( 10 ) in an electrical alternating voltage network, with the following features: a dq transformation device ( 12a . 12b . 12c ) which is designed to generate a q-component (SQA, SQB, SQC) for at least one phase (A, B, C) using a single-phase transformation, and an evaluation unit ( 14 ; 14a . 14b . 14c ) which is designed to detect a voltage deviation in the AC electrical network as a function of the Q component (SQA, SQB, SQC) and to output an error signal (FS) if there is a voltage deviation, whereby at least one of the phases (A, B, C) a phase retarder ( 16a . 16b . 16c ), wherein the phase retarder ( 16a . 16b . 16c ) is adapted to detect an input signal (SRA, SRB, SRC) of the respective phase (A, B, C) and a signal (SIA, SIB, delayed by a phase angle of 90 ° with respect to the input signal (SRA, SRB, SRC) SIC), and wherein the dq transformation device ( 12a . 12b . 12c ) is adapted to receive the input signal (SRA, SRB, SRC) and the delayed signal (SIA, SIB, SIC). Contraption ( 10 ) according to claim 1, wherein the AC electrical network is formed as a multi-phase electric network. Contraption ( 10 ) according to claim 1 or 2, wherein the phase retarder ( 16a . 16b . 16c ) is formed as a generalized second order integrator SOGI. Contraption ( 10 ) according to claim 3, wherein said generalized second order integrator is time discrete. Contraption ( 10 ) according to claim 3, wherein said generalized second order integrator is continuous time. Contraption ( 10 ) according to any one of claims 1 to 5, wherein the device ( 10 ) additionally a Clarke transformation facility ( 18 ) configured to generate α components and β components from a three-phase electrical network. Contraption ( 10 ) according to claim 6, wherein the device additionally comprises a phase locked loop ( 20 ), which is formed, the α-component and the β-component of the Clark transformation device ( 18 ) and to generate a sinusoidal signal (Si1, Si2, Si3) tuned to the α-component and the β-component and a cosinusoid signal (Co1, Co2, Co3) phase-shifted with respect to the sine signal (Si1, Si2, Si3) , Contraption ( 10 ) according to claim 7, wherein a first signal retarder ( 22a ) is configured to generate a sinusoidal signal (Si2) delayed by 120 ° with respect to the sine signal (Si1) and a cosinusoid signal (Co2) delayed by 120 ° with respect to the cosine signal (Co1) and with a second signal retarder ( 22b ) is designed to generate a sinusoidal signal (Si3) delayed by 240 ° with respect to the sine signal (Si1) and a cosine signal (Co3) delayed by 240 ° with respect to the cosine signal (Co1). Contraption ( 10 ) according to claim 6, wherein the device ( 10 ) three phase locked loops ( 20 ) and wherein each of the phase locked loops ( 20 ), the α-component and the β-component from the Clark transformation device ( 18 ) and, for each of the phases (A, B, C), a sinusoidal signal (Si1, Si2, Si3) tuned to the α-component and the β-component and to the sinusoidal signal (Si1, Si2, Si3) by 90 Phase-shifted cosine signal (Co1, Co2, Co3), each of the three phase-locked loops ( 20 ) generates the respective sine signal (Si1, Si2, Si3) and the respective cosine signal (Co1, Co2, Co3) of another phase (A, B, C). Contraption ( 10 ) according to one of claims 1 to 9, wherein the q-component comprises a q-voltage. Contraption ( 10 ) according to claim 10, wherein the dq transformation device ( 12a . 12b . 12c ), an input signal (SRA, SRB, SRC), a delayed signal (SIA, SIB, SIC) tuned to the input signal (SRA, SRB, SRC), and a sine signal (Si1, Si2, Si3 ) and a cosine signal (Co1, Co2, Co3) which is 90 ° out of phase with the sine signal (Si1, Si2, Si3), perform a park transformation for each of the phases (A, B, C), the parking Transformation by the equation u _q = cos (ωt) u _r + sin (ωt) u _i is defined. Contraption ( 10 ) according to one of claims 1 to 11, wherein the evaluation device ( 14 ; 14a . 14b . 14c ) is configured to compare the q-component (SQA, SQB, SQC) with at least one threshold value and output an error signal (FS) if the threshold value is exceeded or undershot. Contraption ( 10 ) according to claim 12, wherein the evaluation device ( 14 ; 14a . 14b . 14c ) is configured to output an error signal (FS) when the q-component exceeds or falls below the threshold values in at least one of the phases (A, B, C) in the electrical AC voltage network. Contraption ( 10 ) according to one of claims 1 to 13, wherein the evaluation device ( 14 ; 14a . 14b . 14c ) is designed to determine whether a symmetrical or an asymmetrical network error is present. Contraption ( 10 ) according to one of claims 1 to 14, wherein the evaluation device ( 14 ; 14a . 14b . 14c ) is designed to determine a final value of the voltage deviation. Contraption ( 10 ) according to one of claims 1 to 15, wherein the evaluation device ( 14 ; 14a . 14b . 14c ) is designed to output an error signal (FS), which depends on the type of error. Contraption ( 10 ) according to one of claims 1 to 16, wherein the device ( 10 ) Is designed for a nominal frequency of 50, 60 or 16 _^2/3 Hz. Contraption ( 10 ) according to one of claims 1 to 17, wherein the device ( 10 ) is designed to be adaptive to frequency. A method for error detection in an AC electrical network, comprising: generating a q-component by means of a dq-transformation, for at least one phase using a single-phase transformation, Detecting a voltage deviation, dependent on the q-component (SQA, SQB, SQC), outputting an error signal (FS) if a voltage deviation is present, whereby an input signal (SRA, SRB, S) is applied to at least one of the phases (A, B, C) SRC) of the respective phase (A, B, C) is detected, and a signal (SIA, SIB, SIC) delayed from the input signal (SRA, SRB, SRC) by a phase angle of 90 ° is output, and wherein the dq- Transformation receives the input signal (SRA, SRB, SRC) and the delayed signal (SIA, SIB, SIC). A computer program comprising program code for performing the method of claim 19 when the computer program runs on a computer or processor.

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