DE102014218792A1 - Output current measurement of switched converters in PFM mode - Google Patents

Abstract

A method for determining the output current Iout of a switched power converter operating in a pulse frequency modulation (PFM) controlled mode comprises: determining a pulse width of at least one PFM pulse for driving a switching element of the power converter; and determining the output current Iout based on the determined pulse width and on the maximum coil current Imax of the power converter when in the PFM controlled mode, wherein determining a pulse width comprises counting a number of pulses Ncount of a reference clock during the at least one PFM pulse in FIG having at least one PFM cycle.

Description

background

This document relates to the measurement of an output current provided by a switched power converter, such as a buck converter.

Prior art methods and apparatus for measuring the output current of a power converter include a DC measurement at the output connector of the power converter by, for example, measuring a voltage drop across a pass device or by providing a resistor in series with the converter coil. However, such a measurement affects the power supplied to devices connected to the power converter and requires power.

There is thus a need to provide accurate and efficient measurement of the output current of a switched converter.

Summary

According to one aspect, a method of determining the output current I _{out of} a switched power converter operating in a pulse frequency modulation (PFM) controlled mode comprises determining a pulse width of at least one PFM pulse and determining the output current I _out based on the determined pulse width and on the maximum coil current I _{max of} the power converter when in the PFM controlled mode in which the PFM pulse is used to drive a switching element of the power converter. In this case, determining a pulse width comprises counting a number N of pulses of a reference clock during the at least one PFM pulse in at least one PFM cycle. From the pulse width and maximum pulse current, the current delivered during the PFM pulse can be determined without the need to provide current measurements. The particular PFM pulse width may be divided by the length of a PFM cycle to determine a PFM duty cycle that may be used to determine an average coil current during a complete PFM cycle. Thus, the output current I _{out of} the power converter can be determined without interrupting the current supplied by the switched converter to its load, for example another device. It should be noted that the output current determined using this method represents an average output current averaged over a given measurement time T, the measurement time T comprising at least one PFM cycle with a PFM pulse.

According to embodiments, the counting of a number of reference pulses during the given measurement time T. The reference clock can operate at a clock frequency f. The output current I _out can then be determined based on the maximum coil current I _max , the counted number of pulses N _count , the clock frequency f, and the measurement time T. Thus, the output current can be determined based on measurements simply taken during the switched power converter operation can be measured or determined using simple time measurements made by counting the pulses of a reference clock.

In this case, the output current I _{out can be determined} based on the maximum coil current I _max times the ratio of the counted number of pulses N _count over the product of clock frequency f and measurement time T. Thus, the output current I _out can be calculated as

Thus, the output current I _{out can be determined} during a given measurement time T using the known value of I _max for a given power converter and using the known frequency f of the reference clock.

The measurement time T can also be determined using a number N _total of clock pulses of the reference clock. Thus, the measurement time Tals T = N _total / f can be expressed such that:

In embodiments, the measurement time T may correspond to an integer multiple of the reference clock period, where the multiple is a power of 2, N _total = 2 ⁿ , such that the division of the number N _{count of} the counted pulses by the total number N _total of reference clock pulses during the measurement time T as a simple move operation can be performed. Thus, the computational complexity for calculating the ratio of the number N _count of counted clock pulses divided by the total number N _{total of} the clock pulses during the measurement time T is reduced. The output current I _out can thus be calculated in a very simple way: the counted number N _count of clock pulses is shifted by the predetermined number of bits, the shift operation corresponding to the division N _count / N _total , and the shifted value then becomes multiplied by a known constant corresponding to the multiplication by I _max / 2.

According to another aspect, an apparatus for determining the output current I _{out of} a switched power converter operating in a pulse frequency modulation (PFM) controlled mode comprises a reference clock for generating count pulses having a frequency f and a counting unit for determining a pulse width of at least one PFM pulse. In this case, a switching element of the power converter is driven by the at least one PFM pulse. Typically, at least one switching element of the power converter is turned ON during the PFM pulse. The counting unit counts a number N _count of _count pulses of the reference clock during the at least one PFM pulse in at least one PFM cycle. The apparatus further comprises a calculation unit for determining the output current I _out based on the determined PFM pulse width (for example, based on the number N _count of counted reference clock pulses) in the at least one PFM cycle and on the maximum coil current I _{max of} the power converter. when in the PFM controlled mode. In this case, the determined PFM pulse width can be divided by the length of the PFM cycle to determine an "on / off ratio" of the coil current during the PFM controlled mode. Thus, the device performs current measurement by counting pulses of a reference clock, ie without the need to directly measure currents of the switched power converter. Thus, the output current I _{out of} the switched power converter can be measured without affecting the output power and without interrupting the power supply of the power converter to other devices. Since the power consumption of clocks and counters is generally low, the device determines the output current I _{out of} the switched power converter while consuming very little energy for the measurement.

According to embodiments, a controller may be provided to generate control signals, for example to start and stop the pulse count, and / or to generate control signals for sampling the counted number of pulses and calculating the output current I _out based thereon. The control unit may operate at a lower clock frequency than the reference clock, thereby reducing the power consumption of the control unit.

The control unit may include a state machine and may generate the control signals in various states of the state machine. In this case, a first state of the state machine may include starting the measurement, a second state may stop the measurement, and a third state may include sampling the counted number of pulses. The value of the output current I _out can be calculated in a fourth state. Other states and arrangements are possible wherein the state machine may perform additional tasks in further states or where some of the above-mentioned actions may be performed by other components and not by the state machine.

According to embodiments, the counting unit may comprise an n-bit counter or an accumulator. The n-bit counter or accumulator may count and / or accumulate the reference clock pulses that occur during a PFM pulse of the switched power converter. Thus, the length of the PFM pulse may be determined by sampling the count stored in the n-bit counter or accumulator after a PFM pulse is completed, for example, when triggered by a corresponding control signal from the controller.

According to embodiments, the counting unit may comprise one or more logic gates. In this case, a first logic gate receive the PFM pulses and a start control signal. A second logic gate may receive the count pulses and the output of the first logic gate. Thus, the first logic gate ensures that the PFM pulses are passed only to the rest of the counting unit circuits when the current measurement is initiated by the start control signal. The second logic gate then generates a logical "1" An output, when a count pulse occurs during a PFM pulse, such that a counter or accumulator connected to the output of the second logic gate may count the number of reference clock pulses occurring during the length of a PFM pulse.

According to embodiments, the switched power converter may be a multi-phase converter. The polyphase converter has a plurality of individual power converters, such as buck converters, arranged in parallel between the input and the load. The apparatus may have a number of counts, one for each phase of the multiphase converter, and a summation unit for summing the counts of the individual counts. The calculation unit may determine the output current I _out based on the total number of count pulses for all phases as determined by the summation unit. Due to the provision of individual counting units for each phase, the length of the respective PFM pulses for each phase can be accurately determined, so that the output current I _{out of} the switched polyphase power converter can be determined with high accuracy.

In this case, each counting unit can have an n-bit counter and a counter gate, which is controlled by the control unit. The summation unit is connected to all counters via its respective counter gate and is controlled by the control unit to add all counts after expiration of the measurement time T. Thus, when the measurement time T has elapsed, the summation unit may provide the total number N _count of counted clock pulses for all phases of the switched multiphase power converter which may then be sampled, for example by a state machine as described above. As described above for the single power converter, the number N _count of clock pulses may then be divided by the total number N _total of reference clock pulses during the measurement time T to determine a value that is proportional to the output current I _{out of} the polyphase power converter. The output current I _{out of} the switched polyphase power converter can then be calculated by multiplying this value by the maximum coil current I _max / 2, assuming that all phases of the switched polyphase converter are controlled using the same maximum coil current I _max . Otherwise, if different phases of the switched multiphase converter are controlled using different respective maximum coil current values I _max , then multiplying the number of _count pulses N _count for each phase by the corresponding maximum coil current value I _max (or I _max / 2) can be done separately for each Phase before summing the counted clock pulses N _count for the individual phases.

In another embodiment with respect to a multi-phase converter, the device may have a single counting unit for counting the count pulses for all phases. The counting unit may have a respective first and second logic gate and a storage element for each phase. The respective output of the second logic gate of a phase may be connected to an input of the storage element for the phase. The counting unit may further comprise a summation unit for summing the number of active phases for a pulse period of the reference clock. For each pulse period of the reference clock, the summation unit provides the number of active phases during this reference clock pulse period. In this case, an active phase of the switched multiphase converter is a phase in which a PFM pulse is currently provided for a switching element of the respective phase. Thus, the total length of the PFM pulses for all phases of the switched multiphase converter can be determined using a single counting and summing unit, thereby reducing the power consumption of the output current determining device of the switched multiphase converter. In this case, the individual phases of the multiphase converter can all have identical respective maximum coil current values I _max .

The counting unit may comprise an accumulator for accumulating the number of counting pulses of all phases for all reference clock pulse periods during the measuring time T. Thereby, for each pulse period of the reference clock, the accumulator may receive and accumulate the result of the summing unit representing the number of active phases of the switched polyphase converter during this pulse period of the reference clock. Thus, after the measurement time T has elapsed, the accumulator stores the total number of counts or counts for all active phases of the switched multiphase converter.

The memory elements may be RS flip-flops. A reset input of the RS flip-flop may be connected to the inverted reference clock. Thus, the storage elements forward the result of whether their respective associated phase was active during the previous reference clock pulse to the summation unit upon completion of the reference clock pulse. The set input of the RS flip-flop may be connected to the reference clock pulse via logic gates which determine the presence / absence of a PFM pulse during the present reference clock cycle. Thus, an undetermined state of the memory element can be avoided since the set and reset inputs of each RS flip-flop are connected to different values of the reference clock pulse.

A clock input of the accumulator may be connected to the inverted reference clock. Thus, when the respective reset inputs of the memory elements are triggered by the inverted reference clock, the summation unit sums the number of active phases as reflected in the output of the memory elements and the accumulator accumulates the result of the summation unit with the previously counted value.

In another embodiment, where the switched power converter is a multi-phase converter, the apparatus may have a single counter and access logic for selecting, during a time period, a PFM pulse, or multiple PFM pulses of only one pass-through phase the counting unit for determining a pulse width of the PFM pulse (s). The selected phase can rotate among the several phases. The computing unit may adjust the counted pulses by the number of phases to account for counting only a single phase at a time. This embodiment allows the use of a single counting unit to estimate the PFM pulse length of multiple phases. In a multi-phase switched power converter, it is believed that the phases exhibit generally similar behavior, that is, as the PFM pulse length and / or frequency increases or decreases for one phase, the other phases exhibit similar changes in length and / or Frequency of their respective PFM pulses. Thus, counting only a single phase results in an acceptable estimate of the behavior of the other phases.

The access logic may have an AND gate for each phase. One input of the AND gate may receive the PFM pulses of the respective phase and the other input may receive a phase select control signal. The access logic may further comprise an OR gate coupled to the outputs of the AND gates and providing the PFM pulse selected by the AND gate for the counting unit. Thus, it can be ensured that only the PFM pulse of the currently selected phase generates a logic "1" output at the respective AND gate, which is then forwarded via the OR gate to a single counting unit. Thus, the counter receives a value corresponding to the presence or absence of a PFM pulse for the selected phase during the respective reference clock period.

According to embodiments, the reference clock may be controllable to operate at different clock rates. The apparatus may further comprise evaluation logic for evaluating the counted number of pulses or the determined pulse width and for controlling the reference clock based on the evaluation result. The clock rate can be selectively reduced to provide a lower energy consumption of the device for determining the output current I _out of the switched power converter. Alternatively, the clock rate may be increased to provide a very accurate determination of the output current I _out .

The evaluation logic may include a comparison element for comparing the counted number of pulses or the determined pulse width to a threshold, and a clock-up or clock-down signal based on the comparison result produce. For low values of the output current I _out , the clock rate can be reduced, and for high values of the output current I _out , the clock rate can be increased. Thus, for high values of _Iout that can be used to control the switched power converter to switch to a PWM controlled mode, a very accurate determination of the output current I _{out can be} provided while power consumption of the current determination during low values of the output current I _out is kept low.

According to embodiments, the reference clock may be disabled during periods when no PFM pulses are available or during periodic intervals in which measurements are not taken. For example, if the reference clock has an RC oscillator, it can be easily paused and restarted to make a current measurement. If the reference clock is disabled during a measurement for periods when no PFM pulses occur, the total measurement time may be determined using an additional clock, for example, at a lower speed.

In another aspect, a switched power converter operating in a pulse frequency modulation (PFM) controlled mode includes a switching element for supplying power to a coil; a PFM modulation unit for generating PFM pulses for driving the switching element; and a device for determining the output current I _{out of} the power converter as described above.

It should be noted that the above-mentioned aspects for a device for determining the output current I _out of a switched power converter applicable to the proposed method as well, and vice versa. Thus, all aspects disclosed for embodiments of the device may be combined in a variety of ways with the proposed method to achieve similar effects and advantages.

These and other aspects of the invention will be elucidated and made apparent by reference to the embodiments described below by way of example with reference to the drawings.

Detailed description

Various aspects will now be described by way of example with reference to the accompanying drawings, in which:

1 an exemplary switching converter system, embodiments of the claimed method and apparatus can be implemented;

2 a diagram of the coil current of the switched converter of 1 and showing the respective clock pulses and timer settings as used in an embodiment of the claimed method and apparatus;

3 shows an embodiment of an output current measurement for a polyphase switching converter;

4 an embodiment of a measurement cycle that may be used in an embodiment of the claimed method and apparatus;

5 shows another embodiment of an output current measurement for a polyphase switching converter;

6 shows another embodiment of an output current measurement for a polyphase switching converter; and

7 shows a modification of an output current measurement for a polyphase switching converter.

1 shows an exemplary switched power converter 100 , The switched converter 100 has a high-side switch 112 (For example, a PMOS transistor) and a low-side switch 111 (For example, an NMOS transistor), as well as a coil 113 and a capacitor 114 on. Depending on the load connected to the output voltage V _out , the switched converter can 100 either in a pulse width modulation (PWM) mode or in a pulse frequency modulation (PFM) mode. The switched power converter 100 further has a control logic and drivers for controlling the switches 111 . 112 on.

In the PWM mode, the duty cycle of the switched converter 100 (ie the duty cycle of the high side switch 112 ) is controlled by voltage feedback, the output voltage V _{out being} connected to a reference voltage V _reference using, for example, a differential amplification unit (also referred to as an error amplifier) 115 is compared, whereby an error voltage V _{error is} provided. The error voltage V _error can be used to regulate the output voltage V _out generated by the converter system 100 is provided by controlling the duty cycle of the high-side switch 112 , Typically, the PWM mode is employed when a relatively high load is applied to the output voltage V _{out of} the switched power converter 100 is connected, ie, when a high output current I _{out is} to be delivered.

In the PFM mode is the switched converter 100 configured to determine the on-phases of the high-side switch 112 based on the error voltage V _error . This can be the high-side switch 112 be turned on when the output voltage V _out falls below the reference voltage V _reference .

On the other hand, the high-side switch 112 are turned off when the output voltage V _{out is} equal to or higher than the reference voltage V _reference . The low side switch 111 can on complementary way to the high side switch 112 switched (ie the low side switch 111 can be turned off when the high side switch 112 is turned on, and vice versa).

Furthermore, a control unit may be provided which includes an RS flip-flop 116 and a comparator 117 having. The RS flip-flop 116 can be used to monitor the coil current using the current limiting comparator 117 , and can be the high-side switch 112 Control such that the high-side switch 112 is turned off when the power to the coil 113 reaches a predetermined current limit I _max . Thus, a current pulse has, as through the switched converter 100 generated in the PFM mode, a generally triangular shape as in the upper diagram in FIG 2 is shown, wherein the coil current increases during a time t _on , while the high-side switch 112 is on and the low side switch 111 is off. When the electricity goes to the coil 113 reaches the current limit reference value I _max , becomes the high-side switch 112 off and the low side switch 111 is turned on for a time t _off . Thus, as in 2 a single PFM coil current pulse is of length t _on + t _off , with the coil current increasing during time t _on until it reaches the maximum value I _max and the coil current decreasing during time t _off until it reaches zero.

Further, if in the PFM mode, the controller may continue to provide an additional RS flip-flop 118 wherein the coil current using a further comparator 119 can be monitored, such as an active diode comparator when the high-side switch 112 is off and if the low side switch 111 is on: The RS flip-flop 118 may be configured to turn off the low side switch 111 upon detecting a zero crossing of the coil current through the further comparator 119 , whereby negative coil currents are prevented. Thus, the coil can 113 remain floating for a rest t _hz (see 2 ) until the high-side switch 112 is turned on again (when detecting an error voltage V _error ). Thus, in the PFM mode, the switched converter sees 100 triangular coil current pulses, wherein the frequency of the pulses is determined based on the load that is connected to the output voltage V _{out of} the switched converter 100 is attached, and wherein the amplitude of the pulses is determined by the maximum coil current I _max . Typically, the PFM mode is used when a relatively low load is applied to the output voltage V _{out of} the switched converter 100 connected is. In summary, thus, the PFM mode consists of triangular PFM coil current pulses, referred to as "PFM pulses" in the following description. The PFM pulses are generated in a discontinuous manner, with the rest time t _{hz being determined} between pulses based on the load associated with the switched power converter 100 connected is. In the following description, the term "PFM cycle" is used to describe a complete cycle of the PFM-controlled coil current, that is, a time equal to t _on + t _off + t _hz , as in _FIG 2 shown.

2 shows a diagram for illustrating the method according to an embodiment. As described above, when a switched power converter is operated in a discontinuous PFM mode, triangular coil current pulses are generated by operating the high side switch 112 and the low side switch 111 in the opposite way. Between the coil current PFM pulses are both the high side switch 111 as well as the low side switch 112 turned off, leaving the coil 113 remains potential-free. The next PFM pulse is triggered when the output voltage V _{out of} the switched converter falls below the reference value V _reference .

According to one embodiment, the output current for a PFM controlled switched converter 100 , operating in a discontinuous mode, can be measured by determining how much coil current is delivered during each PFM cycle. A PFM cycle includes a PFM pulse and includes the time period between successive PFM pulses. The amount of coil current delivered in a PFM cycle may be determined based on determining the amount of charge delivered during the single triangular PFM pulse. Since the maximum coil current I _{max is} known, the charge delivered during each PFM pulse is (1/2) * I _max * (t _on + t _off ) for a triangular coil current pulse. Then, the duty cycle of the discontinuous PFM controlled mode may be determined by determining the ratio of the length of a PFM pulse over the length of a PFM cycle.

wobei I_out (PFM) der Ausgangsstrom ist, der durch den geschalteten Wandler 100 in dem PFM-gesteuerten Modus vorgesehen ist, und I_max der Wert der vorgegebenen Stromgrenze für jeden Strompuls ist, der zum Beispiel von der Steuereinheit zum Steuern der Operation des hochseitigen Schalters 112 verwendet wird.As a result, as in the upper diagram of the 2 shown the current at the coil 113 represents the total time while the power is being supplied, the sum of the "on" time t _on and the "off" time t _{off of} the high side switch 112 , During the rest period t _hz are both switches 111 . 112 closed and no power is applied to the coil 113 delivered. Thus, to the average output current of the switched converter 100 to determine the "on" time t _on , the "off" time t _off, and the length of the PFM cycle using a time reference, such as a clock. Then, for a given PFM cycle, or for a series of consecutive PFM cycles, the charge derived from the PFM Pulse (s) is supplied, divided by the length of the PFM cycle / cycles to calculate the current during the PFM cycle / cycles. Since the maximum current value I _{max of} each triangular current pulse is known and is equal to the fixed current limit I _max in the PFM mode, it is possible to estimate the output current information using the following relationship:

where I _out (PFM) is the output current passed through the switched converter 100 is provided in the PFM controlled mode, and I _{max is} the value of the predetermined current limit for each current pulse generated by, for example, the control unit for controlling the operation of the high side switch 112 is used.

As will be explained in detail below, this measurement depends only on the accuracy of the PFM current limit I _max and the accuracy of the zero-crossing detection performed by the control unit that controls the operation of the low side switch 111 controls as these factors control the charge delivered in a single PFM pulse. The above-described measurement of the output current I _out is independent of the value of the input or output voltages of the switched power converter 100 , It is also independent of coil parameters, such as coil size and inductance of the coil, which affects the slope of the sides of the triangular PFM current pulse but does not affect the total amount of charge per pulse.

The above equation (1) describes the calculation of the output current I _out for a single PFM cycle. However, with the following considerations, the (average) output current I _{out can be determined} over any given measurement time T which is at least as long as a complete PFM cycle. If, as in 2 shown, the pulses of a reference clock are counted when a PFM pulse is active, the result N _count reflects the total duration of all PFM pulses that occur during a measuring time T (see 2 ). The total duration of all PFM pulses during a measurement time T is thus N _count / f, where f is the reference clock frequency. Thus, the ratio (t _on + t _off ) / (t _on + t _off + t _hz ) can be determined by setting a fixed measuring time T, and by selectively counting these clock pulses during the measuring time T, which coincide with PFM pulses from the switched power converter 100 be used. The total PFM pulse duration during the measurement time T thus corresponds to N _count / f, and the ratio of the PFM pulse duration over the PFM cycle thus corresponds to N _count / (f * T) as given in Equation (2):

Thus, using the above relationship, the average output current during a measurement time T can be determined using the number N _count of reference clock counts that match PFM pulses, the reference clock frequency f, and the measurement time T, as set forth in Equation (3) below:

In this case, the measurement time T can be measured using the same reference clock used to determine the number N _count of clock pulses occurring during PFM pulses of the switched power converter. If the measurement time T is chosen to correspond to 2 ⁿ reference clock pulses, that is, such that T = 2 ⁿ / f, the division by (f · T) as shown in Equation (3) can be considered as a simple shift Operation be performed. The selection of a clock frequency f and a measurement time T affects only the quantization error and the accuracy of the result, but introduces no systematic errors in the above-described measurement of the average output current.

The technique described above for determining an (averaged) output current may be extended to switched polyphase converters by providing a separate counter for each single phase of the switched converter. To determine the total output current provided by the switched multiphase converter, the results from all of the counters can be added to determine a value N _count which is proportional to the output current I _{out of} the switched one Multiphase converter is, as for example in the in 3 shown embodiment, which will be described in more detail below.

The following section looks at the digital side of implementing the invention, that is, presenting a number of embodiments for implementing the above-described concept. In general, pulses of a digital reference clock signal are counted during one or more (analog) PFM pulses and the number N _count of reference clock pulses during the PFM pulse / pulses is then divided by the total number N _total of reference clock pulses during a measurement time T and multiplied by a constant value I _max / 2. As stated above, the digital page is responsible for arithmetically counting (or calculating) the total duration of the PFM pulses coming from the analog side. This information is in turn converted into a number representing the output current provided by the switched power converter, and thus also representing the load connected to the switched power converter.

In the 3 to 6 The illustrated embodiments represent three different respective architectures for implementing the method described above.

3 shows a device 200 for measuring the output current of a switched polyphase power converter 100 (please refer 1 ). The device 200 from 3 is generated according to the general architecture of "count, then sum", with the respective PFM pulses of each phase of the switched power converter being applied to multiple inputs 201 the device 200 be provided. For every entrance 201 is a separate counting unit 202 provided for counting the clock pulses during an analog PFM pulse, as above in connection with 2 explained. 4 shows the corresponding signal waveforms for operation of the device of FIG 3 ,

The respective results of each counting unit 202 are then calculated using summation logic 203 and then may be further processed in a register or storage device 204 be registered. The whole scheme is done using a finite state machine (FSM). 205 controlled.

Each counting unit 202 has several components that work together to provide the digital summation of the respective clock signal and to isolate the digital processes from the analog asynchronous PFM pulses. During operation of the device 200 sends the FSM 205 a "start" control signal to each of the counting units 202 (please refer 4 ). The counting units 202 each have a blocking gate 206 which blocks the analog PFM pulses when no measurement is made. In the in 3 The specific implementation shown is the blocking gate 206 an AND gate, but also other implementations, for example with an OR gate or a multiplexer, are also possible.

The PFM pulses, which are now free for distribution to the next stage, become the next blocking gate 207 fed. This barrier gate 207 generates a signal, the clock pulses from a reference clock 208 (see "Fast Clock" signal from 4 ) at its output only if the analog PFM pulse is high and if the measurement is currently being performed, as from the FSM 205 signaled. Thus, the blocking gate gives 207 a "pulse to gate" signal as in 4 shown. According to some embodiments, the above-described blocking gates 206 and 207 be combined into a single logic gate.

After passing the barrier gate 206 . 207 the pulses become a counter 209 and the number of pulses is counted separately per phase. Throughout this time, the last barrier gate is forcing ahead 210 the output of the counting unit 202 to a logical "0". The reason for using such a last blocking gate 210 is twofold: on the one hand, disturbances can be caused by the summation logic 203 can be prevented and on the other hand, the switching rate and thus the energy consumption of the counting unit 202 and the summation logic 203 by using the last blocking gate 210 be reduced.

The FSM 205 sends an "end" control signal to the last inhibit gate 210 which then allows the content of each counter 209 through to the summation logic 203 to be spread. In the embodiment of 3 is the architecture of the meter 209 Of less importance and there may be several options for a suitable counter 209 although a low-power architecture for the counter 209 is desirable.

The last barrier 210 can be implemented with a mux or other logic that guarantees the output of the blocking gate 210 is forced to a stable known value, as long as the "end" control signal, which signals the end of the measurement period after a measurement time T, from the FSM 205 not arrived.

After the "end" control signal on the respective blocking gates 210 are received, the in the respective n-bit counters 209 stored stable values to the summation logic 203 supplied for generating the sum of the respective counts of all phases. The result is in the register 204 stored and subsequently removed from the register 204 read, for example by using a "sample" control signal (see 4 ). Upon receipt of the "sample" control signal, the counters may 209 be reset. The FSM 205 returns to its initial state and the measurement cycle can begin again.

From the value in the register 204 is stored and sampled from it, the output current I _{out of} the polyphase converter can be determined, as described above. The particular output current value I _out may then be further processed and, for example, compared to a threshold, such as a threshold current value for changing the operation of the switched power converter to a PWM controlled mode, or may be analyzed for particular statistical characteristics.

5 shows a further embodiment of a device 200 for measuring the output current of a polyphase power converter. According to this embodiment, the sum result about the clock signals during the respective PFM pulses is achieved in another way. The inherent difference between the embodiment of 5 in comparison to the embodiment of 3 in that, instead of counting the reference clock pulses for each separate analog PFM pulse input of each of the phases of the polyphase converter, the active analog PFM pulses of all phases are added first in each reference clock cycle and then accumulated.

In the embodiment of 5 lead the blocking gate 206 and 207 and the reference clock 208 similar functions as described above in connection with 3 described. Thus, there is at the output of the blocking gate 207 a "clock pulse after gate" signal, similar to that in 4 shown "pulse to gate" signal when the FSM 205 triggered the measurement process by sending a "Start" control signal (see 4 ). However, for the present embodiment, the "pulse-to-gate" signal for each individual phase of the switched power converter will become a respective memory element 211 fed. The memory elements 211 may comprise RS flip-flops, wherein the set input receives a signal when the pulse of the reference clock coincides with a PFM pulse on the respective phase of the switched polyphase power converter. The reset input is connected to the inverted reference clock signal. Thus, an undetermined state of the RS flip-flop 211 because the values applied to the set and reset inputs can not change simultaneously, but are associated with different values of the same reference clock signal.

The output of all memory elements 211 is due to the summation logic 203 summed. Below is the result, as by the summation logic 203 for the present reference clock, with previous summation logic values 203 through an accumulator 209 sums up the second summation logic 212 having. Thus, after the measuring time T holds the accumulator 209 the respective total _count N _count for all phases of the switched multiphase converter.

In the present embodiment happen on the falling edge of the signal of the reference clock 208 two things: the accumulator / counter 209 is updated with the new value of the reference clock pulse counter during the measurement time and the memory elements 211 are reset and ready for the next incoming pulse.

After the measurement time T has expired, the FSM sends 205 the "end" control signal (see 4 ), which is the last barrier gate 210 releases, and in the accumulator 209 stored value can then be as previously in the "result" tab 204 get saved.

In a modified embodiment, the last blocking gate 210 be removed as the result of the accumulator 209 is provided in synchronism with the digital reference clock signal, since the accumulator is on the falling edge of the reference clock 208 is clocked. In summary, the embodiment of 5 a method and apparatus incorporating a single accumulator 209 can be used to sum all incoming pulses with each clock edge.

In a further modification of the embodiment described above, a system is provided in which the plurality of parallel PFM pulses from different phases of the same switched converter 100 such as a down-converter. Thus, a strong correlation between the respective lengths and frequencies of the different PFM pulses can be assumed. In this case, it is possible according to a further embodiment, the complexity of the device 200 to further reduce and thus reduce energy consumption by using a "counter-jump" scheme, as in 6 shown.

According to the in 6 shown embodiment is a pulse measuring unit 214 which captures only a single analog PFM pulse signal during each measurement process. In the end, the result can be at the output 215 the pulse measuring unit 214 is provided, adapted and multiplied by the number of phases, so that the output of the device 200 reflected the average current of the entire switched multiphase converter system.

As in the above description, the analog PFM pulses hit an input 201 the device 200 and are through a first blocking gate 206 blocked. The FSM 205 generates phase selection control signals (a), (b), ... (n) such that only one phase selection control signal has a logic value "1" while the remainder are logic "0". This transfers the AND gate 206 only the selected phase of the switched multiphase converter to the OR gate on 213 that combines all the information into a single signal that reflects the presence or absence of a PFM pulse on the selected phase. The structure with the AND gates 206 and the OR gate 213 may be considered as "an active multiplexer" with only one of a plurality of incoming phase signals in the pulse measurement unit 214 is issued.

Then that is through the OR gate 213 generated pulse in the pulse measuring unit 214 entered. According to the illustrated embodiment, only a single counter is used. The functionality of the system with respect to the "start", "end" and "sample" signals (see 4 ) is identical to the one described above. In the embodiment of 6 takes care of the FSM 205 that the switching between the different control signals ((a), (b), (n)) is carried out in a "clean" way. When the selected phase. during a PFM pulse on the currently selected phase, the last selected PFM pulse and the first selected PFM pulse could overlap the newly selected phase, giving the impression of an excessively long PFM pulse on a single phase. Thus, the switching is performed only after the last PFM pulse on the previously selected phase is completed, to avoid counting overlapping PFM pulses from different phases together in the same measurement period.

A modification of the device 200 for determining the average output current of a switched converter, as in 7 shows further means for reducing power consumption by dynamically scaling the frequency of the reference clock depending on the required measurement accuracy. With a higher frequency of the reference clock 208 For example, a better resolution is achieved by measuring the analog PFM pulse width and the output current and load of the power converter can be determined with higher accuracy. However, sampling the PFM pulse at higher frequencies means higher power consumption for the measuring device.

At very low loads, with long pauses between two analog PFM pulses, it may be possible to reduce accuracy and instead achieve lower power consumption. As described for the previous embodiments, the analog PFM pulses become the device 200 at the variety of entrances 201 supplied and are by the pulse measuring unit 214 counted. The measurement is done by the FSM 205 controlled.

After the measurement is complete and a result at an output 215 the device 200 available compares a comparison logic 216 the result with a programmable upper and / or lower threshold by the FSM 205 can be provided.

Depending on the comparison, the comparison logic generates 216 a "faster / slower" (clock rate up or down scale) signal sent to a clock divider 217 is supplied. The clock divider 217 effectively reduces the frequency of the fast reference clock 208 and provides a frequency reduced clock signal to the pulse measurement unit 214 when the determined result for the output current I _{out is} low. The pulse measuring unit 214 then operates at a lower clock frequency (with less accuracy) for the next measurement, so that the pulse measurement unit 214 consumes less energy. If the result 215 increases and the determined output current I _out exceeds a programmable upper threshold, the turn of the FSM 205 can be provided, the comparison logic 216 output a signal representing the clock divider 217 causes the clock frequency to increase to the pulse measurement unit 214 is directed. Thus, the accuracy of determining the converter output current and the load at higher clock frequencies can be increased again. By providing the programmable upper and lower thresholds used by the FSM 205 can be dynamically varied in different operating ranges, and the trade-off between measurement accuracy and power consumption can be adjusted based on the system power requirements.

To provide a high accuracy of the current measurement, the frequency of the reference clock 208 be high, even more than 20 MHz. Thus, the total energy consumption of the device 200 can reduce the reference clock 208 be disabled between measurements. Because the reference clock 208 is not very accurate, since only the ratio N _count / N _total and not the actual number of counts is used in the current measurement, the reference clock can 208 be implemented as an RC oscillator that can be turned on and off at any time.

Further, the power consumption of the device can be reduced by making current measurements less frequent, such as performing a measurement cycle with a measurement time T of 20-100 ms every second. Depending on the length of the PFM cycle, shorter or longer measuring times T can be selected. The measurement time T must be at least as large as a full PFM cycle, for low loads associated with the power converter 100 typically about 10 ms. Depending on the coil voltage and other factors, the length of a PFM cycle may vary by more than an order of magnitude.

The FSM 205 can be implemented to be at a slower clock frequency than the reference clock 210 works to high operating frequencies in the FSM 205 to avoid what would increase energy consumption.

The various embodiments allow accurate determination of the output current and the load of a switched power converter, wherein the measurement does not affect the converter output voltage or current, and the energy consumption of the measurement is at a very low level. Using a high frequency pulse width counter and a fast reference clock, the present method and apparatus provide an estimate of the length of the current pulses in a switched-mode PFM mode. Since the maximum coil current I _{max of} the switched converter is known in the PFM mode, the output current of the switched converter can be determined by measuring the duration and frequency of the PFM pulses. Thus, an indirect current measurement can be performed without affecting the current flow in the switched power converter. Some embodiments provide for determining the output current of a polyphase switched converter using only a single counting unit. Thus, the output current of a single-phase or multi-phase switched power converter can be accurately determined in a PFM-controlled mode while keeping the power consumption of the measuring apparatus low.

It should be noted that the description and drawings merely illustrate the principles of the proposed methods and apparatus. It is thus apparent that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included in their spirit and scope. In addition, all of the examples given here are expressly provided for educational purposes only to assist the reader in understanding the principles of the proposed methods and systems, and the concepts contributed by the inventors are for the advancement of the art and are intended to be without Be limited to such specific examples and conditions. In addition, all statements herein are intended to recite the principles, aspects, and embodiments of the invention, as well as specific examples thereof, the equivalents thereof.

Finally, it should be noted that all block diagrams herein represent conceptual views of illustrative circuit arrangements embodying the principles of the invention. Likewise, it will be understood that all of the flowcharts, flowcharts, state transition diagrams, pseudocode, and the like, represent various processes that may be substantially represented in a computer readable medium and thus executed by a computer or processor, whether such computer or processor is explicitly shown, or Not.

Claims (21)

A method of determining the output current I _{out of} a switched power converter operating in a pulse frequency modulation (PFM) controlled mode, comprising - determining a pulse width of at least one PFM pulse for driving a switching element of the power converter; and determining the output current I _out based on the determined pulse width and on the maximum coil current I _{max of} the power converter when in the PFM controlled mode, wherein determining a pulse width comprises counting a number of pulses N _{count of} a reference clock during the at least one PFM Pulse in at least one PFM cycle. The method of claim 1, wherein counting a number of pulses occurs during a given measurement time T and the reference clock operates at a clock frequency f, the output current I _{out being} determined based on the maximum coil current I _max , the counted number of pulses N _count , the clock frequency f and the measuring time T. The method of claim 2, wherein the output current I _{out is} determined based on the maximum coil current I _max times the ratio of the counted number of pulses N _count over the product of clock frequency f and measurement time T. The method of claim 2 or 3, wherein the measurement time corresponds to an integer multiple of the clock period, the multiple being a power of 2. Apparatus for determining the output current log _{t of} a switched power converter operating in a pulse frequency modulation (PFM) controlled mode, comprising: a reference clock for generating count pulses having a frequency f; A counting unit for determining a pulse width of at least one PFM pulse in order to drive a switching element of the power converter, wherein the counting unit counts a number of counting pulses N _{count of} the reference clock during the at least one PFM pulse; and a calculation unit for determining the output current I _out based on the determined PFM pulse width in at least one PFM cycle and the maximum coil current I _{max of} the power converter when in the PFM controlled mode. The apparatus of claim 5, further comprising a control unit for generating control signals for starting and stopping the pulse count and for sampling the counted number of pulses and calculating the output current I _out based thereon. The apparatus of claim 6, wherein the control unit comprises a state machine and generates the control signals in various states of the state machine. The apparatus according to one of claims 5 to 7, wherein the counting unit comprises an n-bit counter or an accumulator. The apparatus of any one of claims 5 to 8, wherein the counting unit comprises a first logic gate receiving the PFM pulses and a start signal and a second logic gate receiving the count pulses and the output of the first logic gate. The apparatus of any one of claims 5 to 9, wherein the switched power converter is a polyphase converter, the apparatus having a number of counts, one for each phase of the polyphase converter, and a summation unit for summing the counts of the individual counts, the computing unit determining the output current I _{out determined} based on the total number of count pulses for all phases. The apparatus of claim 10, wherein each counting unit comprises an n-bit counter and a counter gate controlled by the control unit, the summing unit being connected to all counters via its respective counter gate and being controlled by the control unit, to add all counts after the measurement time T has elapsed. The apparatus of any one of claims 5 to 9, wherein the switched power converter is a multi-phase converter, the apparatus having a single counting unit for counting the counting pulses for all Phases, wherein the counting unit has a respective first and second logic gate and a storage element for each phase, wherein the respective output of the second logic gate of a phase is connected to an input of the storage element for the phase, wherein the counting unit further comprises a summation unit for summing the number of active phases for one pulse period of the reference clock. The apparatus of claim 12, wherein the counting unit comprises an accumulator for accumulating the number of counting pulses of all phases during the measuring time T. The device of claim 13, wherein the memory elements are RS flip-flops with their reset input connected to the inverted reference clock. The device of claim 13 or 14, wherein a clock input of the accumulator is connected to the inverted reference clock. The apparatus of any one of claims 5 to 9, wherein the switched power converter is a multi-phase converter, the apparatus having a single counting unit and access logic for selecting, during a time period, a PFM pulse or multiple one-phase PFM pulses and forwarding to the counting unit for determining a pulse width of the PFM pulse (s), wherein the selected phase rotates among the plurality of phases, wherein the calculating unit adjusts the counted pulses by the number of phases. The apparatus of claim 16, wherein the access logic comprises an AND gate for each phase, wherein one input of the AND gate receives the PFM pulses of the phase and the other input receives a phase select control signal, the access logic further being an OR gate which is coupled to the outputs of the AND gates and provides a selected PFM pulse for the counting unit. The apparatus of any one of claims 5 to 17, wherein the reference clock is controllable to operate at different clock rates, the apparatus further comprising evaluation logic for evaluating the counted number of pulses or the determined pulse width and for controlling the reference clock based on the evaluation result. The apparatus of claim 18, wherein the evaluation logic comprises a comparison element for comparing the counted number of pulses or the determined pulse width to a threshold and generating a clock faster or clock slower signal based on the comparison result. The apparatus of any one of claims 5 to 19, wherein the reference clock can be deactivated during periods of time when no PFM pulses are available or during periodic intervals in which measurements are not taken. A switched power converter operating in a pulse frequency modulation (PFM) controlled mode, comprising: a switching element for supplying power to a coil; A PFM modulation unit for generating PFM pulses for driving the switching element; and - an apparatus for determining the output current I _{out of} the power converter according to one of claims 5 to 20.

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