DE102014218384B3 - Recovery of a binary response pattern from a noisy channel - Google Patents

Abstract

A computer-implemented method comprising: repeating code decoding (S402) an errored word (v '') from a noisy channel (201) to obtain a repetition code decoded word (v '); Determining (S403) soft information (L) based on the erroneous word (v '') and the repetition code decoded word (v '); and cortex decoding (S404) the repetition code decoded word (v ') to reconstruct the input word (w) based on the soft information (L).

Description

FIELD OF THE INVENTION

The invention relates to the field of error correction and error detection in data transmission, in particular to a method for quickly and reliably recovering a binary bit pattern in a noisy channel, whereby aging effects are also taken into account.

BACKGROUND OF THE INVENTION

Noisy data occurs when physical measurements are taken. Safe information retrieval from a noisy channel is always a challenge. Currently used methods use common error-correcting codes. The problem is that these codes are often complex and the implementation takes a lot of resources. There are also limits to the possibility of correcting a certain number of errors in the measured data. In addition, aging effects (change in the behavior of the data over years) are usually not taken into account.

The International Patent Publication WO 2013/083415 A2 discloses a cryptographic system for reproducibly generating a reliable string, such as a cryptographic key from a noisy Physically Unclonable Function (PUF).

JC Carlach, A. Otmani, and C. Vervoux in "A New Scheme for Building Good Self-Dual Block Codes", Proceedings of the IEEE International Symposium on Information Theory, 2000, describe a very simple multilevel coding scheme for self-dual codes, using a [8,4,4] extended Hamming code as short base code and bit permutations (or interleavers as in turbo codes) between the stages.

P. Adde, D. Gomez Toro, and C. Jego in "Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes," IEEE Transactions on Signal Processing, July 2012, pages 3914-3919, describes a maximum likelihood decoding method for linear block codes and an algorithm based on the Chase-2 algorithm for the decoding of systematic binary block codes.

V. van der Leest, B. Preneel, and E. van der Sluis in "Soft Decision Error Correction for Compact Memory-Based PUFs using a Single Enrollment", Proceedings of the 14th International Workshop, Leuven, Belgium, September 9-12, 2012, pages 268-282, describe secure key storage in hardware as an essential building block for high-security applications. It is demonstrated that by soft-decision decoding with only a single measurement during storage, the number of SRAM cells required can be reduced without increasing the size of the en / decoder.

The international patent application WO 2009/099308 A2 discloses a method of transmitting control information in a radio communication system, the method being based on block and repetition code coding.

Adde, Patrick et al, in "Design and Implementation of a Soft Decision Decoder for Cortex Codes", IEEE International Conference on Electronics, Circuits and Systems, 2010, pp. 663-666, ISBN 978-1-4244-8155-2 , describe an implementation of a soft-decision cortex decoder.

From the European patent application EP 2 773 061 A2 For example, linkage of a reconstructed signal with helper data is known in order to obtain an error-free signal.

The challenge of such error-correcting methods requires finding a compromise between the error-correction capability and the algorithm's efficiency.

Therefore, there is a need to provide efficient solutions with good error correction capability.

SUMMARY OF THE INVENTION

According to a first aspect, the invention provides a computer-implemented method comprising: repetitive code decoding of an erroneous word which is noisy by one Channel is obtained to obtain a repetition code decoded word; Determining soft information based on the errored word and the repetition code decoded word; and cortex decoding the repetition code decoded word to reconstruct an input word based on the soft information.

According to a first aspect, the invention provides a computer-implemented method comprising: cortex-coding an input word to obtain a cortex codeword; Repetition code coding of the cortex codeword to obtain a cortex repeat code codeword; and linking the cortex repeat code codeword to a binary signal obtained from a noisy channel to generate helper data.

Further aspects of the invention are set forth in the dependent claims, the following description and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be explained by way of example with reference to the accompanying drawings, in which:

1 schematically shows an embodiment of Enrolments according to the present invention;

2 schematically shows an embodiment of a reconstruction according to the present invention;

3 schematically shows an embodiment of an enrollment process according to the present invention;

4 schematically shows an illustration of a reconstruction process according to the present invention;

5 schematically shows a three-stage coding scheme using the extended [8, 4, 4] Hamming code as a short base code and two bit permutations between the three stages;

6a and 6b schematically shows an application in which the cortex retry code is used to secure an application key; and

7 schematically shows an embodiment of a method for determining the number of errors in a faulty word, which can be used for example for a warning function.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Before the detailed description of the preferred embodiments, a few general explanations will be made.

In the following embodiments, a method is described, comprising: repeating code decoding an errored word obtained from a noisy channel to obtain a repetition code decoded word; Determining soft information based on the errored word and the repetition code decoded word; and cortex decoding the repetition code decoded word to reconstruct an input word based on the soft information.

The noisy channel could be any noisy channel. Preferably, the noisy channel is a noisy channel with an error rate in the range between 0 and 20%. According to the embodiments described below, the noisy channel is a Physically Unclonable Function (PUF). A "Physically Unclonable Function" is a physical entity embedded in a physical structure that is easy to evaluate but difficult to predict. According to the embodiments described below, the noisy channel is a Physically Unclonable Function based on static random access memory (SRAM PUF).

Alternative noisy channels could be, for example, Delay PUFs, Butterfly PUFs, Bistable Ring PUFs, or the like. In yet alternative embodiments, the noisy channel could be a telecommunications channel such as GPRS, UMTS, WLAN, a powerline communication channel, or the like.

The errored word could be any form of bit sequence obtained from a noisy channel. In the embodiments described below, the errored word corresponds to a noisy PUF response. In particular, in the embodiments, the erroneous word is a noisy PUF response combined with helper data obtained in an enrollment process. The errored word may be, for example, a bit sequence of 120 bits which has been combined with helper data of 120 bits in length. Combining the noisy PUF response with helper data may include, for example, an XOR operation of the faulty PUF response and the helper data.

The helper data according to the embodiments may therefore be seen as an XOR-linked version of a cortex repeat code coded input word and a binary signal derived from a noisy channel.

The binary signal from a noisy channel could be, for example, a PUF response, for example a 120 bit bit sequence, obtained from a SRAM PUF. For example, combining the binary signal from a noisy channel and the cortex repeat code encoded input word may include an XOR operation on the noisy input data and the cortex repeat code encoded input word.

According to the embodiments, the method is used to reconstruct an input word used in an enrollment phase to generate a cortex repeat code codeword.

The input word obtained by the method can then be re-encoded to reconstruct a cortex repeat codeword used in the enrollment.

The cortex repeat code codeword reconstructed therewith can then be used to reconstruct an error-free binary signal from a binary signal. The reconstructed binary signal should correspond to the binary signal which was cortex repeat coded during the enrollment phase. The thus obtained error-free binary signal can be seen as a reconstruction of the noisy channel binary signal, which was cortex-replicated during the enrollment phase. In particular, the error-free binary signal can be, for example, a fault-free PUF response.

According to the embodiments described below, the errored word is repetitively decoded to obtain a repetition code decoded word. The idea of a retry code is to repeat a message several times. Repeat code decoding could be performed, for example, by determining the value of a particular bit by looking at the obtained copies of that bit and choosing the value that most often occurs. Repeat code decoding could be performed, for example, according to the well-known majority logic detection. In the embodiments described below, a (5, 1) repetition code is applied to an erroneous word. Thus, if repetition code decoding is applied to an errored word of length 120 bits, it can be assumed that the original code word of 24 bits has been repeated five times. According to this example, repetition code decoding results in a repetition code decoded word of 24 bits in length.

According to the embodiments described below, the method also includes determining soft information based on the errored word and the repetition code decoded word. Soft information may be any information describing the defectiveness of the individual bits of the errored word. In addition, the soft information could specify the locations where errors are most likely to happen. According to the embodiments described below, the determination of the soft information includes the determination of the bit error probabilities based on the errored word and the repetition code decoded word. In this case, the soft information is a vector whose elements represent the number of errors in the normally healthy blocks of the errored word.

In the embodiments, the Rep (5, 1) code is used as a repetition code. In these embodiments, the elements of the soft information can only take on the values {0, 1, 2}. The values are determined in this case by calculating the sum of the individual repeat blocks (5 bits). If the sum is 0 or 5, the soft information equals 0. If the sum is 1 or 4, this corresponds to soft information 1, and if the sum is 2 or 3, it is equal to 2 for the soft information.

In addition, a warning function could be used which triggers an alarm or forces the system implementing the method to shut down if the number of errors reaches a certain limit. In the embodiments, two ways of calculating the number of errors are described. On the one hand, it is possible to use the soft information obtained during the repetition code decoding, which requires almost no additional effort. However, in this way it is only possible to determine the magnitude of the number of errors and not the exact value. Also, the exact number of errors can be determined by re-encoding the cortex decoded word, that is, the input word resulting in the cortex repeat code codeword. The codeword is then compared with the errored codeword and the number of errors is determined. This could include, for example, an XOR operation of the cortex repeat code codeword and the erroneous word.

The expense of re-encoding is not significant because the cortex and repetitive code coding work very efficiently.

According to the embodiments described below, the methods further include cortex decoding the repetition code decoded word to reconstruct an input word using soft information.

Cortex decoding (and encoding) could be performed, for example, according to a turbo-code mechanism.

For example, the cortex coding could be based on a multi-level coding scheme, using the extended Hamming code as base code and permutations between the individual stages. In the embodiments, the cortex code is a G [24, 12, 8] Golay code. The base code is a self-dual extended Hamming code and a three-level implementation with two interleavers (permutations) is used.

In the embodiments, a soft-decision decoding method is employed, i. H. additional information about the bit error probability is collected (using repetitive code decoding) to make the decoding more efficient. The soft decoding enables the generation of error patterns and the addition of these error patterns to the erroneous binary signal, the result being re-encoded until the Euclidean distance to the received word is minimal. For repeated coding, the existing encoder block can be reused. Thus, the effort of the decoder can be reduced.

In case less than four unreliable positions are found, the remaining error patterns can be filled up. According to the embodiments described below, a pseudo-random generator can be implemented which returns values between 1 and 12 with equal probability.

In the event that more than four unreliable positions are marked, the error pattern positions can be reduced with the same procedure.

According to the embodiments described below, the method further comprises re-encoding the recovered input word to reconstruct the cortex repeat code codeword. This re-coding of the input word may include, for example, cortex coding of the input word to obtain the cortex codeword, and repetition code coding of the cortex codeword to obtain the cortex repeat codeword. According to the embodiments described below, the cortex coding is based on a multi-level coding scheme using extended Hamming code as base code and bit permutations between the stages. For example, in the embodiments described below, the cortex decoding is based on a three-level coding scheme using a [8, 4, 4] extended Hamming code as a short base code and two bit permutations between the three stages. The repetition code coding may be on the same repetition code which was applied during the repetitive code decoding of the erroneous word, for example, a (5, 1) repetition code.

The re-encoding results in a reconstructed cortex repeat code codeword. According to the embodiments below, the reconstructed cortex repeat code codeword corresponds to the cortex repeat code codeword used during enrollment to XOR to a binary signal originating from a noisy binary channel when the number of errors does not exceed the error correction capability.

The method could further include combining the reconstructed cortex repeat code codeword with the helper data to reconstruct a noiseless channel noise-free signal. As described above, the helper data could be helper data produced during enrollment by XORing a binary signal from a noisy channel to the cortex repeat code codeword. For example, combining the reconstructed cortex repeat code codeword with the helper data could mean an XOR operation of the reconstructed cortex repeat code codeword with the helper data.

The embodiments as described above may also treat inherent aging effects. For example, aging effects of SRAM could cause bit errors, which are efficiently corrected by the methods described above.

In the above-described embodiments, a method is also described which involves cortex-coding an input word to obtain a cortex codeword; a repetition code coding of the cortex codeword to obtain a cortex repeat code codeword; and combining the cortex repeat code codeword with a binary signal originating from a noisy channel to generate helper data.

For example, this method could be used to encode an input word with the cortex repeat code in an enrollment process and XOR the resulting cortex repeat code codeword with a binary signal originating from a smoky channel.

The helper data produced during the enrollment process, as described above, could be used as helper data, in any of the reconstruction methods described above, to reconstruct an error-free binary signal from a noisy channel.

According to the embodiments, the methods described above are computer implemented. The methods can be implemented in hardware and / or software.

The embodiments described in more detail below also illustrate a system configured to perform the methods described above.

The system could include a cortex encoder and a repeater encoder, the cortex encoder and the repeater code encoder arranged to perform cortex coding and repeat code coding, respectively, as described above.

The system could also include a cortex decoder and a repeater decoder, the cortex decoder, and the repeater decoder are configured to perform cortex decoding as described above.

The cortex decoder and / or encoder can be implemented in hardware or software. Hardware implementation is preferred for efficiency.

In addition, the system may include XOR units that are designed so that XOR operations of input data with other input data can be performed to obtain XOR-linked data.

The system may implement a method to efficiently recover a clear binary signal from a noisy channel, as described above. Due to the arrangement of the two error correcting codes, which allow a quick and easy hardware implementation, the required hardware Resources minimal. The described procedure allows a low-resource implementation due to the innovative interconnection of the two efficient error-correcting codes.

Furthermore, an anti-aging protocol could be inherently implemented which increases the stability of the system over years.

A possible fault monitoring functionality could be provided without additional resources needed with the existing setup. Such functionality ensures that the device shuts itself off as soon as a certain number of errors occur.

For example, an FPGA board (Virtex 5) could be used to implement the Cortex Encoder / Decoder and / or the Repeat Encoder / Decoder and / or the XOR units.

The methods and systems described above, and the detailed description of the embodiments below, could provide a number of possibilities. For example, according to the embodiments, a PUF response is used as the noisy binary channel. The occurring errors are in this case usually equally distributed (no block errors). According to the embodiments based on a 120-bit cortex repetition code codeword, due to the definition of the codes, repetitive code decoding can already correct up to 48 even errors in 120 bits (equivalent to 40%). In particular, if the errors occur in blocks smaller than 5, 32 errors can be corrected in 120 bits in any case (corresponding to 26%). In order to counter block errors more efficiently, the embodiments described below can be easily changed in that instead of the (5, 1) repetition code, a (7, 1) or (11, 1) repetition code is used. This increases the error correction capability, but increases the complexity of the methods. In known embodiments, PUF responses are subject to an error rate of 2-12%, as a result of which the embodiment described below (with Rep (5, 1)) appears to be adequately dimensioned.

The determination of the soft information could provide additional information as to how bit flips change over time, i. H. You get an indication of the aging behavior of the device, which can be considered directly.

Detailed embodiments will now be described with reference to the drawings.

1 schematically shows an embodiment of the enrollment according to the present invention.

A SRAM PUF 101 acts as an example of a noisy channel. SRAM PUF 101 generates a PUF response R which, according to this embodiment, represents a binary bit pattern with a length of 120 bits.

A cortex encoder 103 is intended to obtain a binary input word w of length 12 bits. The input word w is chosen randomly. The cortex encoder 103 This embodiment is a hardware implementation of the mechanism described in more detail below in the chapter "Cortex Encoding". The cortex encoder 103 applies a three-level coding scheme to the input word w, which uses a [8, 4, 4] extended Hamming code as a short base code and two bit permutations between the three stages. The cortex encoder 103 delivers as output a cortex codeword c 'of length 24 bits. The 24-bit cortex codeword c 'can be considered a corresponding [24, 12, 8] Golay codeword.

The 24-bit cortex codeword c 'continues to a repetition encoder 105 which applies a Rep (5, 1) code such that each bit is repeated 5 times. The functionality of the retry encoder 105 is described in more detail in the chapter "Repeat Code Encoding". The repeat encoder 105 provides as output a 120 bit cortex repetition code codeword c.

The 120-bit cortex repetition code codeword c becomes the PUF response R in an XOR unit 107 added to produce the 120-bit long helper data HD. The XOR unit 107 In this embodiment, an XOR operation of all bits of the PUF response implements R with the respective bits of the cortex repeat code codeword c.

2 schematically shows an embodiment of the reconstruction according to the present invention. The reconstruction receives noisy data as an input parameter, here an error-prone word c "of length 120 bits, which is obtained by a PUF response R '(here also, error-prone input data') of length 120 bits from the SRAM PUF 201 with helper data HD of length 120 bits, using an XOR unit 211 be combined. For the purpose of this embodiment, the SRAM are PUF 201 which is used in the reconstruction ( 2 ), and the SRAM PUF 101 which is used in enrollment ( 1 ), and the helper data HD used in the reconstruction are identical to the helper data obtained in enrollment ( 1 ).

The reconstruction starts with a repetition code decoding of the obtained erroneous word v "with the aid of the repetition decoder 203 whereby a repetition code decoded word v 'of length 24 bits and soft information L (eg information about the error probability of the individual bits) are obtained (soft decoder). The functionality of the repeat decoder 203 is described in more detail below in the chapter "Repeat Code Decoding". According to the embodiment, the soft information L is obtained by counting the noisy bits in the separate repeat blocks during the repetition code decoding, for example as described below in the chapter "Determination of soft information". Error-free blocks are expected from either all ones or all zeros, but certain bits are flipping due to noise and the number of bits flipped is a clear indication of the error probability of certain bits. This soft information L becomes the cortex decoder 205 continued, which allows an efficient decoding procedure, since with a high probability the correct error pattern for the decoding are generated.

The repetition code decoded word v 'of length 24 bits is then passed to the cortex decoder 205 , which performs cortex decoding in consideration of the soft information L. The functionality of the Cortex decoder 205 is described in more detail in the chapter "Cortex Decoder" below. Cortex decoding in the Cortex decoder 205 results in a codeword v of length 24 bits. If all the errors have been corrected, then the information bits of this codeword v, ie the 12 bits on the far left correspond exactly to the coded message, ie they are identical to the input word w of 12 bit length, which during enrollment corresponds to the cortex encoder (FIG. 1 ) was supplied.

The recovered input word w of 12 bits in length is then read using the cortex encoder 213 and the repeat encoder 215 re-encodes to recover the 120-bit cortex repeat code codeword c. The functionality of the Cortex encoder 213 and the repeat encoder 215 is identical to the functionality of the Cortex encoder 103 and the repeat encoder 105 in 1 , The same encoding process, regarding the encoder execution in 1 can be used to obtain the 120-bit length cortex repeat code codeword c. In particular, the cortex encoder can 213 and the repeat encoder 215 identical to the Cortex encoder 103 and the polling encoder 105 (for example, an identical physical unit or software could be used for these units).

The newly recovered 120-bit cortex repeat code codeword c, which was obtained after re-encoding, is then used with the helper data HD of length 120 bits using the XOR unit 217 XOR-linked to recover the flawless PUF response R of 120 bits in length as a noise-free binary signal. The helper data HD, which is the XOR unit 217 are identical to the helper data HD, which is the XOR unit 211 be supplied. These helper data HD correspond to the helper data obtained during enrollment ( 1 ) were won. Since the helper data HD and the cortex repeat code codeword c are identical to the values obtained in enrollment, the recovered PUF response R of 120 bits is identical to the PUF response R of the enrollment process in FIG 1 , That is, with the help of the reconstruction process, the PUF response R as noise-free binary data from the noisy channel 201 be won.

According to this embodiment, due to the concatenation of the two error correcting codes (cortex code and repetition code) and the calculation of the soft information for the cortex decoder, random errors can be corrected efficiently.

Since information about bit flips is computed during each decoding step in the repetition decoder, the method described here inherently takes into account changes in the output signal that could happen over the life of the system (aging).

3 describes schematically an embodiment of the enrollment process according to the present invention. In step S301, the binary input word w (12 bits) is encoded with a three-stage cortex encoder to obtain a cortical codeword c '(24 bits). In step S302, the cortex codeword c 'is coded with a repetition code Rep (5,1,5) to obtain a cortical repetition code codeword c (120 bits). to obtain. In step S303, the PUF response R (120 bits) and the codeword c (120 bits) are XOR-linked, and the result is stored the helper data HD (120 bits).

4 describes schematically an embodiment of the reconstruction process according to the present invention. In step S401, a noisy PUF response R '(120 bits) and helper data HD (120 bits) is XORed to obtain an erroneous word v''(120 bits). In step S402, repetition code decoding is applied to the errored codeword v '' to generate the repetition code decoded word v '(24 bits). In step S403, information about the bit error probability L (soft information) is obtained on the basis of the erroneous word v '' (120 bits) and the repetition code decoded word v '(24 bits). In step S404, using the soft information L, cortex decoding is performed on the repetition code decoded word v '(24 bits) to recover the input word w (12 bits). In step S405, the recovered input word w (12 bits) is re-encoded, first by cortex coding and then by repetitive code coding to recover the cortex repeat code codeword c (120 bits). In step S406, the recovered codeword c (120 bits) is XORed with the helper data HD to obtain the noise-free PUF response R as a error-free binary signal.

In the following, embodiments relating to a cortex repeat code will be described in detail.

Cortex-Repetition coding

In this embodiment we consider the (120, 12) concatenated code generated by the concatenation of the C (24, 12) cortex code and the Rep (5, 1) repetition code. In the following, we use the C _b (8, 4) Hamming code as the base code for the Cortex coding.

Cortex-coding

The cortex coding described in this embodiment uses the self-dual block code generation scheme described in JC Carlach, A. Otmani, and C. Vervoux in "A New Scheme for Building Good Self-Dual Block Codes, "Proceedings of the IEEE International Symposium on Information Theory, 2000 was presented.

5 describes a three-stage construction which uses the (8, 4) extended Hamming code as a short base code and two bit permutations between the three stages. As an alternative to the extended Hamming code, the Hadamard code could also be used as the base code.

In the following, an example of a three-stage construction for coding an input word w will be explained. The input word w has, according to the coding scheme in 5 a length of 12 bits. The coding scheme generates a 24 bit cortex codeword c '.

We consider the input word w = (0010 0110 1101) and define x (0) / i = w _{i + 1} , i ε {0, 1, ..., 11}.

In addition, we determine the generator matrix G _{[8, 4] of} the binary linear code C _b (8, 4). The generator matrix G _{[8, 4] used} in this embodiment corresponds to the generator matrix of the (8, 4) extended Hamming code (total 8 bits, 4 control bits, 4 information bits).

This results in the following control bits:

In addition, we need a permutation of the elements {0, ..., 11}. In this case we choose π ₀ as follows:

Cortex coding begins by dividing w into 4-bit blocks (first block: x (0) / 0, x (0) / 1, x (0) / 2, x (0) / 3 second block: x (0) / 4, x (0) / 5, x (0) / 6, x (0) / 7 third block: x (0) / 8, x (0) / 9, x (0) / 10, x (0) / 11 ). The control bits r (0) / i, i ε {0, 1, ..., 11} are determined for each block with the base code C _b (8, 4).

In the next step of the coding, the permutation π ₀ becomes R ⁽⁰⁾ = (r (0) / 0, r (0) / 1, ...., r (0) / 11) applied. This results

Then x ^{(1) is} also split into blocks of 4 bits (first block: x (1) / 0, x (1) / 1, x (1) / 2, x (1) / 3, second block: x (1) / 4, x (1) / 5, x (1) / 6, x (1) / 7, third block: x (1) / 8, x (1) / 9, x (1) / 10, x (1) / 11 ) and the control bits r (1) / i, i ε {0, 1, ..., 11} are determined with the aid of the basic code C _b (8, 4).

The permutation π ₁ = π ₀ is now applied to R ⁽¹⁾ . This results

In the next step, X ^{( 2 ) is} divided into 4-bit blocks and the control bits r (2) / i, i ε {0, 1, ..., 11} are determined.

The codeword c '(here "cortex codeword") now corresponds c '= (x (0) / 0 ... x (0) / 11, r (2) / 0 ... r (2) / 11) ,
c '= (0010 0110 1101 1010 0101 0011)

Repeat code encoding

In general, the repetition code coding is performed with Reb (n, 1) repetition code by repeating each bit exactly n times. In this embodiment, the Rep (5, 1) repetition code is used, that is, each bit is repeated 5 times. Therefore, the coding for c '= (0010 0110 1101 1010 0101 0011) gives the new cortex repeat codec codeword C:

Cortex-repetition code decoding

An embodiment of the cortex repeat decoder will now be described. In this embodiment, the repetition code decoding is performed first because the repetition code represents the inner code in this concatenation.

Repeat code decoding

Let v "be an example of a received word (the" errored word ") to be decoded.

• 1. Teile das Codewort in Blöcke von n Bits
• 2. Wenn mehr als [ / n2] Bits in einem Block von n Bits den Wert 0 haben, dann ergibt die Decodierung des Blocks den entsprechenden Wert 0. Wenn mehr als [ / n2] Bits in einem Block von n Bits den Wert 1 haben, dann ergibt die Decodierung des Blocks den entsprechenden Wert 1.
• 3. Wenn n eine gerade Zahl ist und genau [ / n2] Bits 0 und [ / n2] Bits 1 sind, dann ist die Decodierung nicht eindeutig. Um diesen Fall zu vermeiden, kann in einer praktischen Anwendungen n ungerade gewählt werden.

When decoding the Rep (n, 1) repetition code, n - 1 errors can be detected and [n - 1/2] Errors are corrected. The decoding is done as follows:

• 1. Divide the codeword into blocks of n bits
• 2. If more than [/ n2] If bits in a block of n bits have the value 0, then the decoding of the block gives the corresponding value 0. If more than [/ n2] If bits in a block of n bits have the value 1, then the decoding of the block gives the corresponding value 1.
• 3. If n is an even number and exactly [/ n2] Bits 0 and [/ n2] Bits are 1, then the decoding is not unique. In order to avoid this case, n odd may be selected in a practical application.

In our example, the errored word v "is decoded as described above. The decoding yields the word v '(the "repetition code decoded word"):
v '= (0000 0110 1101 1010 0101 0111)

Determine soft information

According to this embodiment, not only the erroneous word v "is decoded to the repetition code decoded word v 'during the repetitive code decoding, but also soft information is determined. The following describes an embodiment in which the soft information is a vector whose elements represent the number of errors in a normally error free block of v ''. Since we use the Rep (5, 1) repetition code, the elements of L can only take the values {0, 1, 2}. These values are determined by calculating the sum of each repetitive block (5 bits). If the sum takes the values 0 or 5, then the soft information at the corresponding location is 0. If the sum takes the values 1 or 4, then the soft information at the corresponding location is 1 and when the sum is the value 2 or 3, the soft information is at the corresponding location 2. L can be calculated by repeating v 'n times, subtracting the result from v' ', determining the absolute values of each element (-1 replaced by 1) and counting the number of 1's in each block of n bits.

The vector L thus contains the soft information. In this example, L is as follows:
L = (0020 0000 0020 0020 0000 0200)

In addition, a warning function could be used which could trigger an alarm or drive down the system implementing the process if the number of detected faults reaches a certain threshold. Two ways are described here to determine the number of errors. On the one hand, there is the possibility of calculating the magnitude of the errors directly using the soft information determined during the repetition code decoding. The use of soft information requires little additional computational effort, but it can not be the exact number of errors determined but only the magnitude of the number of errors. On the other hand, the exact number of errors can be determined by re-encoding the cortex-decoded word (corresponding to the input word). The re-encoding of the input word yields the cortex repeat code codeword c. The codeword c is compared with the errored word v "and the exact number of errors can be determined. 7 describes the re-coding schematically. The computational effort required to re-encode the input word is negligible since both the cortex and the repeating encoders are efficiently implemented.

Cortex decoding

For the cortex decoding, the inverse permutation of π _{0 is} determined:

We assume here that the repetition code decoded word v 'is further decoded with the cortex decoder, which exploits the principle of the cortex encoder (as described above). This means that 4-bit blocks of a 12-bit input word are encoded with the (8, 4) extended Hamming code. The resulting codeword v 'consists of k = 12 information bits and 12 control bits.

Initially we consider the k information bits of the word v 'after the repetition code decoding:
v '= (0000 0110 1101 1010 0101 0111) = (v' | v ' _p ),
where v '= (0000 0110 1101) represents the information bits and v' _p = (1010 0101 0111) the control bits. According to this embodiment, the least reliable bits L _{rs of} the information bits are precisely those bits whose associated soft information indicates the highest error probability. In this embodiment, these are those bits whose soft information takes the value 2. Since we use the Rep (5, 1) repetition code, the soft information can only accept the values {0, 1, 2}, ie there are three different levels of soft information. The values of the soft information are determined by calculating the sum of each repetitive block (5 bits). If the sum takes the values 0 or 5, then the soft information at the corresponding location is 0. If the sum takes the values 1 or 4, then the soft information at the corresponding location is 1 and when the sum is the value 2 or 3, the soft information is at the corresponding location 2.

The soft information thus obtained is helpful in that it indicates the positions in the received word at which errors are most likely to occur. The higher an element in vector L, the more likely it is that the associated bit is erroneous. Furthermore, L _s denotes the soft information for the k information bits and L _p the soft information for the k control bits. In the embodiment described herein, the least reliable bits L _rs can be described as follows:
L _rs = L _s = (0020 0000 0020), where '2' indicates a least reliable bit.

N error patterns V _si , i = 1 ... N, are formed from the information bits v ' _s of v' by inverting some of the least reliable bits, ie, 1 becomes 1 + 1 mod 2 = 0 and 0 becomes 0 + 1 mod 2 = 1. In this example, we set N: = 4, but in other embodiments, N can also be larger.
v _s1 = (0000 0110 1101)
v _s2 = (0010 0110 1111)
v _s3 = (0000 0110 1111)
v _s4 = (0010 0110 1101)

These error patterns are then re-encoded with the Cortex Reroute Encoder. This results in the following list of codeword candidates:
v ' _s1 = (0000 0110 1101 1111 0110 1000)
v ' _s2 = (0010 0110 1111 0100 1110 0001)
v ' _s3 = (0000 0110 1111 0001 1101 1010)
v ' _s4 = (0010 0110 1101 1010 0101 0011)

Subsequently, the Euclidean distance between v '(the received word after repetition code decoding) and the re-coded error patterns is calculated. These calculations yield:
d (v ', v' _s1 ) = 8d (v ', v' _s3 ) = 8d (v ', v' _s2 ) = 10d (v ', v' _s4 ) = 2

Now, the same process is performed for the k = 12 control bits v ' _p . We first consider the least reliable bits L _{rp of} the control bits v ' _p of v'. As above, N = 4 is selected and the error patterns V _pi , i = 1 ... N are determined by inverting some of the least reliable bits.

L _p = L _rp = (0200 0000 0200), where '2' indicates a least reliable bit
V _p1 = (1000 0101 0011)
V _p2 = (1010 0101 0111)
V _p3 = (1000 0101 0111)
V _p4 = (1010 0101 0011)

This time, the error patterns with the cortex repeat encoder, which is the permutation π -1 / 0 used as interleaver, re-coded. This results in a second list of codeword candidates:
v ' _p1 = (1011 0001 0111 1000 0101 0011)
v ' _p2 = (0111 1000 0100 1010 0101 0111)
v ' _p3 = (1110 1111 1110 1000 0101 0111)
v ' _p4 = (0010 0110 1101 1010 0101 0011)

Subsequently, the Euclidean distance between v '(the received word after repetition code decoding) and the re-coded error patterns is calculated. These calculations yield:
d (v ', v' _p1 ) = _16d (v ', v' _p3 ) = 8d (v ', v' _p2 ) = 8d (v ', v' _p4 ) = 2

The word v ε {v ' _si , v' _pi , i ε {1, ..., 4}} with minimum distance to v 'is used for the decoding of v'. The minimum distance between v 'and one of the re-coded error patterns is 2, therefore v' _is decoded to v ' _s4 = v' _p4 , ie
v = (0010 0110 1101 1010 0101 0011).

The first 12 bits of V correspond exactly to the input word.

Key protection

6a and 6b describe an application in which the cortex retry code is used to secure an application key. For practical applications, the procedure described above should optionally be performed several times to secure a key of desired length. In the use case described below, the procedure becomes 10 repeated.

6a describes the enrollment. Enrollment is performed each time a new key is generated or saved. PUF 601 , here a SRAM PUF, generates a binary PUF response R which is 1200 bits long. An application key KY, which is 120 bits long, is written in 602 is coded with the cortex repeat encoder and gives a codeword c which is 1200 bits long. The codeword c and the binary PUF response R are XORed together to generate helper data HD which is 1200 bits long. This helper data is used as the activation code for the KY application key.

6b describes the reconstruction. During reconstruction, the helper data generated in the enrollment are compared with a noisy PUF response R 'obtained from PUF 601 was generated and is 1200 bits long, XOR-linked. The result of this linkage is the binary errored word v "which is coupled to the cortex repeat decoder in FIG 603 is decoded to reconstruct the application key KY.

According to this embodiment, the PUF response R is used to secure an application key or other critical user data. The PUF response can be considered as an individual fingerprint of the SRAM block used as a private key. To restore the KY application key, both the PUF response R and the activation code are needed. Therefore, an attacker must be able to access and read the activation code as well as the SRAM PUF. The SRAM PUF can be considered as protection for the key.

An SRAM PUF may be used, for example, to secure data on a storage medium containing the SRAM PUF. The application key can be used, for example, to safely encode data stored on a storage medium. The data encoded with the PUF response can only be decoded on the storage medium containing the SRAM PUF. If the data is copied to another medium, decoding is not possible because the SRAM PUF can not be cloned on another medium. Therefore, it is impossible to decode the encoded data on another device.

The above-described methods and systems can also be used to secure sensitive data on smart card ICs and similar media.

7 schematically shows an embodiment of a method for determining the number of errors in the error word v ''.

Helper data HD generated in the enrollment are (according to the 6b ) with a noisy PUF response R ', which of PUF 701 was generated and is 1200 bits long, XOR-linked. The result of this combination is the errored codeword v '' which is connected to the cortex repeat decoder in 703 is decoded to reconstruct the application key KY. The application key KY is now replaced by the cortex repeat code encoding 702 re-coded. The output obtained is the cortex repeat code coded codeword c, which is then compared to the error codeword v "and the number of errors determined. As a result of the comparison, an error vector e is obtained. The comparison is achieved in this embodiment by an XOR operation of the cortex repeat code codeword c and the errored word v ".

This method of 7 can be used for example for a warning function.

It should be noted that the embodiments describe all methods with only exemplary order of the individual steps. The specific order of the procedures has been given for illustrative purposes only and should not be considered as binding. For example, the order of S402 and S403 in the execution of 4 The steps S403 and S403 may also be performed simultaneously in a combined manner.

It should also be noted that the subdivision of the systems of 1 and 2 in the blocks 105 . 203 . 205 . 213 . 215 has been made for illustrative purposes only and the execution is not limited to the specific allocation of functions to the specified blocks. The cortex encoder 103 from 1 and the Cortex decoder 213 For example, they can be part of the same physical unit or software unit. Similarly, the re-encoding, which in the cortex decoder 205 takes place with the same physical unit or software unit as the cortex encoding in 103 1 ,

All parts described in this embodiment and claimed in the following claims may be used as an integrated circuit, for example, unless otherwise specified. B. be implemented on a chip. Functions of these parts may be implemented as software unless otherwise specified.

The described methods may be implemented as a computer program so that a computer and / or a processor performs the procedures when the computer program is executed on the computer and / or on the processor. In some embodiments, a non-transitory and computer-readable storage medium is provided which stores a computer program. When this program is executed by a processor as described above, the described methods are performed.

Claims (14)

A computer-implemented method comprising: repetition code decoding (S402) an erroneous word (v '') received from a noisy channel ( 201 ) is obtained to obtain a repetition code decoded word (v '); Determining (S403) soft information (L) based on the erroneous word (v '') and the repetition code decoded word (v '); and cortex decoding (S404) the repetition code decoded word (v ') to reconstruct an input word (w) based on the soft information (L). The method of claim 1, further comprising re-encoding (S405) the input word (w) to reconstruct a cortex repeat code codeword (c). The method of claim 2, wherein the re-encoding (S405) of the input word (w) comprises cortex-coding the input word (w) to obtain a cortex codeword (c ') and a repetition code coding of the cortex codeword (i ') to obtain a cortex repeat code codeword (c). A method according to claim 2 or 3, further comprising linking (S406) the reconstructed cortex repeat code codeword (c) with helper data (HD) to obtain an error-free binary signal (R) from the noisy channel (3). 201 ) to obtain. The method of claim 4, wherein the error-free signal (R) comprises a flawless physically-unclonable function-response, PUF-response, from a noisy channel ( 201 ). Method according to one of the preceding claims, which also includes a linkage of erroneous input data (R ') from a noisy channel ( 201 ) with helper data (HD) to obtain the erroneous word (v ''). Method according to Claim 6, in which the erroneous input data (R ') are a noisy PUF response (R') and from a noisy channel ( 201 ) be won. The method of any one of the preceding claims, wherein determining the soft information (L) comprises determining bit error probabilities based on the obtained word and the repetition code decoded word. Method according to one of the preceding claims, wherein a warning function is given, which responds as soon as a certain number of errors is reached. A method according to any one of the preceding claims, wherein aging effects are inherently treated. A computer-implemented method, comprising: cortex-coding (S301) an input word (w) to obtain a cortex codeword (c '); Repetition code coding (S302) of the cortical codeword (c ') to obtain a cortical repetition code codeword (c); and linking the cortex repeat code codeword (c) with a binary signal (R) received from a noisy channel ( 101 ) to generate helper data (HD). Method according to one of the preceding claims, wherein the noisy channel ( 201 ) is a static random access memory PUF, SRAM PUF. The method of any one of claims 4, 6, or 11, wherein the association comprises an XOR operation. A system adapted to carry out one of the methods of claims 1 to 13.

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