DE102014212483A1 - Complex circuit element and capacitor with CMOS-compatible high-k antiferroelectric materials - Google Patents

Abstract

The invention provides high performance integrated circuit devices and high capacity MIM / MIS capacitors and methods for fabricating corresponding integrated circuit devices and MIM / MIS integrated capacitors. In various aspects, a substrate and a dielectric layer or insulating layer are provided over the substrate. Further, an electrode layer is disposed over the dielectric layer or insulating layer. The dielectric layer or insulating layer herein is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element is a MOSFET structure or a capacitor structure.

Description

The invention relates generally to integrated circuits fabricated according to advanced CMOS techniques, and more particularly to circuit elements and capacitors employing high-k annitroelectric materials.

Integrated circuits (ICs) are increasingly being used in modern electronic equipment in ever new fields of application. In particular, the demand for more mobility and flexibility with respect to electronic devices coupled with high performance and low power consumption is driving developments towards more compact devices having features of sizes down to the deep sub-micron range, especially as current semiconductor technologies do so are able to produce structures with dimensions on the order of 10 nm. An IC represents a set of electronic circuit elements integrated on a semiconductor material, usually silicon, so that corresponding ICs are made much smaller in comparison with discrete circuits, especially since discrete circuits are composed of individual independent circuit components. The majority of today's ICs are using a plurality of circuit elements, such as. As field effect transistors (FETs) or metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors), and passive elements such. As resistors and capacitors, which are integrated on a semiconductor substrate with a given surface. Currently, contemporary integrated circuits include millions of individual circuit elements integrated on a semiconductor substrate.

The basic function of a MOSFET is that of an electronic circuit element wherein a current through a channel of a MOSFET is controlled between source and drain by means of a gate to which a voltage is applied relative to source and drain. In particular, the conductivity state of a MOSFET is changed by the voltage applied to the gate when a certain voltage value or characteristic voltage level is exceeded, which is usually referred to as a threshold voltage (Vt) and characterizes the switching behavior of a MOSFET. In general, Vt does not depend trivially on the characteristics of the transistor, such as. B. material etc.

It is known that at 300 K for conventional MOSFETs, a change in channel potential of at least 60 mV is required to cause a current change by a factor of 10 (this is also referred to as subthreshold swing). The minimum subthreshold swing establishes a fundamental lower limit of operating voltage, and thus also limits the power loss of switches based on standard MOSFETs.

In the publication of S. Salahuddin et al., "Use of negative capacitance to provide voltage amplification for low power nanoscale devices", nanolett. 8, 405 (2008) It has been proposed to form the gate oxide of a FET through a ferroelectric insulating material having a thickness smaller than a critical thickness, thereby forming a gate voltage boosting step-up voltage converter. This proposal is based on the theory that an effective negative capacitance can theoretically be attributed to a ferroelectric insulating material having a thickness less than a critical thickness due to internal positive feedback, thereby offering the possibility of reducing the subthreshold swing. In the publication of Khan et al. entitled "Ferroelectric Negative Capacitance MOSFET: Capacitance Tuning & Antiferroelectric Operation", IEDM, 2011 , a design methodology of ferroelectric negative-capacitance FETs (NCFETs) has been presented combining a high-k gate oxide of a MOSFET device with a ferroelectric dielectric layer formed thereon. The thickness of the ferroelectric material was appropriately selected to give a negative capacitance of about the same order of magnitude, which compensates for the capacitance in the MOSFET device, so that the stability of the negative capacitance (NCFET) MOSFET improves and the resulting gate capacitance becomes effective increased and a Subthreshold swing of 60 mV / decade or less is enabled. A metal layer was further disposed between the ferroelectric dielectric layer and the high-k gate oxide to average out the nonuniformities due to domain formation in the ferroelectric dielectric. In total was from Khan et al. proposed to specify the hysteresis loop of NCFETs with an antiferroelectric property within the VDD window.

In addition to MOSFETs, typical integrated circuits may further include capacitors and resistors known as so-called integrated passive devices (IPCs) or integrated passive components (IPCs) for forming functional blocks, such as integrated circuits. B. impedance tuning circuits, harmonic filters, couplers, transformers, etc. are used. IPDs or IPCs can generally be fabricated using standard semiconductor fabrication technologies known in the fabrication of MOSFETs. Capacitors can be replaced by metal Insulator semiconductor structures (MIS structures, "metal insulator semiconductor structures") or metal-insulator-metal structures (MIM structures, "metal insulator metal structures") are reacted, which have a metal layer on an insulating material is formed, which in turn is arranged in MIS structures on a semiconductor material or in MIM structures on a metal layer. Typical applications of MIS / MIM capacitors involve power supply buffering, RF decoupling or boost converters.

In the improvement of ICs, it has been found that with respect to energy storage capacitors of higher capacity are required to store more energy in the electrostatic field of the capacitor, while the demand for higher performance also requires faster charging / discharging in shorter time periods. Currently, the capacitance of MIS / MIM integrated planar capacitors is limited to 20 fF / μm ² since the available chip area and available chip materials to be used as dielectrics in advanced capacitors dictate constraints. For example, from the available chip materials, particularly in the CMOS techniques due to impurity problems, conditions that limit the dielectrics used in MIS / MIM capacitors to materials, e.g. For example, in CMOS technology, materials that are compatible with CMOS technology.

Although the capacitance of a capacitor can generally be increased by increasing its surface area, decreasing the distance between its electrodes, and increasing the dielectric constant or k-value of a dielectric disposed between the electrodes of a capacitor, this generally causes a number of problems. In advanced ICs is z. B. the reduction of the distance between the electrodes due to the occurrence of leakage currents with decreasing thickness of the dielectric only limited possible.

Furthermore, in current developments, enlargement of the electrode surface is considered by so-called 3D capacitors, in which a dense network of pores is formed in the surface of a semiconductor substrate, wherein the pores are filled with a high-k dielectric material, so that higher capacitance densities can be obtained. Again, an increase in capacity leads to problems related to 1 described below.

1 Graphically illustrates a relationship between the charge of an MIS / MIM capacitor (plotted as ordinate) and the voltage applied to the capacitor (plotted as abscissa). The MIS / MIM capacitor was formed according to conventional techniques and measured by the inventors. As in 1 In the illustrated example, a high target charge of, for example, 15 μC / cm ² requires a high voltage drop of 7V across the capacitor, potentially causing breakdown of the dielectric and consequently threatening to reduce the reliability of the entire integrated circuit with the capacitor.

Capacitors with high capacitances are conventionally arranged on or in chip interposers. Because suitable integrated capacitors that have high capacitances are not available, currently external passive components are the only currently available option, but require extra space.

Ferroelectric dielectrics have recently been considered for ferroelectric FETs (FeFETs) for nonvolatile memory applications. The font US 8,304,823 B2 represents an approach in this direction, according to which the use of hafnium and / or zirconium in ferroelectric materials in FeFETs has been proposed as the gate oxide.

Although ferroelectric and antiferroelectric dielectrics are generally known to have high dielectric constants or k values, new problems arise in the application of antiferroelectric dielectrics when concrete applications in advanced semiconductor technology are considered. Typical antiferroelectric films have e.g. Example, a thickness of several 100 nm and conventional antiferroelectric materials such as perovskite, z. As PZT, BaTiO ₃ and SBT are not compatible with environments in which complex semiconductor devices are manufactured, since there is a risk of introducing impurities that would ultimately lead to yield losses in semiconductor device units.

In view of the situation discussed above, it is therefore desirable to provide integrated circuit devices and high capacitance MIM / MIS capacitors. It is further desirable to provide a method of manufacturing a high capacity integrated circuit device.

The invention provides high performance integrated circuit devices and high capacity MIM / MIS capacitors and methods for fabricating corresponding integrated circuit devices and MIM / MIS integrated capacitors. In various aspects, a substrate is provided and becomes a dielectric layer or insulating layer formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Here, the dielectric layer or insulating layer is at least partially in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may be a MOSFET structure or a capacitor structure.

In a first aspect of the invention, there is provided an integrated circuit element, wherein the integrated circuit element comprises a substrate, a dielectric layer disposed over a surface of the substrate, and an electrode layer disposed over the dielectric layer, wherein the dielectric layer is in an antiferroelectric phase.

In a second aspect of the invention, there is provided an integrated MIM / MIS capacitor, wherein the MIM / MIS integrated capacitor comprises a semiconductor substrate, a lower electrode formed on the semiconductor substrate, an insulating layer formed on the lower electrode, and an upper electrode which is formed on the insulating layer, wherein the insulating layer is in an antiferroelectric phase. In some illustrative examples herein, the lower electrode and / or the upper electrode is formed by a metal material, e.g. TiN, TaN, Ru, Pt and / or the like.

In a third aspect of the invention, there is provided a method of fabricating an integrated circuit device, the method comprising providing a substrate, depositing an amorphous high-k dielectric material layer on the substrate, depositing a capping layer on the amorphous high-k dielectric material layer, and inducing crystallization in at least a portion of the amorphous high-k dielectric material layer, wherein the crystallized high-k dielectric material layer is in an antiferroelectric phase. In some illustrative embodiments herein, the crystallization may be induced prior to the deposition of the overcoat. In some alternative embodiments herein, the crystallization may be caused after the capping layer has been deposited on the high-k amorphous dielectric material layer.

In one illustrative embodiment herein, there is provided a method of making an MIM / MIS integrated capacitor, the method comprising providing a substrate, depositing an amorphous high-k dielectric material layer on the substrate, depositing a capping layer on the amorphous high-k Dielectric material layer and inducing crystallization in the high-k amorphous dielectric material layer, wherein the crystallized high-k dielectric material layer is in an antiferroelectric phase. In some illustrative embodiments herein, the crystallization may be induced prior to the deposition of the overcoat. In some alternative embodiments herein, the crystallization may be caused after the capping layer has been deposited on the high-k amorphous dielectric material layer.

In some illustrative embodiments of the above aspects, the dielectric layer comprises Hf _a X _b O ₂ with a, b> 0, where X represents one of Zr and Si and Al and Ge and Mg and Ca and Sr, and Ba and Ti and a rare earth element. In a specific example, about X is provided by Zr with a <0.5, b> 0.5. In an alternative specific example, X is approximately Si with 0.88 <a <0.95, 0.05 <b <0.2, or 0.88 <a <0.95, 0.05 <b <0, 12 given. In another alternative example, X is provided by Al at 0.88 <a <0.95, 0.05 <b <0.2 or 0.88 <a <0.95, 0.05 <b <0.12 ,

The invention will be described below with reference to the accompanying figures, in which like reference numerals designate like elements, and in which:

1 schematically illustrates a graphical relationship between charge density and voltage of a capacitor measured by the inventors;

2a - 2 B schematically illustrate in cross-sectional views integrated circuit elements during manufacturing phases according to illustrative embodiments of the invention;

3 schematically illustrates a graphical relationship between a ZrO ₂ content relative to a precursor to provide a HfO ₂ -ZrO ₂ mixture;

4 schematically represents a hysteresis loop and a dependence of the dielectric constant for different HfO ₂ -ZrO ₂ mixtures with different mixing ratios of the oxides; and

5 schematically illustrates a graphical relationship between charge densities on electrodes of a capacitor according to the invention and the associated voltages between the electrodes.

The present invention relates to semiconductor devices integrated on or into a chip and semiconductor device structures integrated on or into a chip, the devices and / or device structures being referred to as integrated circuit elements are considered, such. As metal oxide semiconductor devices (MOS devices) or capacitors, such as. B. MIM / MIS capacitors.

The term "MOS device" is not limited to metal-containing gate material and / or gate dielectric material comprising oxide.

The term "MIM / MIS" is not limited to a metal-containing electrode.

Integrated circuit elements of the invention, and particularly MOS devices and / or capacitors, as illustrated by some illustrative embodiments described herein, relate to elements fabricated using advanced technologies. Integrated circuit elements of the invention are fabricated using technologies used to achieve technology nodes less than 100 nm, for example, technology nodes smaller than 50 nm or smaller than 35 nm. It is noted that the invention includes integrated circuit elements having structures of minimum length and / or width dimensions less than 100 nm, for example, minimum dimensions less than 50 nm or less than 35 nm.

It is noted that MOS transistors may be fabricated as P-channel MOS transistors or PMOS transistors and as N-channel transistors or NMOS transistors, each MOS transistor being made with or without mobility enhancing stress features or stress inducing features can. A circuit designer can mix and match different types of devices, such as using PMOS and NMOS transistors, clamped and unstrained, to take advantage of the best features of each type of device, as best suited to the circuit to be formed. It is noted that stress and strain can generally be described in terms of Young's modulus.

With reference to the 2a - 2 B Various illustrative embodiments of the invention with respect to integrated circuit elements will be described in greater detail. 2a shows an integrated circuit element ICea in a manufacturing stage, in which a substrate 20a is provided. A layer stack 25a is above the substrate 20a formed, in particular over a surface of the substrate 20a , The substrate 20a may comprise a semiconductor material selected from silicon, germanium, silicon / germanium, silicon / carbon, silicon / germanium / carbon, gallium arsenide, indium arsenide, indium phosphate, and other suitable semiconductor materials. In some specific illustrative embodiments, the semiconductor substrate is formed of silicon. It is noted that the semiconductor substrate 20a may be formed of a monocrystalline silicon layer having a surface orientation such that a crystallographic orientation of the surface normal of an upper surface of the semiconductor substrate 20a has a major crystallographic orientation. The semiconductor substrate 20a may be a bulk substrate, a semiconductor on insulator (SOI) substrate or a hybrid substrate. The semiconductor substrate 20a may have built-in stress, but this is not a limitation of the invention. The semiconductor substrate 20a may be doped to form one or more well regions therein. Alternatively, the semiconductor substrate 20a in the in 2a not shown doped production phase.

As shown in 2a can be a thin dielectric layer 21a on the substrate 20a be formed. In one illustrative embodiment, the thin dielectric layer is 21a a thin silicon oxide layer having a thickness of a few angstroms to a few nanometers, such. This is not a limitation of the invention and it is noted that the thin dielectric layer 21a is not provided in some alternative embodiments.

The layer stack 25a is above the substrate 20a formed so that at least one surface area of the substrate 20a is covered. The layer stack 25a includes a first layer 22a , an insulating layer 23a and a second layer 24a , The first shift 22a is above the substrate 20a arranged. The insulating layer 23a is over the first layer 22a arranged. The second layer 24a is over the insulating layer 23a arranged. The first shift 22a may comprise a semiconductor material-containing layer and / or a metal-containing layer. In a first illustrative example, the first layer is 22a a lower electrode layer comprising TiN, TaN, Ru, Pt and / or the like. in a second illustrative example, the first layer is 22a a semiconductor layer, for example a silicon layer or a silicon-containing layer.

The insulating layer 23a may comprise hafnium and / or zirconium and / or one or more dopants, such as. As silicon and / or aluminum and / or germanium and / or magnesium and / or calcium and / or strontium and / or barium and / or titanium and / or one or more rare earth elements. It is noted that in hafnium-containing material, additional dopants may be incorporated to prevent the to cause antiferroelectric phase and / or to adjust the voltage position of the local capacitance / polarization / k-value boost. In some illustrative examples, a concentration of additional dopants may be in the range of 0.2 to 30 mol%, for example in a range of 0.5 to 20 mol%. The insulating layer 23a can on the first layer 22a are formed by performing a deposition process, such. By an ALD process or a CVD process or a PVD process. The thickness of the insulating layer 23a may be in a range of 1 to 100 nm, for example, in a range of 6 to 60 nm.

In some specific illustrative examples, the insulating layer may 23a be formed from a Hf _a X _b O ₂ material, wherein X is Zr or Si or Al. In a first explicit example, X is represented by Zr and a is less than 0.5 and b is greater than 0.5 (eg, a <0.3 and b> 0.7). In a second explicit example, X is represented by Si, and 0.05 <b and / or b <0.2 and 0.88 <a and / or a <0.95. In an illustrative example herein, b is further in a range given by 0.05 <b <0.12, and / or for a, 0.88 <a <0.95. In a third explicit example, X is Al, where 0.05 <a <0.12 and 0.88 <b <0.95. It is noted that these explicit examples do not limit the invention and are intended to be illustrative only.

The second layer 24a may comprise a material that is represented by a metal nitride material and / or a noble metal material and / or their corresponding oxides. In an explicit example, the second layer comprises TiN, TaN, Ru, Pt and / or the like. In some illustrative embodiments, the second layer comprises an underlayer comprising TiN, TaN, Ru, Pt, and / or the like. The thickness of the second layer 24a may be up to 30 nm, for example, up to 15 nm or up to 10 nm. Depending on the application, the second layer may form an upper electrode or a lower layer of an electrode layer, such as an electrode. B. a work function setting material layer of a gate electrode of a MOS transistor. In illustrative examples of a MOS transistor, a gate electrode layer (not shown) may further be provided over the second layer 24a be formed, such. B. a polysilicon layer. In applications relating to passive elements, in particular capacitors, the second layer 24a represent an electrode and include TiN or other suitable electrode materials. The second layer 24a For example, it may be a capping layer formed by TiN for encapsulation of the insulating layer 23a is formed, but can also serve as an electrode.

It is noted that the first and second layers 22a . 24a and the insulating layer 23a can be formed by performing deposition processes, for example, PVD and / or CVD and / or ALD processes. It is noted that suitable precursor systems for forming the first and second layers 22a . 24a and / or the insulating layer 23a can be used.

In the following, an illustrative example will be described, which is not to be regarded as limiting the invention, but represents an illustrative process.

According to the illustrated illustrative embodiment, an ALD process is performed to form the insulating layer 23a prepare with a HfO ₂ -ZrO ₂ mixture ("HfO ₂ -ZrO ₂ solid solution"). In a specific illustrative example herein, the ALD deposition cycles may include the alkylamide precursors TEMAH and TEMAZ. It is noted that the ZrO ₂ content can be adjusted by ALD pulsation ratios of the alkylamide precursors used. Due to the approximately similar growth of both precursors in each deposition cycle, the stoichiometry can be controlled linearly and almost directly by the ALD cycle ratio. In this regard shows 3 vivid cycle ratios giving different ZrO ₂ contents (measured in mol% and plotted along the abscissa). In some illustrative embodiments of the invention, the insulating layer becomes 23a formed as an amorphous layer.

After the deposition of the insulating layer 23a becomes a second layer forming material on the insulating layer 23a deposited to the second layer 24a to build. According to an exemplary embodiment, the second layer is subjected to a deposition process with a deposition temperature below the crystallization temperature of the insulating layer 23a educated. As a result, the insulating layer becomes 23a deposited as an amorphous layer, which is encapsulated by the second layer, while the amorphous state of the insulating layer 23a preserved.

After the formation of the insulating layer 23a For example, a thermal anneal process TAa is performed to crystallize in at least a portion of the insulating layer 23a cause. Possible bake temperatures may range from 250 ° C to about 1200 ° C. In some specific illustrative examples herein, the bake temperatures may range from 250 ° C to 800 ° C, or from 500 ° C to 1100 ° C. It is noted that these explicitly disclosed examples do not limit the invention. It is noted that the Baking temperature depending on the thickness of at least the insulating layer 23a and / or the material composition of at least the insulating layer 23a can depend. The baking temperature can z. B. depending on a hafnium content and / or a zirconium content and / or aluminum content and / or a silicon content and / or a germanium portion are selected.

In some illustrative examples herein, the thickness of the insulating layer 23a in a range of 5 nm to 15 nm. In an explicit example with an insulating layer comprising an HfO-ZrO ₂ composition or pure ZrO ₂ , the process TAa may be implemented so that a thermal budget translates a bake temperature from a range of 250 ° C to 800 ° C. In another explicit example with an insulating layer comprising dopants of silicon and / or aluminum, the process TAa may be implemented so that a thermal budget is implemented which provides a bake temperature in a range of 500 ° C to 1100 ° C , For example, with respect to an insulating material having a dopant concentration of silicon of about 6%, the bake temperature may be at least 550 ° C while a bake temperature of at least 550 ° C is provided for an aluminum dopant concentration of about 7%. It is noted that crystallization generally depends on the material and material composition of the insulating layer 23a can depend. Consequently, the ICea as shown in FIG 2a be formed such that it in this production phase an insulating layer 23a which is at least partially in the antiferroelectric phase.

In some illustrative embodiments herein, the thermal anneal process TAa may precede the formation of the second layer 24a on the insulating layer 23a be performed. Alternatively, the thermal anneal process TAa is performed after the second layer 24a on the insulating layer 23a was formed. It is noted that in some illustrative embodiments, the thermal anneal process TAa may be a rapid thermal anneal (RTA) process.

In illustrative embodiments, performing the thermal anneal process TAa prior to formation of the second layer 24a on the insulating layer 23a can provide, the thermal budget of the thermal annealing process TAa may be slightly above the crystallization temperature, which may be selected depending on optional dopants and / or doping concentrations and / or layer thicknesses.

In illustrative embodiments, in which the second layer 24a on the insulating layer 23a is formed before performing the thermal annealing process TAa, the thermal budget of a process leading to the formation of the second layer 24a is slightly above the crystallization temperature, which is adjusted depending on optional dopants and / or dopant concentrations and / or layer thicknesses.

Other illustrative embodiments of the invention will be described with reference to FIG 2 B described. 2 B shows an integrated circuit element ICeb in a manufacturing stage, in which a substrate 20b is provided. A layer stack 25b is above the substrate 20b formed, in particular over a surface of the substrate 20b , The substrate 20b can be essentially analogous to the substrate 20a provided above with reference to FIG 2a has been described.

The layer stack 25b includes as shown in 2 B a first layer 22b and a second layer 23b , In some illustrative embodiments, the first layer 22b the first layer 22a correspond to the above with reference to 2a is described. The second layer 23b may be an insulating material layer according to the insulating layer 23a with reference to FIG 2a is described. In other illustrative embodiments, the first layer provides 22b an insulating material layer according to the insulating layer 23a as previously described with reference to 2a described above, wherein the second layer 23b according to the in 2 B production phase is not provided.

The layer stack 25b may be formed in correspondence to processes as described above with respect to the layer stack 25a has been described.

In the illustrated manufacturing stage of the integrated circuit element ICeb, a thermal baking process TAb is performed, as in FIG 2 B is shown. The thermal baking process TAb may be performed as described above with respect to the baking process TAa. In particular, the baking process TAb can be designed analogously to the previously described baking process TAa.

It is noted that the integrated circuit element ICeb as shown in FIG 2 B represents a transistor element in an early manufacturing stage or a capacitor in an early manufacturing stage. Although in 2 B not shown, a small layer (not shown) may optionally be between the first layer 22b and the substrate 20b be arranged. The optional small layer (not shown) may be an oxide liner or a germanium channel.

Electrical properties of some illustrative embodiments of the present invention will be described with reference to FIG 4 explained in more detail. The following discussion serves to describe illustrative embodiments and does not limit the invention.

4 Fig. 10 graphically shows hysteresis loops which are an insulating layer having an HfO ₂ -ZrO ₂ mixture ratio of about 70 mol% ZrO ₂ and 100 mol% ZrO ₂ . Increasing the proportion of ZrO ₂ to 100 mol% decreases the remanent polarization (the ordinate represents the polarization P in units of μC / cm ² ) and the coercive force (the abscissa represents the applied electric field in units of MV / cm). to about 0. Despite the decrease of the coercive field strength and the remanence polarization the in 4 illustrated loop a nonlinear behavior that has two local maxima in the relative dielectric constant (ε _r in the graph under the hysteresis loops). It is noted that the relative dielectric constant is related to the slope of the hysteresis loop dP / dE ("E" here means "electric field strength"). This particular behavior is generally referred to as "ferroelectric" as "antiferroelectric", which term is selected to be "antiferromagnetic" and "ferromagnetic" in analogy to the corresponding magnetic counterparts. In contrast, a paraelectric medium exhibits a fundamental linear dependence of the polarization on the applied electric field without remanent polarization.

It is noted that the dielectric constant or k-value in dielectric materials is higher in the antiferroelectric phase than in paraelectric materials or even in ferroelectric materials (at least in part). In some illustrative embodiments, the dielectric constant, or k value, may be effectively increased by up to 400% or even more over conventional high-k dielectric materials, as described herein.

5 Graphically illustrates a relationship between the charge density on the electrodes of a capacitor and the corresponding voltage drop across the electrodes. In particular, a curve A in FIG 5 a charge-voltage relationship expected for conventional capacitors, as for example with reference to FIG 1 has been described above. On the other hand, a curve B represents a charge-voltage relationship in capacitors comprising, according to the invention, an insulating material in the antiferroelectric phase.

Due to the antiferroelectric behavior of the insulating material, the charge density in the case of curve B at low voltage is very low, while it increases much more with increasing voltage over conventional capacitors (see curve A). Consequently, a high target load of, for example, about 15 μC / cm ^{2 can} already be achieved with comparatively low voltages falling along the capacitor. In the example shown, a correspondingly high charge density can already be achieved at approximately 2 V compared with the much higher voltage drops in conventional 7 V capacitors.

In the 5 The exemplary curves shown were obtained by preparing a sample with an insulating layer doped with HfO ₂ and having the antiferroelectric phase, this layer having a thickness of 10 nm (see curve B), while curve A is a sample with a conventional one has insulating layer of HfO ₂ in the paraelectric phase at a thickness of 10 nm. The present example demonstrates that capacitors of the invention can store a greater amount of charge with relatively low voltages across the capacitor, thereby avoiding the risk of dielectric breakdown due to high voltage drops over conventional capacitors.

Capacitors of the invention can be used in integrated circuits as buffer / memory / boost capacitors. As a result, external passive components can be dispensed with and compactification or scaling is made possible. It is noted that the invention makes it possible to apply advantages of antiferroelectric dielectrics in CMOS techniques without having to resort to materials incompatible with CMOS process flow.

Some aspects of the invention relate to an integrated circuit element as described with reference to FIGS 2a - 2 B above, according to a capacitor type passive circuit element. In other aspects of the invention, with reference to FIGS 2a and 2 B discloses a MOSFET-type integrated circuit element. In some illustrative embodiments, as shown in FIGS 2a and 2 B a cover layer may be disposed between an insulating layer and an electrode layer. The cover layer may comprise, for example, TiN and / or TiAN and / or Ru and / or Pt. In some illustrative embodiments, a silicon oxide layer may be formed between the substrate and the dielectric layer and the cap layer may be, e.g. B. TiN include. In some illustrative embodiments, the second layer may be formed by a cover layer. Alternatively or additionally, the first layer can be provided by a cover layer. As a result, the insulating layer can be reliably encapsulated.

The present invention, in some illustrative embodiments, provides a method of forming an integrated circuit device, the method comprising providing a substrate, depositing an amorphous high-k dielectric material layer on the substrate, depositing a cap layer on the high-k amorphous dielectric material layer and a step of at least partially crystallizing in the amorphous high-k dielectric material layer, wherein the at least partially crystallized high-k dielectric material layer is in an antiferroelectric phase. In some specific illustrative embodiments herein, the crystallization may be effected by performing a bake process employing a bake temperature in the range of 250 ° C to 1100 ° C. In some alternative examples herein, the anneal process may be performed prior to deposition of the overcoat. In some other illustrative embodiments, the capping layer may be deposited prior to causing the at least partial crystallization, and the deposition of the capping layer may include performing a deposition process at process temperatures below the crystallization temperature of the high-k amorphous dielectric material layer. In some illustrative embodiments, the deposition of the capping layer may include depositing a TiN layer while performing an ALD process at 500 ° C. In some illustrative embodiments, the process temperatures may be below 600 ° C. In some illustrative embodiments, the high-k amorphous dielectric material layer may comprise Hf ₃ X _b O ₂ with X of one of Zr and Si and Al and Ge and Mg and Ca and Sr and Ba and Ti and rare earth elements, where a, b> 0. In some illustrative embodiments, the at least partial crystallization may be induced in the deposition of the capping layer. In illustrative examples herein, the deposition of the capping layer may include depositing a TiN layer while performing an ALD process at about 500 ° C or more.

It is noted that due to the antiferroelectric behavior of the gate dielectric under application of a voltage to the gate electrode, the dielectric constant or the k value of the gate dielectric may be adjusted depending on the history of the voltage application (hysteresis loop history).

The use of high-k dielectric materials in MOSFET devices can provide an improved subthreshold slope due to the nonlinear capacitance-voltage characteristic. It is noted that a gate dielectric in the antiferroelectric phase is ideally adapted to HK / MG applications.

In particular, using Hf _a X _b O ₂ with X selected from Zr and Si and Al and Ge and other suitable additional dopants, as described above, corresponding to process sequences for forming advanced integrated circuit elements can easily exhibit antiferroelectric behavior in the process flow for manufacturing semiconductor devices in HK / MG applications.

In other applications, the invention may provide 3D capacitors in which a dense network of pores is formed in the surface of a semiconductor substrate, the pores being filled with a high-k dielectric material in the antiferroelectric phase. Corresponding 3D capacitors can be scaled up very high. It is noted that z. For example, by using Hf _a X _b O ₂ as described, corresponding 3D capacitors can be fabricated in a manner compatible with CMOS techniques. This allows applications of CMOS techniques as well as applications of 3D capacitors in integrated circuits along with very highly scaled CMOS devices.

In other applications, antiferroelectric capacitors may be provided as individual elements of electronic circuits. In this regard, a single circuit element may be provided wherein the circuit element comprises a first electrode and a second electrode and an antiferroelectric dielectric material disposed between the first and second electrodes.

In summary, the invention provides integrated circuit devices and high capacity MIM / MIS capacitors and methods of fabricating corresponding integrated circuit devices and integrated MIM / MIS capacitors. In various aspects, a substrate and a dielectric layer or insulating layer are provided over the substrate. Further, an electrode layer is disposed over the dielectric layer or insulating layer. The dielectric layer or insulating layer herein is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element is a MOSFET structure or a capacitor structure.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 8304823 B2 [0012]

Cited non-patent literature

• S. Salahuddin et al., "Use of negative capacitance to provide voltage amplification for low power nanoscale devices", nanolett. 8, 405 (2008) [0005]
• Khan et al. entitled "Ferroelectric Negative Capacitance MOSFET: Capacitance Tuning & Antiferroelectric Operation", IEDM, 2011 [0005]
• Khan et al. [0005]

Claims (20)

Integrated circuit element (ICea, ICeb), comprising: a substrate ( 20a . 20b ); a dielectric layer ( 23a . 22b ) overlying a surface of the substrate ( 20a . 20b ) is formed; and an electrode layer ( 24a . 24b ) above the dielectric layer ( 23a . 22b ), wherein the dielectric layer ( 23a . 22b ) is at least partially in an antiferroelectric phase. Integrated circuit element (ICea, ICeb) according to claim 1, wherein the dielectric layer ( 23a . 22b ) Hf _a X _b O ₂ with a, b> 0, where X represents one of Zr and Si and Al and Ge and Mg and Ca and Sr and Ba and Ti and rare earth elements. The integrated circuit element (ICea, ICeb) of claim 2, wherein X is provided by Zr and a <0.5, b> 0.5. The integrated circuit element (ICea, ICeb) of claim 2, wherein X is provided by Si and 0.88 <a <0.95, 0.05 <b <0.2. The integrated circuit device (ICea, ICeb) of claim 2, wherein X is provided by Al and 0.88 <a <0.95, 0.05 <b <0.2. An integrated circuit element (ICea, ICeb) according to any one of claims 1 to 5, further comprising a cover layer disposed between the dielectric layer (12). 23a . 22b ) and the electrode layer ( 24a . 23b ) is arranged. Integrated circuit element (ICea, ICeb) according to claim 6, wherein the cover layer comprises TiN and / or TaN and / or Ru and / or Pt. Integrated circuit element (ICea, ICeb) according to claim 7, wherein the electrode layer ( 24a . 23b ) Silicon. An integrated circuit device (ICea) according to claim 7 or 8, further comprising a silicon oxide material-containing layer (FIG. 21a ) between the dielectric layer ( 22a ) and the substrate ( 20a ) is arranged. Integrated circuit element (ICea, ICeb) according to one of claims 1 to 9, wherein the electrode layer ( 24a . 23b ) comprises a metal nitride material and / or a noble metal material and / or their corresponding oxides. The integrated circuit element (ICea) of claim 10 further comprising a cover layer (12). 21a ) between the substrate ( 20a ) and the dielectric layer ( 23a ) is arranged. Integrated circuit element (ICea) according to claim 11, wherein the cover layer ( 21a ) comprises a metal nitride material and a noble metal and / or their corresponding oxides. Integrated capacitor (ICeb, ICea), comprising: a semiconductor substrate ( 20a . 20b ); an insulating layer ( 22b . 23a ); and an upper electrode layer ( 24a . 23b ) above the substrate ( 20a . 20b ) is formed; the insulating layer ( 23a . 22b ) is at least partially in an antiferroelectric phase. An integrated capacitor (ICea, ICeb) according to claim 13, wherein the insulating layer ( 23a . 22b ) Hf _a X _b O ₂ with a, b> 0, wherein X is provided by Zr or Si or Al or Ge or Mg or Ca or Sr or Ba or Ti or a rare earth element. The integrated capacitor (ICeb, ICea) of claim 14, wherein X is provided by Zr and a <0.5, b> 0.5. An integrated capacitor (ICea) according to any one of claims 13 to 15, further comprising a bottom electrode layer (12). 22a ) on the semiconductor substrate ( 20a ), and wherein the insulating layer ( 23a ) on the lower electrode layer ( 22a ) is formed. Integrated capacitor (ICeb) according to one of Claims 13 to 16, in which the substrate ( 20b ) is doped to form a lower electrode of the integrated capacitor. The integrated capacitor (ICeb) of any one of claims 13 to 17, wherein the integrated capacitor is a buffer or memory or boost capacitor in an integrated circuit. A method of forming an integrated circuit device (ICea, ICeb) comprising: providing a substrate ( 20a . 20b ); Depositing an amorphous high-k dielectric material layer ( 23a . 22b ) on the substrate ( 20a . 20b ); Depositing a cover layer ( 24a . 23b ) on the amorphous high-k dielectric material layer ( 23a . 22b ); and causing at least partial crystallization in the high-k amorphous dielectric material layer ( 23a . 22b ), wherein at least the partially crystallized high-k dielectric material layer ( 23a . 22b ) in an antiferroelectric phase. A method according to claim 19, wherein the cover layer ( 24a . 23b ) is deposited prior to causing the at least partial crystallization and the deposition of the cover layer ( 24a . 23b ) comprises performing a deposition process at process temperatures below the crystallization temperature of the high-k amorphous dielectric material layer ( 24a . 23b ) are.

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