DE102014108497A1 - Circuit arrangement and method for bidirectional data transmission - Google Patents

Abstract

A transmitter arrangement for signal transmission is provided, the transmitter arrangement having at least one transmitter with a primary coil and a secondary coil and a controller. The controller is configured to control a first current that is to flow through the primary coil in a magnetization phase so that it is increased until a predefined criterion is met, the magnetization phase being longer than a time constant of the primary coil of the at least one transformer . The controller is configured to apply a voltage to the at least one transformer in a voltage application phase, so that a second current flows through the primary coil, the second current having a polarity that changes during the voltage application phase compared to the first current, wherein the voltage application phase is shorter than twice the time constant of the primary coil of the at least one transformer.

Description

Cross-reference to related application

This application is related to US Provisional Application No. 61 / 835,745 entitled "BIDIRECTIONAL DATA TRANSMISSION CIRCUIT ARRANGEMENT AND METHOD" filed on Jun. 17, 2013, which is incorporated herein by reference, and claims the benefit of the date of filing thereof.

Technical area

Various embodiments generally relate to the transmission of clock signals and data signals over a galvanically isolated interface. The galvanically isolated interface can be a transformer, for example a transformer without an iron core. The clock signal may be transmitted in one direction and the data signal in the same or in an opposite direction via the interface. The transmission of the data signal and the clock signal can be synchronized.

Background of the invention

Various embodiments may be used in products in which power can be transmitted through another transformer without an iron core. Due to the poor efficiency of the energy transfer, it is desirable to keep the power consumption on the side that receives the clock signal and transmits the data signals low. An example of such a product may be a galvanically isolated analog-to-digital converter (ADC) with an integrated, galvanically isolated power supply. The transmitted clock signal may be used as the clock signal of the analog-to-digital converter. The analog-to-digital converter may be a sigma-delta converter. The data signals to be transmitted in the other direction may be the data provided by one or two sigma-delta converters. The transmissions in both directions should be robust with respect to common mode signals on the galvanically isolated interface. In particular, the clock signal should be transmitted robust enough that common-mode signals do not cause any additional jitter in it.

short version

Various embodiments for transmitting edges of a clock signal to a receiver may apply edges of opposite polarities to a primary coil (or to a pair of primary coils) of a transformer. For a reverse edge of the clock signal, reverse polarities can be used. Before transmitting an edge of a clock signal, the primary coil (s) may be magnetized in opposite directions. The time required for the magnetization may be longer than the L / R time constant of the primary coil (s). After the transmission of the edge of the clock signal, the primary coil (s) can be demagnetized. Drivers with a balanced impedance can be used to magnetize and demagnetize the coils to prevent common mode signals between the two transformers from being converted into differential signals.

During demagnetization, the value zero does not have to be reached; it can be stopped at a low value. By then shutting off the driver, the magnetization can jump to zero, whereby a vibration with its resonant frequency can be induced in the pair of transformers. The resonant frequency can be reduced by providing an additional capacitor in the resonant circuit. The damping of the resonant circuit or the oscillation can be partially or completely compensated for by providing a circuit with a negative differential resistance. The vibration in the pair of transmitters may then be left for a longer time or remain undamped.

The damping of the resonant circuit can be amplified from the secondary side by a switch for shorting the secondary coils. The resulting attenuation should be strong enough that the induced vibration can be attenuated fast enough even if there is a circuit with a negative differential resistance. On the primary side it can be detected whether and how quickly the oscillation decays, for example by means of an amplitude detector or by counting the number of oscillations exceeding a given amplitude.

The opening and closing of the switch can be done with very little power consumption and allow the transmission of a bit with each edge of a clock signal. Thus, two bits can be transmitted during a cycle time. The transmission is very robust to common mode signal interference because of the symmetrical design of the pair of transmitters and the high resonant frequency.

Brief description of the drawings

In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale, with the focus instead in the Generally, it is an illustration of the principles of the invention. In the drawings, the leftmost digit (s) of a reference numeral may indicate the drawing in which the numeral appears for the first time. The same numbers may be used throughout the drawings to refer to like features and components. In the following description, various embodiments of the invention will be described with reference to the following drawings, in which:

shows an embodiment of a transformer arrangement;

shows an embodiment with details of a transformer arrangement;

Examples of signal sequences of a transformer arrangement;

an embodiment of a circuit;

Examples of signal sequences of a transformer arrangement;

Examples of signal sequences of a transformer arrangement;

an embodiment of a circuit arrangement shows;

Examples of signal sequences of a transformer arrangement;

an embodiment of a circuit arrangement shows;

Examples of signal sequences of a transformer arrangement;

shows an embodiment of a circuit for encoding data and clock signals; and

shows an embodiment of a circuit for decoding clock signals and additional data signals.

description

The following detailed description refers to the accompanying drawings which show, by way of illustration, specific details and embodiments with which the invention may be practiced.

The use of the term "exemplary" as used herein means "by way of example, case or illustration." Any embodiment or embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or embodiments.

shows an embodiment of a transformer assembly 100 for bidirectional signal transmission. The transformer arrangement 100 can have a low side (LS) and a high side (HS). The low-voltage side LS and the high-voltage side HS can by at least one transformer 102 be galvanically isolated from each other. A clock signal T on the low voltage side LS may be used to generate a clock signal t on the high voltage side HS. The data signals d1, d2 on the high voltage side HS can be used to generate data signals D1, D2 on the low voltage side LS. The high voltage side HS can be one or two analog-to-digital converters 108 have, which can provide the data signals d1, d2 available. They can be clocked by the clock signal t, which can be based on the clock signal T. The data signals may be synchronized with the clock signals.

The at least one transformer 102 can have a variety of transformers. The following embodiments have two transformers 102 However, a different number of transmitters may be used. Every transformer 102 may comprise a primary coil P1, P2 and a secondary coil S1, S2. The primary coils P1, P2 may be disposed on the low-voltage side LS or primary side, and the secondary coils S1, S2 may be disposed on the high-voltage side HS or secondary side. The primary coils P1, P2 of the plurality of transformers may be connected in series. A node PG between the primary coils P1, P2 may be connected to a reference voltage. The secondary coils S1, S2 of the plurality of transformers may be connected in series. A node SG between the secondary coils S1, S2 may be connected to another reference voltage. A high symmetry of the transformers 102 can lead to a good suppression of common mode interference. But it can also be embodiments with only one transformer 102 be used. The transformer 102 can be a transformer without iron core.

The low voltage side LS may be a low voltage circuit 104 exhibit. The low voltage circuit 104 may have an input for a clock signal T and two data outputs D1, D2. It may also be connected to the primary coils P1, P2 and the node PG. The high voltage side HS may be a high voltage circuit 106 exhibit. The high voltage circuit 106 may have an output for a clock signal t and two data inputs d1, d2. She is further connected to the secondary coils S1, S2 and the node SG.

shows an embodiment with details of the low voltage circuit 104 and the high voltage circuit 106 , The low voltage circuit 104 can be a controller 202 exhibit. The high voltage circuit 106 can be a receiver circuit 204 exhibit.

The control 202 may be coupled to the primary coils P1, P2. It can be used as a driver for the primary coils P1, P2, for example for transmitting a clock signal via the transmitter 102 , The transmission may include a magnetization phase (MP), a voltage application phase (VP) and a demagnetization phase (DP). In the magnetization phase MP, resistors can be coupled in parallel stepwise between the primary coils P1, P2 and a supply voltage. In the voltage application phase VP, which may also be referred to as a pulse phase, the voltage across the primary coils P1, P2 and the current through the primary coils may change polarity. In the demagnetization phase DP, the resistances between the primary coils P1, P2 and the supply potential can be separated step by step.

The control 202 may be configured to control a first current to flow through the primary coil P1, P2 in a magnetization phase MP so that it is increased until a predefined criterion is met. The magnetization phase MP may be longer than a time constant TP = L / R of the primary coil P1, P2 of the transformer 102 , L, the inductance of the primary coil P1, P2 and R may be the resistance of the primary coil P1, P2. The magnetization phase MP may, for example, be longer than twice the time constant TP of the primary coil P1, P2 of the transformer 102 , The control 202 may be configured such that the time for the magnetization phase MP is in the range of about 5 ns to about 30 ns. For example, it may then be in the range of about 7 ns to about 20 ns. For example, it can range from about 9 ns to about 15 ns. For example, it may be about 10 ns.

The time constant TP = L / R TP of the primary coil P1, P2 of the transformer 102 may be in the range of about 1 ns to about 10 ns. For example, it may range from about 2 ns to about 6 ns. For example, it may range from about 3 ns to about 4 ns. The control 202 may further be configured to apply voltage to the transmitter in a voltage application phase VP 102 to apply, so that a second current flows through the primary coil P1, P2. The second stream can be the transformer 102 magnetize. The second current may have a polarity that changes during the voltage application phase VP compared to the polarity of the first current. The voltage application phase VP can be shorter than twice the time constant TP of the primary coil P1, P2 of the transformer 102 , For example, it may be shorter than the time constant TP of the primary coil P1, P2 of the transformer 102 , The control 202 may be configured such that the time for the voltage application phase VP is in the range of about 0.5 ns to about 6 ns. For example, it can range from about 1 ns to about 4 ns. For example, it may range from about 2 ns to about 3 ns.

The control 202 Further, it may be configured to control, in a demagnetization phase DP, a third current flowing through the primary coil P1, P2 to be reduced. The third stream can be the transformer 102 demagnetize. The demagnetization phase DP can be longer than the time constant TP of the primary coil P1, P2 of the transformer 102 , For example, it may be longer than twice the time constant TP of the primary coil P1, P2 of the transformer 102 , The control 202 may be configured such that the time for the demagnetization phase DP is in the range of about 5 ns to about 30 ns. For example, it can range from about 7 ns to about 20 ns. For example, it can range from about 9 ns to about 15 ns. For example, it may be about 10 ns.

shows examples of a signal sequence 302 of a current IP1 flowing through the primary coil P1, a signal sequence 304 a voltage VP1 through the primary coil P1 and a signal sequence 306 a voltage VS1 through the secondary coil S1. The signal sequences 302 . 304 and 306 may correspond to a magnetization phase MP from time t0 to t1, a voltage application phase VP from time t1 to t2, and a demagnetization phase DP from time t2 to t3.

At time t0, the current IP1 through the primary coil P1 may begin to slowly increase in the negative direction. It can increase until it reaches a negative peak at time t1. The period between t1 and t0 may be longer than the time constant TP = L / R of the primary coil P1. The increase of the current IP1 may be selected such that only a small and approximately constant negative voltage VS1 is present at the secondary coil S1.

At the time t1, the primary coil P1 can be connected to a predefined voltage Vpd, for example a supply voltage. It can remain connected until the time t2, see signal sequence 304 , The period between t1 and t2 may be shorter than the time constant TP = L / R of the primary coil P1. He can be chosen so that the Current IP1 at the times t1 and t2 opposite polarities, for example, the same size. For example, IP1 may be negative at time t1 and have a size -A, and at time t2 IP1 may be positive and have a size + A. It follows that a large positive pulse can be induced in the secondary coil S1, see signal sequence 306 , The momentum can decrease exponentially.

At time t2, the current IP1 through the primary coil P1 may begin slowly decreasing to zero. It can reach zero at time t3. The period between t2 and t3 may be greater than the time constant TP = L / R of the primary coil P1. The decrease in the current IP1 can be selected so that only a small and approximately constant negative voltage VS1 is present at the secondary coil S1.

The magnetization of the transformer in an opposite direction prior to inducing the pulse in the secondary coil S1 may have the advantage that the maximum current that must be supplied by the power supply can be reduced. Further, the ratio of the voltage induced in the secondary coil in the opposite direction to the amount of the charge supplied from the power supply is higher.

Each signal sequence IP1, VP1, VS1 may have a complementary signal sequence IP2, VP2, VS2 when the transmitter 102 is symmetrical, that is, it has two complementary primary coils P1, P2 and two complementary secondary coils S1, S2. When there is no common mode interference and when the current flowing into the primary coil P1 is the same as the current flowing out of the primary coil P2, no current flows through the common node PG. The control 202 is responsible for the in shown signal sequences can be achieved.

shows an embodiment of a circuit 400 to the controller 202 can be coupled. The control 202 may be configured to receive the first current passing through the primary coil P1, P2 of the transformer 102 flow, gradually increase. The circuit 400 can be used to provide for the slow increase and decrease of the current IP1, IP2, which drives the primary coils P1, P2. It can handle a large number of subcircuits connected in parallel 402 exhibit. Every subcircuit 402 may comprise a series connection of a switch S and a resistor R. A first connection 404 every subcircuit 402 may be coupled to a reference potential Vs, Ground (GND), and a second terminal 406 every subcircuit 402 can to the transformer 102 , For example, be coupled to one of its primary coils P1, P2. The node PG between the primary coils P1 and P2 may be connected to a reference voltage (Vref). The reference voltage Vref may be about half of a supply voltage Vs.

A first variety 408 of subcircuits 402 may be connected to a first voltage, for example the supply voltage Vs, connected first terminals 404 and second terminals connected to the primary coil P1 406 exhibit. The switches S in the first plurality 408 of subcircuits 402 may be controlled by signals g5 to g8 to provide a gradual current IP1 in one direction in the primary coil P1. The current IP1 can gradually decrease in strength.

A second variety 412 of subcircuits 402 may be connected to a second voltage, for example a ground voltage GND, connected first terminals 404 and second terminals connected to the primary coil P2 406 include. The switches S in the second plurality 412 of subcircuits 402 can also be controlled by the signals g5 to g8 to provide a stepwise current IP2 in one direction of the primary coil P2. The current IP2 may gradually decrease in strength.

A third variety 410 of subcircuits 402 may be connected to a first voltage, for example the supply voltage Vs, connected first terminals 404 and second terminals connected to the primary coil P2 406 exhibit. The switches S in the third plurality 410 of subcircuits 402 can be controlled by the signals g1 to g4 to have a gradual current IP2 in an opposite direction to the direction of the current IP2, that of the second plurality 412 provided in the primary coil P2. The current IP2 can gradually increase in strength.

A fourth variety 414 of subcircuits 402 may be connected to a second voltage, for example a ground voltage GND, connected first terminals 404 and second terminals connected to the primary coil P1 406 exhibit. The switches S in the fourth plurality 414 of subcircuits 402 can also be controlled by the signals g1 to g4 to have a gradual current IP1 in an opposite direction to the direction of the current IP1, that of the first plurality 408 the primary coil P1 is provided. The current IP21 can gradually increase in strength.

To clarify are the pluralities 408 . 410 . 412 . 414 of subcircuits 402 , which are used for magnetization and demagnetization, with four subcircuits 402 shown. It can however any number, for example six to eight, subcircuits 402 be used. Some of the subcircuits 402 , for example the subcircuits controlled by signal g5 402 , can have a resistance R with a zero resistance.

In principle, series-connected resistors R can also be used to provide increasing and decreasing currents. However, this can be detrimental to the overall chip area needed for the switches and their parasitic capacitances.

In driving the primary coils P1, P2, maximum symmetry can be achieved by connecting resistors stepwise in parallel between the primary coils P1, P2 and the power supply Vs. The use of resistors can have the advantage that a symmetrical output resistance of the driver is always provided. It may be difficult to achieve balanced output resistance with stepped PMOS and NMOS transistors because the output resistance will only be as symmetrical as the symmetry of the complementarily-generated transistors allows. The switches can be arranged symmetrically.

shows a circuit 400 for transmitting positive pulses from positive edges. The same circuit 400 may be required to transmit negative pulses. In this case, the connections to P1 and P2 may need to be swapped. The resistor R can be commonly used, so that only the switches S must be provided again.

The resistance of at least some of the resistors R may be greater than the resistance of the primary coil. The resistance of at least some of the resistors R may range from about 10 ohms to about 1000 ohms. The resistance of all resistors R can be the same. The resistance of the primary coil P1, P2 can range from about 1 ohm to about 50 ohms.

shows examples of signal sequences 502 with the signals g1 to g8 for controlling the switches S, a signal sequence 504 of a current IP1 flowing through the primary coil P1, a signal sequence 506 a voltage VP1 through the primary coil P1 and a signal sequence 508 a voltage VS1 through the secondary coil S1. For the sake of clarity shows only the signal sequences 504 . 506 and 508 of the current IP1 and the voltages VP1, VS1 of the primary coil P1. The current IP2 flowing through the primary coil P2, the voltage VP2 through the primary coil P2 and the voltage VS2 through the secondary coil S2 may be complementary to the signal sequences shown or vice versa.

All switches S can be open when no signal is to be transmitted. They may be open before the magnetization phase MP starts at time t0. The switches S, which are controlled by the signals g1 to g4, can be closed one after the other in the magnetization phase MP. The current IP1 through the primary coils P1 can then increase gradually, since the resistors R are connected in parallel.

At the time t1, all the switches S controlled by the signals g1 to g4 can be opened and the switches S controlled by the signal g5 can be closed at the same time. Between times t1 and t2, which may be the voltage application phase VP or the pulse phase, the switches S controlled by the signals g6 to g8 may be closed simultaneously, for example. The current IP1 through the primary coils P1 can then increase sharply in the opposite direction.

Between times t2 to t3, which may be the demagnetization phase DP, the switches S controlled by the signals g5 to g8 may be successively opened, for example in this order, starting with the switches S controlled by the signals g5. The current IP1 through the primary coils P1 can then gradually decrease, since the resistors R are separated one after the other. After the demagnetization phase has ended, all switches S can be opened.

The evaluation of the voltages VS1, VS2 at the secondary coils S1, S2 and the reconstruction of the clock signal T can be achieved using comparators and a memory element, for example an RS flip-flop. As in 2, the transmission of a rising edge signal on a coil on the primary side P1 to a large positive pulse PP in the coil of the secondary side 51 which can be accompanied by a large number of smaller NP negative pulses. Conversely, the transmission of a negative edge signal to a coil on the primary side can result in a large negative pulse in the coil on the secondary side, which may be accompanied by a multiplicity of smaller positive pulses. Therefore, a comparator should only detect the large pulses and be insensitive to the smaller pulses if they are of opposite polarity. The sensitivity of the comparator, or in other words the comparator threshold, should therefore be between the amplitude of the large pulses and the amplitude of the smaller pulses. The sensitivity may be fixed or a temperature dependence have, which compensates for the temperature dependence of the transmission path.

Vibrations in gaps between the transmission of clock signals can be used to transmit data in the reverse direction, and they can also be present in the signals on the coils on the secondary side and at the input of the comparator. The amplitudes of these vibrations can be difficult to reproduce. They may depend on the quality Q of the resonant circuit formed by the transmitter or the pair of transformers. The embodiments may therefore have an automatic adjustment or adjustment of the sensitivity of the comparator.

shows examples of a signal sequence 602 a secondary coil voltage VS1, a signal sequence 604 an output K1 of a first comparator, a signal sequence 606 an output K2 of a second comparator, a signal sequence 608 a first output K3p of a third comparator and a signal sequence 610 a second output K3n of the third comparator.

The signal sequence 602 shows a typical voltage waveform VS1 at a secondary coil S1 with a positive edge (PE) transmission of the clock signal, oscillation (Oscillation, OS) for transmission in an opposite or reverse direction and transmission of a negative edge (Negative Edge, NE) of the clock signal. A receiver circuit 204 can use two window comparators with adjustable sensitivity or with adjustable thresholds. The thresholds can be symmetrical about zero. The comparator output may be inactive and may, for example, have a signal "0" if no input signal is applied thereto. If the input signal exceeds the threshold of the comparator, the comparator output may be active and, for example, output a signal "1".

The threshold of one of the window comparators may be adjusted, that is, it may be increased or decreased until the duty cycle from active to inactive has reached a predetermined value, for example 2%. The equilibrium threshold is in the signal sequence 602 out shown as E1p for positive voltages and E1n for negative voltages. The output of the comparator is in the signal sequence 604 shown as K1. The time during which signal VS1 is greater than E1p may be T1. The time during which signal VS1 is less than E1n may also be T1. The thresholds E1p, E1n may be near or near the amplitudes of the large pulses. If some of the large pulses do not have the same amplitude, which may be, for example, if there are spurious signals, then no large pulse may appear in K1. However, this is not important since only the average duty cycle over a plurality of pulses is relevant.

The threshold of the other window comparator may be adjusted, that is, it may be increased or decreased until the duty cycle from active to inactive reaches another predefined value, for example 10%. The equilibrium threshold is in the signal sequence 602 out shown as E2p for positive voltages and E2n for negative voltages. The output of the comparator is in the signal sequence 606 shown as K2. The time during which signal VS1 is greater than E2p may be T2. The time during which signal VS1 is less than E2n may also be T2. If the large pulses are shorter than 10% of the time between them, the equilibrium threshold may be such that some but not all of the pulses may be in the reverse direction at output K2 of the comparator.

Furthermore, two comparators can be used, which are not window comparators, that is, they only detect signals in one direction. However, they may have the same dependence on a control signal for adjusting the sensitivity or threshold of the comparator as the window comparators. It is possible that one of the comparators only detects signals that exceed its threshold E3p in a positive direction and that the other comparator only detects signals that exceed its threshold E3n in a negative direction. The sensitivities or thresholds E3 of the two comparators can be set to the average value of the equilibrium thresholds E1 and E2. This can lead to the highest transmission reliability, in which the two transformers evaluate all large pulses and none of the smaller pulses or oscillations for clock signal recovery.

Alternatively, two identical comparators with reversed inputs can be used. Furthermore, each of the window comparators can be implemented by means of two comparators with reversed inputs, with the outputs of the two comparators being ORed. This can have the advantage that all comparators can be built in the same way and have very similar properties. A circuit arrangement using these alternatives is shown in FIG shown.

shows an embodiment of a circuit arrangement 700 , The circuit arrangement 700 can be a receiver circuit 204 for pulses at the secondary coils S1, S2, which are in the Related to shown and described. The circuit arrangement 700 can have at least three comparators 702 . 706 . 704 and have a control circuit. The first comparator circuit 702 , the second comparator circuit 704 and the third comparator circuit 706 can be coupled to the secondary coil S1, S2. The first comparator circuit 702 , the second comparator circuit 704 and the third comparator circuit 706 each may be configured to receive the same signal, for example a voltage VS between the secondary coils S1, S2. The three comparators 702 . 706 . 704 can be built and designed in the same way. The sensitivity or comparator threshold of each comparator 702 . 706 . 704 can be independent of the other comparators 702 . 706 . 704 be set. The control circuit may be a first control system 710 , a second regulatory system 712 and coupling elements 714 . 716 exhibit.

The first comparator 702 can be a first regulatory system 710 exhibit. The first control system 710 may be the sensitivity or the first comparator threshold E1p, E1n of the first comparator 702 in response to a duty cycle of a signal K1 at an output of the first comparator 702 Adjust to achieve a first Bezugstastgrad. A feedback signal F1 from the first control system 710 can be output to a threshold setting input 718 of the first comparator 702 be connected. The first control system 710 For example, a capacitor may be charged when the output of the first comparator is charged 702 is active, and discharges when the output of the first comparator 702 is inactive. The discharge current may be, for example, 2% of the charging current. A voltage through the capacitor may be or may be the first comparator threshold. The capacitor can serve as an integrating circuit and smooth the feedback signal F1. A remaining ripple in the feedback signal F1 usually remains without consequences.

Similarly, the second comparator 704 a second regulatory system 712 exhibit. The second control system 712 may be the sensitivity or the second comparator threshold E2p, E2n of the second comparator 704 in response to a duty cycle of a signal K2 at an output of the second comparator 704 adjust to achieve a second reference duty cycle. A feedback signal F2 from the second control system 712 can be output to a threshold setting input 720 of the second comparator 704 be connected. The second control system 712 For example, it may have a capacitor that is charged when the output of the second comparator 704 is active, and discharges when the output of the second comparator 704 is inactive. The discharge current may be, for example, 10% of the charging current. A voltage across the capacitor may be or may be the second comparator threshold. The capacitor can serve as an integrating circuit and smooth the feedback signal F2. A remaining ripple in the feedback signal F2 usually remains without consequences.

The sensitivity or the third comparator threshold E3p, E3n of the third comparator 706 can be set to be between the sensitivities E1p, E1n, E2p, E2n of the first comparator 702 and the second comparator 704 lies. A signal F3 may be applied to a threshold adjustment input 722 of the third comparator 706 be connected. The signal F3 can via a coupling element 714 to the feedback signal F1 and via a coupling element 716 be coupled to the feedback signal F2. The value of the signal F3 may therefore be between the value of the feedback signal F1 and the value of the feedback signal F2. The coupling elements 714 . 716 For example, resistors may have the same resistance, for example.

The control circuit may be configured to adjust the first comparator threshold E1p, E1n such that the first comparator circuit 702 in a first comparator output state, for example, a logic "1" for a first time period T1 of a predefined time interval.

The control circuit may be further configured to adjust the second comparator threshold E2p, E2n such that the second comparator circuit 704 for a second time period T2 of the predefined time interval in a first comparator output state, for example a logical "1", wherein the second time period T2 is longer than the first time period T1.

The control circuit may be configured to set the third comparator threshold E3p, E3n to lie between the first comparator threshold E1p, E1n and the second comparator threshold E2p, E2n.

At least one of the first time period T1 and the second time period T2 may be the sum of a plurality of time subsections.

At least one of the first comparator circuit 702 and the second comparator circuit 704 can be configured as a window comparator circuit. The third comparator circuit 706 may be configured to provide an evaluation output signal K3p, K3n.

A storage element 708 can be connected to the output K3n, K3p of the third comparator circuit 706 be coupled to store the Auswerteausgangssignal. The storage element 708 may be a flip-flop, for example an RS flip-flop. A set input S may be connected to the output K3p, and a reset input R may be connected to the output K3n. The output of the memory element 708 may be the clock signal t.

The control circuit 710 . 712 may be configured to include at least one of the first threshold E1p, E1n based on that of the first comparator circuit 702 or the second threshold E2p, E2n based on that of the second comparator circuit 704 adapted output signal K2 adapt.

The control circuit 710 . 712 may be configured to include at least one of the first threshold E1p, E1n based on a time-based evaluation of that from the first comparator circuit 702 adapted output signal K1 or the second threshold E2p, E2n based on a time-based evaluation of the second comparator circuit 704 adapted output signal K2 adapt.

The control circuit 710 . 712 may be configured to adjust at least one of the first threshold E1p, E1n based on the output signal K1 provided by the first comparator circuit, wherein a first signal state of the output signal K1 and a second signal state of the output signal K1 are weighted differently, or the second threshold E2p, E2n based on that of the second comparator circuit 704 adjusted output signal K2, wherein a first signal state of the output signal K2 and a second signal state of the output signal K2 are weighted differently.

The control circuit 710 . 712 may be configured to include at least one of the first threshold E1p, E1n based on averaging of that of the first comparator circuit 702 or the second threshold E2p, E2n based on averaging of the second comparator circuit 704 adapted output signal K2 adapt.

shows examples of a signal sequence 802 a current IP1 through a primary coil P1, a signal sequence 804 a voltage VP1 via a primary coil P1 and a signal sequence 806 a switching control signal SD over time t. The signal sequences 802 . 804 . 806 can occur during a data transmission via a transformer, for example a transformer without an iron core, wherein time points are transmitted by pulses in one direction. Each pulse can induce a vibration in the transmitter. By attenuating or not attenuating the induced vibration, data may be transferred in the other direction.

The current IP1 can be compared to the in and shown current IP1 be modified so that it is also slowly, starting at the time t2, slowly reduced, but not until it reaches zero. Rather, it is suddenly interrupted at time t3 and jumps to zero, which can induce or trigger vibration in the transmitter or in the pair of transmitters. The frequency of the oscillation may be the resonant frequency of the transformer or the pair of transformers. The frequency can be lowered when a resonant circuit capacitor is used.

A common tank capacitor may be useful when using a pair of transformers. The oscillations at the primary coils P1, P2 may initially have mutually opposite phases. A common resonant circuit capacitor can prevent a change in this phase relationship due to slightly different resonant frequencies of the transmitter coils. The resonant circuit may then consist of the series-connected primary coils and the capacitor.

The damping of the vibration may largely depend on the quality factor Q of the resonant circuit, which may be affected by the quality factor of the transformer. The quality factor of a transformer integrated in a semiconductor chip may be relatively low, ranging, for example, from 5 to 10. An exciter circuit, for example with a dynamic negative internal resistor that compensates for the losses in the transmitter, may be used to extend the time of the ringing. For example, an excitation circuit of an LC oscillator may be used. The degree of excitation can be reduced with the amplitude of the oscillation to avoid overexcitation. In the case of overexcitation, it may be difficult to separate the large impulses from the vibrations, as related to was discussed.

There may be a switch on the secondary side or high voltage side HS 206 be provided, for example, as it is in is shown. The desk 206 can be used to short-circuit the secondary coil or secondary coils S1, S2. The quality factor on the primary side or low side LS can be much lower when the switch 206 is closed as if the switch 206 is open. If the excitation is not too great, the amplitudes of the oscillation decrease very rapidly when the switch 206 is closed.

A circuit on the high voltage side HS for controlling the switch 206 may be configured to, after having received a pulse in the direction of the clock signal, the switch 206 for a certain period of time, TD closes when a bit to be transmitted in the data signal direction has a certain value, for example "1", and it can be configured so that, if the bit to be transmitted has a different value, for example "0". , the switch 206 does not close. The period TD may be shorter than the period TT between two clock edges so as not to disturb the reception of the next clock edge.

It is possible that the LC oscillator does not stop the oscillation immediately after the switch 206 is opened, starts because the vibration has already largely subsided and at this time due to an abrupt halting of the demagnetization is no excitation. It is possible that the LC oscillator provides only an exponentially increasing oscillation amplitude, which, however, starts from a very small value if the oscillation has previously been sufficiently sufficiently damped.

In principle it is possible to use the switch 206 keep closed until the next edge of the clock signal has been received. A prerequisite for this may be that the switch has a current limiting behavior, that is, it has a strongly increasing on resistance for stronger currents flowing through it. Such behavior can be achieved by operating field effect transistors with a gate voltage slightly above the threshold voltage. A voltage pulse on the secondary side may be attenuated by the closed current limit switch when the next clock edge is received. However, it will still have a sufficient value that can be detected if the current limit is correct. The detection circuit and the method associated with and may be useful in this regard.

The detection of data bits in the data direction on the low voltage side LS can be achieved, for example, by amplitude detection, for example by an amplitude detection circuit 210 as they are for example in is shown. When the switch 206 On the high voltage side HS is closed only for a certain period of time, the amplitude of the oscillation can be detected at a time that can be delayed with respect to the transmission of the last edge of the clock signal by the same period during which the switch 206 is closed on the high voltage side HS, but at the latest shortly before the transmission of the next edge of the clock signal. When the switch 206 remains closed on the high voltage side HS until the next edge of the clock signal, it is sufficient if the detection takes place immediately before the transmission of the next clock signal edge, or more precisely, before the next magnetization phase.

Alternatively to the above, the number of oscillations or cycles detected by a comparator having a certain threshold may be counted. When a "1" is transmitted, only a few oscillations or cycles are detected compared to the case where a "0" is transmitted, in which significantly more oscillations or cycles can be detected. A digital evaluation circuit can statistically evaluate the respective counts and set a threshold below which the number of oscillations is interpreted as a "1" and above which the number of oscillations is interpreted as a "0".

Since a data bit can be transferred between the transmission of two edges of the clock signal, it is possible to transmit two bits of data of one data stream during each clock period. For example, it is possible to transmit the data streams from two sigma-delta modulators, which are clocked using the clock signal. Alternatively, and as an example, the data stream may be transmitted by a sigma-delta modulator as well as additional redundancy information. If more than two bits are to be transmitted during one clock period, it is possible to repeat the transmission of each clock edge after one quarter of the clock period and thereafter to transmit another bit in the data stream direction.

A transformer arrangement for signal transmission may comprise at least one transmitter, a controller and a circuit. The transformer may have a primary coil and a secondary coil. The transmitter arrangement may have a resonant frequency. The controller may be configured to terminate driving the primary coil so that the transmitter assembly resonates at resonant frequency. The circuit may be coupled to the secondary coil and configured to vibrate the transmitter assembly in a first switching state and reduce the vibration of the transmitter assembly in a second switching state. The driving of the primary coil may be at least one of a magnetization phase; a demagnetization phase or a voltage application phase. The primary coil can be driven after a certain period of time has elapsed after completion of the driving of the primary coil. The transmitter assembly may further include an amplitude detection circuit that may be coupled to the primary coil. The predetermined period of time may be chosen to be long enough to reduce the oscillation when the circuit is in a second switching state and to be long enough for the reduction in the oscillation in the amplitude detection circuit to be detected. The period in which the circuit is in the second switching state may be shorter than the predetermined time before the start of the driving of the coil. The magnetization direction of the continuous driving of the primary coil phases may have opposite polarities. The magnetization direction of the continuous driving of the primary coil phases may have the same polarity at a certain number of the continuous driving of the primary coil phases. During the certain time before the start of the driving of the coil, a bit can be transmitted by detecting whether the oscillation has decreased or not.

The related to described circuit arrangement 400 For magnetization and demagnetization of the transformer or pair of transformers, it is necessary to provide continuous timings at short intervals to sequentially add or remove the resistors. The time intervals between these points can be significantly shorter than the L / R time constant of the primary coil (s). The L / R time constant of a transformer integrated in a semiconductor chip may be in the range of 5 ns. Therefore, it may be necessary to provide timings with time intervals of 1 ns to 2 ns between them.

The symmetry of the peak currents in the primary coil at times t1 and t2 may largely depend on the maintenance of the time intervals between t0 and t1 and between t1 and t2. Furthermore, the amplitude of the post-oscillation after the pulse after the abrupt termination of the demagnetization phase DP may depend on the maintenance of the time intervals between t2 and t3. The generation of successive digital signals in short time intervals can be achieved by using a chain of inverse circuits. However, a chain of inverter circuits may not be accurate enough, as the delay through the inverter circuits may be heavily dependent on processing parameters, supply voltage, and temperature. Another method of generating successive signals at nanosecond intervals may be the use of a digital PWM (Pulse Width Modulator) modulator. Here, the period of a clock signal can be divided into equal time intervals by using a control circuit and adjustable delay elements. Such a circuit may require adjusting the number of delay elements depending on the frequency of the clock signal, which may involve a significant overhead in chip design when using the transmission channel in a higher level system. A simple and autonomous circuit arrangement for generating sequential signals using relatively accurate and reproducible time intervals is presented.

The circuit arrangement is based on the recognition that the total delay between an input signal and an output signal is irrelevant; rather, the time interval between the output signals is important. Delay circuits with different delay times can be used. An input signal may be simultaneously applied to the inputs of the delay circuits, which may result in signals at the outputs of the delay circuits, which may be offset from one another. The delay elements are designed so that at least one processing parameter has the greatest impact on the delay elements with the shortest delay and an offset lower impact on delay elements with longer delays. Processing parameters that may be designed to affect the circuit include, for example, the width or side dimension of resistors and capacitors. The size of the capacitor can increase with the desired delay. A capacitor with a larger delay time may be less dependent on changes in the pattern width if the capacitor is not built using unit capacitors.

The delay element with the shortest delay may have resistors with a small width. The resistors in delay elements with a longer delay may have a larger width. The width of the resistor can be proportional to the delay time. For a given resistor, resistors with a larger width may need to be longer. Finally, the achievable ratio between the longest and shortest time delays may be a matter of chip area.

The delay circuits may use phase-shifted or out-of-phase signals in a delay element. As a result, the dependence on the threshold voltages of the inverter circuits can be reduced. The delay circuits can be constructed symmetrically. You can both one Process signal as well as a complementary signal. As a result, the coding of the required control signals for the switches can be simplified because there is a complementary signal to each signal and the number of gates in each signal path is constant.

shows an embodiment of a circuit arrangement 900 , The circuit arrangement 900 can be three delay circuits 902 . 904 . 914 exhibit. Each delay circuit 902 . 904 . 914 can have two delay levels 920 . 924 . 928 exhibit. The two delay stages 920 . 924 . 928 can be operated in phase opposition. The delay level 920 can be a resistance 906 with a resistor R and a capacitor 910 having a capacity C. The width of the resistor 906 may be 400 nm, for example. The capacitor 910 may, for example, have a size of 2 × 2 μm. The delay level 924 can be a resistance 908 with a resistor R and a capacitor 912 having a capacity of 1.5C. The width of the resistor 908 may be 600 nm, for example. The capacitor 912 may, for example, have a size of 2 × 3 μm. The delay level 928 can be a resistance 916 with a resistor R and a capacitor 918 having a capacity 2 C. The width of the resistor 916 may be 800 nm, for example. The capacitor 918 may, for example, have a size of 2 × 4 μm.

The signal DL2 at an output of the delay circuit 904 can with respect to the signal DL1 at an output of the delay circuit 902 to be delayed by RC. The signal DL3 at an output of the delay circuit 914 can be delayed by more RC. R may be the resistance selected by the design multiplied by the changes in the film resistance but without influence of changes of the structural width or side dimension. The capacitors 910 . 912 . 918 can be manufactured as MOS capacitors with very tight tolerances. The non-linearity normally associated with MOS capacitors may be achieved by the series connection of the antiphase delay stages 920 . 924 . 928 be compensated so that the symmetry of the delay time for rising and falling edges is not affected.

The running time and the delay time of the wiring used are the same for all the delay circuits and do not affect the time difference between the output signals DL1, DL2, DL3.

The circuit arrangement 900 may be a pulse generating circuit configured to provide a pulse. It can generate two signals or pulses from a common input signal. A first signal of the two signals may have a shorter time delay from the common input signal than a time delay of a second signal from the common input signal. The time delay of the first signal may have a greater sensitivity to a production parameter than the time delay of the second signal.

It can be a first signal delay circuit 902 and a second signal delay circuit 904 exhibit. The first signal delay circuit 902 and the second signal delay circuit 904 are configured to receive the same signal S to be delayed. The second signal delay circuit 904 may have a longer signal delay time than the first signal delay circuit 902. The circuit arrangement 900 can be used in a pulse generating circuit configured to provide a pulse. The pulse generating circuit may be configured to provide the pulse such that the pulse is started from a signal provided by the first signal delay circuit and such that the pulse is terminated by a signal provided by the second signal delay circuit.

The first signal delay circuit 902 may have a first component subject to process scattering. The first component may affect the signal delay time of the first signal delay circuit 902 to have.

The second signal delay circuit 904 may have a second component that undergoes the same process dispersion as the first component. The second component may have an effect on the signal delay time of the second signal delay circuit.

The extent of the influence of Process scattering of the second component to the signal delay time of the second signal delay circuit 904 may be less than the amount of influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit 902 ,

The extent of the influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit may be inversely proportional to the effect of the first component on the signal delay time of the first signal delay circuit. The extent of the influence of the process dispersion of the second component on the signal delay time of the second signal delay circuit may be inversely proportional to the effect of the second component on the signal delay time of the second signal delay circuit.

Therefore, the extent of the influence of the process spread on the signal delay times of the first component and the second component may be computationally equal, for example in nanoseconds. Consequently, the difference between the first signal delay and the second signal delay may be independent of the process variations, that is, the extent of the influence of the process variations decreases.

The first component may have a first resistance 906 exhibit. The second component may have a second resistor 908 exhibit. The first resistance 906 and the second resistance 908 can have different resistance widths. The first resistance 906 and the second resistance 908 can have the same nominal resistance value R

The first signal delay circuit 902 may further include a first capacitor 910 having a first capacity C. The second signal delay circuit 904 may further include a second capacitor 912 with a second capacity. The second capacity may be different from the first capacity. The second capacity may be larger than the first capacity. For example, the first capacitance C and the second capacitance may be 1.5C.

The circuit arrangement 900 may further include a third signal delay circuit 914 have a third component that undergoes the same process dispersion as the first component 906 , The third component may affect the signal delay time of the third signal delay circuit 914 to have. The extent of the influence of the process variation of the third component on the signal delay time of the third signal delay circuit 914 is smaller than the extent of the influence of the process dispersion of the second component on the signal delay time of the second signal delay circuit 904 ,

The first signal delay circuit 902 may be a series connection of a plurality of delay subcircuits 920 to have. Each delay subcircuit 920 can be a first component 906 and a signal reversing circuit 922 to have. The second signal delay circuit 904 may be a series connection of a plurality of delay subcircuits 924 to have. Each delay subcircuit 924 can be a second component 908 and a signal reversing circuit 926 to have.

As described above and for example in is shown, pulses with opposite polarities can be alternately transmitted in the clock signal direction via the transformer without iron core. Changing the pulses may involve a large amount of redundancy. Part of the redundancy can be abandoned to transfer additional data in the clock signal direction.

The additional data may be, for example, configuration information, which may be used, for example, to alter or calibrate the gain of a sigma-delta modulator. As another example, a step-by-step analog-to-digital converter may be used instead of a sigma-delta modulator, the conversion of which may be started by the transmission of additional information in addition to the clock signal. Further, the additional data may transmit trimming or configuration information that may be stored, for example, on the low voltage side LS, on circuit elements on the high voltage side HS, for example, when the high voltage side HS has no nonvolatile memory. The trimmer or configuration information may be used, for example, to calibrate a bandgap reference or a zero-point error of an analog-to-digital converter located on the high voltage side HS.

The additional data may be transmitted by inverting individual pulses in the clock signal direction. For example, in an alternating series of positive and negative pulses, a negative pulse may be replaced by a positive pulse, or a positive pulse may be replaced by a negative pulse. So that the integrity of the received pulses can still be checked, only a small part of the total number of transmitted pulses should be reversed. For example, every eighth or every sixteenth pulse may be reversed.

A receiver circuit using an RS flip-flop as memory, as in would simply ignore successive pulses of the same polarity. It is possible for the receiver circuit to compare the polarity of the received pulse with the state of the memory cell and to change the memory cell in the event of a deviation from the series of alternating pulses. It can output an additional pulse for decoding logic for the additional data. Synchronization of the memory cell with the received pulses may be necessary if the polarity of a plurality of consecutive received pulses is opposite to the polarity expected due to the state of the memory cell.

shows examples of a signal sequence 1002 a clock signal, a signal sequence 1004 for the transmission of the clock signal and a signal sequence 1006 of additional data. For the sake of simplicity, rectangular pulses without magnetization and demagnetization are shown. A rising edge in the signal sequence 1002 can be a positive impulse in the signal sequence 1004 result, which is shown by the suffix "r". A falling edge in the signal sequence 1002 can have a negative pulse in the signal sequence 1004 result, which is shown by the suffix "f". Positive and negative edges of the clock signal can be transmitted by pulses of opposite polarity. If no additional data is to be transmitted, the signal sequence may 1002 a sequence of pulses of alternating polarity.

As an example, instead of a negative pulse, a positive pulse may be transmitted on the trailing edges of the third and seventh clock pulses. The polarities of the pulses 3f, 7f have been changed from negative to positive. The receiver circuit can detect that the polarity of the received clock pulse (positive) does not match the expected polarity (negative). It can generate at its output a "1" which, for example, stops during a clock period TT, which is in the signal sequence 1006 is shown. The signal sequence 1006 can be used to transfer data in the clock signal direction.

If all N pulses are to be reversed, the receiver circuitry may be configured to output a "1" for N pulses. For example, if at most the eighth pulse is to be reversed, the receiver circuit may output a "1" for the duration of eight pulses or four clock periods. In this way, many "1's" and "0's" can be transmitted in the additional channel. Data can be transmitted over the same interface in the same direction as the clock signal by reversing the polarity of a few pulses, depending on the data being transferred.

shows a circuit 1100 for the transmission of data and clock signals, for example via the transmitter 102 , The term "additional data" may be used for data transmitted in the same direction as the clock signal T, for example via a transmitter 102 , It can be data transmitted from the primary side (or the low voltage side) to the secondary side (or the high voltage side). This is in contrast to data transmitted in a direction opposite to the direction of the clock signal T, that is, data transmitted from the secondary side (or the high voltage side) to the primary side (or the low voltage side), for example d1, d2. Therefore, data can travel in both directions via the transmitter 102 are transmitted, although the clock signal T is transmitted in one direction only.

The circuit 1100 may be similar to the circuit 202 be related to is shown and described, and include an input for a clock signal T. It may also have an input for the additional data signal AD to be transmitted in the same direction as the clock signal T. The circuit 1100 can one to a primary coil of a transformer 102 have coupled output. For example, the primary coil may be a single coil, or primary coils P1, P2 connected in series. A first connection 1118 the primary coil P1 may provide a first terminal of the primary coil, a second terminal 1124 the primary coil P2 may provide a second connection point of the primary coil. A second connection 1120 the primary coil P1 can be connected to a first terminal 1122 the primary coil P2 be coupled to form a node PG between the primary coils P1, P2. The node PG may be connected to a reference voltage.

The circuit 1100 can be a delay circuit 900 , an encoder 1101 , a rising-edge logic 1102 , a fallback logic 1104 , a first multiplex circuit 1106 , a second multiplex circuit 1108 , a first driver circuit 400 and a second driver circuit 400 ' exhibit.

The clock signal T can be sent to the delay circuit 900 be created. The delay circuit 900 can provide a variety of signals with different delays of the clock signal T. The delays of the signals relative to each other can increase from signal to signal by a constant delay. The delay circuit 900 can for example be implemented in the same way as those associated with described circuit arrangement 900 , The delays can be activated by a rising edge or a falling edge of the clock signal T. Thus, delayed signals for rising edges and falling edges of the clock signal T can be provided.

The plurality of signals with different delays can be used as input to the rising edge logic 1102 and the trailing edge logic 1104 be coupled. The rising edge logic 1102 can generate signals g1r to g8r for each rising edge. The signals g1r to g8r may, for example, be like the signals g1 to g8 associated with shown and described. The rising edge logic 1102 however, does not generate signals for trailing edges. The waste edge logic 1104 can generate signals g1f to g8f for each trailing edge. The Signals g1f to g8f may, for example, be like the signals g1 to g8 associated with shown and described. The waste edge logic 1102 however, does not generate signals for rising edges.

The rising edge logic 1102 and the trailing edge logic 1104 may be implemented as circuits that are complementary to each other, that is, they may have components and potentials of opposite polarity. In another embodiment, they may be implemented in the same way, but with one of the rising edge logic 1102 and the trailing edge logic 1104 reverses the multiplicity of signals with different delays at their input.

Depending on one of the encoder 1101 provided signal SE, the first multiplexing device 1106 the signals g1r to g8r or the signals g1f to g8f as signals g1 to g8 to the first driver 400 transfer. Similarly, depending on one of the encoder 1101 provided signal SE, the second multiplexing device 1108 the signals g1f to g8f or the signals g1r to g8r as signals g1 'to g8' to the second driver 400 ' transfer.

The first driver circuit 400 and the second driver circuit 400 ' can be related to shown and described. You can share a common set of resistors as described above. A first exit 1110 the first driver circuit 400 and a second exit 1116 the second driver circuit 400 ' can be at the first connection point 1118 be coupled to the primary coil. A second exit 1112 the first driver circuit 400 and a first exit 1114 the second driver circuit 400 ' can to the second connection point 1124 be coupled to the primary coil.

It may be that the additional data AD must be synchronized with the clock signal T so that they do not interfere with the signals generated by the clock signal T, for example the signals appearing in FIG are shown for the non-reversed case. A signal ADsync, for example, a delayed clock signal having a delay at least as long as the delay of the signal having the longest delay, that of the delay circuit 900 can be used for synchronization. The synchronization can be in the encoder 1101 respectively.

If no additional data AD is to be transmitted, the signal SE may have a first value representing the first multiplexing circuit 1106 and the second multiplexing circuit 1108 controls. The signals g1r to g8r may be transmitted as signals g1 to g8 by the first multiplexing device 1106 to the first driver 400 be transmitted. The signals g1f to g8f can be used as signals g1 'to g8' by the second multiplexing device 1108 to the second driver 400 ' be transmitted.

At each rising edge of the clock signal T, the first driver circuit 400 the primary coils P1, P2 with signals 504 and 506 supply, as related to shown and described. At each falling edge of the clock signal T, the second drive circuit supplies 400 ' the primary coils P1, P2 with signals related to shown and described signals 504 and 506 are reversed. In other words, adjacent pulses can be transmitted through the transformer 102 change their polarity when no additional data AD is transmitted.

When the additional data AD is to be transmitted, the encoder may provide the signal SE with a second value to the first multiplexing device 1106 and the second multiplexing device 1108 so that the signals g1f to g8f as input to the first multiplexing device 1106 can be used and the signals g1r to g8r as input to the second multiplexing device 1108 can be used when data is to be transferred. In other words, a falling edge of the clock signal T may be output to the first driver 400 and a rising edge of the clock signal T may be output to the second driver 400 to lead.

The encoder 1101 can encode the additional data AD in various ways. As a first example, after a rising edge of the additional data signal AD has occurred, exactly one rising edge of the clock signal T with respect to its polarity at the primary coil can be reversed by passing the signals g1r to g8r through the second multiplexing circuit 1108 be guided. After a falling edge of the additional data signal AD has occurred, exactly one falling edge of the clock signal T with respect to its polarity at the primary coil can be reversed by passing the signals g1f to g8f through the first multiplexing circuit 1106 be guided. The encoder 1101 may output a corresponding signal SE to the first multiplexing circuit 1106 and the second multiplexing circuit 1108 depending on the additional data AD to control.

As a second example, if a first value, for example a "zero", is added to the encoder as additional data AD 1101 is applied, the polarities of the pulses corresponding to the rising and falling edges of the clock signal T is not reversed. If a second value, for example, a "one", as additional data AD to the encoder 1101 is applied, the polarity of each Nth pulse can be reversed. "N" can be an integer. The whole Number can be greater than two, that is N> 2. In this case, there is sufficient time for adjacent pulses to change their polarity so that the transmission of the clock signal T can be detected. For example, "N" could be N = 8.

shows an embodiment 1200 a circuit for decoding clock signals and additional data signals, for example via a transformer 102 can be transmitted. The circuit 1200 may have an input connected to a secondary coil of the transformer 102 is coupled. The secondary coil may be, for example, a single coil or two secondary coils S1, S2 connected in series. A first connection 1202 the secondary coil S1 may provide a first terminal of the secondary coil, a second terminal 1208 the secondary coil S2 may provide a second connection point of the secondary coil. A second connection 1204 the secondary coil S1 can be connected to a first terminal 1206 the secondary coil S2 be coupled to form a node PG between the secondary coils S1, S2. The node SG may be connected to a reference potential, for example at ground potential. The circuit 1200 can the in shown receiving circuit, with an output for the clock signal t and an additional output for an additional data signal ad.

The circuit 1200 can be a first comparator 1210 , a second comparator 1213 , a first counter 1218 , a second counter 1230 , a first OR gate 1242 , a second OR gate 1244 , a memory element, for example a flip-flop 1246 , and a decoder 1248 exhibit. The memory element can output the transmitted clock signal t. The decoder 1248 can output the additional data signal ad.

The first connection point 1202 the secondary coil is connected to a positive input 1211 of the first comparator 1210 and to a negative input 1215 of the second comparator 1213 connected. The second connection point 1208 the secondary coil is connected to a negative input 1212 of the first comparator 1210 and to a positive entrance 1214 of the second comparator 1213 connected. The first comparator 1210 and the second comparator 1213 can be related to that shown and described comparator 706 correspond.

The output K3p of the first comparator 1210 can be connected to a clock input 1220 the first counter 1218 and to a reset input 1232 of the second counter 1230 be coupled. The output K3n of the second comparator 1213 can be sent to a reset input 1222 the first counter 1218 and to a clock input 1234 of the second counter 1230 be coupled.

The first counter 1218 and the second counter 1230 can each have a first output 1224 . 1236 , a second exit 1226 . 1238 and a third exit 1228 . 1240 exhibit. The counters 1218 . 1230 can be configured as follows: A first pulse at the clock input 1220 . 1234 can give a pulse at the first output 1224 . 1236 produce. A second pulse at the clock input 1220 . 1234 may be a pulse at the second output 1226 . 1238 produce. A third pulse and further pulses at the clock input 1220 . 1234 can generate appropriate pulses at the third output 1228 . 1240 produce.

The first OR gate 1242 has three inputs connected to the first output 1224 and the third exit 1228 the first counter 1218 as well as to the second exit 1238 of the second counter 1230 are coupled. The second OR gate 1244 has three inputs connected to the first output 1236 and the third exit 1240 of the second counter 1230 as well as to the second exit 1226 the first counter 1230 are coupled.

The output of the first OR gate 1242 can be connected to a set input S of the flip-flop 1246 be coupled. The output of the second OR gate 1244 can to a reset input R of the flip-flop 1246 be coupled. The flip flop 1246 may have an output at which a clock signal t may be provided. The clock signal t may be the transmitted clock signal T on the primary side of the transformer 102 in correspond. The flip flop 1246 For example, the storage element 708 be related to that shown and described.

The decoder 1248 can have two inputs. One of the inputs can be connected to the second output 1226 the first counter 1218 be coupled, the other input can be connected to the second output 1238 of the second counter 1230 be coupled.

If no additional data AD is transmitted, the transmitter can 102 transmit adjacent pulses of opposite polarity, see also the description of , A pulse with a positive polarity can be used as the output of the first comparator 1210 be recognized. The output K3p can ensure that the first counter 1218 a pulse at its first output 1224 and outputs the second counter 1230 reset to default. A pulse having a negative polarity may be considered an output K3n of the second comparator 1213 be recognized. The output K3n can make sure that the second counter 1230 a pulse at its first output 1236 and can do that first counter 1218 reset to default. In other words, if no additional data is transmitted, pulses alternate at the first inputs 1224 . 1236 the counter 1218 . 1230 output. The flip flop 1246 can flip at every transmitted pulse. In other words, the counters 1218 . 1230 and the OR gates 1242 . 1244 be considered transparent, and the circuit 1200 can be related to that shown and described circuit act.

If additional data AD is transmitted, two pulses of the same polarity can successively pass through the transmitter 102 be transmitted. In this case, one of the counters 1218 . 1230 continue its counting because it is not reset by a pulse of opposite polarity. With a correct additional data transfer, in which the polarity of a pulse is reversed, a third pulse with the same polarity can follow the previous two pulses. After the third pulse, a pulse of opposite polarity may follow, which may reset the corresponding counter. Therefore, the first and second counters count 1218 . 1230 usually not more than three. The flip flop 1246 may continue to flip at each transmitted pulse since the second pulse is via one of the OR gates 1244 . 1242 to an input R, S of the flip-flop 1246 is connected and the first and the second pulse via the other OR gate 1242 . 1244 to the other input S, R of the flip-flop 1246 are connected.

The flip flop 1246 can flip for each transmitted pulse independently of the transmission of additional data AD, so that the clock signal t can always be derived when only a few individual pulses are reversed. Furthermore, the flip flop remains 1246 not forever in the wrong state when it has lost its count, for example, when the polarity has been reversed by more than one pulse.

The decoding of the transmitted additional data may depend on the way in which the additional data AD was decoded. If, according to the first, in connection with in which, after a rising edge of the additional data signal AD, the polarity of exactly one rising edge of the clock signal T is reversed and after a falling edge of the additional data signal AD has occurred, the polarity of exactly one falling edge of the clock signal T is reversed, the second outputs 1226 . 1238 the counter 1218 . 1230 be connected directly to the two inputs R, S of a second flip-flop. The additional data ad may then be accessible at the output of the second flip-flop. In this case, the encoder 1248 comprise the second flip-flop (or memory element).

In the second example, in which the polarity of each Nth pulse can be reversed to transmit a "one", the second counter outputs 1226 . 1238 and then fed to a clock input of an additional counter. The encoder 1248 may include the additional meter. The additional counter may provide a one ("1") at its output when a pulse is applied to its set input. The additional counter can then receive the pulses at the first outputs 1224 . 1236 the counter 1218 . 1230 counting. Since the pulses at the second and third counter output 1226 . 1228 and 1238 . 1240 can not be counted, the extra counter can be reset once a count of N - 2 has been reached. If more pulses at the second counter outputs 1226 . 1238 provided, the additional counter need not be reset.

In another embodiment, the additional counter may count the decoded pulses at the clock output t and reset the counter after N / 2 counts.

While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims are. The scope of the invention is, therefore, indicated by the appended claims, and all changes which come within the meaning and range of equivalency of the claims are thus considered to be included.

• 1. Übertrageranordnung zur Signalübertragung, wobei die Übertrageranordnung Folgendes umfasst: mindestens einen Übertrager, der eine Primärspule und eine Sekundärspule umfasst; und eine Steuerung, die dafür konfiguriert ist in einer Magnetisierungsphase einen ersten Strom, der durch die Primärspule fließen soll, so zu steuern, dass er erhöht wird, bis ein vordefiniertes Kriterium erfüllt ist, wobei die Magnetisierungsphase länger ist als eines von: einer Zeitkonstante der Primärspule des mindestens einen Übertragers; und dem Zweifachen der Zeitkonstante der Primärspule des mindestens einen Übertragers; in einer Spannungsanlegephase eine Spannung an den mindestens einen Übertrager anzulegen, so dass ein zweiter Strom durch die Primärspule fließt, wobei der zweite Strom eine Polarität aufweist, die sich während der Spannungsanlegephase im Vergleich zu dem ersten Strom ändert, wobei die Spannungsanlegephase kürzer ist als eines von: dem Zweifachen der Zeitkonstante der Primärspule des mindestens einen Übertragers; und der Zeitkonstante der Primärspule des mindestens einen Übertragers.
• 2. Übertrageranordnung nach Absatz 1, wobei die Steuerung ferner dafür konfiguriert ist, in einer Entmagnetisierungsphase einen dritten Strom, der durch die Primärspule fließen soll, so zu steuern, dass er abnimmt, wobei die Entmagnetisierungsphase länger ist als eines von: der Zeitkonstante der Primärspule des mindestens einen Übertragers; und dem Zweifachen der Zeitkonstante der Primärspule des mindestens einen Übertragers.
• 3. Übertrageranordnung nach Absatz 1 oder 2, wobei die Steuerung dafür konfiguriert ist, den ersten Strom, der durch die Primärspule des mindestens einen Übertragers fließen soll, schrittweise zu erhöhen.
• 4. Übertrageranordnung nach einem der Absätze 1 bis 3, wobei der mindestens eine Übertrager ein Übertrager ohne Eisenkern ist.
• 5. Übertrageranordnung nach einem der Absätze 1 bis 4, die ferner Folgendes umfasst: eine Schaltung, die an die Steuerung gekoppelt ist, wobei die Schaltung eine Vielzahl von parallel geschalteten Unterschaltungen umfasst; wobei jede Unterschaltung eine Reihenschaltung eines Schalters und eines Widerstands umfasst; wobei ein erster Anschluss jeder Unterschaltung an ein Bezugspotential und ein zweiter Anschluss jeder Unterschaltung an den mindestens einen Übertrager gekoppelt ist.
• 6. Übertrageranordnung nach Absatz 5, wobei die Steuerung dafür konfiguriert ist, alle Schalter zu öffnen, bevor die Magnetisierungsphase startet.
• 7. Übertrageranordnung nach Absatz 5 oder 6, wobei die Steuerung dafür konfiguriert ist, eine erste Gruppe von Schaltern nacheinander zu schließen, um den Strom in der Magnetisierungsphase schrittweise zu erhöhen.
• 8. Übertrageranordnung nach Absatz 7, wobei die Steuerung dafür konfiguriert ist, während der Spannungsanlegephase die erste Gruppe von Schaltern zu öffnen und eine zweite Gruppe von Schaltern zu schließen.
• 9. Übertrageranordnung nach Absatz 8, wobei die Steuerung dafür konfiguriert ist, die zweite Gruppe von Schaltern nacheinander zu öffnen, um den Strom in der Entmagnetisierungsphase schrittweise zu verringern.
• 10. Übertrageranordnung nach einem der Absätze 5 bis 9, wobei die Steuerung dafür konfiguriert ist, alle Schalter zu öffnen, nachdem die Entmagnetisierungsphase beendet wurde.
• 11. Übertrageranordnung nach einem der Absätze 5 bis 10, wobei ein Widerstand mindestens einiger der Widerstände größer ist als der Widerstand der Primärspule.
• 12. Übertrageranordnung nach Absatz 11, wobei der Widerstand mindestens einiger der Widerstände im Bereich von etwa 10 Ohm bis etwa 1000 Ohm liegt.
• 13. Übertrageranordnung nach Absatz 11 oder 12, wobei der Widerstand der Primärspule im Bereich von etwa 1 Ohm bis etwa 50 Ohm liegt.
• 14. Übertrageranordnung nach einem der Absätze 1 bis 13, wobei der mindestens eine Übertrager eine Vielzahl von Übertragern umfasst, wobei jeder Übertrager der Vielzahl von Übertragern eine Primärspule und eine Sekundärspule umfasst; wobei die Primärspulen der Vielzahl von Übertragern in Reihe geschaltet sind; und wobei ein Knoten zwischen den Primärspulen an eine Bezugsspannung angeschlossen ist.
• 15. Übertrageranordnung nach Absatz 14, wobei die Bezugsspannung etwa die Hälfte einer Versorgungsspannung beträgt.
• 16. Übertrageranordnung nach einem der Absätze 1 bis 15, wobei die Steuerung ferner derart konfiguriert ist, dass die Magnetisierungsphase entweder: im Bereich von etwa 5 ns bis etwa 30 ns liegt; im Bereich von etwa 7 ns bis etwa 20 ns liegt; im Bereich von etwa 9 ns bis etwa 15 ns liegt; oder etwa 10 ns beträgt.
• 17. Übertrageranordnung nach einem der Absätze 1 bis 16, wobei die Steuerung ferner derart konfiguriert ist, dass die Spannungsanlegephase entweder: im Bereich von etwa 0,5 ns bis etwa 6 ns liegt; im Bereich von etwa 1 ns bis etwa 4 ns liegt; oder im Bereich von etwa 2 ns bis etwa 3 ns liegt.
• 18. Übertrageranordnung nach einem der Absätze 2 bis 17, wobei die Steuerung ferner derart konfiguriert ist, dass die Entmagnetisierungsphase entweder: im Bereich von etwa 5 ns bis etwa 30 ns liegt; im Bereich von etwa 7 ns bis etwa 20 ns liegt; im Bereich von etwa 9 ns bis etwa 15 ns liegt; oder etwa 10 ns beträgt.
• 19. Übertrageranordnung nach einem der Absätze 1 bis 18, wobei die Zeitkonstante der Primärspule des mindestens einen Übertragers entweder: im Bereich von etwa 1 ns bis etwa 10 ns liegt; im Bereich von etwa 2 ns bis etwa 6 ns liegt; oder im Bereich von etwa 3 ns bis etwa 4 ns liegt.
• 20. Übertrageranordnung nach einem der Absätze 5 bis 19, die ferner Folgendes umfasst: eine weitere Schaltung, die an die Steuerung gekoppelt ist, wobei die Schaltung eine Vielzahl von parallel geschalteten Unterschaltungen umfasst; wobei jede Unterschaltung eine Reihenschaltung eines Schalters und eines Widerstands umfasst; wobei ein erster Anschluss jeder Unterschaltung an ein Bezugspotential und ein zweiter Anschluss jeder Unterschaltung an den mindestens einen Übertrager gekoppelt ist, wobei die weitere Schaltung mit einer zu der Schaltung entgegengesetzten Polarität an den Übertrager angeschlossen ist.
• 21. Übertrageranordnung nach Absatz 20, wobei die Unterschaltungen der Schaltung und der weiteren Schaltung ihre jeweiligen Widerstände gemeinsam nutzen.
• 22. Übertrageranordnung nach Absatz 20 oder 21, wobei die Schalter der Unterschaltungen der Schaltung und der weiteren Schaltung symmetrisch zueinander angeordnet sind.
• 23. Übertrageranordnung nach einem der Absätze 20 bis 22, wobei die Schalter der Unterschaltungen der Schaltung und der weiteren Schaltung durch dasselbe Steuersignal gesteuert werden.
• 24. Übertrageranordnung nach einem der Absätze 20 bis 23, wobei der Widerstand aller Widerstände gleich ist.
• 25. Schaltungsanordnung, die Folgendes umfasst: eine erste Komparatorschaltung mit einer ersten Komparatorschwelle; eine zweite Komparatorschaltung mit einer zweiten Komparatorschwelle; eine dritte Komparatorschaltung mit einer dritten Komparatorschwelle; eine Steuerschaltung, die dafür konfiguriert ist die erste Komparatorschwelle so anzupassen, dass sich die erste Komparatorschaltung für einen ersten Zeitabschnitt eines vordefinierten Zeitintervalls in einem ersten Komparatorausgabezustand befindet, die zweite Komparatorschwelle so anzupassen, dass sich die zweite Komparatorschaltung für einen zweiten Zeitabschnitt des vordefinierten Zeitintervalls in einem ersten Komparatorausgabezustand befindet, wobei der zweite Zeitabschnitt länger ist als der erste Zeitabschnitt, und die dritte Komparatorschwelle so einzustellen, dass sie zwischen der ersten Komparatorschwelle und der zweiten Komparatorschwelle liegt.
• 26. Schaltungsanordnung nach Absatz 25, wobei mindestens einer von dem ersten Zeitabschnitt und dem zweiten Zeitabschnitt die Summe einer Vielzahl von Zeitunterabschnitten ist.
• 27. Schaltungsanordnung nach Absatz 25 oder 26, die ferner Folgendes umfasst: mindestens einen Übertrager, der eine Primärspule und eine Sekundärspule umfasst; wobei die erste Komparatorschaltung, die zweite Komparatorschaltung und die dritte Komparatorschaltung mit der Sekundärspule gekoppelt sind.
• 28. Schaltungsanordnung nach einem der Absätze 25 bis 27, wobei die erste Komparatorschaltung, die zweite Komparatorschaltung und die dritte Komparatorschaltung jeweils dafür konfiguriert sind, dasselbe Signal zu empfangen.
• 29. Schaltungsanordnung nach einem der Absätze 25 bis 28, wobei mindestens eine von der ersten Komparatorschaltung und der zweiten Komparatorschaltung als Fensterkomparatorschaltung konfiguriert ist.
• 30. Schaltungsanordnung nach einem der Absätze 25 bis 29, wobei die dritte Komparatorschaltung dafür konfiguriert ist, ein Auswerteausgangssignal bereitzustellen.
• 31. Schaltungsanordnung nach Absatz 30, die ferner Folgendes umfasst: ein Speicherelement, das an den Ausgang der dritten Komparatorschaltung gekoppelt ist, um das Auswerteausgangssignal zu speichern.
• 32. Schaltungsanordnung nach einem der Absätze 25 bis 31, wobei die Steuerschaltung dafür konfiguriert ist, mindestens entweder die erste Schwelle basierend auf dem von der ersten Komparatorschaltung bereitgestellten Ausgangssignal anzupassen; oder die zweite Schwelle basierend auf dem von der zweiten Komparatorschaltung bereitgestellten Ausgangssignal anzupassen.
• 33. Schaltungsanordnung nach Absatz 32, wobei die Steuerschaltung dafür konfiguriert ist, mindestens entweder die erste Schwelle basierend auf einer zeitbasierten Auswertung des von der ersten Komparatorschaltung bereitgestellten Ausgangssignals anzupassen; oder die zweite Schwelle basierend auf einer zeitbasierten Auswertung des von der zweiten Komparatorschaltung bereitgestellten Ausgangssignals anzupassen.
• 34. Schaltungsanordnung nach einem der Absätze 25 bis 33, wobei die Steuerschaltung dafür konfiguriert ist, mindestens entweder die erste Schwelle basierend auf dem von der ersten Komparatorschaltung bereitgestellten Ausgangssignal anzupassen, wobei ein erster Signalzustand des Ausgangssignals und ein zweiter Signalzustand des Ausgangssignals unterschiedlich gewichtet werden; oder die zweite Schwelle basierend auf dem von der zweiten Komparatorschaltung bereitgestellten Ausgangssignal anzupassen, wobei ein erster Signalzustand des Ausgangssignals und ein zweiter Signalzustand des Ausgangssignals unterschiedlich gewichtet werden.
• 35. Schaltungsanordnung nach Absatz 33 oder 34, wobei die Steuerschaltung dafür konfiguriert ist, mindestens entweder die erste Schwelle basierend auf einer Mittelwertbildung des von der ersten Komparatorschaltung bereitgestellten Ausgangssignals anzupassen; oder die zweite Schwelle basierend auf einer Mittelwertbildung des von der zweiten Komparatorschaltung bereitgestellten Ausgangssignals anzupassen.
• 36. Übertrageranordnung zur Signalübertragung, wobei die Übertrageranordnung Folgendes umfasst: mindestens einen Übertrager, der eine Primärspule und eine Sekundärspule umfasst; wobei die Übertrageranordnung eine Resonanzfrequenz aufweist; eine Steuerung, die dafür konfiguriert ist, das Ansteuern der Primärspule zu beenden, so dass die Übertrageranordnung mit Resonanzfrequenz schwingt; einen Schaltkreis, der an die Sekundärspule gekoppelt und dafür konfiguriert ist, die Übertrageranordnung in einem ersten Schaltzustand schwingen zu lassen und die Schwingung der Übertrageranordnung in einem zweiten Schaltzustand zu verringern.
• 37. Übertrageranordnung nach Absatz 36, wobei das Ansteuern der Primärspule mindestens entweder eine Magnetisierungsphase; eine Entmagnetisierungsphase; oder eine Spannungsanlegephase umfasst.
• 38. Übertrageranordnung nach Absatz 36 oder 37, die ferner Folgendes umfasst: das Ansteuern der Primärspule, nachdem ein bestimmter Zeitraum nach Beendigung des Ansteuerns der Primärspule verstrichen ist.
• 39. Übertrageranordnung nach einem der Absätze 36 bis 38, die ferner Folgendes umfasst: eine Amplitudenerfassungsschaltung, die an die Primärspule gekoppelt ist.
• 40. Übertrageranordnung nach Absatz 39, wobei der bestimmte Zeitraum so gewählt ist, dass er lang genug ist, um die Schwingung zu verringern, wenn sich der Schaltkreis in einem zweiten Schaltzustand befindet, und dass er lang genug ist, dass die Verringerung der Schwingung in der Amplitudenerfassungsschaltung erfasst werden kann.
• 41. Übertrageranordnung nach Absatz 38 bis 40, wobei der Zeitraum, in dem sich der Schaltkreis in dem zweiten Schaltzustand befindet, kürzer ist als die bestimmte Zeit vor Beginn des Ansteuerns der Spule.
• 42. Übertrageranordnung nach einem der Absätze 36 bis 41, wobei der mindestens eine Übertrager ein Übertrager ohne Eisenkern ist.
• 43. Übertrageranordnung nach einem der Absätze 37 bis 42, wobei die Magnetisierungsrichtung des fortlaufenden Ansteuerns der Primärspulenphasen entgegengesetzte Polaritäten aufweisen.
• 44. Übertrageranordnung nach einem der Absätze 37 bis 42, wobei die Magnetisierungsrichtung des fortlaufenden Ansteuerns der Primärspulenphasen bei einer bestimmten Anzahl des fortlaufenden Ansteuerns der Primärspulenphasen die gleiche Polarität hat.
• 45. Übertrageranordnung nach einem der Absätze 38 bis 44, wobei während der bestimmten Zeit vor Beginn des Ansteuerns der Spule ein Bit übertragen wird, indem erkannt wird, ob die Schwingung abgenommen hat oder nicht.
• 46. Schaltungsanordnung, die Folgendes umfasst: eine erste Signalverzögerungsschaltung, die eine erste Komponente umfasst, die einer Prozessstreuung unterliegt, wobei die erste Komponente eine Auswirkung auf die Signalverzögerungszeit der ersten Signalverzögerungsschaltung hat; eine zweite Signalverzögerungsschaltung, die eine zweite Komponente umfasst, die der gleichen Prozessstreuung unterliegt, wobei die zweite Komponente eine Auswirkung auf die Signalverzögerungszeit der zweiten Signalverzögerungsschaltung hat; wobei die erste Signalverzögerungsschaltung und die zweite Signalverzögerungsschaltung dafür konfiguriert sind, dasselbe zu verzögernde Signal zu empfangen; wobei die zweite Signalverzögerungsschaltung eine längere Signalverzögerungszeit hat als die erste Signalverzögerungsschaltung; wobei ein Ausmaß des Einflusses der Prozessstreuung der zweiten Komponente auf die Signalverzögerungszeit der zweiten Signalverzögerungsschaltung geringer ist als das Ausmaß des Einflusses der Prozessstreuung der ersten Komponente auf die Signalverzögerungszeit der ersten Signalverzögerungsschaltung.
• 47. Schaltungsanordnung nach Absatz 46, wobei das Ausmaß des Einflusses der Prozessstreuung der ersten Komponente auf die Signalverzögerungszeit der ersten Signalverzögerungsschaltung umgekehrt proportional zu der Auswirkung der ersten Komponente auf die Signalverzögerungszeit der ersten Signalverzögerungsschaltung ist; und wobei das Ausmaß des Einflusses der Prozessstreuung der zweiten Komponente auf die Signalverzögerungszeit der zweiten Signalverzögerungsschaltung umgekehrt proportional zu der Auswirkung der zweiten Komponente auf die Signalverzögerungszeit der zweiten Signalverzögerungsschaltung ist.
• 48. Schaltungsanordnung nach Absatz 46 oder 47, wobei die erste Komponente einen ersten Widerstand umfasst; und die zweite Komponente einen zweiten Widerstand umfasst; wobei der erste Widerstand und der zweite Widerstand unterschiedliche Widerstandsbreiten aufweisen; und wobei der erste Widerstand und der zweite Widerstand den gleichen Nennwiderstandswert haben.
• 49. Schaltungsanordnung nach einem der Absätze 46 bis 48, wobei die erste Signalverzögerungsschaltung ferner einen ersten Kondensator mit einer ersten Kapazität umfasst; wobei die zweite Signalverzögerungsschaltung ferner einen zweiten Kondensator mit einer zweiten Kapazität umfasst; wobei sich die zweite Kapazität von der ersten Kapazität unterscheidet.
• 50. Schaltungsanordnung nach Absatz 49, wobei die zweite Kapazität höher ist als die erste Kapazität.
• 51. Schaltungsanordnung nach einem der Absätze 46 bis 50, die ferner Folgendes umfasst: eine dritte Signalverzögerungsschaltung, die eine dritte Komponente umfasst, die derselben Prozessstreuung unterliegt, wobei die dritte Komponente eine Auswirkung auf die Signalverzögerungszeit der dritten Signalverzögerungsschaltung hat; wobei das Ausmaß des Einflusses der Prozessstreuung der dritten Komponente auf die Signalverzögerungszeit der dritten Signalverzögerungsschaltung geringer ist als das Ausmaß des Einflusses der Prozessstreuung der zweiten Komponente auf die Signalverzögerungszeit der zweiten Signalverzögerungsschaltung.
• 52. Schaltungsanordnung nach einem der Absätze 46 bis 51, wobei die erste Signalverzögerungsschaltung eine Reihenschaltung einer Vielzahl von Verzögerungsunterschaltungen umfasst, wobei jede Verzögerungsunterschaltung eine erste Komponente und eine Signalumkehrvorrichtung umfasst; und wobei die zweite Signalverzögerungsschaltung eine Reihenschaltung einer Vielzahl von Verzögerungsunterschaltungen umfasst, wobei jede Verzögerungsunterschaltung eine zweite Komponente und eine Signalumkehrvorrichtung umfasst.
• 53. Impulserzeugende Schaltungsanordnung, die Folgendes umfasst: eine impulserzeugende Schaltung, die dafür konfiguriert ist, einen Impuls bereitzustellen; und eine Schaltungsanordnung, die Folgendes umfasst: eine erste Signalverzögerungsschaltung, die eine erste Komponente umfasst, die einer Prozessstreuung unterliegt, wobei die erste Komponente eine Auswirkung auf die Signalverzögerungszeit der ersten Signalverzögerungsschaltung hat; eine zweite Signalverzögerungsschaltung, die eine zweite Komponente umfasst, die der gleichen Prozessstreuung unterliegt, wobei die zweite Komponente eine Auswirkung auf die Signalverzögerungszeit der zweiten Signalverzögerungsschaltung hat; wobei die erste Signalverzögerungsschaltung und die zweite Signalverzögerungsschaltung dafür konfiguriert sind, dasselbe zu verzögernde Signal zu empfangen; wobei die zweite Signalverzögerungsschaltung eine längere Signalverzögerungszeit hat als die erste Signalverzögerungsschaltung; wobei das Ausmaß des Einflusses der Prozessstreuung der zweiten Komponente auf die Signalverzögerungszeit der zweiten Signalverzögerungsschaltung geringer ist als das Ausmaß des Einflusses der Prozessstreuung der ersten Komponente auf die Signalverzögerungszeit der ersten Signalverzögerungsschaltung; wobei die impulserzeugende Schaltung dafür konfiguriert ist, den Impuls derart bereitzustellen, dass der Impuls von einem Signal gestartet wird, das von der ersten Signalverzögerungsschaltung bereitgestellt wird, und derart, dass der Impuls von einem Signal beendet wird, das von der zweiten Signalverzögerungsschaltung bereitgestellt wird.
• 54. Schaltungsanordnung nach Absatz 53, wobei die Signalverzögerungszeit proportional zu einer Seitenabmessung eines Widerstands ist.
• 55. Verfahren zur Übertragung von Daten in eine Übertragungsrichtung eines Taktsignals, wobei positive und negative Flanken des Taktsignals durch Impulse mit entgegengesetzter Polarität übertragen werden; wobei eine Polarität der Impulse nicht umgekehrt wird, wenn keine Daten übertragen werden; und wobei die Polarität von mindestens einem Impuls umgekehrt wird, wenn Daten übertragen werden.
• 56. Verfahren nach Absatz 55, das ferner Folgendes umfasst: das Erkennen, ob Daten übertragen werden, durch Erkennen, ob ein Impuls eine unerwartete Polarität aufweist, das Erkennen umfasst, ob fortlaufende Impulse die gleiche Polarität haben.
• 57. Verfahren nach Absatz 55 oder 56, wobei die Polarität von nur jedem N-ten Impuls umgekehrt wird, wenn Daten übertragen werden; wobei N eines ist von: größer als 2; gleich 5; gleich 8; und gleich 16.
• 58. Verfahren nach einem der Absätze 55 bis 56, wobei die Polarität genau einmal nach einer Anstiegsflanke der Daten umgekehrt wird und erneut genau einmal nach einer Abfallflanke der Daten umgekehrt wird.
• 59. Verfahren nach einem der Absätze 55 bis 58, wobei die Daten mindestens eines von: einem Konfigurationsparameter eines Wandlers; einem Signal zum Starten einer Umwandlung eines Wandlers; und Kalibrationsinformationen sind.

Alternatively and / or additionally, the scope of the disclosure is intended to include, without limitation, at least the embodiments described in the paragraphs enumerated below. Equivalents are also explicitly included.

• A transmitter arrangement for signal transmission, the transmitter arrangement comprising: at least one transmitter comprising a primary coil and a secondary coil; and a controller configured to, in a magnetization phase, control a first current to flow through the primary coil to increase it until a predefined criterion is met, the magnetization phase being greater than one of: a time constant; Primary coil of the at least one transformer; and twice the time constant of the primary coil of the at least one transformer; applying a voltage to the at least one transmitter in a voltage application phase such that a second current flows through the primary coil, the second current having a polarity that changes during the voltage application phase as compared to the first current, wherein the voltage application phase is shorter than one of: twice the time constant of the primary coil of the at least one transformer; and the time constant of the primary coil of the at least one transformer.
• 2. The transmitter assembly of paragraph 1, wherein the controller is further configured to control, in a demagnetization phase, a third current to flow through the primary coil to decrease, the demagnetization phase being greater than one of: the primary coil time constant the at least one transmitter; and twice the time constant of the primary coil of the at least one transformer.
• 3. The transmitter assembly according to paragraph 1 or 2, wherein the controller is configured to gradually increase the first current to flow through the primary coil of the at least one transformer.
• 4. Transformer assembly according to any one of paragraphs 1 to 3, wherein the at least one transformer is a transformer without iron core.
• 5. The transmitter assembly of any one of paragraphs 1 to 4, further comprising: a circuit coupled to the controller, the circuit including a plurality of subcircuits connected in parallel; wherein each subcircuit comprises a series connection of a switch and a resistor; wherein a first terminal of each subcircuit is coupled to a reference potential and a second terminal of each subcircuit is coupled to the at least one transmitter.
• 6. The transmitter assembly of paragraph 5, wherein the controller is configured to open all switches before the magnetization phase starts.
• 7. The transmitter assembly of paragraph 5 or 6, wherein the controller is configured to sequentially close a first group of switches to incrementally increase the current in the magnetization phase.
• 8. The transmitter assembly of paragraph 7, wherein the controller is configured to open the first group of switches and close a second group of switches during the voltage application phase.
• 9. The transmitter assembly of paragraph 8, wherein the controller is configured to open the second group of switches in sequence to gradually decrease the current in the demagnetization phase.
• The transmitter assembly of any one of paragraphs 5 to 9, wherein the controller is configured to open all of the switches after the demagnetization phase has ended.
• 11. Transformer assembly according to any one of paragraphs 5 to 10, wherein a resistance of at least some of the resistors is greater than the resistance of the primary coil.
• 12. The transducer assembly of paragraph 11, wherein the resistance of at least some of the resistors is in the range of about 10 ohms to about 1000 ohms.
• 13. A transformer arrangement according to paragraph 11 or 12, wherein the resistance of the primary coil is in the range of about 1 ohms to about 50 ohms.
• 14. The transmitter assembly of any one of paragraphs 1 to 13, wherein the at least one transmitter comprises a plurality of transformers, each transmitter of the plurality of transformers comprising a primary coil and a secondary coil; wherein the primary coils of the plurality of transformers are connected in series; and wherein a node between the primary coils is connected to a reference voltage.
• 15. Transformer assembly according to paragraph 14, wherein the reference voltage is about half of a supply voltage.
• 16. The transmitter assembly of any one of paragraphs 1 to 15, wherein the controller is further configured such that the magnetization phase is either: in the range of about 5 ns to about 30 ns; is in the range of about 7 ns to about 20 ns; is in the range of about 9 ns to about 15 ns; or about 10 ns.
• 17. The transmitter assembly of any one of paragraphs 1 to 16, wherein the controller is further configured such that the voltage application phase is either: in the range of about 0.5 ns to about 6 ns; is in the range of about 1 ns to about 4 ns; or in the range of about 2 ns to about 3 ns.
• 18. The transmitter assembly of any one of paragraphs 2 to 17, wherein the controller is further configured such that the demagnetization phase is either: in the range of about 5 ns to about 30 ns; is in the range of about 7 ns to about 20 ns; is in the range of about 9 ns to about 15 ns; or about 10 ns.
• 19. A transformer arrangement according to any one of paragraphs 1 to 18, wherein the time constant of the primary coil of the at least one transformer is either: in the range of about 1 ns to about 10 ns; is in the range of about 2 ns to about 6 ns; or is in the range of about 3 ns to about 4 ns.
• 20. The transmitter assembly of any one of paragraphs 5 to 19, further comprising: another circuit coupled to the controller, the circuit including a plurality of subcircuits connected in parallel; wherein each subcircuit comprises a series connection of a switch and a resistor; wherein a first terminal of each subcircuit is coupled to a reference potential and a second terminal of each subcircuit is coupled to the at least one transmitter, the further circuit being connected to the transmitter with a polarity opposite to the circuit.
• 21. Transformer arrangement according to paragraph 20, wherein the subcircuits of the circuit and the further circuit share their respective resistances.
• 22. Transformer arrangement according to paragraph 20 or 21, wherein the switches of the subcircuits of the circuit and the further circuit are arranged symmetrically to each other.
• 23. The transformer arrangement according to any one of paragraphs 20 to 22, wherein the switches of the subcircuits of the circuit and the further circuit are controlled by the same control signal.
• 24. Übertrageranordnung according to paragraphs 20 to 23, wherein the resistance of all resistors is the same.
• 25. A circuit arrangement comprising: a first comparator circuit having a first comparator threshold; a second comparator circuit having a second comparator threshold; a third comparator circuit having a third comparator threshold; a control circuit configured to adjust the first comparator threshold so that the first comparator circuit is in a first comparator output state for a first time period of a predefined time interval to adjust the second comparator threshold so that the second comparator circuit is enabled for a second time period of the predefined time interval a first comparator output state, the second time period being longer than the first time period, and setting the third comparator threshold to be between the first comparator threshold and the second comparator threshold.
• 26. The circuit of claim 25, wherein at least one of the first time period and the second time period is the sum of a plurality of time subsections.
• 27. A circuit arrangement according to paragraph 25 or 26, further comprising: at least one transformer comprising a primary coil and a secondary coil; wherein the first comparator circuit, the second comparator circuit and the third comparator circuit are coupled to the secondary coil.
• 28. Circuitry according to any one of paragraphs 25 to 27, wherein the first comparator circuit, the second comparator circuit and the third comparator circuit are each configured to receive the same signal.
• 29. Circuitry according to any one of paragraphs 25 to 28, wherein at least one of the first comparator circuit and the second comparator circuit is configured as a window comparator circuit.
• 30. Circuitry according to any one of paragraphs 25 to 29, wherein the third comparator circuit is configured to provide an evaluation output signal.
• 31. The circuit of claim 30, further comprising: a memory element coupled to the output of the third comparator circuit for storing the evaluation output signal.
• 32. The circuit of any one of paragraphs 25 to 31, wherein the control circuit is configured to adjust at least one of the first threshold based on the output provided by the first comparator circuit; or adjust the second threshold based on the output provided by the second comparator circuit.
• 33. The circuit of claim 32, wherein the control circuit is configured to adjust at least one of the first threshold based on a time-based evaluation of the output signal provided by the first comparator circuit; or adjust the second threshold based on a time-based evaluation of the output signal provided by the second comparator circuit.
• 34. The circuit of any one of paragraphs 25 to 33, wherein the control circuit is configured to adjust at least one of the first threshold based on the output signal provided by the first comparator circuit, wherein a first signal state of the output signal and a second signal state of the output signal are weighted differently; or adjust the second threshold based on the output provided by the second comparator circuit, wherein a first signal state of the output signal and a second signal state of the output signal are weighted differently.
• 35. The circuitry of paragraph 33 or 34, wherein the control circuit is configured to adjust at least one of the first threshold based on averaging the output signal provided by the first comparator circuit; or adjust the second threshold based on averaging the output signal provided by the second comparator circuit.
• 36. A transmitter arrangement for signal transmission, the transmitter arrangement comprising: at least one transmitter comprising a primary coil and a secondary coil; wherein the transmitter assembly has a resonant frequency; a controller configured to terminate driving the primary coil so that the transmitter assembly resonates at a resonant frequency; a circuit coupled to the secondary coil and configured to oscillate the transmitter assembly in a first switching state and to reduce the vibration of the transmitter assembly in a second switching state.
• 37. The transformer arrangement according to paragraph 36, wherein the driving of the primary coil at least either a magnetization phase; a demagnetization phase; or a voltage application phase.
• 38. The transmitter arrangement according to paragraph 36 or 37, further comprising: driving the primary coil after a certain period has elapsed after completion of the driving of the primary coil.
• 39. The transmitter arrangement of any one of paragraphs 36 to 38, further comprising: an amplitude detection circuit coupled to the primary coil.
• 40. The transmitter arrangement according to paragraph 39, wherein the certain period of time is selected to be long enough to reduce the vibration when the circuit is in a second switching state, and that it is long enough that the reduction of the vibration in the amplitude detection circuit can be detected.
• 41. The transformer arrangement according to paragraphs 38 to 40, wherein the time period in which the circuit is in the second switching state, is shorter than the predetermined time before the start of the driving of the coil.
• 42. Übertrageranordnung according to any of paragraphs 36 to 41, wherein the at least one transformer is a transformer without iron core.
• 43. A transformer arrangement according to any one of paragraphs 37 to 42, wherein the magnetization direction of the continuous driving of the primary coil phases have opposite polarities.
• 44. The transformer arrangement according to any one of paragraphs 37 to 42, wherein the magnetization direction of the continuous driving of the primary coil phases at a certain number of the continuous driving of the primary coil phases has the same polarity.
• 45. A transformer arrangement according to any one of paragraphs 38 to 44, wherein during the determined time before the start of the driving of the coil, a bit is transmitted by detecting whether the oscillation has decreased or not.
• 46. A circuit arrangement, comprising: a first signal delay circuit including a first component subject to process dispersion, the first component having an effect on the signal delay time of the first signal delay circuit; a second signal delay circuit including a second component subject to the same process dispersion, the second component having an effect on the signal delay time of the second signal delay circuit; wherein the first signal delay circuit and the second signal delay circuit are configured to receive the same signal to be delayed; wherein the second signal delay circuit has a longer signal delay time than the first signal delay circuit; wherein an extent of the influence of the process dispersion of the second component on the signal delay time of the second signal delay circuit is less than the extent of the influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit.
• 47. Circuitry according to paragraph 46, wherein the extent of the influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit is inversely proportional to the effect of the first component on the signal delay time of the first signal delay circuit; and wherein the extent of the influence of the process variation of the second component on the signal delay time of the second signal delay circuit is inversely proportional to the effect of the second component on the signal delay time of the second signal delay circuit.
• 48. Circuit arrangement according to paragraph 46 or 47, wherein the first component comprises a first resistor; and the second component comprises a second resistor; wherein the first resistor and the second resistor have different resistance widths; and wherein the first resistor and the second resistor have the same nominal resistance value.
• 49. The circuit of any one of paragraphs 46 to 48, wherein the first signal delay circuit further comprises a first capacitor having a first capacitance; wherein the second signal delay circuit further comprises a second capacitor having a second capacitance; wherein the second capacity is different from the first capacity.
• 50. Circuitry according to paragraph 49, wherein the second capacity is higher than the first capacity.
• 51. The circuit of any one of paragraphs 46 to 50, further comprising: a third signal delay circuit including a third component subject to the same process dispersion, the third component having an effect on the signal delay time of the third signal delay circuit; wherein the extent of the influence of the process variation of the third component on the signal delay time of the third signal delay circuit is less than the extent of the influence of the process dispersion of the second component on the signal delay time of the second signal delay circuit.
• 52. The circuit of any one of paragraphs 46 to 51, wherein the first signal delay circuit comprises a series connection of a plurality of delay subcircuits, each delay subcircuit comprising a first component and a signal inversion device; and wherein the second signal delay circuit comprises a series connection of a plurality of delay subcircuits, each delay subcircuit comprising a second component and a signal inversion device.
• 53. A pulse generating circuit comprising: a pulse generating circuit configured to provide a pulse; and a circuit arrangement comprising: a first signal delay circuit including a first component subject to process dispersion, the first component having an effect on the signal delay time of the first signal delay circuit; a second signal delay circuit including a second component subject to the same process dispersion, the second component having an effect on the signal delay time of the second signal delay circuit; wherein the first signal delay circuit and the second signal delay circuit are configured to receive the same signal to be delayed; wherein the second signal delay circuit has a longer signal delay time than the first signal delay circuit; wherein the extent of the influence of the process dispersion of the second component on the signal delay time of the second signal delay circuit is less than the extent of the influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit; wherein the pulse generating circuit is configured to provide the pulse such that the pulse is started from a signal provided by the first signal delay circuit and such that the pulse is terminated by a signal provided by the second signal delay circuit.
• 54. The circuit of paragraph 53, wherein the signal delay time is proportional to a side dimension of a resistor.
• 55. A method of transmitting data in a transmission direction of a clock signal, wherein positive and negative edges of the clock signal are transmitted by pulses of opposite polarity; wherein a polarity of the pulses is not reversed when no data is transmitted; and wherein the polarity of at least one pulse is reversed when transmitting data.
• 56. The method of paragraph 55, further comprising: detecting whether data is being transmitted by detecting whether a pulse has an unexpected polarity that includes detecting whether continuous pulses have the same polarity.
• 57. The method of paragraph 55 or 56, wherein the polarity of only every Nth pulse is reversed when transmitting data; where N is one of: greater than 2; equal to 5; equal to 8; and equal to 16.
• 58. The method of any one of paragraphs 55 to 56, wherein the polarity is inverted just once after a rising edge of the data and again inverted exactly once after a falling edge of the data.
• 59. The method of any of paragraphs 55 to 58, wherein the data is at least one of: a configuration parameter of a transducer; a signal for starting a conversion of a converter; and calibration information.

Claims (20)

A transmitter arrangement for signal transmission, the transmitter arrangement comprising: at least one transmitter comprising a primary coil and a secondary coil; and a controller that is configured for it in a magnetization phase, controlling a first current to flow through the primary coil to be increased until a predefined criterion is met, wherein the magnetization phase is longer than one of: a time constant of the primary coil of the at least one transformer; and twice the time constant of the primary coil of the at least one transformer; applying a voltage to the at least one transmitter in a voltage application phase such that a second current flows through the primary coil, the second current having a polarity that changes during the voltage application phase as compared to the first current, wherein the voltage application phase is shorter than one from: twice the time constant of the primary coil of the at least one transformer; and the time constant of the primary coil of the at least one transformer. Transformer arrangement according to claim 1, wherein the controller is further configured to control, in a demagnetization phase, a third current to flow through the primary coil to decrease, the demagnetization phase being greater than one of: the time constant of the primary coil of the at least one transformer; and twice the time constant of the primary coil of the at least one transformer. The transmitter assembly of claim 1 or 2, wherein the controller is configured to incrementally increase the first current to flow through the primary coil of the at least one transmitter. Transformer assembly according to one of claims 1 to 3, wherein the at least one transformer is a transformer without iron core. A transmitter assembly according to any one of claims 1 to 4, further comprising: a circuit coupled to the controller, the circuit including a plurality of subcircuits connected in parallel; wherein each subcircuit comprises a series connection of a switch and a resistor; wherein a first terminal of each subcircuit is coupled to a reference potential and a second terminal of each subcircuit is coupled to the at least one transformer, wherein the controller is preferably configured to open all the switches before the magnetization phase starts. The transmitter assembly of claim 5, wherein the controller is configured to open all of the switches after the demagnetization phase has ended. Transformer arrangement according to one of claims 1 to 6, wherein the at least one transmitter comprises a plurality of transformers, wherein each transmitter of the plurality of transformers comprises a primary coil and a secondary coil; wherein the primary coils of the plurality of transformers are connected in series; and wherein a node between the primary coils is connected to a reference voltage; wherein the reference voltage is preferably about half of a supply voltage. A transmitter assembly according to any one of claims 5 to 7, further comprising: another circuit coupled to the controller, the circuit including a plurality of subcircuits connected in parallel; wherein each subcircuit comprises a series connection of a switch and a resistor; wherein a first terminal of each subcircuit is coupled to a reference potential and a second terminal of each subcircuit is coupled to the at least one transmitter, the further circuit having a polarity opposite to the circuit being connected to the transformer. A circuit arrangement comprising: a first comparator circuit having a first comparator threshold; a second comparator circuit having a second comparator threshold; a third comparator circuit having a third comparator threshold; a control circuit configured to adjust the first comparator threshold so that the first comparator circuit is in a first comparator output state for a first time period of a predefined time interval to adjust the second comparator threshold so that the second comparator circuit is enabled for a second time period of the predefined time interval a first comparator output state, wherein the second time period is longer than the first time period, and adjust the third comparator threshold to lie between the first comparator threshold and the second comparator threshold. The circuit of claim 9, wherein at least one of the first time period and the second time period is the sum of a plurality of time subsections. Circuit arrangement according to one of claims 9 or 10, further comprising: at least one transmitter comprising a primary coil and a secondary coil; wherein the first comparator circuit, the second comparator circuit and the third comparator circuit are coupled to the secondary coil. Circuitry according to one of claims 9 to 11, wherein the first comparator circuit, the second comparator circuit and the third comparator circuit are each configured to receive the same signal. A transmitter arrangement for signal transmission, the transmitter arrangement comprising: at least one transmitter comprising a primary coil and a secondary coil; wherein the transmitter arrangement comprises a resonant frequency; a controller configured to terminate driving the primary coil so that the transmitter assembly resonates at the resonant frequency; a circuit coupled to the secondary coil and configured to oscillate the transmitter assembly in a first switching state and to reduce the vibration of the transmitter assembly in a second switching state. Transformer arrangement according to claim 13, wherein the driving of the primary coil is at least either: a magnetization phase; a demagnetization phase; or includes a voltage application phase. A transmitter assembly according to any one of claims 13 or 14, further comprising: the driving of the primary coil after a certain period has elapsed after completion of the driving of the primary coil. Circuitry comprising: a first signal delay circuit including a first component subject to process dispersion, the first component having an effect on the signal delay time of the first signal delay circuit; a second signal delay circuit including a second component subject to the same process dispersion, the second component having an effect on the signal delay time of the second signal delay circuit; wherein the first signal delay circuit and the second signal delay circuit are configured to receive the same signal to be delayed; wherein the second signal delay circuit has a longer signal delay time than the first signal delay circuit; wherein an amount of influence of the process dispersion of the second component on the signal delay time of the second signal delay circuit is less than an amount of influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit. Circuit arrangement according to Claim 16, wherein the extent of the influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit is inversely proportional to the effect of the first component on the signal delay time of the first signal delay circuit; and wherein the extent of the influence of the process variation of the second component on the signal delay time of the second signal delay circuit is inversely proportional to the effect of the second component on the signal delay time of the second signal delay circuit. A pulse generating circuit comprising: a pulse generating circuit configured to provide a pulse; and a circuit arrangement comprising: a first signal delay circuit including a first component subject to process dispersion, the first component having an effect on the signal delay time of the first signal delay circuit; a second signal delay circuit including a second component subject to the same process dispersion, the second component having an effect on the signal delay time of the second signal delay circuit; wherein the first signal delay circuit and the second signal delay circuit are configured to receive the same signal to be delayed; wherein the second signal delay circuit has a longer signal delay time than the first signal delay circuit; wherein the extent of the influence of the process dispersion of the second component on the signal delay time of the second signal delay circuit is less than the extent of the influence of the process dispersion of the first component on the signal delay time of the first signal delay circuit; wherein the pulse generating circuit is configured to provide the pulse such that the pulse is started from a signal provided by the first signal delay circuit and such that the pulse is terminated by a signal provided by the second signal delay circuit. The circuit of claim 18, wherein the signal delay time is proportional to a side dimension of a resistor. Method for transmitting data in a transmission direction of a clock signal, wherein positive and negative edges of the clock signal are transmitted by pulses of opposite polarity; wherein a polarity of the pulses is not reversed when no data is transmitted; and wherein the polarity of at least one pulse is reversed when transmitting data.

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