DE102014107387A1 - Semiconductor chip with improved bondability and method for producing a bond compound - Google Patents

Semiconductor chip with improved bondability and method for producing a bond compound

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Publication number
DE102014107387A1
DE102014107387A1 DE102014107387.8A DE102014107387A DE102014107387A1 DE 102014107387 A1 DE102014107387 A1 DE 102014107387A1 DE 102014107387 A DE102014107387 A DE 102014107387A DE 102014107387 A1 DE102014107387 A1 DE 102014107387A1
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DE
Germany
Prior art keywords
semiconductor chip
lateral direction
main electrode
chip according
strip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102014107387.8A
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German (de)
Inventor
Wolfgang Wagner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102014107387.8A priority Critical patent/DE102014107387A1/en
Publication of DE102014107387A1 publication Critical patent/DE102014107387A1/en
Application status is Ceased legal-status Critical

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    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

One aspect of the invention relates to a semiconductor chip (1) having a semiconductor body (100) which has an upper side (101) and a lower side (102) opposite the upper side (101). Arranged in the semiconductor body (100) is a multiplicity of component cells which are designed as strip cells and are arranged next to one another in a first lateral direction (x). In addition, the strip cells (10) each extend in a different from the first lateral direction (x) second lateral direction (y). On the upper side (101), a main electrode (71) is applied. Between the main electrode (71) and the upper side (101) a dielectric layer (30) is arranged, which is formed as a network and has a plurality of passage openings (31).

Description

  • The present invention is concerned with the problem that the bonding of bonding wires to a metallization of a semiconductor chip often leads to damage of the semiconductor chip. This problem is particularly pronounced when the semiconductor chip is a power semiconductor chip through which high currents flow. If these currents are to be conducted via one or more bonding wires connected in parallel electrically, the bonding wires must have a correspondingly suitable current carrying capacity and mechanical stability.
  • This can be increased, for example, by using bonding wires with a large conductor cross-section. Typical is z. Example, the use of aluminum-based bonding wires with a diameter of 300 microns. With increasing cross-section of the bonding wire, however, changed bonding parameters are necessary, for example the contact pressure with which the bonding wire has to be pressed against the semiconductor chip during bonding increases if a bond that is stable over time is to be produced. As the force increases, so does the risk of mechanical damage to the semiconductor chip. The same applies to a change in other bond parameters such as the duration or the ultrasound energy entered during bonding. Typical damages are "chip cratering", which can lead to an increase of the leakage current of the semiconductor chip or even to its complete failure.
  • One measure for increasing the current carrying capacity is to use bonding wires that have a higher electrical conductivity than the conventional aluminum-based bonding wires. Because of the good electrical and mechanical properties compared to aluminum, copper-based bonding wires are particularly suitable here. Compared to aluminum-based bonding wires, copper-based bonding wires are significantly harder, which in turn results in the bond parameters required to bond a copper-based bonding wire, e.g. Contact force, ultrasonic energy, duration of the bonding process, must be chosen to be much higher or longer than with an aluminum-based bonding wire of the same cross-section. But this increases as already explained the risk of mechanical damage to the semiconductor chip.
  • The object of the present invention is to provide a semiconductor chip showing only a small risk of occurrence of damage in wire bonding. Another object is to provide a method of making a wire bond between a semiconductor chip and a bond wire that presents little risk of damage to the semiconductor chip. These objects are achieved by a semiconductor chip according to patent claim 1 or by a method for producing a wire bond according to patent claim 16. Embodiments and developments of the invention are the subject of dependent claims.
  • A first aspect of the invention relates to a semiconductor chip having a semiconductor body which has an upper side and a lower side opposite to the upper side. In the semiconductor body, a plurality of component cells is arranged, which are formed as strip cells and are arranged side by side in a first lateral direction. In addition, each of the stripe cells extends in a second lateral direction different from the first lateral direction. On top of a main electrode is applied. Between the main electrode and the upper side, a dielectric layer is arranged which has a net-shaped structure. The reticular structure has a plurality of passage openings.
  • A second aspect relates to a method of making a wire bond. For this purpose, a semiconductor chip designed according to the first aspect is provided, as well as a bonding wire. A wire bond is made between the bonding wire and the main electrode.
  • The invention will be explained in more detail with reference to the accompanying figures. The same reference numerals designate identical or equivalent elements. Show it:
  • 1 a vertical section through a portion of a semiconductor chip having a net-shaped, dielectric layer between a semiconductor body and a main electrode;
  • 2 a vertical section through the semiconductor chip according to 1 in a sectional plane E1-E1;
  • 3 a vertical section through the semiconductor chip according to 1 in a sectional plane E2-E2;
  • 4 a horizontal section through the semiconductor chip according to 1 in a section plane E3-E3;
  • 5 a horizontal section through the semiconductor chip according to 1 in a sectional plane E4-E4;
  • 6 a vertical section through a portion of another semiconductor chip, the between a semiconductor body and a main electrode having a reticular dielectric layer;
  • 7 a vertical section through the semiconductor chip according to 6 in a section plane E5-E5;
  • 8th a vertical section through the semiconductor chip according to 7 in a section plane E6-E6;
  • 9 a horizontal section through the semiconductor chip according to 8th in a section plane E7-E7;
  • 10 a horizontal section through the semiconductor chip according to 9 in a section plane E8-E8;
  • 11 a plan view of a portion of a reticulated dielectric;
  • 12 a perspective view of the section according to 11 ;
  • 13 a plan view of a reticulated dielectric having elongated openings.
  • 14 a perspective view of a portion of a first main electrode.
  • 15 a plan view of a semiconductor chip, in which the course of the stripe cells is shown schematically.
  • 16 a view of a semiconductor chip, wherein the first lateral direction and the second lateral direction are not perpendicular to each other.
  • 17 a view accordingly 4 with the difference that the lengths and the distances of the extensions of the first main electrode are inhomogeneous.
  • 18 the bonding of a bonding wire to a main electrode of a semiconductor chip, wherein a net-shaped dielectric is arranged between the bonding point and the semiconductor body.
  • 19 a top view of a semiconductor chip, in which a plurality of through holes is arranged vertically below a simply continuous surface portion of the first main electrode.
  • In experiments that preceded the present invention, it has been found that semiconductor chips exhibit increased susceptibility to damage in bonding, particularly if they have streak cell cell structure. In the course of further investigations, it was found that the dielectric which is usually located between the semiconductor and the metallization to which it is bonded has a substantially higher influence on the mechanical stability of the chip structure than previously assumed. Especially in striped cell designs, the dielectric essentially consists of mutually parallel strips. In embodiments of the invention, it is now provided to use a reticulated dielectric in a semiconductor chip with a strip cell design. Due to the cross-linking, the chip structure with the dielectric and the overlying metallization has a substantially higher mechanical stability than if the dielectric consists essentially only of mutually parallel strips.
  • 1 shows a vertical section through a portion of a semiconductor chip formed as a transistor 1 , The semiconductor chip 1 is merely exemplified as a planar MOSFET or as a planar IGBT. The semiconductor chip 1 has a semiconductor body 100 with a top 101 and one of the top 101 opposite bottom 102 on. The top 101 is in a vertical direction v from the bottom 102 spaced. The vertical direction v is substantially perpendicular to the bottom 102 , The semiconductor body 100 has a drift zone 11 , Source or emitter zones 14 , as well as complementary to the source and emitter zones 14 doped body zones 12 on. Each of the body zones is between the drift zone 11 and one or more of the source zones 14 arranged. Between each source or emitter zone 14 and the drift zone 11 extends a section of a body zone located between them 12 towards the top 101 , as well as towards one of several from the top 101 spaced gate electrodes 20 passing through a dielectric layer 30 dielectric with respect to the semiconductor body 100 are isolated. In the case of a semiconductor chip designed as a MOSFET 1 has the semiconductor body 100 also a drain zone 16 of the conductivity type of the drift zone 11 but which is more highly doped than the drift zone 11 , In the alternative case of a semiconductor chip designed as an IGBT 1 has the semiconductor body 100 a collector zone 16 on, the one to the conductivity type of the drift zone 11 has complementary conductivity type and which is also more highly doped than the drift zone 11 , In the illustrated semiconductor chip 1 are the source and emitter zones 14 and the drift zone 11 n-doped while the body zones 12 p-doped. In a MOSFET is an n-doped drain zone 16 present, in an IGBT a p-doped collector zone 16 , Likewise, in complementary MOSFETs or IGBTs, the individual device regions could be doped complementary to the illustrated device regions.
  • In the following, when referring to source, a source zones or a source electrode, it is meant in the case of an IGBT emitter, an emitter zone or an emitter electrode. Accordingly, by drain, drain or drain in the case of an IGBT is meant a collector, a collector region and a collector electrode, respectively.
  • The dielectric layer 30 can in principle be constructed of any dielectric materials and produced in any way. It may consist uniformly of the same dielectric material or it may be composed of two or more different dielectric materials.
  • The production of the dielectric layer 30 can also be done in sections successively, ie it can first a first portion of the later dielectric layer 30 be prepared, then z. B. on the gate electrodes 20 can be generated, and then on the gate electrodes 20 a second portion of the later dielectric layer 30 be generated.
  • On the top 101 is a first main electrode 71 Applied to the bottom 102 a second main electrode 72 , There is also a control electrode 73 present on the top 101 is arranged. Alternatively, the control electrode could 73 also on the bottom 102 be arranged. The dielectric layer 30 is between the first main electrode 71 and the semiconductor body 100 arranged. In any case, the control electrode 73 opposite to the semiconductor body 100 dielectrically isolated. At the first main electrode 71 In the case of a MOSFET, this is a source electrode (S), in the case of an IGBT, an emitter electrode (E). Accordingly, the second main electrode is concerned 72 in the case of a MOSFET, around a drain electrode (D) and in the case of an IGBT around a collector electrode (C). In both a MOSFET and an IGBT, the control electrode is a gate electrode (G) 1 As in the other figures, the figures in square brackets refer to an IGBT, ie for an IGBT the indication immediately before a square brace must be replaced by the indication in the square brackets.
  • The transistor further has a cell structure with a plurality of transistor cells 10 , A transistor cell 10 in any case has at least one body zone 12 or at least a section of a bodyzone 12 on, at least one source zone 14 or at least a portion of a source zone 14 , as well as at least one gate electrode 20 ,
  • The transistor cells 10 lie in a (here by way of example parallel to the xy plane) planar layer of the Cartesian coordinate system, and can be electrically connected in parallel to each other. These are the source zones 14 electrically to the first main electrode 71 connected, the drain or collector zone 16 is electrically connected to the second main electrode 72 connected, and the gate electrodes 20 are electrically conductive with the control electrode 73 connected. Thus, an electrical load path between the first main electrode 71 and the second main electrode 72 is formed or an electric current through this load path, by applying a suitable electrical control potential to the control electrode 73 be controlled in a conventional manner. The electrical connections between the control electrode 73 and the gate electrodes 20 are realized outside the presentation level and therefore only indicated schematically.
  • The transistor cells 10 each have a body zone 12 on, as well as one or more source zones 14 , Furthermore, the transistor cells 10 designed as so-called striped cells. That means the transistor cells 10 are elongated and extend parallel to each other in a further, second lateral direction y, which is perpendicular to both the first lateral direction x and the vertical direction v. The longitudinal direction of the transistor cells 10 is thus oriented in the second lateral direction y. In 1 the second lateral direction y is perpendicular to the plane of the drawing. At each of the strip cells 10 extends the bodyzone 12 this strip cell 10 and at least one source zone 14 this strip cell 10 each in the second lateral direction y over the entire length L10 of this strip cell 10 ,
  • The following 2 . 3 . 4 and 5 show sectional views in the in 1 sectional planes E1-E1 ( 2 ), E2-E2 ( 3 ), E3-E3 ( 4 ) and E4-E4 ( 5 ). It is in the 2 and 3 in the second lateral direction y, ie in the direction in which the transistor cells 10 extend, the same portion of the semiconductor chip 1 shown in different, mutually parallel cutting planes E1-E1 and E2-E2. Similarly, in the 4 and 5 the same portion of the semiconductor chip 1 shown in different, mutually parallel cutting planes E3-E3 and E4-E4.
  • As in 2 It can be seen, the source zones 14 , the body zones 12 and the drift zone 11 - independently of each other - be formed in the second lateral direction y as a continuous (ie continuous), stripe-shaped semiconductor zones extending in the second lateral direction y over the entire length of the respective stripe cell 10 extend. Also the gate electrodes 20 may be continuous (ie, uninterrupted) throughout the entire length of at least one of the strip cells in the second lateral direction y 10 extend.
  • How to continue 3 it can be seen has the dielectric layer 30 Unlike in conventional striped cell structure components, this is a reticulated structure having a plurality of through holes 31 which are arranged one behind the other in the second lateral direction y and spaced from each other and through which a plurality of mutually spaced extensions 711 the first main electrode 71 to the semiconductor body 100 extend where they are at the top 101 each the same of the source zones 14 to contact. The passage openings 31 are therefore also called "contact holes". One of each through holes 31 is of the material of the dielectric layer 30 completely enclosed in a ring.
  • The extensions 711 form a number of mutually parallel rows spaced apart in the first lateral direction x (see Figs 1 . 4 and 5 ), wherein each of the rows is a plurality of extensions 711 which are spaced apart from each other at a distance d711 in the second lateral direction y (see FIGS 3 . 4 and 5 ). Different distances d711 may be identical or different from each other. Accordingly, the passage openings form 31 a number of mutually parallel rows spaced apart in the first lateral direction x (see Figs 1 . 4 and 5 ), wherein each of the rows has a plurality of through holes 31 which are also spaced apart from each other at intervals d711 in the further second lateral direction y (see FIGS 3 . 4 and 5 ). In the second lateral direction y, the extensions have 711 each have a length L711. Different lengths of L711 may be identical or different from each other. In addition, two have in the second lateral direction y immediately consecutive extensions 711 a distance d711. Different distances d711 may be identical or different from each other. Accordingly, the passage openings 31 in the second lateral direction y on a length L31 and the distance between two in the second lateral direction y directly successive through holes 31 is d31. Here, different ones of the distances d31 may be identical or different from each other, and / or different ones of the lengths L711 may be identical or different from each other.
  • In the 6 to 10 is an example of another semiconductor chip 1 shown, a transistor having a plurality of transistor cells 10 contains, which are formed as stripe cells and electrically connected in parallel to each other.
  • 6 shows a vertical section through a portion of the semiconductor chip 1 , The semiconductor chip 1 again has a semiconductor body 100 with a top 101 and one of the top 101 opposite bottom 102 on. The top 101 is in a vertical direction v from the bottom 102 spaced. The vertical direction v is substantially perpendicular to the bottom 102 , The semiconductor body 100 has a drift zone 11 , Source zones 14 , as well as complementary to the source zones 14 doped body zones 12 on. One of each of the body zones 12 is between the drift zone 11 and one or more of the source zones 14 arranged. In the case of a semiconductor chip designed as a MOSFET 1 this also has a drain zone 16 of the conductivity type of the drift zone 11 but which is more highly doped than the drift zone 11 , In the alternative case of a semiconductor chip designed as an IGBT 1 has the semiconductor body 100 a collector zone 16 on, the one to the conductivity type of the drift zone 11 has complementary conductivity type and which is also more highly doped than the drift zone 11 , In the illustrated semiconductor chip 1 are the source zones 14 and the drift zone 11 n-doped while the body zones 12 p-doped. For a MOSFET, the drain is 16 n-doped, in an IGBT is the collector zone 16 p-doped. Likewise, in complementary MOSFETs or IGBTs, the individual device regions could be doped complementary to the illustrated device regions.
  • On the top 101 is a first main electrode 71 Applied to the bottom 102 a second main electrode 72 , There is also a control electrode 73 present on the top 101 is arranged. Alternatively, the control electrode could 73 also on the bottom 102 be arranged. In any case, the control electrode 73 opposite to the semiconductor body 100 dielectrically isolated. At the first main electrode 71 In the case of a MOSFET, this is a source electrode (S), in the case of an IGBT, an emitter electrode (E). Accordingly, the second main electrode is concerned 72 in the case of a MOSFET, around a drain electrode (D) and in the case of an IGBT around a collector electrode (C). In both a MOSFET and an IGBT, the control electrode is a gate electrode (G).
  • The source zones 14 are electrically connected to the first main electrode 71 connected, the drain or collector zone 16 is electrically connected to the second main electrode 72 connected, and the gate electrodes 20 are electrically connected to the control electrode 73 connected. Thus, an electrical load path between the first main electrode 71 and the second main electrode 72 is formed or an electric current through this load path to be controlled by applying a suitable electrical control potential to the control electrode in a conventional manner. The electrical connections between the control electrode 73 and the gate electrodes 20 are realized outside the presentation level and therefore only indicated schematically.
  • Unlike the semiconductor chip 1 according to the 1 to 5 are at the semiconductor chip 1 according to the 5 to 10 the gate electrodes 20 in trenches 40 arranged, each one of them starting from the top 101 to the bottom 102 towards the semiconductor body 100 extends into it. In each of the trenches 40 is one of the gate electrodes 20 arranged. In doing so isolated in each of the trenches 40 a trench dielectric 41 those in the trench in question 40 located gate electrode 20 electrically opposite the semiconductor body 100 , Between the first main electrode 71 and the top 101 is also a dielectric layer 30 arranged, which is the first main electrode 71 opposite to the gate electrodes 20 electrically isolated.
  • Optionally, in each of the trenches 40 still one field electrode each 21 be arranged with the first main electrode 71 is electrically connected. The corresponding electrical connections are realized outside the display plane and therefore only indicated schematically. At each of the field electrodes 21 is a section of the tomb dielectric 41 this field electrode 21 and the semiconductor body 100 arranged, whereby a direct contact between the field electrode 21 and the semiconductor body 100 is prevented.
  • As well as the dielectric layer 30 can also be the gate dielectric 41 be constructed of any dielectric materials and produced in any way. It may consist uniformly of the same dielectric material, or it may be composed of two or more different dielectric materials. The production of the dielectric layer 30 can also be done in sections successively, ie it can first a first section of the later trench dielectric 41 be prepared, then z. B. on the field electrodes 41 can be generated, then on the field electrodes 21 a section of the tomb dielectric 41 be generated later between the field electrode 41 and that in the same ditch 40 located gate electrode 20 is arranged.
  • The transistor cells 10 each have a body zone 12 on, as well as one or more source zones 14 , The transistor cells 10 are designed as so-called striped cells. That means the transistor cells 10 are elongated and they extend parallel to each other in a further second lateral direction y, which is perpendicular to both the first lateral direction x and the vertical direction v. In 6 is thus the course direction y of the strip cells 10 oriented perpendicular to the plane of the drawing. At each of the strip cells 10 extends the bodyzone 12 this strip cell 10 and at least one source zone 14 this strip cell 10 in the second lateral direction y over the entire length L10 of this strip cell 10 ,
  • The following 7 . 8th . 9 and 10 show sectional views in the in 6 sectional planes E5-E5 ( 7 ), E6-E6 ( 8th ), E7-E7 ( 9 ) and E8-E8 ( 10 ). It is in the 7 and 8th in the second lateral direction y, ie in the direction in which the transistor cells 10 extend, the same portion of the semiconductor chip 1 in different, parallel cutting planes E5-E5 and E6-E6 shown. Similarly, in the 9 and 10 the same portion of the semiconductor chip 1 shown in different, parallel cutting planes E7-E7 and E8-E8.
  • As in 7 It can be seen, the source zones 14 , the body zones 12 and the drift zone 11 - independently of each other - be formed in the second lateral direction y as a continuous (ie continuous), stripe-shaped semiconductor zones extending in the second lateral direction y over the entire length of the respective stripe cell 10 extend. Also the gate electrodes 20 may be continuous (ie, uninterrupted) throughout the entire length of at least one of the strip cells in the second lateral direction y 10 extend.
  • How to continue 8th it can be seen has the dielectric layer 30 - Again, a plurality of through holes 31 which are arranged one behind the other in the second lateral direction y and spaced from each other and through which a plurality of mutually spaced extensions 711 the first main electrode 71 in trenches 70 extend into it from the top 101 starting in the semiconductor body 100 into it. Each one of the extensions contacts 711 at least one of the source zones 14 , as well as one of the body zones 12 ,
  • The extensions 711 form a number of mutually parallel rows spaced apart in the first lateral direction x (see Figs 6 . 9 and 10 ), wherein each of the rows is a plurality of extensions 711 which are spaced apart from each other at a distance d711 in the second lateral direction y (see FIGS 8th . 9 and 10 ). Accordingly, the passage openings form 31 a number of mutually parallel rows spaced apart in the first lateral direction x (see Figs 6 . 9 and 10 ), wherein each of the rows has a plurality of through holes 31 having.
  • 11 shows in plan view only the dielectric layer 30 with their passage openings 31 , as in the above-explained semiconductor chips 1 can be used. All other components of the semiconductor chip 1 are not shown. 12 shows a perspective view of this dielectric layer 30 ,
  • As further described by an in 13 illustrated example of a dielectric layer 30 is explained, a through hole 31 optionally in the first lateral direction x have a maximum width B31, and in the second lateral direction y a maximum length L31 which is greater than the width B31. In this case, the maximum length L31 can be selected, for example, less than or equal to 40 μm, and / or the maximum width B31, for example, less than or equal to 5 μm.
  • In 13 are the passages 31 Although shown as rectangular openings, but they - as in all other embodiments of the invention - in principle, any shapes, for example, square, circular, elliptical, irregular, and so on. Regardless of the shape can through holes 31 be formed so that they each have an opening area A31, which is less than or equal to 200 microns 2 . The "opening area" A31 is the size of the flat area to be considered that the respective passage opening 31 in your orthogonal projection on a projection plane that is perpendicular to the vertical direction v.
  • 14 shows a perspective view of an inverted first main electrode 71 with the extensions 711 , All other components of the semiconductor chip 1 are not shown. Here as in the 4 . 5 . 9 and 10 is shown schematically that the extensions 711 may be arranged in a matrix, so that there are a plurality of rows, each extending in the second lateral direction y and in each case a plurality of extensions 711 which are arranged one behind the other and spaced apart in the second lateral direction y.
  • For the examples explained above, as well as in all other embodiments of the invention, therefore, a dielectric layer is formed 30 between a first main electrode 71 and the semiconductor body 100 is arranged and the a plurality of through holes 31 has and is formed net-shaped, in combination with component cells 10 used, which are designed as strip cells. The reticular structure of the dielectric layer 30 causes a significant improvement in the bondability in that the likelihood of damage to the semiconductor chip caused by the wire bonding process 1 compared to conventional semiconductor chip with stripe cell structure is significantly reduced. This applies in particular to the bonding of copper-based and / or thick bonding wires.
  • The semiconductor chips explained above 1 As well as all other semiconductor chips in the sense of the invention may have further features, which are explained below and - unless otherwise stated - are each optional and can be used in any combination with each other.
  • The first main electrode 71 can be chosen very thick. It can be in the vertical direction v above the dielectric layer 30 a minimum layer thickness D71 (see the 1 . 2 . 3 and 6 . 7 . 8th ) of, for example, at least 5 μm, at least 10 μm or at least 20 μm.
  • The first main electrode 71 may in principle consist of any electrically conductive materials or electrically conductive material combinations or have such materials or combinations of materials. For example, the first main electrode 71 Having aluminum or an aluminum alloy, and / or copper or a copper alloy, and / or a polycrystalline semiconductor material such as polycrystalline silicon, or may - except polycrystalline semiconductor material - consist of one of these materials. In particular, the first main electrode 71 to a proportion of at least 90% by weight (by weight) of copper.
  • The first main electrode 71 can z. B. also be designed as that the extensions 711 of doped polycrystalline semiconductor material, while the other portions of the first main electrode 71 consist of one of the above metals or metal alloys.
  • Furthermore, a first main electrode 71 be composed of two, three or more than three electrically conductive layers, each two adjacent these layers consist of different materials. So can a first main electrode 71 z. B. have a first sub-layer, and one between the first sub-layer and the semiconductor body 100 arranged second sub-layer. The second sub-layer may be formed as a barrier layer, which is the penetration of material from the first sub-layer into the semiconductor body 100 prevented or at least significantly. This is particularly relevant if the first sub-layer contains copper or consists of copper, since in the semiconductor body 100 penetrating copper adversely affects the properties of the semiconductor chip. Suitable materials of a barrier layer are z. B. Titanium, tungsten, titanium nitride, tungsten nitride, titanium tungsten or any combination thereof.
  • Furthermore, for one, several or each of the through holes 31 that their maximum length L31, which they have in the second lateral direction y, is not greater than 50 times their maximum width B31 present in the first lateral direction x.
  • According to a further option, the semiconductor chip may have a total number of strip-shaped gate electrodes 20 have in the second lateral direction y and parallel to each other, and the number of extensions 711 may be at least 5 times the total number of stripe-shaped gate electrodes 20 be. Accordingly, the number of through holes 31 at least 5 times the total number of stripe-shaped gate electrodes 20 be.
  • In the case of a transistor device, one, more than one or each of the device cells 10 a source or emitter zone 14 which is formed as an elongate strip whose longitudinal direction is identical to the second lateral direction y. It is possible for each of these component cells 10 a plurality of N ≥ 5 extensions 711 be arranged in series in the second lateral direction y, and one each through another of the through holes 31 extends through and reaches up to the source or emitter zone and this touches while electrically contacted. The extensions 711 a row thus touch the same source or emitter zone 14 , Optionally, for one, several or each of the rows of N projections, the distance d711 (see the figures) may be the two directly consecutive ones of the N extensions 711 in the second lateral direction y, on average less than 10 microns.
  • 15 shows a plan view of a semiconductor chip according to the invention 1 with a semiconductor body 100 in which a variety of strip cells 10 is arranged. The strip cells 10 , which are arranged successively in the first lateral direction x, each have an elongated shape. Their longitudinal direction is identical to the second lateral direction y. Each of the strip cells 10 has at least one strip-shaped source or emitter zone ( 14 in the 1 . 2 . 3 . 6 . 8th and 16 ) or at least one strip-shaped section of a source or emitter zone, and at least one strip-shaped body zone ( 12 in the 1 . 2 . 3 . 6 . 8th and 16 ) or at least a portion of a strip-shaped body zone, and a strip-shaped gate electrode ( 20 in the 1 . 2 . 5 . 6 . 7 and 16 ). The aforementioned strip-shaped zones or their sections and the strip-shaped gate electrode each extend over the entire length L10 of the respective strip cell 10 , It follows that each cutting plane E, which is perpendicular to the second lateral direction y and a strip cell 10 cuts, also one to this strip cell 10 associated source or emitter zone ( 14 ) as well as one to this strip cell 10 proper body zone ( 12 ) and one to this strip cell 10 associated gate electrode ( 20 ).
  • It should be noted that the illustration according to 15 only a few strip cells 10 shows and that in real components the number of streak cells 10 can be much higher. For example, the number of stripe cells 10 be greater than 400.
  • The semiconductor body 100 has a length L100 in the second lateral direction y, and the stripe cells 10 each have a length L10. Optionally, one, more than one or each of the strip cells 10 of the semiconductor chip 1 have a length L10 which is at least 80% of the length L100 of the semiconductor body 100 is. Also optionally, one, more than one or each of the stripe cells of the semiconductor chip 1 have a length L10 of at least 800 microns.
  • While in the embodiments shown above, the first lateral direction x and the second lateral direction y are perpendicular to each other, these directions x, y in the embodiment according to close 16 an angle α of less than 90 °.
  • In the embodiments shown above, the dimensions d31, d711, B31, L31, L711, d10, etc. are each identical. In addition, the first lateral direction x and the second lateral direction y are perpendicular to each other. In principle, however, the dimensions d31, d711, B31, L31, L711, d10, etc. may in themselves be different. This means, for example, that different distances d711 can be different. The same applies to the other of the dimensions mentioned. As an example of this shows 17 a view accordingly 4 with the difference that the extensions 711 are designed inhomogeneous and have different distances.
  • In conclusion, referring to 18 nor the production of a bond between a bonding wire 200 and the first main electrode 71 the example of the in the 6 to 10 illustrated semiconductor chips 1 explained. Basically, a bonding wire 200 in the same way to the first main electrode 71 each one inventive semiconductor chips 1 be bonded.
  • If in this context of "bonding" is mentioned, it is always meant "wire bonding", ie a connection technique in which a mechanically stable and electrically conductive connection is made by a provided bonding wire 200 at a given bonding point on the first main electrode 71 is positioned so that it is the first main electrode 71 touched, and that he then by means of a sonotrode 300 with a contact force F against the first main electrode 71 is pressed while the sonotrode 300 at applied contact force F side, for example, with an ultrasonic frequency, oscillates back and forth until a firm connection between the bonding wire 200 and the first main electrode 71 is present. This bonding technique is also referred to as ultrasonic bonding. The connection can be made so that only the materials of the bonding wire 200 and the first main electrode 71 contribute to the connection, ie there must be no additional connection means such as solder or glue supplied.
  • In particular, the bonding technique used may be wedge bonding. In wedge bonding, the already bonded bonding wire on one side of the bond is torn off. Wedge bonding is particularly suitable for thick bonding wires 200 ie for bonding wires 200 which have (outside the bonding site or before bonding) a diameter D200 of at least 300 μm or even at least 400 μm, or in the case of bonding wires 200 , which have no circular cross-section, (outside the bonding or before bonding) has a cross-sectional area of at least 70000 microns 2 (corresponds approximately to a bonding wire with a circular cross-section and a diameter of 300 microns) or a cross-sectional area of at least 125000 microns 2 (corresponds about a bonding wire with a circular cross-section and a diameter of 400 microns). The cross-sectional area is to be determined in a sectional plane perpendicular to the direction of the bonding wire. As a bonding wire 200 in this sense, flat ribbons are considered, which have an approximately rectangular Querschitt. Basically, the shape of the bonding wire 200 however, be chosen arbitrarily. Moreover, in this sense, not only a quasi-endless bonding wire as a bonding wire 200 but also arbitrarily shaped wire sections such as electrical connection plates.
  • In principle, the bonding wire 200 have any materials, for example aluminum or an aluminum alloy, and / or copper or a copper alloy. In particular, a bonding wire 200 also a share of at least 98 Have percent by weight of copper.
  • It should be noted that the illustration according to 18 insofar as only schematically, as the bonding wire 200 and the sonotrode 300 in relation to the semiconductor chip 1 are represented too small by a multiple. In real (fully bonded) arrangements, the bond site covers, ie, the entire surface area 712 the first main electrode 71 to which the bonding wire 200 at a bonding site cohesively with the first main electrode 71 is connected or is, a plurality of through holes 31 and therefore also a multiplicity of extensions 711 ,
  • An example of this shows 19 on the basis of a semiconductor chip 1 in plan view of the first main electrode 71 , Shown is the in the mathematical sense simply coherent surface section 712 , at the later one (not shown) bonding wire 200 - as based on 18 explained - so to the first main electrode 71 Bonded is that the bonding wire 200 the first main electrode 71 at every point of the surface section 712 contacted.
  • Vertically below the surface section 712 There is a large number of through holes 31 passing through the first main electrode 71 hidden and therefore shown in phantom. "Vertically below" refers in this context to the vertical direction v vertical surface of the first main electrode 71 , So on the semiconductor body 1 opposite side of the first main electrode 71 to which the bonding wire 200 is bonded. This means that each straight line parallel to the vertical direction v, the one perpendicular to the surface section 712 located passage opening 31 cuts, also the surface section 712 cuts.
  • For the sake of representability are in 19 only thirty vertically below the simply contiguous surface section 712 located passage openings 31 shown. For a real semiconductor chip 1 however, the number of through holes 31 , which are perpendicular below a simply connected surface section 712 a later or existing bond, are chosen to be much larger. For example, can be vertically below a simply contiguous surface section 712 a number of at least 4000 through holes 31 are located. Optionally, at least 4000 of these through holes 31 each have an opening area A31 which is smaller than 200 microns 2 , wherein the opening areas A31 of different passage openings 31 may be the same or different.
  • Also optionally, the ratio of the number of through holes 31 which are perpendicular below a simply continuous surface section 712 the first main electrode 71 are arranged to the (basic) area A712 of the single-connected surface portion 712 greater than 2000 / mm 2 .
  • Alternatively or additionally, the area A712 may be, for example, at least 0.8 mm 2 . The high areal density of more than 2000 / mm 2 can thus be selected, for example, only locally at the locations where later a bonding wire 200 to the first main electrode 71 is bonded. However, it is also possible the ratio of the number of through holes 31 perpendicular to the first main electrode 71 are arranged, to the surface A71 of the semiconductor body 100 opposite side of the first main electrode 71 greater than 2000 / mm 2 .

Claims (20)

  1. A semiconductor chip, comprising: a semiconductor body ( 100 ) with a top side ( 101 ) and one of the top ( 101 ) opposite bottom ( 102 ); a plurality of device cells designed as strip cells ( 10 ) juxtaposed in a first lateral direction (x) and each extending in a second lateral direction (y) different from the first lateral direction (x); a main electrode ( 71 ) on the top ( 101 ) is applied; one between the main electrode ( 71 ) and the top ( 101 ) arranged dielectric layer ( 30 ), which has a net-like structure, wherein the net-like structure has a multiplicity of passage openings ( 31 ) having.
  2. Semiconductor chip according to Claim 1, in which the main electrode ( 71 ) consists of at least 90 percent by weight of copper.
  3. A semiconductor chip according to claim 1 or 2, wherein for one, more than one or each of the through holes 31 is that its maximum length (L31), which it has in the second lateral direction y, is not greater than 50 times its maximum width (B31) present in the first lateral direction (x).
  4. Semiconductor chip according to one of the preceding claims, in which the main electrode ( 71 ) a plurality of spaced-apart extensions ( 711 ), each of which extends in the direction of the underside ( 102 ), wherein through one of the passage openings ( 31 ) another of the extensions ( 711 ) is passed.
  5. Semiconductor chip according to Claim 4, in which none of the through-openings ( 31 ) more than one of the extensions ( 711 ) extends therethrough.
  6. Semiconductor chip according to one of Claims 4 or 5, which has a total number of strip-shaped gate electrodes ( 20 ), which extend in the second lateral direction (y) and parallel to one another, wherein the number of through-openings ( 31 ) at least 5 times the total number of stripe-shaped gate electrodes ( 20 ) is.
  7. Semiconductor chip according to one of Claims 4 to 6, which has a total number of strip-shaped gate electrodes ( 20 ) running in the second lateral direction (y) and parallel to one another, the number of extensions ( 711 ) at least 5 times the total number of stripe-shaped gate electrodes ( 20 ) is.
  8. A semiconductor chip according to any one of claims 4 to 7, wherein one, more than one or each of the stripe cells ( 10 ) a source or emitter zone ( 14 ), which is formed as an elongated strip whose longitudinal direction is identical to the second lateral direction (y), wherein for each of the strip cells ( 10 ) at least 5 of the extensions ( 711 ) are arranged in a row one behind the other in the second lateral direction (y), each of the at least five extensions ( 711 ) of this row through another of the through holes 31 through to the source or emitter zone of this stripe cell ( 10 ) and touches this source or emitter zone while electrically contacting.
  9. Semiconductor chip according to Claim 8, in which, for each of the rows, their at least 5 extensions arranged in succession in the second lateral direction (y) ( 711 ) have on average a distance of less than 10 microns.
  10. A semiconductor chip according to any one of the preceding claims, wherein at least one of the following three criteria (i), (ii) and (iii) is satisfied: (i) a plurality of stripe-shaped gate electrodes ( 20 each of which has a longitudinal direction identical to the second lateral direction (y) and in which it spreads over the entire strip cell (FIG. 10 ) extends; (ii) in the semiconductor body ( 100 ) are a variety of striped body zones ( 12 each of which has a longitudinal direction which is identical to the second lateral direction (y) and in which it extends over the entire strip cell (FIG. 10 ) extends; (iii) in the semiconductor body ( 100 ) are a plurality of stripe-shaped source zones ( 14 each of which has a longitudinal direction which is identical to the second lateral direction (y) and in which it extends over the entire strip cell (FIG. 10 ).
  11.  The semiconductor chip according to claim 10, wherein two or three of the criteria (i), (ii), (iii) are satisfied.
  12.  Semiconductor chip according to one of the preceding claims, wherein the strip cells are electrically connected in parallel to each other.
  13. Semiconductor chip according to one of the preceding claims, which is designed as a MOSFET, in which the main electrode ( 71 ) forms a source terminal; or is designed as an IGBT, in which the main electrode ( 71 ) forms an emitter terminal.
  14. Semiconductor chip according to one of the preceding claims, in which the first main electrode ( 71 ) on its the semiconductor body ( 1 ) facing away from a simple contiguous surface section ( 712 ) having an area (A712); and the ratio of the number of vertically below the surface portion ( 712 ) arranged through openings 31 to the (basic) area (A712) is greater than 2000 / mm.
  15. A semiconductor chip according to claim 14, wherein the area (A712) of the single-connected surface portion (A712) 712 ) is at least 0.8 mm 2 .
  16. Semiconductor chip according to one of the preceding claims, in which the first main electrode ( 71 ) on its the semiconductor body ( 1 ) facing away from a simple contiguous surface section ( 712 ) having a total area (A71); and the ratio of the number of vertically below the main electrode ( 71 ) arranged passage openings ( 31 ) to the total area (A71) is greater than 2000 / mm.
  17. Method for producing a wire bond connection comprising the following steps: providing a semiconductor chip (according to one of the preceding claims) ( 1 ); Provide a bonding wire ( 200 ); Making a wire bond between the bonding wire ( 200 ) and the main electrode ( 71 ).
  18.  The method of claim 16, wherein the wire bonding connection is made by wedge bonding.
  19. A method according to claim 17 or 18, wherein the bonding wire ( 200 ) consists of at least 98 percent by weight of copper.
  20. Method according to one of Claims 17 to 19, in which the bonding wire ( 200 ) has a diameter of at least 300 μm and / or a cross-sectional area of at least 70,000 μm 2 before producing the wire bond connection; or has a diameter of at least 400 microns and / or a cross-sectional area of at least 125000 microns 2 .
DE102014107387.8A 2014-05-26 2014-05-26 Semiconductor chip with improved bondability and method for producing a bond compound Ceased DE102014107387A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1022322A (en) * 1996-06-28 1998-01-23 Denso Corp Semiconductor device
US20100264546A1 (en) * 2007-11-09 2010-10-21 Sanken Electric Co., Ltd. Semiconductor device and manufacturing method thereof
DE102012008068A1 (en) * 2011-04-21 2012-10-25 Fairchild Semiconductor Corp. Multi-level options of a power MOSFET

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1022322A (en) * 1996-06-28 1998-01-23 Denso Corp Semiconductor device
US20100264546A1 (en) * 2007-11-09 2010-10-21 Sanken Electric Co., Ltd. Semiconductor device and manufacturing method thereof
DE102012008068A1 (en) * 2011-04-21 2012-10-25 Fairchild Semiconductor Corp. Multi-level options of a power MOSFET

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