DE102014105863A1 - Converter circuit and method for converting an input voltage into an output voltage - Google Patents

Abstract

A converter circuit is described, comprising: a switch circuit that is designed to provide an output voltage, a control circuit that includes an analog control component and a digital control component, and a noise generator that is designed to generate white noise, wherein the noise generator is designed to feed the generated white noise to the digital control portion of the control circuit, and wherein the control circuit is designed to control the switching circuit on the basis of the white noise.

Description

Various embodiments generally relate to converter circuits and methods for converting an input voltage to an output voltage.

System power supplies, such as switched-mode power supplies (SMPS), may be implemented as feedback loops that regulate voltage and / or current to an external load. Control loops are typically designed conservatively, i. H. such that a high degree of stability is achieved. For example, closed-loop control and stability margins are supported, consistent with expected operating condition ranges and tolerances on parameters of load power stages (eg, inductors and / or capacitors of a power stage of an SPMS).

However, non-idealities of components outside of an SPMS may result in performance degradation or closed loop stability losses if there are significant operating point changes associated with degradation of the components.

A converter circuit is described, comprising: a switch circuit configured to provide an output voltage; a control circuit including an analog control portion and a digital control portion, and a noise generator configured to generate white noise; the noise generator is adapted to supply the generated white noise to the digital control portion to the control circuit and wherein the control circuit is adapted to control the switch circuit based on the white noise.

According to various embodiments, the control circuit is configured to control the switch circuit based on the white noise to determine at least one property of at least one of: the load or the converter circuit.

The control circuit may be further configured to determine one or more elements of a group consisting of:
an inductance of an inductor;
a capacitance of a capacitor;
an equivalent series resistance of a capacitor; and
an electrical property of the load.

According to one embodiment, the control circuit is configured to control the switch circuit to provide the output voltage based on a duty cycle; and the control circuit is configured to control the switch circuit based on the white noise by adding the generated white noise to the duty cycle.

The control circuit includes, for example, an analog-to-digital converter configured to receive a reading of the output voltage and provide a digital value indicative of the sensed reading of the output voltage.

For example, the analog-to-digital converter is further configured to compare the sensed output voltage reading to a reference voltage and to generate a deviation signal representative of a difference between the sensed output voltage reading and the reference voltage. For example, the deviation signal may be a digital value that specifies the difference between the recorded measurement of the output voltage and the reference voltage.

The control circuit is designed, for example, to add the generated white noise to the deviation signal.

The control circuit may be configured to sequentially increase the reference voltage.

According to one embodiment, the control circuit further comprises a proportional-integral-derivative (PID) controller configured to receive the deviation signal and generate a PID output based on the picked-up deviation signal.

The control circuitry may still be configured to add the generated white noise to the PID output.

According to one embodiment, the control circuit further comprises a pulse width modulation controller configured to receive the PID output and to generate a pulse width modulated control signal configured to regulate a power stage to provide the output with the load.

For example, the control circuitry may be configured to add the generated white noise to the pulse width modulated control signal.

In one embodiment, the noise generator is configured to generate the white noise using a sigma-delta converter.

In one embodiment, the noise generator is further configured to reduce a resolution of the sigma-delta converter to increase an amplitude of the generated white noise.

The sigma-delta converter may contain more than one feedback loop. For example, at least one zero of the sigma-delta converter is located near the resonant frequency of the load.

According to one embodiment, the control circuit further comprises an analog-to-digital (AD) converter configured to receive a measurement of an output voltage at the load, compare the sensed measurement of the output voltage to a reference voltage, and generate a deviation signal representing a difference between the sensed measurement of the output voltage and the reference voltage, and the control circuit is configured to process the deviation signal to determine one or more of: the cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

The control circuitry may be further configured to process the deviation signal to determine a spectral power density.

According to one embodiment, the control circuit is further configured to determine one or more of the following based on the determined spectral power density: a loop cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

According to one embodiment, the control circuit is further configured to adjust at least one coefficient of a PID controller configured to receive the deviation signal and generate a PID output based on one or more of: the determined loop cutoff frequency of the control circuit or certain equivalent series resistance of a capacitor.

Furthermore, a method is provided for converting an input voltage into an output voltage according to the converter circuit described above.

In the drawings, like reference characters generally indicate the same parts throughout the different views. The drawings are not necessarily to scale, for the focus is generally placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention will be described with reference to the following drawings:

1 shows a converter circuit according to an embodiment.

2 FIG. 10 is a flowchart illustrating a method of converting an input voltage to an output voltage. FIG.

3 is a block diagram showing an example of a switching power supply (SPMS).

4 FIG. 10 is a block diagram showing another example of an SPMS according to an embodiment.

5 shows an example of an addition circuit according to an embodiment.

6 illustrates various examples of arrangements for adding white noise.

7 FIG. 12 is a voltage waveform diagram of the reference voltage versus time in an embodiment in which the reference voltage is gradually increased. FIG.

8th shows a state diagram for an SPMS according to an embodiment.

9 FIG. 10 is a block diagram illustrating an example of an SPMS that includes a state machine according to one embodiment.

10 shows results for one embodiment in an exemplary operating scenario.

11A illustrates the steady state taking into account ΔΣ and DPWM with the same resolution.

11B illustrates the case where the noise source is a ΔΣ modulator in the loop.

12 shows PSD (power spectral density) results considering a ΔΣ noise source in the loop.

13 illustrates the result of modifying a third order noise transfer function (NTF) to add an in-band zero near the resonant frequency.

14 shows a switched mode power supply (SMPS) converter in a buck converter configuration.

15A shows a control loop.

15B shows a signal curve of the output signal of the control loop 15A ,

15C shows a signal curve of the manipulated variable of the control loop 15A ,

15D shows a Nyquist diagram for the control loop 15A ,

16 shows a graph showing the amplitude and phase of a controlled system as a function of frequency.

The following detailed description refers to the accompanying drawings which illustrate, by way of illustration, specific details and embodiments in which the invention may be practiced.

The term "exemplary" is used herein to mean "by way of example, expression or illustration." Any embodiment or type described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or constructions.

The word "about," as used with respect to a deposited material formed "over" a page or surface, may be used herein to mean that the deposited material is "directly on," e.g. B. in direct contact with, said side or surface is formed. The word "about," as used with respect to a deposited material formed "over" a page or surface, may be used herein to mean that the deposited material is formed "indirectly on" said side or surface, with one or more a plurality of additional layers disposed between said side or surface and the deposited material.

According to one embodiment, a converter circuit with a control loop, z. For example, an SPMS (switching power supply) is provided which includes a white noise generator that excites the control loop over a wide range of frequencies. From the response of the control loop to the excitation may be Information about external components, such as As an output network derived, which may be used in turn for a configuration of the control loop, z. B. for a setting of controller parameters.

The following is here with reference to 1 an example of a converter circuit 100 which is consistent with the techniques described herein.

1 shows a converter circuit 100 according to one embodiment.

The converter circuit 100 contains a switch circuit 101 which is designed to be an output voltage 106 to provide, and a control circuit 102 , which has an analog control share 103 and a digital control share 104 contains.

The converter circuit 100 also contains a noise generator 105 which is designed to white noise 107 wherein the noise generator is adapted to transfer the generated white noise to the digital control portion 104 of the control circuit 102 supply, and the control circuit 102 designed to be the switch circuit 101 based on the white noise 107 to regulate.

The converter circuit is designed, for example, as a DC-DC converter circuit, for example as a switching power supply circuit.

In other words, according to various embodiments, white noise may be introduced into a control loop to excite the system at different frequencies. Based on the results of these suggestions, parameters may be determined, such as ESR (equivalent series resistance) and the LC resonance frequency of an output network.

For example, white noise is noise given by a random variable whose distribution is not zero over an interval equal to the quantization level. White noise may also be understood as a random signal with a flat (constant) spectral power density.

According to various embodiments, the switch circuit includes at least one switching transistor.

For example, the at least one switching transistor includes at least one switching transistor.

For example, the at least one power switching transistor may include at least one of the following: a field effect transistor or an insulated gate bipolar transistor.

According to various embodiments, the control circuit is configured to control the switch circuit based on the white noise to determine at least one property of at least one of: the load or the converter circuit. In other words, a property of the load (such as an inductance, a capacitance, and / or an equivalent series resistance) may be determined based on, for example, a response of the converter circuit to the white noise; H. the behavior of the converter circuit in response to the white noise.

The control circuit may be further configured to determine one or more elements of a group consisting of:
an inductance of an inductor;
a capacitance of a capacitor;
an equivalent series resistance of a capacitor; or
an electrical property of the load.

According to one embodiment, the control circuit is configured to regulate the switch circuit to provide the output voltage based on a duty cycle, and the control circuit is configured to control the switch circuit based on the white noise by adding the generated white noise to the duty cycle. In other words, the white noise is added, for example, to a pulse width modulation signal, based on which the converter circuit generates the output voltage according to pulse width modulation.

The control circuit includes, for example, an analog-to-digital converter configured to receive a reading of the output voltage and provide a digital value indicative of the sensed reading of the output voltage.

For example, the analog-to-digital converter is further configured to compare the sensed output voltage reading to a reference voltage and to generate a deviation signal representative of a difference between the sensed output voltage reading and the reference voltage. The deviation signal is, for example, a digital value that specifies the difference between the recorded measured value of the output voltage and the reference voltage.

The control circuit is designed, for example, to add the generated white noise to the deviation signal. In other words, a digital value of a digital white noise is added to a digital value representing a difference between the recorded measured value of the output voltage and the reference voltage.

The control circuit may be configured to sequentially increase the reference voltage. For example, the reference voltage may be incrementally increased from an initial value (eg, zero) to a setpoint. For example, this may be done in an initial phase (eg, a startup phase).

According to one embodiment, the control circuit further comprises a PID controller configured to receive the deviation signal and generate a PID output based on the received deviation signal.

The control circuitry may still be configured to add the generated white noise to the PID output.

According to one embodiment, the control circuit further comprises a pulse width modulation controller configured to receive the PID output and to generate a pulse width modulated control signal configured to regulate a power stage to provide the output with the load. In other words, for example, a signal from the pulse width modulation controller (eg, from a digital pulse width modulation module) specifying a pulse width modulation pulse width is input, and supplied to a power stage that measures the pulse width modulation output voltage based on the pulse width specifying value Signals generated.

For example, the control circuitry may be configured to add the generated white noise to the pulse width modulated control signal.

In one embodiment, the noise generator is configured to generate the white noise using a sigma-delta converter.

In one embodiment, the noise generator is further configured to reduce a resolution of the sigma-delta converter to increase an amplitude of the generated white noise. The resolution of the sigma-delta converter is, for example, the resolution of an output quantizer of the sigma-delta converter.

The sigma-delta converter may contain more than one feedback loop. For example, at least one zero of the sigma-delta converter is located near the resonant frequency of the load.

According to one embodiment, the control circuit further comprises an analog-to-digital (AD) converter configured to receive a measurement of an output voltage at the load, compare the sensed measurement of the output voltage to a reference voltage, and generate a deviation signal representing a difference between the sensed measurement of the output voltage and the reference voltage, and the control circuit is configured to process the deviation signal to determine one or more of: the cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

The control circuitry may be further configured to process the deviation signal to determine a spectral power density.

According to one embodiment, the control circuit is further configured to determine one or more of the following based on the determined spectral power density: a loop cutoff frequency of the control circuit or an equivalent series resistance of a capacitor.

According to one embodiment, the control circuit is further configured to adjust at least one coefficient of a PID controller configured to receive the deviation signal and generate a PID output based on one or more of: the determined loop cutoff frequency of the control circuit or certain equivalent series resistance of a capacitor. In other words, based on the result of the determination, the control circuit may adjust one or more parameters of the PID controller.

The converter circuit 100 For example, execute a procedure as described in 2 is illustrated.

2 shows a flowchart 200 ,

The flowchart 200 illustrates a method of converting an input voltage to an output voltage.

In 201 White noise is generated.

In 202 The generated white noise is supplied to a digital control portion of a control circuit.

In 203 The control circuit controls a switch circuit based on white noise to provide the output voltage.

It should be noted that in the context of the converter circuit 100 described embodiments analogous to the in 2 Illustrated methods apply and vice versa.

Hereinafter, embodiments will be described in more detail. It should be noted that the various concepts described below may be used together or separately.

3 shows a switching power supply (SMPS) 300 ,

The SMPS 300 is possibly a down-converter SMPS operating in a digital loop. It may contain an analog-to-digital (AD) converter 301 which receives a reference voltage Vref and the output voltage Vout. The SMPS 300 is designed to reach an output voltage Vout that is as close as possible to the reference voltage Vref. The AD converter 301 generates a deviation signal e [n], which is the digitized difference between the reference voltage Vref and the output voltage Vout. The deviation signal e [n] is then transmitted via a PID block 302 filtered. The parameters of the PID module are, for example, to achieve a certain stability and a certain dynamic performance of the SMPS 300 set. The PID module 302 generates a digital map of the duty cycle d [n] achieved by the control loop, which is converted into a digital PWM (Pulse Width Modulation) block 303 (DPWM block) is fed. The DPWM 303 is a digital PWM with finite resolution (for example, less than the resolution of the PID device 302 and the digital mapping of the PID device 302 generated duty cycles d [n]). It modulates, based on a digital counter, the duty cycle d (t) of a square wave according to a time required for the digital counter to reach d [n]. The duty cycle d (t) becomes a power stage component 304 fed. The power stage module 304 connects a SW node 308 by means of a low impedance path (ie, switched by a switch) to a supply potential Vg when d (t) is high level and to ground (gnd) when d (t) is low level.

An output network contains an inductor 305 in line after the SW node 308 is arranged, and a capacitor 306 and an ESR 307 in series between a ground node 309 and the output voltage node 310 (by not using the SW node 308 connected connection of the inductor is formed) are connected.

According to various embodiments, white noise v (n) may be added which excites all frequencies of the output stage (ie, the stage that is the power stage 304 and the output network contains, that is, the stage, by the inductor 305 , the condenser 306 and the ESR 307 is formed). This will be in 4 illustrated.

4 shows an SMPS 400 ,

Analogous to the SPMS 300 contains the SPMS 400 an AD converter 401 , a PID module 402 , a DPWM module 403 , a performance level 404 and an output network (output filter) that has an inductor 405 , a capacitor 406 and an ESR 407 which may be arranged and designed as to how it may be 3 was declared. In addition, the SPMS contains 400 a digital processing module 408 which receives the deviation signal e [n] and one after the PID block 402 arranged addition circuit 409 , the white noise to output the PID device 402 added. A result of this addition, ie an output of the addition circuit 401 , becomes the DPWM building block 403 fed. Furthermore, in this example, it is assumed that a load resistance 410 is connected between the output voltage node and the ground node, ie parallel to the capacitor 406 and the ESR 407 ,

For example, the addition of the white noise may be done in several ways. The use of a second-order or higher-order delta-sigma (ΔΣ) modulator in a deviation feedback configuration is disclosed in U.S. Pat 5 illustrated.

5 shows an addition circuit 500 according to one embodiment.

The addition circuit 500 corresponds for example to the addition circuit 409 ,

The input signal of the addition circuit 500 is the digital duty cycle d [n], as it is from the PID module 402 is issued. The adder 501 adds the output of a 1-NTF block 502 , The 1-NTF device 502 is, for example, an HP (high pass) filter used for noise shaping.

Its input is the difference (generated by a subtractor 503 ) between the output of the adder 501 and the output of the addition circuit 500 , The output of the addition circuit 500 is the output of the adder 501 quantized by a quantizer 504 , The deviation signal qe (which is the difference between the output of the adder 501 and the output of the addition circuit 500 specified) has the characteristics of white noise.

6 illustrates the arrangements 601 . 602 for the addition of white noise.

The first arrangement 601 For example, it may be considered the part of the SPMS 400 used by the dashed box 411 is specified.

Similarly, the second arrangement 602 possibly as part of the SPMS, for example 400 used by the dashed box 411 is specified.

In the first arrangement, a ΔΣ device leads 603 that is outside the control loop of the SMPS 400 can be seen, its output (ie white noise) of an addition circuit 604 to that of the addition circuit 409 corresponds to that between a PID device 605 , according to the PID module 402 , and a DPWM device 606 , according to the DPWM module 403 , is arranged.

In the second arrangement 602 is used instead of the addition circuit 409 a ΔΣ building block 607 possibly as inside the control loop chain between a PID device 608 , according to the PID module 402 , and a DPWM device 608 , according to the DPWM module 403 , can be seen arranged. In this case, the ΔΣ block 607 Also used to calculate the effective mean resolution of the DPWM device 403 to increase.

According to various embodiments, a low noise power is added, e.g. B. from the addition circuit 409 to stimulate a loop reaction. The loop response may mainly include information about a load of the SPMS 400 that z. B. the load resistance 710 contains. In the case of a configuration where delta-sigma is within the loop in the deviation feedback (eg, as in the second arrangement 602 ), the addition of noise introduces no delays in the signal path. In this case, the noise may be switched so that it is sufficient to stimulate the load without bringing the system into an unstable state. A temporal analysis of the steady state indicates that it may be possible to achieve the Vout results despite the noise input close to Vref. By processing the output of the ADC 401 possibly load parameters are determined.

In a ΔΣ conversion form outside the loop (eg, as in the first arrangement 601 ) becomes the steady state of the SPMS 400 possibly considering the added noise as follows: Vout = 1 / N · d _DPWM where N is the relationship between the switching period (in which, for example, a power MOS transistor is driven) and a DPWM clock signal period T _SW = N * Tclk.

Considering the delta-sigma implementation in the loop (as in the second arrangement 602 ), the added noise may be amplified by decreasing the resolution of a quantizer of the ΔΣ device with respect to the DPWM resolution. The resolution of the quantizer of the ΔΣ block may be set via a parameter res_ΔΣ. In this case you can write: Vout = d _DPWM * Vin = 1 / N * (d _PID [n] + noise) * Vin

Here the parameter "Noise" can be 1-NTF [n]. It should be noted that the variance of the signal e [n] and / or dpid [n] may be much larger than the variance of the quantizer of the ΔΣ block. The PID signal (ie the output signal of the PID block 402 ) is quantized, for example, with a quantizer of ΔΣ having a lower resolution than the PID signal. The least significant bit of the ΔΣ device is quantization noise. For example, white noise is noise given by a random variable whose distribution is not zero over an interval equal to the quantization level. White noise may also be understood as a random signal with a flat (constant) spectral power density.

Both the DPWM 403 as well as the quantizer of the ΔΣ-block 603 . 607 may have the same final value range V _FS . The resolution of the ΔΣ quantizer may be 2 ^a times less than that of the DPWM. In this case, the expression for the noise can be determined as a function of the resolution difference:

Considering that the DPWM may work mainly as a one-step counter from 1 to 2 ^ N, the expression for the noise may be simplified taking into account V _FS = 2 ^ N, because: Noise = ∥2 ^a - 1∥

In that by the first arrangement 601 The noise term is simply a white noise consisting of the (output) quantizer of the ΔΣ device 603 as he is in 5 is modeled results. Providing a ΔΣ device outside the loop (as in the first arrangement 601 ) as a noise source allows the noise amplitude to be sized as desired and adjusted according to the loop parameters and DPWM resolution to account for system stability. This may have advantages because the added noise may be true white noise and no emulation, as described in the embodiments above. A PRBS sequence typically has resolution problems. Quantization noise typically results very close to the ideal white noise. As in 5 is shown, the hardware required to implement a ΔΣ device in a deviation feedback configuration may be kept small on the chip surface, and the same circuit may be used in compensation phases to increase the resolution of the system in the steady state to improve.

The through the second arrangement 602 illustrated approach uses the ΔΣ in the configuration in the loop. In this case, the noise could be calculated taking into account a lower resolution of the quantizer with respect to d _PID [n] (see 5 ) And optionally with respect to the lower resolution DPWM resolution. The term 2 ^a gives the difference between the d _PID [n] resolution and the resolution of the quantizer, which is part of the ΔΣ block 607 is.

Extending the output of the ΔΣ block 607 in the output voltage could be expressed as: V _out = 1 / N · (d _PID [n] - NTF (z) · (q _e ) + noise) · Vin = = 1 / N · (d _PID [n] - NTF (z) · (d _PID n - 1] - d _ΔΣ [n - 1]) ± | 2 ^a - 1 |) · Vin

During the loop compensation phase ^, the noise term (∥2 ^a - 1∥) is zero because the DPWM and ΔΣ devices have the same resolution in this embodiment. Under this condition, the averaged resolution of the output voltage may be improved by the ΔΣ device with a process composed of dithering, oversampling, and filtering. The filtering may be through the output filter, which forms a buck converter power output. Dithering may be considered as the noise intrusion; During an identification process, this component may be incremented by decreasing the ΔΣ resolution with respect to the resolution of the DPWM.

If, for example, noise is to be introduced, but the amplitude of the output voltage in the steady state is to be limited, a control / processing circuit (eg the state machine 910 or the processing module 908 as described below with reference to 9 the parameter a may be set to "1", resulting in: Vout = 1 / N · (d _PID [n] - NTF (z) · (d _PID [n-1] _{-d ΔΣ} [n-1]) ± 1) · Vin

The approach with a ΔΣ block in the loop also allows to influence the noise power taking into account different NTF (z) configurations. A noise shaper filter of the ΔΣ block (eg corresponding to the 1-NTF block 502 ) may have different orders (starting with the second) but could also have one or more in-band zeros. The in-band zero may be used to aggregate the noise injection. Banding noise isolation helps during parameter identification, especially during ESR detection. The noise shaper filter, for example, has a polynomial term that defines the order of the ΔΣ block. For example, a 3rd order NTF may be considered, possibly adding one or two in-band zeros. For example, a 3rd order noise shaper filter with an in-band zero is as follows: NTF (z) = (1 - z ^-1 ) · (1 - K ₁ z ^-1 + z ^-2 )

Considering f _SW as the switching frequency, f ₀ as the output resonant frequency, K ₁ results with:

Illustratively, a two-step approach may be used: first, f _{0 is} determined (eg, by a control / processing circuit) and then the ESR, and the particular ESR is looped in the control loop (eg, by the control / processing circuitry) compensated.

With K ₁ = 1, the NTF becomes a normal third order NTF without in-band zeros. In the above formula for K ₁ , the expression A represents a scaling factor that allows to set the in-band zero position with respect to the resonance frequency. Assuming the Nth order of ΔΣ, the number of in-band zeros could range from 0 to N / 2 when the order is even or to (N-1) / 2 when the order is odd. For example, a 5th order NTF could have 0 or 1 or 2 in-band zeroes, and a 6th order NTF could have 0 or 1 or 2 or 3 in-band zeros. If zero (s) are used for ESR identification, they may be spread over the frequency.

For example, in the case of three in-band zeroes, one may be placed above the resonant frequency to limit the noise overhead at that frequency and then try to excite a specified range of frequencies where higher resolution is desired. This may happen in particular when searching for the ESR contribution.

Parameter determination may be performed by the digital signal processing module 408 out 4 , After the ADC output deviation e [n] has been recorded, the digital signal processing module is executed 408 possibly algorithms for processing the timing of the output deviation e [n], including windowing, filtering and / or averaging, correlating (to reduce the noise contribution), FFT and spectral power density (PSD) analysis. It is possible that some other control / processing circuit will perform this processing instead of the digital signal processing module 408 by.

Before any algorithms for processing results in the digital signal processing module 408 downsampling and / or windowing in the time domain of the recorded (temporal recording) vector e [n].

• – Downsampling. Unter Aufnahme einer Abtastung aller N wird die maximal betrachtete Frequenz um einen Faktor von 1/N reduziert.
• – Fensterung. Zum Beispiel wird ein Blackman-Fenster w(n) in Betracht gezogen: w(n)= a₀ – a₁cos( 2πn / N-1) + a₂cos( 4πn / N-1) a₀ = 1-α / 2 ; a = 1 / 2 ; a₂ = α / 2

For example, from the digital signal processing module 408 Processing algorithms used in the time domain may include the following:

• - Downsampling. Taking a sample of all N, the maximum frequency considered is reduced by a factor of 1 / N.
• - Windowing. For example, a Blackman window w (n) is considered: w (n) = a ₀ -a ₁ cos (2πn / N-1) + a ₂ cos (4πn / N-1) a ₀ = 1-α / 2 ; a = 1/2 ; a ₂ = α / 2

The windowed result vector results as: e [n] = e [n] * w ^T [n] e [n] may or may not be down sampled.

• – Korrelation. Möglicherweise wird ein Korrelationsalgorithmus vom Digitalsignalverarbeitungsbaustein 408 sowohl zur Signalbereinigung (Vektoren im Zeitbereich und Frequenzraum) als auch zur PSD-Analyse verwendet.

Windowing in the time domain may be performed by the digital signal processing chip 408 to analyze a periodic behavior of the function in a short period of time. The fenestration in frequency space may be from the digital signal processing chip 408 is used as a bandpass filter process.

• - correlation. It may become a correlation algorithm from the digital signal processing chip 408 used both for signal pruning (vectors in the time domain and frequency domain) and for PSD analysis.

The time record e (n) could be before downsampling and / or windowing. Considering the FFT of the autocorrelated vector, the PSD may be obtained as follows:

PSD = E(k)·E*(K) The PSD could also be evaluated as a product of the deviation and its own complex conjugates:

PSD = E (k) * E * (K)

Before the FFT is applied, the digital signal processing chip leads 408 possibly downsampling and / or windowing and / or autocorrelating the temporal record. For down sampled and / or normal data records is from the digital signal processing chip 408 possibly using fenestration and autocorrelation. Each of these cases may be from the digital signal processing chip 408 in frequency domain using FFT. Each vector in frequency space is from the digital signal processing block 408 possibly filtered and / or averaged.

• – Filtern. Um einen Vektor zu bereinigen (z. B. den Vektor e[n] oder das Ergebnis der Verarbeitung dieses Vektors) filtert der Digitalsignalverarbeitungsbaustein 408 ihn möglicherweise im Frequenzraum mit einem TP(Tiefpass)-, einem HP(Hochpass)- oder einem BP(Bandpass)-Filter. Der Vektor, der gefiltert wird, ist zum Beispiel möglicherweise das Ergebnis einer FFT- oder einer PSD-Analyse. In beiden Fällen wird das Mitteln möglicherweise vom Digitalsignalverarbeitungsbaustein 408 vor oder nach dem Filtern vorgenommen. Vor dem Verarbeiten des Vektors wird er möglicherweise downgesampelt. Während der ESR-Identifizierung wird die Filterungsverarbeitung möglicherweise verwertet, indem die Grenzfrequenz gemäß der bereits geschätzten Resonanzfrequenz eingestellt wird. Vektoren, die dem Mitteln unterzogen werden, sind allesamt Datenaufzeichnungen unter Berücksichtigung des Frequenzraums, die möglicherweise vom Digitalsignalverarbeitungsbaustein 408 vor der Verarbeitung gemittelt werden.

The from the digital signal processing module 408 Processing algorithms used in the frequency domain may include the following:

• - Filter. To clean up a vector (eg, the vector e [n] or the result of processing this vector) the digital signal processing chip filters 408 it may be in frequency space with a TP (low pass), HP (high pass) or BP (bandpass) filter. For example, the vector being filtered may be the result of FFT or PSD analysis. In either case, the means may be handled by the digital signal processing module 408 made before or after filtering. It may be down sampled before processing the vector. During ESR identification, filtering processing may be exploited by adjusting the cutoff frequency according to the already estimated resonant frequency. Vectors subjected to averaging are all data records in consideration of the frequency space possibly occupied by the digital signal processing chip 408 be averaged before processing.

HP Filter: For example, a high-order first order filter may become corrupted by the digital signal processing device 408 used as follows: y (k) = A • [x (k) - x (k - 1) + y (k - 1)] with k = 1 ... n - 1

TP Filter: For example, a first-order low-pass filter may be produced by the digital signal processing device 408 used as follows: y (k) = A * [(τ / T _S ) x (k) + y (k-1)] with k = 1 ... n-1

BP Filter: Bandpass filtering may be done by mixing HP and TP filter structures.

• – Mitteln. Unter Berücksichtigung von Datenaufzeichnungen im Frequenzraum wird möglicherweise ein Prozess des Mittelns eines einzelnen Vektors (z. B. e[n] oder einer verarbeiteten Version von e[n]) oder von zwei oder mehr Vektoren verwendet. Zum Beispiel wird möglicherweise ein Vektor im Frequenzraum gemittelt. Dies erfolgt möglicherweise zum Beispiel vor dem Filtern.

The T _S factor is related to the downsampling factor. The data is at the switching frequency f _{SW of} the system (eg the SPMS 400 ). If the data record has been downsampled by a factor N, T _{S is} equal to N / f _SW . Otherwise it is equal to 1 / f _SW . The factor τ is related to the cutoff frequency chosen for the processing filter, it is equal to 1 / (ω _c ), where ω _{c is} the cutoff frequency. For both considered filters, the term A is: A = (τ / T _S ) / (1 + τ / T _S )

• - funds. Considering data records in frequency space, a process of averaging a single vector (e.g., e [n] or a processed version of e [n]) or two or more vectors may be used. For example, a vector may be averaged in frequency space. For example, this may be done before filtering.

The above with reference to 4 The approach described deals with the identification by adding noise. The control loop resolution is lowered to stimulate the load for many frequencies. The loop response includes the load frequency information, and the processing of the timing of the load parameters may be determined by signal processing. The system (ie the SMPS 400 ) does not need to be brought into a particular state associated with the identification. In both cases, the digital loop may retain the same configuration as during normal operation. For example, in one embodiment, only the loop resolution may be changed to excite the load, ie, other components and parameters may remain unchanged.

Further, according to the above approaches, the system need not be brought near unstable states. Furthermore, the PID controller 402 also used during identification. During this phase, the PID coefficient could be mitigated (eg by a control / processing circuit). After the parameter identification, it may be tuned to obtain a desired control state.

It should be noted that resolution problems in a non-parametric identification approach, such as based on the PRBS (considered non-parametric, all approaches attempting to detect each impulse response of the system) typically do not allow for the possible presence of the zero introduced by the ESR to identify.

In particular, according to the approaches described above, the ESR may be identified by autocorrelation by working with PSD analysis processing the deviation vector e [n] (which could be downsampled and / or windowed). The recovered vector typically exhibits a second peak (where the first peak corresponds to the resonant frequency).

The averaging and / or filtering of temporal data records in frequency space helps to clean up the signal for parameter determination. The results of this further processing may be useful during the identification of the ESR. After the resonance frequency, the gain of the system may rapidly decrease in frequency, so that the ESR contribution could be very difficult to detect. In this case, an NTF may be used with in-band zeros (which focus the introduction of noise in the frequency range of interest) associated with numerical filtering and / or averaging to clean up the signal in frequency space. The resolution of the data processing may be improved out of the time domain, taking into account processing algorithms for downsampling, windowing and / or autocorrelation.

Also, directly processing the data record e [n] with an FFT result could result in a high value of the ESR from the digital signal processing chip 408 be identified. The resolution of the results could be improved taking into account the averaging and / or filtering of frequency vectors.

Another consideration with respect to ESR detection is that after the resonant frequency is known, the ΔΣ configuration is controlled by a control / processing circuit (eg, the digital signal processing device 408 ) can be adjusted to filter out the resonant frequency where and emphasize the ESR frequency range. The NTF of the ΔΣ block can be adjusted by a control / processing circuit that adds approximately where or where one or more zeros. In this case, a two-step approach may be used. First, the zero ΔΣ building block is used where to find where, as previously described. Then, in a second stage, the ΔΣ block is modified by adding zeroes at about where.

Another level that can be added or used instead of the second part to find ESR influence is the analysis of spectral power, which increases with bandwidth.

For a signal x [n] the spectral power is defined as: E (ω) = X (ω) · X * (ω).

That is, by computing by means of signal processing the spectral power of e [n] for a given system, it is possible to evaluate and calculate the bandwidth. In case the ESR zero frequency is close to where, the bandwidth increases. This can be found out about the spectral power, and this information can be used to adjust the system compensation coefficient.

Another level that can be added or that from the digital signal processing block 408 can be used to find out where is the following: During startup of the system, the Vout must reach the final setting voltage. If the reference voltage is increased stepwise, the response of the output voltage Vout includes the frequency information of the output filter.

7 shows a voltage curve image 700 ,

The voltage curve image 700 illustrates the output voltage over time in a first curve 701 when the reference voltage (shown in the second curve 702 ) in several stages 703 elevated. In the voltage curve image 700 the voltage increases from bottom to top along a voltage axis 704 and the time runs from left to right along a time axis 705 ,

The output voltage Vout, which results in this case, can be processed, for. B. from the digital signal processing module 408 (eg, similar to what has been described above for white noise excitation) and where can be identified. In this case, the determination may be based on the system's step response. The step response is strictly related to the impulse response of the system: By deriving the step response (Y (z)), the impulse response (G (z)) may be obtained: G (z) = ((z-1) / z) * Y (z)

For example, this approach is used only during startup. For example, it may be used by a control / processing circuit as a first estimate and, finally, the other approaches described above may be used to also discover the ESR and track system changes during system run time (ie in the case of low temperatures increase by 1-2 orders of magnitude for some ESR capacitor types).

• 1. Weißes Rauschen wird aufgeschaltet, indem es zum d[n]-Wert addiert wird.
• 2. Das Rauschen wird im normalen Betrieb und bei geschlossener Regelschleife aufgeschaltet, ohne das Frequenzverhalten des geschlossenen Regelschleifensystems zu ändern.
• 3. ΔΣ wird verwendet, um Rauschen gemäß der ersten Anordnung 601 oder der zweiten Anordnung 602 zu erzeugen.
• 4. Gemäß der zweiten Anordnung wird die ΔΣ-Auflösung verringert, um die Rauschamplitude zu erhöhen.
• 5. ΔΣ einer Ordnung > 2 wird verwendet, um die Nullstellen etwa bei wo zu platzieren und die Frequenz um die ESR-Nullstellenfrequenz hervorzuheben.
• 6. Das oben Genannte (Punkte 1 bis 5) wird kombiniert, und durch Anwenden von Signalverarbeitung auf den gespeicherten e[n]-Vektor werden wo und/oder die ESR-Nullstellenfrequenz ermittelt, und diese Informationen werden verwendet, um den PID-Koeffizienten anzupassen.
• 7. Das oben Genannte (Punkte 1 bis 5) wird kombiniert, und durch Anwenden von Signalverarbeitung auf den gespeicherten e[n]-Vektor wird die spektrale Leistungsdichte berechnet, und die Schleifengrenzfrequenz und die ESR-Nullstelleneffekt werden geschätzt.
• 8. Beim Anlauf wird die Referenzspannung stufenweise erhöht, und die e[n]-Sprungantwort wird analysiert.
• 9. Punkt 8 wird mit allen oder einem Teil der Punkte 1 bis 4 kombiniert.

In one embodiment, one or more of the following is summarized:

• 1. White noise is switched on by adding it to the d [n] value.
• 2. The noise is switched on in normal operation and with the control loop closed, without changing the frequency response of the closed loop control system.
• 3. ΔΣ is used to generate noise according to the first arrangement 601 or the second arrangement 602 to create.
• 4. According to the second arrangement, the ΔΣ resolution is reduced to increase the noise amplitude.
• 5. ΔΣ of order> 2 is used to place the zeroes at about where and highlight the frequency around the ESR zero frequency.
• 6. The above (points 1 to 5) is combined, and by applying signal processing to the stored e [n] vector, where and / or the ESR zero frequency are determined, and this information is used to obtain the PID coefficient adapt.
• 7. The above (items 1 to 5) is combined, and by applying signal processing to the stored e [n] vector, the spectral power density is calculated, and the loop cutoff frequency and the ESR nulling effect are estimated.
• 8. At startup, the reference voltage is incrementally increased and the e [n] jump response is analyzed.
• 9. Point 8 is combined with all or part of points 1 to 4.

According to various embodiments, approaches may be considered that may be primarily considered to contain some sort of parametric identification process because they focus on determining load characteristics such as resonant frequency, ESR, and bandwidth. When a low noise power is applied, the system results are far from instable and load frequencies are more stimulated. The output filter response could be determined from the deviation affected by the digital control loop: the added noise could be considered close to ideal white noise.

The DPWM could be considered as a truncation function. In the absence of a ΔΣ block, this noise may be added within the control loop. This type of noise may be related to LSB truncation. It may be very close to the resonant frequency and cause ring oscillation, the amplitude of which is normally greater the closer its frequency results are to the resonant frequency. In a digital control loop, the ΔΣ (with the same resolution as the DPWM) typically oversubssteps this deviation because the ring oscillation frequency is necessarily less than the frequency at which the deviation is processed (which is the switching frequency). This process typically causes the LSB (least significant bit) truncation to not always be the same on average. Thus, ring oscillation has a different frequency component.

When a noise source is introduced, the LSB truncation becomes random, stimulating a wide range of load frequencies in the AD converter output of the AD converter 401 become visible. By definition, the white noise encompasses all frequencies, so it is able to stimulate the load. The ADC output is simply a digital conversion of the output filter scaled by the reference voltage Vref: e [n] = Vout [n] - Vref [n] → temporal data recording

The applied noise power may be chosen so that it is not too large so that it does not bring the system into special states that are far from normal behavior and close to the unstable state of the loop. The loop configuration and the main behavior remain similar to a normal control runtime. The added noise increases the output noise.

The approaches described above do not break the loop by adding any delay to the signal path. It may use the same hardware that could be used to improve the average resolution while working in the steady state.

In the digital loop used in accordance with one embodiment as described with reference to FIG 6 is described, the added noise is represented as a summing node. This source of the noise node is a ΔΣ device (the two configurations of the first device 601 and the second arrangement 602 possible), which could also be utilized after the identification process to improve the temporal resolution of the loop.

When working with a ΔΣ model in the loop (as determined by the second arrangement 602 illustrated), the same loop may be used during both identification and fine-tuning control. To use the ΔΣ in the loop as a noise source, the resolution may be adjusted: The resolution of the ΔΣ quantizer may be reduced compared to that of the DPWM. This further LSB truncation allows stimulation of the range of stimulated frequencies.

Embodiments may be considered to also focus on the identification of non-ideals that could affect the stability of the system. The most important non-ideal phenomenon is the equivalent series resistance (ESR), which adds a zero in the closed-loop transfer function. This problem of another zero is related to its position: the frequency response of the system could change dramatically if it turns out to be close to or even within the bandwidth of the system. The ESR may be easily determined from the PSD (often there are two peaks in the PSD, the higher at about the resonant frequency and the second in relation to the zero introduced).

In a two-step approach, noise injection may be focused first on the frequencies before and secondly on the frequencies behind the resonance frequency. The switched noise can be controlled by affecting the NTF: The noise transfer function (NTF) can simply be a high pass filtering of noise (noise shaping), possibly based on both the order and structure of the NTF. Based on the order of the NTF means on the basis of the trade-off between the noise power, at low, and the noise power, which is switched on at medium high frequencies. On the basis of the NTF structure, it means that it is possible to add some in-band zeros in order to avoid introducing noises at particular frequencies (increasing the number of zeros also increases the order of the NTF).

In PSD analysis, there is a peak related to the resonance frequency. For example, if a third-order NTF is modified with the addition of a zero very close to the resonance frequencies, it can excite the relative peak due to the ESR nulling effect. A two-step approach may be used because the position of the second zero is related to the resonant frequency, which is usually the major contributor, and because it can obscure the ESR contribution.

The parameter determination may be performed by the recorded ADC deviation output signal processing algorithms, which is simply a digitized expression of the scaled output voltage Vout. According to various embodiments, the signal processing process is primarily related to PSD analysis. Before the FFT, an autocorrelation of the time recording may be performed. The autocorrelated timing could take place before being downsampled and / or windowed to reduce the high frequency content and reduce the signal processing hardware. In order to obtain lower-noise results after the FFT, it is possible to correct the signal resulting from the FFT by averaging and / or filtering. The parameter determination may be simple and may simply be based on searching for the absolute and / or relative maxima in the processed data: Normally, considering the PSD and / or FFT (averaged and / or filtered in frequency space, the time domain is windowed and / or downsampled), the resonant frequency may be determined as the absolute maximum and, if present, the position of the ESR frequency as the second peak.

After parameter discovery, the PID parameters may be adjusted to produce a well-controlled system that complies with closed loop (bandwidth and phase margin) constraints.

Ripple-based approaches may be combined with a start-up identification method. The reference voltage (Vref) should be the voltage level required at the output of the SMPS. If a reference voltage having a stepwise development is considered, the digitized system hop response may be recorded by recording the AD converter output becomes. The step response is mathematically linked to the impulse response of the system. By processing the AD converter output as described above, the resonance frequency (maximum of the FFT and / or the PSD) and finally the ESR (as a second peak) may be determined. Also, this approach does not modify the digital control loop, and it could be considered to work during a normal runtime: A stepwise evolving Vref is a realistic behavior during soft start of the system.

The approach according to various embodiments is in 8th illustrated.

8th shows a state diagram 800 of a system, e.g. For a SMPS, or a controlling state machine for a SMPS (such as the one described in U.S. Patent Nos. 4,974,855, 5,866,807, 5,848,846, 5,872,846, 5,872,846, 5,872,846, 5,872,846, 5,872,842, 5,872,842, 5,872,842, 5,801,842, etc. 9 illustrated state machine 910 ).

In the state diagram 800 represents a state (or condition) IDLE 801 the state in which the system parameters (PID default parameters, NTF order and resolution of the ΔΣ quantizer) and the options of the identification algorithm (ΔΣ in the loop or ΔΣ out of loop, identification process at start-up by a stepwise development of the reference voltage ) have settled.

In the case that the identification process is based on the presence of a ΔΣ in the loop as a noise source (as in the second arrangement 602 ), the signal res_ΔΣ (which indicates the resolution of the DPWM) assumes a value equal to the DPWM resolution minus one.

When the system is turned on, it goes from the IDLE state 801 in the state START-UP 802 above. This state is the first one to consider options for the algorithm: If it decides to apply the identification process already during the startup of the system (as described above with respect to the step response coming from the stepwise evolving reference voltage) the system with a WAIT-STEP 803 further. Otherwise, the system may transition to a WAIT-SS (Steady State) state if it decides that the identification process will be implemented so that it will only be executed during the steady state.

Taking into account an identification process combining steady-state analysis and start-up, the actual state of the system is the WAIT-STEP state 803 , When the reference voltage stage starts, the next state is an ADC-REC-SU (SU means start-up, start-up) 805 , Here, the AD converter output (deviation signal) is recorded. At the end of the stage, recorded data can be processed. This operation is by a DATA-PRO state 806 shown. While the system is running with the default configuration, all necessary data processing algorithms are applied by the system in this state. When the processing algorithm ends, the first load parameter determination is available, which is in a state PARAM-ID 807 is made. The system mainly determines the absolute and relative maxima of the data record just processed in this state. The value of the resonance frequency resulting from an identification in the startup process may be trusted in this state and it will be used as a basis. The ESR value could be determined during the first adjustment of the control parameters (PID), but not taken into account.

After the parameter determination, the system runs in a PID-COMP state 808 , In this state, the PID parameters (Ki, Kp, Kd, and Kgain) are set in accordance with both the just-determined load parameters and the closed-loop conditions that should be achieved after a successful control process.

If it is decided that the identification process to be performed is to be implemented only during the steady state of the system, the system may run after the START-UP state 802 in the state WAIT-SS 804 in which the system waits until the end of the startup. If startup is considered complete, the ADC output will include steady state deviation. After the state WAIT-SS 804 the system goes into a state ADFC-REC-SS 809 in which the deviation is recorded. In this state, different down-sampled data records of equal length may be recorded to evaluate multi-averaged results. When data recording is finished, the same routine as described above is performed: Processing (DATA-PRO state 806 ), Load parameter determination (state PARAM-ID 807 ) and PID control (state PID-COMP 808 ).

The above describes the first identification loop, which considers either identification at start-up or identification in the steady state.

In summary, in the case of identification at start-up, this first identification loop is composed of the following states:
IDLE → START-UP → WAIT-STEP → ADC-REC-SU → DATA-PRO → PARAM-ID → PID-COMP

The first identification loop in the case of identification in the steady state (then in the case of lack of the identification process at startup) consists of these states:
IDLE → START-UP → WAIT-SS → ADC-REC-SS → DATA-PRO → PARAM-ID → PID-COMP.

Each time new data is recorded, it is processed in the normal sequence of states (DATA-PRO → PARAM-ID → PID-COMP). In the steady state, a state loop may be introduced, which could be called the monitoring loop, to evaluate any load quality degradation and calculate the compensated PID coefficients. This sequence could be repeated because load parameter identification is needed. If no monitoring loop is needed, the state of PID-COMP goes to a NORM-RUN state 810 (in which normal operation is performed) because no further data needs to be recorded.

The last possible transition from the PID-COMP state 808 is directly in the state NTF 811 , Considering that the ΔΣ configuration is in the loop (that is, the entire identification process has been done using the ΔΣ configuration in the loop, or that the configuration of ΔΣ out of the loop switches to ΔΣ within the loop, if this Part of the algorithm), it is possible to manipulate the structure of the ΔΣ-NTF to possibly extrapolate or emphasize the ESR effect. In the case that the ESR zeroes occur during previous identification runs (that occur without any modification of the NTF structure that is in the IDLE state 801 or identifying that no further in-band zeros are added, the algorithm provides the capability of modifying the NTF structure. Modifying the NTF structure means changing the order by adding zeros in the noise shaping function. Because the ESR nulling is done by determining a relative maximum, the contribution of the absolute maximum given by the resonant frequency may be suppressed or reduced. It is possible to add one or more zeros in the NTF that are very close to the LC resonance frequency. In this way, the switched noise may be channeled in the range of frequencies greater than the LC resonant frequency. Because in this algorithm the zero position in the NTF noise shaping function is related to the resonance frequency, in this case the algorithm needs a previous stage for the identification of the LC. Therefore, the transition PID-COMP → NTF → ADC-REC-SS after a identification process in the steady state, which allows both the determination of the resonance frequency and the singling of the ESR zero contribution.

Thus, every time the system is in the PID-COMP state 808 during the steady state, it is possible to change the NTF structure by adding in-band zeros (setting the signal zero_loc in 9 ) to excite the frequencies following the resonant frequency.

9 shows an SMPS 900 ,

Analogous to the SPMS 400 contains the SPMS 900 an AD converter 901 , a PID module 902 , a DPWM module 903 , a performance level 904 , an output network (output filter) that has an inductor 905 , a capacitor 906 and an ESR 907 contains, and a digital processing block 908 , The SMPS 900 contains a ΔΣ block in the loop as in the second arrangement 602 , The referring to 8th states described may be due to a state machine 910 triggered, possibly the results of the digital processing block 908 receives. The reference voltage in this example is from a reference voltage source 911 which may increase the reference voltage gradually. In addition, it is assumed in this example that a load transistor 912 is connected between the output voltage node and the ground node.

• – C Lastfilter-Kapazität und ihr ESR, zum Beispiel die Haupt-Filterkapazität, und parallel ein kleiner Lastkondensator CL = C/1000.
• – L = Filterinduktor, ω₀ = 1/(LC) ist wenigstens 2 Ordnungen niedriger als 2π·*f_SW.
• – Vg Eingangsspannung der Leistungsstufe, wobei sich die Leistungsstufe aus Treiber und Umschaltern zusammensetzt.
• – Vref = Soll-Vout, d. h. 3,3 V, sie ist der Eingang des AD-Wandlers.
• – Fck = schnelles digitales Taktsignal und DPWM-Basiszähler
• – DPWM ist der digitale PWM, er weist eine Auflösung von DPWM_res = 6 Bit auf (Zähler von 1 bis 2^6 = 64, er bestimmt die f_SW)
• – ΔΣ, wie unter Bezugnahme auf 5 beschrieben wurde. Die Auflösung kann gleich der DPWM sein oder sie kann während des Identifizierungsprozesses um 1 verringert werden (DPWM_res-1). Die ΔΣ-Auflösung wird durch das Signal res_ΔΣ abgestimmt. Hier ist sie während der Identifizierung gleich DPWM_res-1 und, während die volle Auflösung läuft, gleich mit DPWM_res. Das zero_loc des ΔΣ-Eingangs, das eventuell während der ESR-Identifizierung benötigt wird, umfasst die Soll-Nullstellenposition für die NTF. Das Signal zero_loc ist wie ein Vektor mit einem 4 Nullstellenwert für die ΔΣ-Nullstellen.
• – PID ist der Digitalfilter mit den Parametern Kp, Kd, Ki, Kgain.

In this example, the digital loop is dimensioned for the following parameters:

• C load filter capacitance and its ESR, for example the main filter capacitance, and in parallel a small load capacitor CL = C / 1000.
• - L = filter inductor, ω ₀ = 1 / (LC) is at least 2 orders lower than 2π * * f _SW .
• - Vg input voltage of the power stage, where the power stage consists of drivers and switches.
• - Vref = target Vout, ie 3.3V, it is the input of the AD converter.
• Fck = fast digital clock signal and DPWM base counter
• - DPWM is the digital PWM, it has a resolution of DPWM_res = 6 bits (counter from 1 to 2 ^ 6 = 64, it determines the f _SW )
• - ΔΣ, as with reference to 5 has been described. The resolution may be equal to the DPWM or it may be decreased by 1 during the identification process (DPWM_res-1). The ΔΣ resolution is tuned by the signal res_ΔΣ. Here it is equal to DPWM_res-1 during identification and, while the full resolution is running, equal to DPWM_res. The zero_loc of the ΔΣ input that may be needed during ESR identification includes the target zero position for the NTF. The signal zero_loc is like a vector with a 4 zero value for the ΔΣ zeros.
• - PID is the digital filter with the parameters Kp, Kd, Ki, Kgain.

Taking these parameters into account, the resonance frequency in this example is ω ₀ = 2π × 5 kHz and the ESR zero frequency ω _ESR = 2π × 14 kHz. The following describes results that account for some signal processing procedures used to obtain a reliable identification process. The description focuses mainly on the identification process, without considering the results under the scheme. All results are based on the same configuration values (including the PID coefficients).

Taking into account the identification process at startup, with reference to the with reference to 8th states described, the state machine is running 910 through the state sequence:
IDLE → START-UP → WAIT-STEP → ADC-REC-SU → DATA-PRO → PARAM-ID → PID-COMP
(Results of the parameter identification are presented, for example, in the stage PARAM-ID, eg a user).

Because the steady-state identification process is done by adding noise, time-domain results are also shown to show that our system is not disturbed too much.

During the status START-UP 802 the system evolves by inputting a stepwise reference voltage, as in 7 is illustrated, to be considered. During the development of the reference voltage the algorithm waits (ie the state machine 910 ) to the voltage level (in the state WAIT-STEP 803 ) to start recording the ADC output (ADC-REC-SU state 805 ). The WAIT-STEP 803 may be important because there may be multiple levels and it might be decided to record the output on only one of them. In addition, to record each response of the system, a longer level may be selected, and the other levels could be shorter.

In WAIT-STEP 803 the state machine decides 910 to wait for the third stage to activate the ADC output record. In this example, the state machine decides 910 to stop recording when the fourth stage comes. The algorithm then proceeds to data processing (state DATA-PRO 806 ).

10 shows PSD results considering ω _ESR = 0 (no in-band zeros).

As in the example in 10 is shown, the resonance frequency may be determined from the start-up phase. Considering a stepwise evolution of Vref and, for example, determining the maximum of the PSD (or FFT), the LC contributions of the output filter may be determined.

In this approach, the presence of the second peak may not be easy to obtain for ESR detection.

After processing results have been calculated, the state machine moves 910 the system enters the state of the parameter determination (state PARAM-ID 1107 ) in which it seeks and determines absolute and / or relative maxima to define the correct PID parameters needed for the correction (the correction is not shown here).

The steady state identification process involves the state machine 910 by the following sequence of states as described with reference to 8th is described:
IDLE → START-UP → WAIT-SS → ADC-REC-SS → DATA-PRO → PARAM-ID → PID-COMP
(Results may be presented in the PARAM-ID stage)

After startup, the steady state (state WAIT-SS 804 ) reached. Then the system starts to record the ADC output (state ADC-REC-SS 809 ).

As mentioned above, the case is evaluated in which the noise is switched by reducing the resolution of the ΔΣ in the loop using the signal res_ΔΣ.

11A illustrates the steady state, taking into account ΔΣ and DPWM with the same resolution.

11B Fig. 10 illustrates the case where the noise source is a ΔΣ modulator in the loop (with respect to the SMPS 900 out 9 with ΔΣ_res = DPWM_res-1).

11A and 11B show the corresponding output voltage of the SMPS over time.

In 11B the case of a noise applied by a 5-bit ΔΣ quantizer is considered. In 11A Both the DPWM and ΔΣ have 6-bit quantizer resolutions. As well in 11A as well as in 11B As can be seen, since noise is applied to a large range of load frequencies, these frequencies are filtered out by an LC filter which forms a buck converter. By analyzing the digitized deviation coming from the ADC, load parameters may be determined.

After recording the ADC output in steady state (in this case, only one time record is made, but possibly multiple records are taken to perform multiple averaging processing), the state machine computes 910 the processing results in the DATA-PRO state 806 , When processing is finished, the state machine is running 910 in the state PARAM-ID 807 in which load parameters are determined by the normal search for absolute (resonant frequency) and relative maxima (ESR contribution).

12 shows PSD results in two curves 1201 . 1202 considering a ΔΣ noise source in the loop. The two curves 1201 . 1202 differ from each other because ESR posts in the upper curve 1201 are not considered (there is only the absolute maximum, which refers to the resonance frequency, in the lower curve 1202 the additional relative maximum refers to the ESR).

From the in 12 It can be seen that it is possible to evaluate ESR effects taking into account the relative maximum in the PSD.

Furthermore, it is possible to stimulate the ESR effects in terms of the resonant frequency effects (absolute maximum) by processing the noise input. In this case, the two external inputs of the ΔΣ device have this possible configuration: -zero_loc = [0.9 0 0 0]. That is, a zero is added at 90% of the resonant frequency. This confirms that the approach may be composed of two stages: It may be necessary to know the resonant frequency in order to place the NTF null (s) near it. Previously, at least one of the following may be used: an identification process at start-up and / or in the steady state. It may be useful to have an identification stage in advance to detect and / or singulate the in-band ESR, and then it is possible to have a second stage ESR situation (in which the NTF term is modified ) to be sure.

13 Figure 11 illustrates the result of modifying a third-order NTF to add an in-band zero near the resonant frequency (Z1 = 0.9 x f ₀ ). A first turn 1301 (ESR contribution) shows a difference between the absolute and the relative maximum, which is lower than in 12 is where no in-band zeros have been introduced. A second turn 1302 corresponds to the case without ESR contributions.

If the resonant frequency and the ESR position are known, the expected idle bandwidth of the system may be determined.

Then, the timing may be processed to determine the resonant frequency, and in a second stage, the NTF may be modified by adding one or more in-band zeros to determine the ESR null. There may be two stages used to place the in-band zeros into a position related to the resonant frequency. In any case, it can be seen in the PSD analysis that the ESR could also be extrapolated without any modification of the NTF structure: modifying the NTF results in a process used to validate and / or singulate minimum ESR contributions could. Averaging and / or filtering processing functions, both in combination with downsampling and windowing, could arouse these effects to have truly reliable, determined data.

In the following, conventional approaches for determining parameters of external components, such as an output network, will be described.

14 shows an example of a typical SMPS converter 1400 in a down converter configuration. The converter 1400 is a voltage regulator that regulates an output voltage Vout.

The SMPS converter 1400 contains an input voltage source 1401 , whose plus output via a field effect transistor 1402 with an inductor 1403 is interconnected. The field effect transistor 1402 includes a gate. The cathode of a diode 1404 is between the field effect transistor 1402 and the inductor 1403 connected. The anode of the diode 1404 is with the minus output of the input voltage source 1401 (this is eg a ground connection). The inductor 1403 lies between the cathode of the diode 1404 and the connection node of a load 1405 , The other connection node for the load is the anode of the diode 1404 , The voltage across the load 1405 is the output voltage Vout. A capacitor 1406 is parallel to the load 1405 , The output voltage Vout becomes a multiplier 1407 fed, which generates a multiplied output voltage. The multiplied output voltage becomes a regulator 1408 fed, which is a subtractor 1409 which determines a difference e (t) between the multiplied output voltage and a reference voltage Vref. This difference (deviation signal) may become an error amplifier and compensator 1410 fed to a pulse width modulator 1411 fixes a driver 1412 regulates the voltage of the gate of the field effect transistor 1402 and thus regulates the output voltage.

The inductor 1403 and the capacitor 1406 are for the SMPS converter 1400 external components. The transistor 1402 is a reference switch. The system regulates Vout based on the voltage Vref. The output network (including the inductor 1403 and the capacitor 1406 ) creates a pair of complex poles. The regulator 1408 is designed to maintain loop stability and high open loop gain of the system to increase the accuracy of Vout.

The regulator 1408 generates a low frequency pole and two zeros to achieve the desired loop transfer function.

A variation of the inductor 1403 , the capacitor 1406 or the equivalent series resistance (ESR, in 14 not shown) the system could become unstable. The regulator 1408 should be able to take these fluctuations into account. To do so, it may be interpreted in a conservative manner, that is, in a safe manner that makes it robust to instability. If the regulator 1408 however, in this way, the dynamic performance of the system loop (ie the load step response) may be too low and may not meet system requirements.

A parameter drift in the power stage, such as a fluctuation in the inductor 1403 , at the condenser 1406 or other components, can be mitigated by off-line recalibration of the controller to meet target dynamic performance specifications. These techniques are often called auto-tuning or self-tuning. Typically, it may be desirable to identify an external component (eg, an inductor and / or a capacitor) or the output power filter frequency characteristics (poles and zeros). Such methods may require complex numerical computations, for this reason they are suitable for digitized systems and for advanced silicon technologies that enable high chip integration, so that a small chip area is required to provide the computational resources for the computations (e.g. B. may require a complex calculation on a small area of silicon).

In the following there will be described two typical conventional approaches to a SMPS (switched mode power supply) which is implemented with an external filter (eg implemented by both an inductor and a capacitor, such as the inductor 1403 and the capacitor 1406 , illustrated in 14 ), which is outside the SMPS, which introduces a few complex conjugate poles.

The first approach is based on evoked control loop vibrations caused by introducing both a relay and an integrator into the control loop. This will be in 15 illustrated.

15 shows a control loop 1501 ,

The control loop 1501 contains a subtractor 1505 which is adapted to generate the signal of the difference between a reference signal yref (eg, a reference voltage) and an output signal y (eg, an output voltage). A relay 1506 generates a control signal u from the difference signal e. The relay (eg a self-holding relay) 1506 is used in this example to provide hysteresis. The control signal u has according to the regulated system 1507 the output voltage y result. 15B shows a signal curve 1502 of the output signal y of the control loop 15A ,

The signal curve 1502 shows the evoked vibrations of the output signal y over time.

15C shows a signal curve 1503 the manipulated variable u of the control loop off 15A ,

The second signal curve 1503 shows the control signal u (manipulated variable), ie the output of the relay 1506 , over time.

A user may use both the frequency and / or amplitude of the vibrations to identify system characteristics and, in particular, the load. For example, a user may cause the system to vibrate with appropriate excitation. The relay 1506 introduces a nonlinearity.

15D shows a Nyquist diagram 1504 for the control loop off 15A ,

The Nyquist diagram 1504 shows a graph 1505 of G (jω) (ie the function that the regulated system 1507 in frequency space) of the control loop 15A , The graph 1505 is mainly characterized by a real part with a phase of -180 ° (the imaginary part could be considered negligible because it is related to the small delay introduced by the relay hysteresis). When the loop is closed, the system oscillates at a frequency caused by the overlap of the graph 1505 with the characterizing function of the relay curve 1506 is given. This means that it oscillates at a frequency where the phase is -180 °, because in this case the feedback signal amplifies the input signal.

16 shows a graph 1600 that has an amplitude (shown as a solid line 1604 , relative to a first axis 1601 ) and a phase (shown as a dashed line 1605 , relative to a second axis 1602 ) of G (jω) as a function of the frequency (given by a third axis 1603 ) shows.

In this example, G (jω) is composed of a low-frequency pole (integrator) and the complex poles of an output power network (including the inductor L and the capacitor C, eg similar to the inductor 1403 and the capacitor 1406 , illustrated in 14 ) of the regulated system 1507 together. The regulated system 1507 oscillates at the frequency f _{0 of} the complex poles, as through the peak 1608 will be shown. This frequency can be determined and determined from the processing of the relay output.

The relay 1506 may be replaced by a component that provides a special phenomenon caused in a digital loop, known as Limit Cycle Oscillation (LCO). A pulse width modulator PWM of the controlled system 1507 in this case may be implemented by a digital counter. In the event that the regulated system 1507 If there is an AD converter connected to the PWM, it may happen that the resolution of the duty cycle generated by the PWM is too coarse and that the deviation related to the output voltage (ie, the output signal y in this example) is can not be mapped in the zero error class division of the AD converter (analog-to-digital converter). In this case, the output voltage may oscillate between ± 1 LSB (least significant bit) of the ADC. The oscillation frequency of this oscillation typically correlates with the complex pole frequency of LC.

In the (first) approach mentioned above, effects of non-idealities, such as ESR contributions, are not taken into account. Large ESRs typically affect the identification process, possibly leading to erroneous results. The bandwidth of the control loop may still be in use 1501 reduces and the dynamic performance of the control loop may be reduced. One in the control loop 1501 introduced vibration (usually low frequency) could interfere with other sensitive devices.

According to a second approach, a multi-period pseudorandom binary sequence (PRBS) is introduced which can be considered as a digital emulation of white noise. The response of a system, such as a closed-loop SMPS, to ideal white noise is related to the system's impulse response. Frequency space analysis of the impulse response may include all the frequency information needed to characterize the system. System parameters can be determined by signal processing.

However, PRBS is typically not exactly ideal white noise. A spectrum obtained by a PRBS is very noisy, mainly at medium frequencies. Thus, results of determining the parameters of the system may be compromised, resulting in erroneous identification. For example, it may not be possible to evaluate the ESR contribution.

While the invention has been particularly shown and described with respect to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims , The scope of the invention is, therefore, indicated by the appended claims, and it is therefore intended that all changes which have the same meaning as the claims come within a scope of the same meaning as the claims.

Claims (24)

Converter circuit comprising: a switch circuit configured to provide an output voltage to a load; a control circuit comprising an analog control portion and a digital control portion; a noise generator configured to generate white noise; wherein the noise generator is adapted to supply the generated white noise to the digital control portion of the control circuit; and wherein the control circuit is configured to control the switch circuit based on white noise. The converter circuit of claim 1, wherein the control circuit is configured to control the switch circuit based on the white noise to determine at least one property of at least one of: the load or the converter circuit. Converter circuit according to claim 2, wherein the control circuit is further configured to determine one or more elements of a group consisting of: an inductance of an inductor; a capacitance of a capacitor; an equivalent series resistance of a capacitor; and an electrical property of the load. Converter circuit according to one of claims 1 to 3, wherein the control circuit is configured to regulate the switch circuit to provide the output voltage based on a duty cycle; and wherein the control circuit is adapted to control the switch circuit based on the white noise by adding the generated white noise to the duty cycle. Converter circuit according to one of claims 1 to 4, wherein the control circuit comprises: an analog-to-digital converter configured to receive a reading of the output voltage and to provide a digital value indicative of the recorded reading of the output voltage. Converter circuit according to claim 5, wherein the analog-to-digital converter is further configured to compare the received measured value of the output voltage with a reference voltage; and generate a deviation signal representative of a difference between the recorded measured value of the output voltage and the reference voltage. The converter circuit of claim 6, wherein the control circuit is configured to add the generated white noise to the deviation signal. Converter circuit according to claim 6 or 7, wherein the control circuit is adapted to increase the reference voltage sequentially. The converter circuit of claim 6, wherein the control circuit further comprises a proportional-integral derivative (PID) controller configured to receive the deviation signal and generate a PID output based on the received deviation signal. The converter circuit of claim 9, wherein the control circuit is further configured to add the generated white noise to the PID output. The converter circuit of claim 9, wherein the control circuit further comprises a pulse width modulation controller configured to receive the PID output and to generate a pulse width modulated control signal configured to regulate a power stage to provide the output voltage to the load. A converter circuit according to any one of claims 1 to 11, wherein the noise generator is adapted to generate the white noise using a sigma-delta converter. The converter circuit of claim 12, wherein the noise generator is further configured to reduce a resolution of the sigma-delta converter to increase an amplitude of the generated white noise. A converter circuit according to claim 12 or 13, wherein the sigma-delta converter includes more than one feedback loop; and wherein at least one zero of the sigma-delta converter is located near the resonance frequency of the load. Converter circuit according to one of claims 12 to 14, wherein the control circuit further comprises: An analog-to-digital (AD) converter designed to: take a reading of an output voltage at the load; compare the recorded measured value of the output voltage with a reference voltage; and generate a deviation signal representing a difference between the recorded measured value of the output voltage and the reference voltage; and wherein the control circuit is configured to: process the deviation signal to determine one or more of: the cutoff frequency of the control circuit or an equivalent series resistance of a capacitor. Converter circuit according to claim 15, wherein the control circuit is further configured to process the deviation signal to determine a spectral power density, and wherein the control circuit is preferably further configured to determine one or more of the following based on the determined spectral power density: a loop cutoff frequency of the control circuit or an equivalent series resistance of a capacitor. The converter circuit of claim 15, wherein the control circuit is further configured to adjust at least one coefficient of a PID controller configured to receive the deviation signal and generate a PID output based on one or more of: the determined loop cutoff frequency the control circuit or the specific equivalent series resistance of a capacitor. A method of converting an input voltage to an output voltage, the method comprising: the generation of white noise; supplying the generated white noise to a digital control portion of a control circuit; and controlling a switch circuit based on white noise to provide the output voltage. Method according to claim 18, wherein the switch circuit is controlled based on white noise to determine at least one property of at least one of: the load or the converter circuit; and wherein the at least one property comprises at least one of the following: the load or the converter circuit, preferably one or more elements from a group consisting of: an inductance of an inductor; a capacitance of a capacitor; an equivalent series resistance of a capacitor; and an electrical property of the load. Method according to claim 18 or 19, wherein the switch circuit is controlled to provide the output voltage based on a duty cycle; and wherein the switch circuit is controlled based on white noise by adding the generated white noise to the duty cycle. The method of any of claims 18 to 20, further comprising: analog-to-digital converting a sensed output voltage reading to provide a digital value indicative of the sensed output voltage reading; wherein the analog-to-digital conversion preferably comprises: comparing the recorded measured value of the output voltage with a reference voltage; and generating a deviation signal that represents a difference between the recorded measured value of the output voltage and the reference voltage, and wherein the generated white noise is preferably added to the deviation signal, and wherein the reference voltage is preferably increased sequentially. The method of claim 21, further comprising: receiving the deviation signal; and generating a PID output based on the picked-up deviation signal by means of a PID controller of the control circuit, wherein the generated white noise is preferably added to the PID output. The method of claim 22, comprising: receiving the PID output by a pulse width modulation controller of the control circuit; and generating a pulse width modulated control signal by the pulse width modulation controller to regulate a power level to provide the output voltage to the load. Method according to one of claims 18 to 23, wherein the white noise is generated using a sigma-delta converter and wherein the method further preferably comprises: reducing a resolution of the sigma-delta converter to increase an amplitude of the generated white noise.

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