DE102014019830B4 - Current digital to analog converter - Google Patents

Abstract

Current-to-digital-to-analog converter, DAC (1900), comprising:
a plurality of n-type devices having gates coupled to a first bias voltage, the source of each of the n-type devices coupled to ground;
a first plurality of switches operable to couple the drains of some or all of the n-type devices together to produce a first output current whose magnitude depends on the number of n-type devices electrically coupled together ,
a plurality of transistor devices having gates coupled to a second bias voltage; and
a second plurality of switches operable to couple the drains of some or all of the transistor devices together to produce a second output current, the magnitude of which depends on the number of the transistor devices electrically coupled together.

Description

Priority claim

This application claims priority over the US Provisional application 61,799,833 , filed March 15, 2013, entitled “Integrated Voltage Regulators” and the US Provisional application 61,829,992 , filed May 31, 2013, entitled “On-chip compensator for an integrated voltage regulator.”

background

DC-DC converters typically generate a DC (direct current) voltage by full-wave rectification and filtering of one or more time-varying signals. Because of the switching involved in the full-wave rectification process, significant portions of the current are often switched forward and back at a high rate through large transistors. It is often helpful to measure the current across these transistors, for example to determine whether or not the DC-DC converter is under load, to monitor current waves caused by switching, etc. A DC-DC converter is known, for example US 2004 / 0 008 011 A1 . Similar devices are also known US 2004 / 0 217 741 A1 , US 2012/ 0 229 107 A1 , US 2003 / 0 218 455 A1 , DE 10 2006 019 681 A1 , DE 100 38 372 A1 , US 2012 / 0 218 003 A1 , US 2012 / 0 007 572 A1 , or US 2008 / 0 309 307 A1 .

Also revealed US 2005 / 0 001 752 A1 a current output D/A converter for converting a digital signal into an analog signal, having a control signal input terminal for receiving an externally supplied control signal, and an output load element having a switching mechanism for electrically connecting or disconnecting the output load element to/from an analog output node on the basis of the control signal applied to the control input terminal.

The invention is defined in claim 1. Embodiments of the invention are set out in the dependent claims.

Short description of the characters

• 1 ist ein Spannungsregulator mit einem Phasen- und Strom-Ausgleich gemäß einem Ausführungsbeispiel der Offenbarung.
• 2 ist eine Phasen-Ausgleichschaltung gemäß einem Ausführungsbeispiel der Offenbarung.
• 3 zeigt Stromabtastungsorte gemäß einem Ausführungsbeispiel der Offenbarung.
• 4 zeigt eine Schaltung mit einer Brücke und Stromsensoren vom n-Typ und p-Typ gemäß einem Ausführungsbeispiel der Offenbarung.
• 5 ist eine Architektur auf Transistorniveau von n-Typ- und p-Typ-Stromsensoren gemäß einem Ausführungsbeispiel der Offenbarung.
• 6 zeigt differenziell gleitende Stromquellen gemäß einem Ausführungsbeispiel.
• 7 ist eine Vorspannungsschaltung für die differenziell gleitenden Stromquellen gemäß einem Ausführungsbeispiel der Offenbarung.
• 8A-B sind niederimpedante Empfänger zum Empfangen eines differenziellen Stroms von den Stromquellen gemäß einem Ausführungsbeispiel der Offenbarung.
• 9 ist eine Schaltung mit einer Empfängerschaltung und einem p-Typ-Stromsensor gemäß einem Ausführungsbeispiel der Offenbarung.
• 10 ist eine Schaltung mit einer Empfängerschaltung und einem n-Typ-Stromsensor gemäß einem Ausführungsbeispiel der Offenbarung.
• 11 ist eine Teilschaltung eines Spannungsregulators mit n-Typ- und p-Typ-Stromsensoren gemäß anderen Ausführungsbeispielen der Offenbarung.
• 12 ist eine Transistorniveauarchitektur von n-Typ- und p-Typ-Stromsensoren gemäß einem anderen Ausführungsbeispiel der Offenbarung.
• 13 ist eine Stromsensorempfängerschaltung gemäß einem Ausführungsbeispiel der Offenbarung.
• 14 ist eine Grundarchitektur (high-level architecture) von Spannungsregulator-Stromsensoren mit telemetrischen und Überstromsicherheitstreibern gemäß einem Ausführungsbeispiel der Offenbarung.
• 15 ist eine Schaltung für Stromphasenmittelung gemäß einem Ausführungsbeispiel der Offenbarung.
• 16 ist eine Phasenausgleichschaltung mit einer Versatzsteuerung gemäß einem Ausführungsbeispiel der Offenbarung.
• 17 ist eine Grundarchitektur für eine Versatzstreichung eines Komparators und eine Stromsensorfehlanpassung gemäß einem Ausführungsbeispiel der Offenbarung.
• 18 ist ein Flussdiagram für ein Verfahren zur Versatzstreichung eines Komparators und eine Stromsensorfehlanpassung gemäß einem Ausführungsbeispiel der Offenbarung.
• 19 ist ein Digital-zu-Analog-(DAC)-Stromwandler gemäß einem Ausführungsbeispiel der Offenbarung.
• 20 ist ein bekannter Typ-3-Kompensator.
• 21 ist ein differenzieller Typ-3-Kompensator gemäß einem Ausführungsbeispiel der Offenbarung.
• 22 ist eine Frequenzantwort eines differenziellen Typ-3-Kompensators gemäß einem Ausführungsbeispiel der Offenbarung.
• 23 ist der differenzielle Typ-3-Kompensator mit DFT-(Design-für-Test)-Merkmalen und Konfigurationsplänen gemäß einem Ausführungsbeispiel der Offenbarung.
• 24 ist eine Pilotbrücke gemäß einem Ausführungsbeispiel der Offenbarung.
• 25 ist ein Teil einer Spannungsregulierungsvorrichtung mit dem differenziellen Typ-3-Kompensator gemäß einem Ausführungsbeispiel der Offenbarung.
• 26 ist ein Smart-Gerät oder ein Computersystem oder ein SoC (Systemon-Chip) mit einem oder mehreren Schaltungen, die im Zusammenhang mit den 1-25 beschrieben wurden, gemäß einem Ausführungsbeispiel der Offenbarung.

The embodiments of the disclosure will be better understood from the detailed description provided below and from the accompanying drawings of the various embodiments of the disclosure, which, however, should not be construed as limiting the disclosure to the specific embodiments, but rather only Explanation and understanding are provided.

• 1 is a voltage regulator with phase and current compensation according to an embodiment of the disclosure.
• 2 is a phase compensation circuit according to an embodiment of the disclosure.
• 3 shows current sampling locations according to an embodiment of the disclosure.
• 4 shows a circuit with a bridge and n-type and p-type current sensors according to an embodiment of the disclosure.
• 5 is a transistor-level architecture of n-type and p-type current sensors according to an embodiment of the disclosure.
• 6 shows differentially sliding current sources according to an exemplary embodiment.
• 7 is a biasing circuit for the differentially sliding current sources according to an embodiment of the disclosure.
• 8A -B are low impedance receivers for receiving a differential current from the power sources according to an embodiment of the disclosure.
• 9 is a circuit including a receiver circuit and a p-type current sensor according to an embodiment of the disclosure.
• 10 is a circuit including a receiver circuit and an n-type current sensor according to an embodiment of the disclosure.
• 11 is a subcircuit of a voltage regulator with n-type and p-type current sensors according to other embodiments of the disclosure.
• 12 is a transistor level architecture of n-type and p-type current sensors according to another embodiment of the disclosure.
• 13 is a current sensor receiver circuit according to an embodiment of the disclosure.
• 14 is a high-level architecture of voltage regulator current sensors with telemetric and overcurrent safety drivers according to an embodiment of the disclosure.
• 15 is a current phase averaging circuit according to an embodiment of the disclosure.
• 16 is a phase compensation circuit with an offset control according to an embodiment of the disclosure.
• 17 is a basic architecture for comparator offset cancellation and current sensor mismatch according to an embodiment of the disclosure.
• 18 is a flowchart for a method for comparator offset cancellation and current sensor mismatch according to an embodiment of the disclosure.
• 19 is a digital-to-analog (DAC) power converter according to an embodiment of the disclosure.
• 20 is a well-known type 3 compensator.
• 21 is a Type 3 differential compensator according to an embodiment of the disclosure.
• 22 is a frequency response of a Type 3 differential compensator according to an embodiment of the disclosure.
• 23 is the Type 3 differential compensator with DFT (design for test) features and configuration plans according to an embodiment of the disclosure.
• 24 is a pilot bridge according to an embodiment of the disclosure.
• 25 is a part of a voltage regulation device with the differential type 3 compensator according to an embodiment of the disclosure.
• 26 is a smart device or a computer system or a SoC (system-on-chip) with one or more circuits related to the 1-25 have been described, according to an embodiment of the disclosure.

Detailed description

The exemplary embodiments describe a device and method for current balancing, current sensing and phase compensation, offset cancellation, digital-to-analog current converters with monotonic outputs using binary-coded inputs (without binary-to-thermometer decoders), compensators for a voltage regulator (VR), etc The embodiments have various technical effects including improved VR reliability, improved VR efficiency, reduced power consumption, etc.

In the following description, various details are discussed to provide an improved understanding of the embodiments of the present disclosure. It will be apparent that one skilled in the art would be able to implement the embodiments of the present disclosure without these specific details. In other examples, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring embodiments of the present disclosure.

It is noted that in the corresponding figures of the exemplary embodiments, signals are represented with lines. Some lines may be shown thicker to indicate more distinct signal paths and/or have arrows at one or more ends to indicate a primary information flow direction. Such information should not be construed as restrictive. Instead, lines are used in connection with one or more exemplary embodiments to aid in easier understanding of a circuit or logical device. Each signal shown may, if dictated by design requirements or preferences, actually include one or more signals that may propagate in any direction and may be implemented with an appropriate type of signaling scheme.

Throughout the specification and claims, the term “connected” is used to mean that a direct electrical connection is formed between the things that are connected, without any other intermediate devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection via one or more passive or active intermediate devices. The term “circuit” means one or more passive and/or active components arranged to cooperate with another to provide a desired function. The term “signal” means at least a current signal, voltage signal or data/clock signal. The terms “a” and “the” also include plural expressions. The meaning of “in” includes “in” and “on”.

The term “scaling” generally refers to converting a design (schematic or layout) of one process technology to another process technology. The term “scaling” generally refers to reducing the size of a layout and devices within the same technology node. The term “scaling” may also refer to adjusting (e.g., slowing down) a signal frequency relative to other parameters such as a power supply level. The terms “substantially,” “closed,” “approximately,” “round,” and “Approximately” generally refers to ranges of +/- 20% of a target value.

Unless otherwise specified, common adjectives "first", "second" and "third", etc. are used to describe a common object, but they only indicate that one is referring to different instances of the same objects or similar objects, and it is not intended that the objects so described are necessarily present in the given sequence, either temporally, spatially, or in rank, or in any other form.

For purposes of embodiments, transistors include metal oxide semiconductor (MOS) transistors having a drain, source, control contact, and space contact. The transistors can also be three-gate and FinFet transistors, gate-all-around cylindrical transistors, or other devices that have transistor functionality such as carbon nanotubes or spintronic devices. Source and sink connections may be identical contacts and may be used interchangeably therein. Those skilled in the art will understand that other transistors such as Bi-Polar Junction Transistors - BJT PNP/NPN, BiCMOS, CMOS, eFET, etc. may be used without departing from the scope of the disclosure. The term “MN” indicates an n-type transistor (e.g. NMOS, NPN BJT, etc.) and the term “MP” indicates a p-type transistor (e.g. PMOS, PNP BJT, etc.).

1 is a VR 100 with phase and current compensation according to an embodiment of the disclosure. Typical VRs can generate phase currents that differ between phases. For example, one phase can deliver a 1A current and another phase can deliver a 4A current. This phase current mismatch causes the VR to lose efficiency and also contributes to a voltage error in the corresponding output voltage. The following embodiment solves at least the above problem.

In one embodiment, a VR 100 includes multiple bridges 101 _1-N , where “N” is greater than one; a pulse width modulator (PWM) 102 and a compensator 103. In this example, N=16. However, the exemplary embodiments are not limited to N=16. Any number of “N” can be used. In one embodiment, the bridges 101 _1-N are coupled to a plurality of inductors L _1-N , which in turn are coupled to a charging capacitor (or decoupling capacitor) Cdecap and a load 104. The voltage Vout of the capacitor is the regulated output voltage. In one embodiment, a compensator 103 receives a reference voltage Vref and an output voltage Vout (the same as Vsense) to generate a modified reference voltage Vfb (feedback voltage) for a PVM 102. In one embodiment, the output of each of the bridges of the plurality of bridges 101 _1-N is coupled to an inductor L of the plurality of inductors L _1-N . For example, the inductor L ₁ is coupled to a bridge 101 ₁ . In one embodiment, multiple current sensors (not shown) are coupled to the multiple bridges 101 _1-N and configured to sense the current iPhase(1-N) for each bridge (or phase).

In one embodiment, the PWM 102 generates a plurality of pulse width modulated signals, the PWM(1-N) signals, for timing and the bridge drivers 105 _1-N . In one embodiment, the output gn(1-N) and gp(1-N) of a timing controller and the bridge drivers 105 _1-N are used to control the plurality of bridges 101 _1-N to produce the regulated voltage Vout.

In one embodiment, PVM 102 includes a wave synthesizer 106, a current mixer 107 _1-N, and a comparator 108 _1-N. In one embodiment, the wave synthesizer 106 (also referred to as a wave generator) generates “N” triangular waves. In one embodiment, the triangular waves are periodic and have a voltage that oscillates between Vh (high voltage threshold) and VI (low voltage reference).

In one embodiment, the comparator 108 _IN generates a number "N" of PWM signals (ie, PWM(1-N) signals), each of which drives a corresponding timing and bridge driver, from the plurality of timing and bridge drivers 105 _{1- N.} In one embodiment, the PWM signals (ie, PWM(1-N) signals have a duty cycle that varies with the DC levels of inputs to the comparators 108 _1-N . The magnitude of the current output through the bridges 101 _1-N , the Ripple of the current and the voltage Vout depends on the duty cycle of the PWM(1-N) signals.

In one embodiment, current mixer 107 _1-N receives sampled phase currents (iPhase(1-N)) from each bridge of the plurality of bridges 101 _1-N and subtracts an average current from all bridges 101 _1-N by a current error ierr(1-N). which is used to generate a corresponding voltage Vtw(1-N) as inputs to the corresponding comparators 108 _1-N . For example, current mixer 107 ₁ receives iPhase1 from bridge 101 ₁ and subtracts the average current from iPhase1 to produce ierr1 gen, which is used to generate Vtw1 for the comparator 108 ₁ . In such an embodiment, the output current from all bridges 101 _1-N is substantially balanced, resulting in phase balancing.

In one embodiment, current sensor signals (iPhase(IN)) are combined and added (or subtracted) to/from current mixers 107 _1-N to the main VR loop at the interface of the waveform output of synthesizer 106 and comparator 108 _1-N . In such an embodiment, the main VR loop (comprising PWM 102 → bridge driver 105 _1-N → bridge 101 _1-N → compensator 103) regulates the output voltage Vout during the current sampling loop (comprising current mixer 107 _1-N → comparator 108 _1-N →Bridge drivers 105 _1-N →Bridges 101 _1-N →Current sensors (not explicitly shown)) checked and ensures that all phases (i.e. bridges 101 _1-N ) generate the same amount of current.

The triangle wave (ie, the output of the waveform synthesizer 106) from each phase (or bridge) is shifted up to or decreased by an amount proportional to I _err = I _ph - I _avg , where I _err is the difference between the individual phase current and the average current of all phases. In one embodiment, shifting the triangular waves up reduces the PWM duty cycle, which reduces the phase current, and shifting the triangular wave down increases the PWM duty cycle, which increases the phase current (ie, from the bridge output of the bridges 101 _1-N ).

2 is a phase compensation circuit 200 according to an embodiment of the disclosure. It should be noted that such elements of the 2 , which have the same reference numbers (or names) as, but are not limited to, elements in another figure operate or may function in a similar manner as described.

In this embodiment, the current mixer Rmix (one of the current mixers 107 _{1 -N} ) is coupled to the wave generator 106 and comparator 108 ₁ . In order not to obscure the exemplary embodiment, the bridge 101 ₁ , the current mixer 107 ₁ , the comparator 108 ₁ , the inductor L ₁ are described with respect to phase 1. The same explanation is equally applicable to the other phases. In one embodiment, each phase may have its own current error. In one embodiment, the current sensor output is a current mode signal iPhase1 and is proportional to the bridge current.

In one embodiment, the phase current iPhase1 is applied as a positive signal while the current average iavg is applied as a negative signal. In one embodiment, the connection between waveform generator 106 and the inputs of comparators 108 is _1-N current mixer 107 _1-N . In one embodiment, each of the current mixers (one of the current mixers 107 _1-N ) mixes the positive phase current and negative average current (iavg) signals together so that the difference in currents flows through the current mixers and produces a corresponding voltage drop Vtw . In one embodiment, this voltage is what shifts the triangle wave up or down. The value of the triangular wave displacement is given by ΔVtri = R _mix *(I _ph - I _avg ). In one embodiment, the power balancing scheme is based on the 1 on average currents, but not on maximum currents.

In one embodiment, each phase in the VR 100 has a mixing resistor Rmix that receives the positive current signal generated by its own phase (eg, iPhase1) as well as the negative average signal (ie, iavg), which is the same for all phases. In one embodiment, the positive phase current signal is generated by folding the differential current signal from the supply string (eg, bridge 101 ₁ ) into a single-ended signal with a positive sign. In one embodiment, the negative average signal (ie -iavg) is generated in a similar manner.

In one embodiment, the polarity of the inputs to the differential-to-single-ended circuit for average current generation is reversed, giving it an increment of -1 with respect to the phase current signal. In one embodiment, the output of a negative current average cell is divided into multiple separate outputs, one for each phase in the VR 100. For "N" phases, there are N outputs, each with 1/N strength compared to the original output. These outputs are then evenly distributed among other average current producing cells so that the total negative average current signal for a given phase is actually a combination of simple 1/N outputs from each of the N phases. In one embodiment, the signals involved are in current mode, so adding these outputs can be accomplished through fusion.

For example, for a 4-phase VR, the mixing resistor Rmix for phase 1 receives the full phase current signal and a ¼ average signal from each of the four phases. If the current in phase 1 is equal to the average current, no Current will flow to the Rmix1 (i.e. 107 ₁ ) and the triangle wave will not change. In this embodiment, Rmix of the other phases gets a branch from the average current cell in phase 1 (as well as a branch from every other phase). In one embodiment, only the phase current signals are used without subtracting the average current. In such an embodiment, VR 100 operates in a form of current mode control that can be used to improve transient performance.

3 shows current sensor positions 300 according to an embodiment of the disclosure. It is noted that such elements of the 3 , which have a same reference numeral (or name) as the elements of other figures, operate or may function in a similar manner to those already described, but they are not limited thereto.

In this exemplary embodiment, a bridge 101 ₁ and a corresponding output inductor L ₁ are shown. In one embodiment, the current sensor may be located at positions “1,” “2,” or “3” as shown. Position “2” refers to a short-circuit inductor technique that induces a current measurement signal in an inductor through a magnetic field coupling that produces a current signal that can be measured by the inductor. Unfortunately, shunt inductance is not practical for rapidly changing currents because the bandwidth of an inductor is limited (i.e., the inductor will exhibit increasing attenuation for a current measurement signal with increasing frequency).

The “3” position refers to a series resistor technique. Serial resistor technology typically does not suffer from the bandwidth limitation problem because pure resistors do not change in their properties as a function of signal frequency. However, the series resistor technique is also not practical for large currents (such as those flowing through DC-DC converter switching transistors) because a large current flowing through a resistor tends to lose a large amount of power (via the relationship P=I ² R), which can result in overheating; or, if the power "problem" is made manageable by a very small series resistor, inaccuracy results because the signal V=I*R is too small a quantity to measure.

The embodiments use position "1" where current sensors sense current via p-type devices MP1 and/or MP2 (which form a high-side switch) and n-type devices MN2 and/or MN1 (which form a form a low-side switch).

4 is a circuit 400 with a bridge and n-type and p-type current sensors according to an embodiment of the disclosure. It should be emphasized that such elements of the 4 with like reference numerals or names as such elements of other figures may operate and function in a manner similar to that described, but are not limited thereto.

In one embodiment, the circuit 400 includes a bridge 101 ₁ , a p-type (eg PMOS) current sensor 401 ₁ , an n-type (eg NMOS) current sensor 402 ₁ , a p-type current sensor (CS) receiver 403 ₁ and an n-type current sensor receiver 404 ₁ . While embodiments are explained with respect to one phase of the bridge, the same explanation is applicable to other bridges/phases.

In this embodiment, the output of a p-type current sensor 401 ₁ is passed via metal connections 405 ₁ to a p-type current sensor receiver 403 ₁ . In this embodiment, the output of an n-type current sensor 402 ₁ is forwarded via metal lines 406 ₁ to n-type current sensor receiver 404 ₁ . In one embodiment, outputs of the p-type current sensor receiver 403 ₁ and n-type current sensor receiver 404 ₁ are combined to produce an iPhase1 current, which represents a phase current of the bridge 101 ₁ . In one embodiment, all bridges 101 _1-N have their respective p-type and n-type current sensors and the corresponding p-type and n-type current sensor receivers are configured to generate their respective iPhase currents.

In one embodiment, the p-type and n-type current sensors 401 ₁ and 402 ₁ determine the load current by detecting the sink source voltage (V _DS or V _SD ) drop on the conductive half of the bridge 101 ₁ . For example, for NMOS (i.e. low side switch with MN2 and MN1) V _DS =Vxbr-Vss; and for PMOS (ie, high side switch with MP1 and MP2) V _SD =Vccin-Vxbr where Vxbr is a bridge output. The current sensing embodiment of the 4 reduces energy loss by eliminating the need to add additional series resistor.

5 is a transistor level architecture 500 of an n-type and p-type current sensor according to an embodiment of the disclosure. It is noted that such elements of the 5 with like reference numerals or names operate or function as elements of other figures in a manner similar to that described, but are not limited thereto.

In one embodiment, the transistor level architecture 500 includes a bridge 101 ₁ and current sensors, ie, a p-type current sensor 401 ₁ and an n-type current sensor 402 ₁ . In one embodiment, the p-type current sensor 401 ₁ includes a first stack of cascade devices comprising p-type MPs1, MPs2 and MPs3 that couple together as shown, and a second stack of cascade devices comprising a p-type Include MPs4, MPs5 and MPs6, which couple in series between VccIn and another VccIn. In one embodiment, the control contact terminals of MPs1 and MPs4 are coupled to cp, the source terminals of MPs1 and MPs4 are coupled to VccIn, and the sink terminal of MPs1 is coupled to Vcp1, while the drain terminal of MPs4 is coupled to Vcp2. In one embodiment, the control contact terminals of MPs2 and MPs5 are coupled to gp (or gp1). In one embodiment, the control contact terminals of MPs3 and MPs6 are coupled to Vccin/2.

In one embodiment, Vcp1 and Vcp2 are coupled to an amplifier that produces a differential output current. In one embodiment, the amplifier of 401 ₁ includes: a floating current source IcsN, a diode connecting p-type devices MPc2 and MPc3, and common control terminal amplifiers MPc1 and MPc4. In one embodiment, Vcp1 is coupled to MPc1 and MPc2, while Vcp2 is coupled to MPc3 and MPc4, as shown. In one embodiment, the outputs of the common control terminal amplifiers MPc1 and MPc3 are received by the p-type current sensor receiver 403 ₁ via a differential connection 405 ₁ .

In one embodiment, the n-type current sensor 402 ₁ includes a first set of devices including n-type MNs1, MNs2 and MNs3 coupled together as shown, and a second set of devices including n-type MNs4, MNs5 and MNs6 coupled together are coupled together between the ground connection and another ground connection. In one embodiment, the control terminals of MNs1 and MNs6 are coupled to cn, the source terminals of MNs1 and MNs4 are coupled to ground, and the sink terminal of MNs1 is coupled to Vcnl, while the sink terminal of MPs4 is coupled to Vcn2. In one embodiment, the control terminals of MNs2 and MNs5 are coupled to gn (or gn1). In one embodiment, control terminals MNs3 and MNs6 are coupled to Vccin/2. In one embodiment, the sink port of MNs3 is coupled to the drain port of MPs3 and the output Vxbr of the bridge 101 ₁ .

In one embodiment, Vcnl and Vcn2 are coupled to an amplifier that produces a differential output current. In one embodiment, the amplifier of 402 ₁ includes the following: a floating current source IcsP, diode-connected n-type devices MNc2 and MNc3, and common gate amplifiers MNc1 and MNc4. In one embodiment, Vcn1 is coupled to MNc1 and MNc2, while Vcn2 is coupled to MNc3 and MNc4 as shown. In one embodiment, the outputs of the common gate amplifiers MNc1 and MNc3 are received by the n-type current sensor receiver 404 ₁ via a differential connection 406 ₁ .

In one embodiment, when both inputs Vcp1 and Vcp2 are equal, there is no signal generated by current sensor 401 ₁ via connection 405 ₁ . Vcp1 and Vcp2 can be equal when the high side switching transistors MP1 and MP2 are turned off. In one embodiment, when both inputs Vcnl and Vcn2 are equal, there is no signal generated by current sensor 402 ₁ for connection 406 ₁ . Vcnl and Vcn2 can be equal when the low-side switching transistors MN1 and MN2 are turned off.

In one embodiment, each PMOS 401 ₁ and NMOS 402 ₁ current sensor samples current when their bridge unit is conductive. For example, when the high-side switching transistors MP1 and MP2 are conducting, the PMOS current sensor 401 ₁ samples the current, and when the low-side switching transistors MN1 and MN2 are conducting, the NMOS current sensor 402 ₁ samples the current Power off.

In one embodiment, when its bridge unit is powered off, the Vxbr node is near the opposite supply string and the current sensor enters a defined non-sampling state to avoid sending erroneous signals as well as a possible gate overvoltage condition can occur. In one embodiment, the current sensor uses the bridge gate and cascode nodes to dynamically switch between sampling and non-sampling states on each half of the switching cycle. In one embodiment, for a conductive bridge, Vxbr is typically closed to the power train. In the NMOS case (i.e., low-side switches have MN2 and MN1), Vxbr often goes below Vss according to one embodiment.

In one embodiment, the current sensors 401 ₁ and 401 ₂ utilize a common gate current mode (gm) amplifier to enable accurate sampling of the bridge output node at these extreme voltages. In In one embodiment, the amplifier is differential so that the output current signals can be propagated over long distances without being susceptible to noise interference.

6 shows differential sliding current sources 600 according to one embodiment. It is noted that such elements of the 6 , which have the same reference numerals (or names) as elements of other figures operate or function in a manner similar to that described, but are not limited thereto.

In one embodiment, a differential floating current source 600 is used to provide a bias current for the power train current sensors (eg, 401 ₁ and 402 ₁ ). In one embodiment, the current sensor and the bias circuit may be separated over a large distance, for example 5000 μm. In one embodiment, the differential current source 600 is immune to supply drops (ie, a drop in Vccin and/or ground) because it is referenced back to itself.

In one embodiment, the differential floating current source 600 includes a differential bias network for providing VbiasN and VbiasP (ie, differential biases) to current sources of the amplifier stage of the corresponding current sensors 401 ₁ and 402 ₁ . For each p-type and n-type current sensor, both MNcsN and MNcsP are used for the sliding current source.

In one embodiment, the differential bias network includes a unity gain amplifier 601 that receives Vccin/2 as input and produces a copy thereof as Vc/2. In one embodiment, the differential bias network includes p-type devices MPb1, MPb2, MPb3 and MPb4 and n-type devices MNb1, MNb2, MNb3 and MNb4. In one embodiment, MNb3 and MNb4 form the power source biased by Vibias (generated by an embodiment of the 7 ). In one embodiment, Vc/2 is used by the unity amplifier 601 to bias the source terminals of MPb3 and MNb1. In one embodiment, the current drawn by MNb3 sets the voltage drop Vc/2 - VbiasP. In one embodiment, the current drawn by MNb4 flows through MPb4, MNb2 and MPb2. In one embodiment, MPb2 mirrors this stream to MPb1. In one embodiment, the current through MPb1 sets the voltage VbiasN - Vc/2. In such an embodiment, the sum of these voltage drops (Vc/2 - VbiasP) + (VbiasN - Vc/2) is equal to VbiasN - VbiasP = V,bias.

In one embodiment, the gate nodes of the diode-connected n-type and p-type devices MNb1 and MPb3 are passed to circuits in the p-type and n-type current sensors (eg, 401 ₁ and 402 ₁ ). copy, which are arranged in the different supply line phases (ie bridges 101 _1-N ). In one embodiment, the voltage drop problem is eliminated because the gate connections carry zero current and thus no IR drop occurs on the long connecting wires.

7 is a biasing circuit 700 for the differential sliding current sources 600 according to an embodiment of the disclosure. It is noted that such elements of the 7 , which bear the same reference numerals (or names) as the elements in other figures, function or may operate in a similar manner as described, but are not limited thereto.

In one embodiment, bias circuit 700 includes amplifiers 701 and 702, adjustable current sources 703 and 704, and resistors R1 and R2. In one embodiment, the bias circuit 700 receives a reference voltage (eg, from a bandgap circuit) and generates Vpb and Vbn, each of which can be used to provide V,ibias 6 . In one embodiment, the adjustable current source 701 is a p-type device that couples to a power supply and a resistor R1. In one embodiment, resistor R1 is coupled to ground and a unit 703. In such an embodiment, amplifier 701 (eg, an operational amplifier) adjusts the strength of unit 703 so that V1 is substantially equal to Vref. In one embodiment, adjustable current source 702 is an n-type device coupled to ground and resistor R2. In one embodiment, resistor R2 is coupled to the supply unit and unit 704. In such an embodiment, amplifier 702 (eg, an operational amplifier) adjusts the strength of unit 704 so that V2 is substantially equal to Vref.

In one embodiment, if "I" is the current flowing through unit 703 and resistor R1, I = Vref/R1. In one embodiment, this current "I" is also used to adjust or compensate for an offset of a comparator 108 ₁ , as with respect to 16 to 18 is described. For example: Voffset = mIRmix, where "m" is the current scaling from the digital-to-analog converter (DAC) 1701. Substituting "I" in the Voffset equation shows that Voffset depends on a ratio of the resistors Rmix and R1 depends, so that there is an influence of Pro process variations in which resistance is essentially eliminated.

In one embodiment, the bias circuit 700 generates a current such that the product of this current and the resistance of an on-chip resistor is substantially constant, ie, process sensitivity is substantially reduced. In one embodiment, the final output signal of the current sensors (e.g. 401 ₁ and 402 ₁ ) may depend on resistors R1 and R2, but the offset voltage across the Rmix resistor does not depend on the resistances of R1 and R2, i.e. ierr*Rmix has im Essentially zero procedural dependency.

The 8A -B are low-impedance receiver architectures 800 and 820 for receiving differential currents from the current sensors (eg, 401 ₁ and 402 ₁ ), respectively, according to an embodiment of the disclosure. It is noted that such elements of the 8A -B have the same reference numerals (or names) as, but are not limited to, elements of other figures operate or may function in a similar manner as described therein.

In one embodiment, the low impedance receiver architecture includes a receiver 802 and a diode-connected n-type device MNd. In one embodiment, receiver 802 receives a current from a p-type current sensor (eg, 401 ₁ ) via its low impedance input. In order not to obscure the embodiment, the differential output of the p-type current sensor 401 ₁ is not shown. In one embodiment, current flows from the p-type current sensor 401 ₁ over a long connection 405 ₁ formed as a PI network 803 of capacitors and resistor-coupled p-type current sensor 401 ₁ and a low impedance receiver 802.

In one embodiment, the low-impedance receiver 802 includes an amplifier 801 and a p-type unit MPin. In one embodiment, the input VinP of the low impedance receiver 802 is coupled to MPin and an input of the amplifier 801. In one embodiment, the amplifier 801 also receives a reference voltage V _REF and adjusts the strength of MPin to set VinP to be substantially equal is too V _REF . In one embodiment, the current through MPin also flows through the diode-connected MNd and a voltage Vgn proportional to this current is generated.

In one embodiment, the low impedance receiver architecture 820 includes a receiver 822 and a diode-connected p-type device MPd. In one embodiment, receiver 822 receives current from an n-type current sensor (eg, 402 ₁ ) via its low impedance input. In order not to obscure the embodiment, the differential output of the n-type current sensor 402 ₁ is not shown. In one embodiment, current flows from an n-type current sensor 402 ₁ over a long connection 406 ₁ formed as a PI network 823 of capacitors and resistors coupled n-type current sensor 402 ₁ and a low impedance receiver 822.

In one embodiment, the low-impedance receiver 822 includes an amplifier 821 and an n-type unit MNin. In one embodiment, an input VinN of the low impedance receiver 822 is coupled to MNin and input of the amplifier 821. In one embodiment, the amplifier 821 also receives a reference voltage V _REF and adjusts the strength of MNin to cause VinN to be substantially equal to V _REF . In one embodiment, the current through MNin also flows through the diode-connected MPd, and a voltage Vgp proportional to this current is also generated.

In this embodiment, low impedance inputs are used to receive differential current mode signals from the power train current sensors. The low impedance input is used because the long distances (e.g. 5000 µm) from the supply string (e.g. bridge 101 ₁ ) to the receiver 802 (and 822) would cause the bandwidth to be very narrow if not for the voltage oscillations at the end points of the Distance can be kept to a minimum. In one embodiment, the low impedance input VinP (and VinN) is generated by inserting a gain-increasing transistor MPin (and MNin) between the long paths 405 ₁ (ie 803) and the diode-connected device MNd (and MPd). the next level is mirrored.

In one embodiment, the input impedance of the pass transistor MPin, which is nominally 1/gm, is amplified by a factor of 1+A _v , where A _v is a gain of the amplifier 801. In such an embodiment, amplifier 801 (and 821) is a single-stage differential pair with a gain of approximately 30 dB. In one embodiment, amplifier 801 (and 821) has only a single stage to eliminate the possibility of instability. In other embodiments, other designs and numbers of stages of amplifiers 801 (and 821) may be used.

9 is a circuit 900 with a receiver circuit (eg 403 ₁ ) and a p-type current sensor (eg 401 ₁ ) according to an embodiment of the disclosure. It is noted that such elements of the 9 , which have the same reference numerals (or names), as elements of other figures operate or may function in a similar manner to those described, but are not limited thereto.

In one embodiment, the circuit 900 is coupled to the receiver circuit (403 ₁ ) to a current sensor (eg 401 ₁ ). In one embodiment, circuit 900 includes two branches to couple the differential outputs of current sensor 901 (eg, 401 ₁ ). The first branch includes MNr1 and the diode-connected MPr1 and the second branch includes MPr2 and MNr2. In one embodiment, the first output current of the current sensor 901 is received by the receiver 802 via connection 405 ₁ and is converted to a voltage Vgn1 via the diode-connected MNd1 (the same MNd as from the 8A) . In this embodiment, MPr1 and MPr2 form current mirrors and are biased by Vr at their gates.

In one embodiment, a current through MNd1 is mirrored to the second branch (with MPr2 and MNr2) via n-type devices MNr1 and a diode-connected MPr1. In one embodiment, the second output current from the current sensor is received by the receiver 802 via connection 405 ₁ and is converted into a voltage Vgn2 via the diode-connected MNd3 (same as MNd from the 8A) . In this exemplary embodiment, the differential current from sensor 901 is converted into a single-ended current iPhase1 (associated with bridge 101 ₁ ).

In one embodiment, a filtered, unregulated power supply is used to power the current sensor receiver 900. The use of higher voltage comes from a voltage drop created by NMOS current signals on the long paths (e.g. 405 ₁ ) between the power train (e.g. 101 ₁ ) and the receiver 900 (e.g. 403 ₁ ). This voltage drop reduces freedom to the point that a supply of at least 1.2V can be used for stable operation.

In one embodiment, the current sensor receiver cannot be powered directly by the Vccin strand because large high frequency noise can interrupt the differential-to-single-ended output stage of the current sensor. In one embodiment, an RC low pass filter is applied to the gate of an NMOS power transistor whose drain is connected to Vccin and whose source powers the current sensor receiver circuit. In one embodiment, the RC low pass filter filters high frequency noise from Vccin without requiring an additional linear regulator. In one embodiment, the new supply Vcccsrcvr (provided to the sources of MPr1 and MPr2) is unregulated at DC and its value is Vccin-Vt,n.

In one embodiment, the pair of pass units (ie, MPc1 and MPc2 and MPc3 and MPc4) in the PMOS current sensor 901 that are controlled by an override signal allow the current sensor 901 to operate without a PMOS cascode turned on. In this embodiment, the output of the current sensor consists of a first order error signal (composite offset), which is used to calibrate the current sensor to "zero". For example, when the FET of bridge 101 ₁ is turned off, the current sensor associated with the power FET does not measure current, that is, the current sensor inputs are connected together. In this example, the output of the phase current sensor is currently a fault current (e.g. due to a process variation). This error current (or offset) is calibrated out during a PVM trim calibration process according to one embodiment. In one embodiment, the receiver circuit 403 ₁ (ie, the remainder of 900 after taking out 901), which receives the differential current signal from the current sensor 901, converts it into a single-ended current signal iPhase1. In one embodiment, the receiver makes different copies of this signal iPhase1 with each sign (positive or negative). In one embodiment, copies of this signal iPhase from different phases may be added to produce a sum or average current sensor signal for a complete voltage domain or for different domains.

10 is a circuit 1000 with a receiver circuit (eg 404 ₁ ) and an n-type current sensor (eg 402 ₁ ) according to an embodiment of the disclosure. It is noted that such elements of the 10 , which have the same reference numerals (or names), as elements of other figures operate or may function in a similar manner as described, but are not limited thereto.

In one embodiment, circuit 1000 couples a receiver circuit (e.g. 404 ₁ ) to a current sensor (e.g. 402 ₁ ). In one embodiment, circuit 1000 includes two branches for coupling to the differential outputs of current sensor 1001 (eg 402 ₁ ). The first branch includes MPr1 and a diode-connected one MNr1 and the second branch includes MNr2 and MPr2. In one embodiment, the first output current of the current sensor 1001 is received by the receiver 822 via a connection 2 406 ₁ and is converted into a voltage Vgp1 via the diode-connected MPdl (the same as MPd from the 8B) . In this embodiment, MNr1 and MNr2 form current mirrors and are biased by Vr at their gates.

In one embodiment, the current through MNd1 is mirrored to the second branch (with MNr2 and MPr2) via the p-type devices MPr1 and the diode-connected MNr1. In one embodiment, the second output current from the current sensor is received by the receiver 822 via connection 2 406 ₁ and is converted into a voltage Vgp2 via the diode-connected MPd2 (the same as MPd from the 8B) . In this exemplary embodiment, the differential current from sensor 1001 is converted into a single-ended current iPhase1, associated with bridge 101 ₁ . In one embodiment, a filtered unregulated power supply is used to power the current sensor receiver 1000, as is the case with respect to the embodiment of FIG 9 was described.

In one embodiment, a resistor (not shown) is connected to one or more receiver outputs such that the voltage of the resistor changes in proportion to the change in the sum of the receiver output currents. In such an embodiment, the change in resistor voltage may be proportional to a phase current, a domain current, or to the VR input current (i.e., when only the high-side switch current is actually used). In one embodiment, the resistance value of this resistor is programmable. In one embodiment, the resistor may be biased by a voltage divider, typically around ½ of an analog supply, so that the current sensor accurately samples currents around zero without causing the voltage clearance problems that non-linearity causes.

11 is a portion of a circuit 1100 of a VR with n-type and p-type current sensors according to another embodiment of the disclosure. It is noted that such elements from the 11 , which have the same reference numerals (or names) as elements of other figures, operate or may function in a similar manner to those described, but are not limited thereto.

The circuit 1100 represents a supply strand bridge 1101 and a receiver module 1102 with a receiver 1106 _1. The exemplary embodiment of 11 is similar to the exemplary embodiment 4 . However, in the exemplary embodiment the 11 a set of differential currents across connection 1105 ₁ for both p-type and n-type current sensors (corresponding to 1103 ₁ and 1104 ₁ ) used to provide power to the current sensor receivers 1106 ₁ . In this embodiment, no or substantially zero DC current flows through 1105 ₁ so that a dynamic range of the sampling current is obtained as a result. Here, the term "preserved" does not generally refer to the loss of reserve, as there is no (or essentially zero) IR drop to 1105. In such an exemplary embodiment, the energy saving is essentially achieved via the exemplary embodiment 4 realized because p-type and n-type current sensors share a single bias current instead of consuming two separate currents.

In this embodiment, instead of sending separate n-type and p-type sensor signals (as with respect to the 4 was described) via 405 ₁ and 406 ₁ , they are combined here in the supply line 1101. In such an embodiment, forwarding resources are saved and integration complexity is reduced. In one embodiment, the current sensor receiver 1106 ₁ operates from a nominal analog quiescent power supply rather than Vccsrcvr.

A simple sum of all phase currents (i.e. iPhase(1-N)) need not accurately represent an average signal if some phases are not active. It can cause phase compensation loop gain variations with the number of active phases, reducing the effectiveness of the phase current compensation loop. Furthermore, it may cause inaccuracy of the overcurrent protection (OCP) on any number of active phases except for some phases (e.g. 4, 8 and 16 for 16 phase VR), whereas it may be desirable to have a reliable overcurrent protection for a wide range of to have active phases.

There are different technical effects of the exemplary embodiment 11 . Compared to the area used for the current sensor receivers 403 ₁ and 404 ₁ , the area of the current sensor receiver 1104 ₁ is halved, the number of long analog routes is halved; the high voltage analog supply is no longer used; supply losses during shutdown are significantly reduced; a constant over-phase activation region is maintained; OCP is accurate for any number of active phases, etc.

12 is a transistor level architecture 1200 of n-type and p-type current sensors according to another embodiment of the disclosure. It is mentioned that such elements of the 12 , which have the same reference numerals (or names) as such elements of other figures, operate or may function in a similar manner to those described, but are not limited thereto.

In one embodiment, output signals from n-type and p-type sensors (1103 ₁ and 1104 ₁ ) are combined by transistors MPcsc1 and MPcsc2 such that each sensor acts as an active load for the other. In one embodiment, MPcsc1 and MPcsc2 are biased by Vccin/2. In one embodiment, the quiescent currents are kept substantially equal by an appropriate bias voltage on both sensors (1103 ₁ and 1104 ₁ ) and the actual signal currents are sent to the receiver 1106 ₁ . In one embodiment, only the offset DC current flows over the long distances of 1105 ₁ . This relaxes the reliability requirements for the wires and reduces the IR drop related to the reserve issues. In one embodiment, each sensor can operate separately. In such an embodiment, the other sensor becomes a DC power source by combining its inputs. For example, if one of the current sensors is active, then the other current sensor, which is inactive, behaves as a current source and provides an operating point for the active current sensor.

13 is a current sensor receiver circuit 1200 (eg 1106 ₁ ) corresponding to an embodiment of the disclosure. It is noted that such elements from the 13 , which have the same reference numerals (or names) as such elements in other figures, operate or function in a similar manner to those described, but are not limited thereto.

In one embodiment, current sensor receiver circuit 1300 includes low impedance input stages for receiving currents Iin+ and Iin- from current sensors 1103 ₁ and 1104 ₁ via differential connection 1105 ₁ . In one embodiment, the low impedance stage on the left includes p-type units MPp1, MPp2 and MPp3 and n-type units MNn1 and MNn2. In one embodiment, MPp1 is biased by pbias and MMn2 is biased by nbias. In one embodiment, pbias and nbias can be generated by any known reference generator. For example, pbias and nbias can be generated using the bias circuit 700 of the 7 . Referring to the 13 , in one embodiment, the output of the low-impedance stage is Vrx+.

In one embodiment, the low-impedance stage to the right includes p-type units MPp11, MPp21, and MPp31 and n-type units MNn11 and MNn21. In one embodiment, MPp11 receives a bias voltage pbias and MNn21 receives a bias voltage nbias. In one embodiment, the output from the low impedance stage is Vrx-.

In the exemplary embodiments of 11-13 A small number of current sensor receivers and a compact receiver implementation reduces energy consumption in the functional mode. In one embodiment, the input voltage to receiver 1300 is regulated to Vgs below the supply voltage. This allows the use of the nominal voltage analog supply for the receiver and eliminates the use of the high voltage Vccsrcvr supply. This change results in a significant reduction in leakage voltage during shutdown.

The 14 is a high-level architecture 1400 of VR current sensors with telemetry and overcurrent protection drivers corresponding to an embodiment of the disclosure. It is mentioned that such elements of the 14 with the same reference numerals (or names) as elements of other figures operate or function in a similar manner to those described, but are not limited thereto.

In one embodiment, the architecture 1400 includes an average combiner 1401, a phase combiner 1402, an overcurrent safety (OC) driver 1403, telemetry drivers 1404, Rmix (current mixer), and a current sensor receiver 1106 ₁ . In one embodiment, the average combiner 1401 receives phase currents from all phases (iPhase(IN)) and generates an iavg current. In one embodiment, the iavg current is subtracted from the iPhase current (e.g. iPhase1) by the current mixer Rmix (e.g. 107 ₂ ) to produce an ierr current that is used to provide the DC voltage shift for the triangle wave for the PWM comparator (e.g. 108 ₁ ),

In one embodiment, an average of all phase currents from all phases (ie, bridges) is received by telemetry driver 1404 for other purposes. For example, the telemetry signal can be used during high volume manufacturing (HVM) to monitor performance parameters. In one embodiment, an average of all Phase currents from all phases received by the OCP driver 1403 to generate an OCP signal. For example, if the OCP signal indicates that iavg is above a threshold, then the entire processor and/or system or subsystem may be turned off.

Accurate average current information is useful for current balancing, telemetry, and overcurrent protection. The iavg signal allows maintaining a constant phase signal and therefore consistent balancing of loop gain over a full phase activation range. A current signal is actively collected by receiver ₁₁₀₆₁ , translated into a voltage and sent to average and phase combiners 1401 and 1402 accordingly. In one embodiment, phase combiner 1402 generates a single-ended current signal. In one embodiment, the average combiner 1401 combines all phase currents together such that mismatched currents are dropped on average and average NMOS and PMOS Vgs voltages are produced.

15 is a circuit 1500 for phase current averaging according to an embodiment of the disclosure. It is noted that such elements of the 15 with like reference numerals (or names) as elements in other figures may operate and function in a similar manner to those already described, but are not limited thereto.

In one embodiment, circuit 1500 includes a phase combiner 1402 and an average combiner 1401 that couple together to provide iPhase and iavg signals. In one embodiment, the phase combiner 1402 includes a p-type device MPpc1 (diode connected), MPpc2, and n-type devices MNpc1 and MNpc2. In one embodiment, Vrx+ and Vrx- are received by the current sensor receiver 1106 ₁ and a corresponding iPhase is generated that is proportional to Vrx+ and Vrx-.

In one embodiment, the averaging combiner 1401 includes p-type units MPac1, MPac2, MPac3, n-type units MNacl, MNac2 and MNac3, switches Sacl, Sac2 and resistors Rac1 and Rac2. In one embodiment, MPac2 and MNac2 are diode-connected units. In one embodiment, switches Sac1 and Sac2 are phase-activated signals that are also capable of combining phase currents from different phases. In this embodiment, each phase causes a current in the diode-connected units MPac2 and MNac2, and the diode-connected units MPac2 and MNac2 are short-circuited to obtain an average current (iavg). In one embodiment, units MPac3 and MNac3 combine the streams to form iavg. In one embodiment, MPac1 and MNac1 provide the current for the phase contribution to the average signal. In one embodiment, when MPac1 and MNac1 are coupled to the rest of the phases through Sac1 and Sac2, they contribute to the average current. In one embodiment, when t MPac1 and MNac1 are decoupled, they can still cause a current in MNac2 and MPac2, but the resulting signal is not added to the overall average current. In one embodiment, resistors Rac1 and Rac2 create a low-pass filter that cancels out ripples and produces an average current that appears constant over a time frame of a switching period.

16 is a phase compensation circuit 1600a with an offset control according to an embodiment of the disclosure. It is noted that such elements of the 16 with the same reference numerals (or names) as elements from other figures operate or function in a similar manner as described there, but they are not limited thereto. 16 is similar to the exemplary embodiment 2 , except that the voltage offset (Voffset) is added or subtracted for the input coupled to the comparator 108 ₁ .

A contributor to the static phase current imbalance is the inherent input offset of the PWM comparators 108 _IN and the output offset of the current sensors themselves. To reduce this offset as much as possible, a trim mechanism called PWM trim is added to the mixer -Added resistance Rmix of each phase along the current sensors. In one embodiment, the PWM trim feeds (as described by the 17 ) a current I _,PWMTrim into the mixer resistor with a magnitude of I _,PWMTrim = -(I, _csoofset + V _offset,in /R _mix ) to eliminate any offset in the comparator 108 ₁ and a current sensor offset current. In one embodiment, I _{, cs offset} is the output offset inherent to the current sensor itself. In one embodiment, I, _{PWM Trim} is the current injected to eliminate this offset and the input offset of comparator 108 ₁ . In one embodiment, both p-type and n-type current sensors have their inputs shorted during the PWM trimming process.

17 is a high-level architecture 1700 for offset elimination of a comparator and current sensor mismatch corresponding to one Embodiment of the disclosure. It is noted that such elements of the 17 , which have the same reference numerals (or names) as elements in other figures operate or function in the same or similar manner as those described, but are not limited thereto.

In one embodiment, architecture 1700 includes a PWM current trim digital-to-analog converter (DAC) 1701; a finite state machine (FSM) 1702, a PWM comparator 108 ₁ , a current sensor and receiver 1703, a current balancing mixer Rmix1 (eg 107 ₁ ), and a circuit 1704 for providing inputs to the comparator 108 ₁ . In one embodiment, an independent architecture 1700 is used for each phase. In one embodiment, architecture 1700 is shared with all phases. In one embodiment, each PWM comparator of comparators 108 _1-N is assumed to have the same offset.

In one embodiment, architecture 1700 utilizes a negative feedback loop to minimize possible skew through continuous calibration. In one embodiment, the loop includes a DAC 1701 that either sources or sinks current through a resistor to compensate for the offset. In one embodiment, the comparison result by comparator 108 ₁ causes FSM 1702 to control DAC 1701. This forms a loop that trims the offset to 0 (or essentially zero) or trims a value that is less than an LSB (Least Significant Bit) of the DAC 1701.

In one embodiment, the PMW trim FSM 1702 first sets the wave generator 106 (shown here as circuit 1704) to a constant DC value and also connects the positive input of the comparator 108 ₁ to the DC source. In one embodiment, the Trim FSM 1702 sets the I, _PWMTrim to its largest negative value via the DAC 1701 and checks the output of the comparator 108 ₁ . In one embodiment, when the output of comparator 108 ₁ is high, FSM 1702 increments I, _PWMTrim across DAC 1701 and retests the output of comparator 108 ₁ . In one embodiment, the FSM 1702 performs this process until the output of the comparator 108 ₁ switches low. At this point, the offsets are eliminated to within LSB (Least Significant Bits) trim accuracy and the FSM 1702 stops the cycle and holds the I, _PWMTrim at its last value.

18 is a flowchart 1800 for a method for eliminating comparator offset and current sensor mismatch according to an embodiment of the disclosure.

Although the blocks in the flowchart are in the 18 are shown in a specific order, the order of actions can be changed. Therefore, the illustrated embodiment can also be executed in a different order and some actions/blocks can also be executed in parallel. Some of the blocks and/or operations included in the 18 are listed are optional according to certain exemplary embodiments. The numbering of the blocks is done for the purpose of clarity only and is not intended to impose any order on the operations in which the different blocks must appear. Additionally, operations from the different flows can be used for a variety of combinations.

In one embodiment, the input pins of comparator 108 ₁ are initialized to the same voltage (Vcc/2) when calibration starts. In one embodiment, all possible offsets are amplified and the outputs of the comparator are set to either Vcc or Vss. In one embodiment, the FSM 1702 continuously monitors the result of the comparator output and adjusts the DAC settings in a manner to reduce the skew. This process continues until the outputs of the comparator turn over, indicating an end to calibration. In one embodiment, the final offset is less than 1 LSB of the DAC 1701.

At block 1801, inputs to comparator 108 ₁ are initialized by circuit 1704 to the same voltage (eg, Vcc/2). Block 1802 indicates the possible offset of the comparator 108 ₁ and the current sensor 1702 within the PWM 102. At block 1803, the FSM 1702 compares the output of the comparator 108 ₁ with its previous state, which is indicated at block 1804. At block 1805, FSM 1702 determines whether the output of comparator 108 ₁ has transitioned or remained the same. In one embodiment, the output of the comparator 108 ₁ guides the process flow. Assuming the range of the PWM DAC 1701 is greater than a maximum possible offset, then, for example, at the largest possible negative trim current, the comparator 108 ₁ will output a high signal. In this example, with the largest possible positive trim signal, the comparator 108 ₁ outputs a low.

At block 1806, if the FSM 1702 determines that the output of the comparator 108 ₁ has transitioned (either from "0" to "1" or "1" to "0"), the FSM 1702 saves the output of the DAC 1701 .At block 1807, if the FSM 1702 determines that the output of comparator 108 ₁ remains the same (ie, the output continues to be a "1" or a "0" without making a transition relative to the previous state), then at block 1808, FSM 1702 adjusts the output current of the DAC 1701. At block 1809, the adjusted current is added to one of the inputs of the comparator 108 ₁ (e.g. via Rmix1) and the process continues until the comparator 108 ₁ changes state.

Program software code/instructions associated with the flowchart 1800 that are executed to implement embodiments of disclosed subjects may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions referred to as “program software code/instructions,” “operating system program software code/instructions,” “application program software code/instructions,” or simply “software.”

The program software code/instructions associated with the flowchart 1800 typically includes one or more instructions stored in different ways on different tangible memories or storage devices in or peripheral to a computing device that, when fetched/read and executed by the Computing device, as defined herein, causes a computing device to perform functions, functionalities, and operations necessary to carry out a method so as to execute elements involving different aspects of functions, functionalities, and operations of the method that involves one aspect of the disclosed objects.

For the purpose of disclosure, a module is a software, hardware or firmware (or combinations thereof) system, process or functionality, component thereof, the processes, features and/or functions, functionalities and/or operations described herein described, executes or implements (with or without human interaction or complementation) as carried out by the identified modules. A module can have submodules. Software components of a module can be stored on tangible machine-readable media. Modules may be integrated on one or more servers or may be loaded and executed by one or more servers. One or more modules can be combined into a machine or an application.

A tangible machine-readable medium may be used to store program software code/instructions and data that, when executed on a computing device, causes the computing device to perform a method as set forth in one or more of the appended claims relating to disclosed subject matter relate, is revealed. The tangible machine-readable medium may include storage for executable program code/instructions and may include data in various tangible locations including, for example, ROM, volatile RAM, non-volatile memory and/or cache and/or other tangible storage as referred to herein takes. Portions of this program software code/instructions and/or data may be stored in any of these memories or storage devices. Additionally, the program software code may be obtained from other storage including, for example, through a centralized server or a peer-to-peer network or the like, including the Internet. Different pieces of software program code/instructions and data may be received at different times and in different communication links or in the same communication link.

The software program code/instructions and data can be fully obtained prior to the execution of the corresponding software program or application by the computing device. Alternatively, portions of software program code/instructions and data may be obtained dynamically at the time they are needed for execution. Alternatively, combinations of these types of obtaining software program code/instructions and data may occur, such as for different applications, programs, objects, modules, routines, or other sequences of instructions or organization of sequences of instructions, to name just a few examples. Therefore, there is no requirement that data and instructions must exist on tangible machine-readable media at any given time.

Examples of tangible machine-readable media include, but are not limited to, rewritable or non-rewritable media, such as volatile and non-volatile storage devices, read-only memory (ROM), random access memory (RAM), flash memory devices, floppy and other removable disks, magnetic storage media, optical storage media (e.g., compact disk read-only memories (CDROMs), digital versatile disks (DVDs), etc.), to name a few. Software program code/instructions may be temporarily stored in digital tangible communication links during implementation mentation of electrical, optical, acoustic or other forms of propagating signals such as transmission waves, infrared signals, digital signals, etc. through such tangible communication links.

In general, a tangible machine-readable medium includes any tangible mechanism that provides (ie stores and/or transmits in digital form, e.g. data packets): information in a form that is accessible to a machine (e.g. a computing device), for example The following may include: in a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, which may or may not be capable of downloading and running applications and supporting applications of communication networks such as for example the Internet, e.g. an iPhone, Blackberry, Droid or similar or other devices, including computing devices. In one embodiment, a processor-based system (e.g. as described in the 26 is shown) in a form of or comprising a PDA, a mobile phone, a notebook computer, a tablet, a gaming console, a set-top box, an embedded system, a TV, a personal desktop computer, etc. Alternatively, traditional communication applications and supported applications are used in some embodiments of the disclosed subjects.

19 is a digital-to-analog (DAC) power converter 1900 (eg, as used in 1701) according to an embodiment of the disclosure. It is mentioned that such elements of the 19 , which have the same reference numerals (or names) as elements of other figures operate or function in a similar manner as described therein, but they are not limited thereto.

In one embodiment, the DAC 1900 includes a p-type switching network 1901 and an n-type switching network 1902 that couple together to provide an output current Iout. In one embodiment, the DAC 1900 includes switches to couple the n-type and/or p-type devices to an output node. In one embodiment, the gates of the n-type devices are coupled to the supply voltage. In one embodiment, the gates of the p-type devices are coupled to ground. In other embodiments, the gates of the n-type and/or p-type devices are biased to other voltage levels. In one embodiment, one of the source/drain terminals of the p-type devices of the network 1901 is coupled to a supply voltage and the other drain/source terminals are coupled to one of the switches s1 to s4. In one embodiment, one of the drain/source terminals of the n-type devices of the network 1902 is coupled to ground and the other drain/source terminals are coupled to one of the switches s1 to s4.

The switching networks 1901 and 1902 are designed to be controlled by binary code, but they behave as thermometer code behaves according to one embodiment. Therefore, the switching networks 1901 and 1902 enable monotonic switching and it is not necessary to have a binary-to-thermometer decoder. For example, the switching network is designed to be controlled by binary code, but it behaves like thermometer coding, i.e. low space and power consumption is achieved by DAC 1900 compared to ordinary DACs.

The exemplary embodiment of the 19 is explained in terms of p-type switch 1901. The same explanation would be applicable for an n-type switch 1902. The following embodiment uses 4 bits of binary code to control four sets of switches - s1, s2, s3 and s4. In one embodiment, s1 is controlled by LSB (Least Significant Bit) and s4 is controlled by MSB (Most Significant Bit) and where s2 and s3 are controlled by LSB+1 and LSB+2 of the binary code.

For example, if s1,s2,s3,s4={0,0,0,0}, then the output node (I-out) is three-stage if s1,s2,s3,s4={0,0,0,1 }, then the output stream Iout comes from Mpdac1; if s1,s2,s3,s4={1,0,0,1}, then the output current Iout comes from Mpdac1 and MPdac2 i.e. the output current is doubled; if s1,s2,s3,d4={1,1,0,1}, then the output current Iout comes from Mpdac1, MPdac2, and Mpdac3, i.e. the current has continued to increase monotonically; if s1,s2,s3,s4={1,1,1,1}, then the output current Iout comes from Mpdac1-8. In one embodiment, each of the Mpdac1-8 is of equal size to provide an increasing current of Iout corresponding to the binary code s1-s4.

The following exemplary embodiments describe a device and a method for compensating a reference voltage for a compensator 103.

A buck converter contains a feedback loop formed by a scan line, a compensator, a pulse width modulator (PWM), supply train signaling, etc is used to keep the output voltage Vout close to a set reference voltage Vref. The output voltage Vout is the voltage provided to a load. The compensator in the voltage mode control buck converter will usually be a classic Type 3 compensator, having either discrete or precision integrated passive resistors and capacitor components. The bandwidth of a common compensator is up to about 1 MHz. Such a common type 3 compensator is in the 20 shown. The ordinary Type 3 compensator 2000 includes an amplifier to receive a reference voltage Vref and output an output Vout through a resistor-capacitor network (R1, R3, C3). The output of the amplifier is coupled to one of the amplifier's input terminals via another resistor-capacitor network (R2, C1 and C2).

An integrated voltage regulator (IVR) compensator differs from conventional compensators in that it operates at a much higher bandwidth (e.g. greater than 100 MHz) by being subject to a much greater level of noise (coupling across the substrate, supply voltages, surrounding/crossing signals ), in that the poles and zero frequencies on the chip should be configurable over a wide range, the resistor and capacitor components have a relatively large parasitic capacitance value and resistance value and vary across the processing limits, by limiting voltage levels to the processing Vmax, which e.g. is about 1V or less in a typical digital advance process.

Some embodiments describe a complete differential design that has no (or negligible) first order sensitivities to substrate noise or noise on the scan lines or reference lines. In one embodiment, the full differential design supports output voltages higher than the process Vmax. In one embodiment, the complete differential design is configurable over a wide range of various parameters. In one embodiment, the complete differential design includes DFT (design-for-test) features for closed-loop testing (where inductors are not yet added) and for characterizing the frequency response.

21 is a differential type 3 compensator 2100 (eg, 103) according to an embodiment of the disclosure. It is noted that such elements of the 21 , which have the same reference numerals (or names) as, but are not limited to, such elements in other figures operate or function in a similar manner as described therein.

In one embodiment, the Type 3 differential compensator 2100 includes a differential amplifier (AMP), passive resistors with values R1a, R1b, duplicated passive resistors R2 and R3, duplicated passive capacitors C1, C2 and C3, and a unit gate buffer (UGB). In one embodiment, the UGB is optional. In one embodiment, R1b=R1/2 and R1a=R1.

In one embodiment, the differential inputs (signal and ground) for Vout and Vref are received by the passive units and ultimately serve as inputs to the differential amplifier. The term “dacgndsense” refers to the ground node near the DAC (e.g. DAC in NLC 102 der 25 ). The term “loadvoltagesense” refers to a node Vout near the load (e.g. Vout near the load 106 of 25 ). The term "loadgndsense" refers to a ground node near the load (e.g. the ground near the load 106 in 25 ). The term “dacvidvoltage” refers to the reference voltage Vref (e.g. as in the 25 shown).

In one embodiment, the resistance network includes passive resistors with values R1a and R1b, so that Vout = Vref x R1a/R1b. In one embodiment, (R1a/R1b)=2 to enable conditions when Vout is greater than Vccags, where Vccags is an analog power supply. In other embodiments, other ratios for R 1 a/R 1 b can be used.

In one embodiment, the duplicated passive units (ie, R2, R2, C21, C2, and C3) are coupled together as described in FIG 21 is shown. In one embodiment, the coupling of the duplicated passive units is such that the frequency response (ie, Vout/Vfb) is preserved. In one embodiment, the coupling of the duplicated passive devices is such that any common mode noise on voltage_sense/ground_sense or reference_voltage/reference_ground node is eliminated.

In one embodiment, the coupling of the duplicated passive units is such that any substrate or supply noise coupling to the amplifier (AMP) via parasitic passive elements causes nearly identical positive and negative inputs, such that there is no net effect (or substantially zero effect) on Vfb. In one embodiment, the passi ven units trimmed to ensure that each RC time constant has approximately a target value regardless of process variation, such as systematic process variation.

In one embodiment, UGB is used to reduce the capacitive load on the amplifier output. In such an embodiment, a single-stage amplifier design can be used for the differential amplifier to obtain phase gains. In one embodiment, a multiple design for an amplifier with a gated output stage is used so that the compensator bandwidth can be configured to reduce power consumption.

22 is a frequency response 2200 of the Type 3 differential compensator according to an embodiment of the disclosure. It is noted that such elements of the 22 with the same reference numerals (or names) as elements in other figures operate or function in a similar manner to those described, but are not limited thereto.

$${\omega }_{z2}\approx \frac{1}{R_1{C}_3}$$

$${\omega }_{p1}\approx \frac{1}{R_2{C}_2}$$

$${\omega }_{p2}=\frac{1}{R_2{C}_3}$$

The frequency response 2200 has two plots. The top plot shows gain (i.e. R2/R1) in dB as a function of frequency. The bottom plot shows a phase angle in degrees versus frequency. The vertical dotted lines show that the maximum phase increase occurs at frequencies that are approximately a power of ten larger than ω _z2 and approximately a power of ten smaller than ω _p1 , where: $${\omega }_{\mathrm{e.g}l}=\frac{1}{R_2{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="DE102014019830B4\_0005.png,DE102014019830B4\_0012.png"\; state="\{\{state\}\}">C</figure-callout>}}_1}$$

$${\omega }_{\mathrm{e.g}2}\approx \frac{1}{R_1{\mathrm{<figure-callout\; id="3"\; label="C"\; filenames="DE102014019830B4\_0007.png,DE102014019830B4\_0013.png"\; state="\{\{state\}\}">C</figure-callout>}}_3}$$

$${\mathrm{<figure-callout\; id="1"\; label="\omega \; p"\; filenames="DE102014019830B4\_0005.png,DE102014019830B4\_0012.png"\; state="\{\{state\}\}">\omega </figure-callout>}}_p\approx \frac{1}{R_2{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102014019830B4\_0005.png,DE102014019830B4\_0007.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}$$

$${\mathrm{<figure-callout\; id="2"\; label="\omega \; p"\; filenames="DE102014019830B4\_0005.png,DE102014019830B4\_0007.png"\; state="\{\{state\}\}">\omega </figure-callout>}}_p=\frac{1}{R_2{\mathrm{<figure-callout\; id="3"\; label="C"\; filenames="DE102014019830B4\_0007.png,DE102014019830B4\_0013.png"\; state="\{\{state\}\}">C</figure-callout>}}_3}$$

23 shows the Type 3 differential compensator 2300 with DFT (Design for Test) features and configuration schemes according to an embodiment of the disclosure. It is noted that such elements of the 23 with the same reference numerals (or names) as elements of other figures operate or function in a similar manner as described, but are not limited thereto.

In one embodiment, an input is coupled to a pilot bridge, producing an output voltage Vpilot=D*Vin/3, where D is the PWM (pulse width modulated) duty cycle, so that the feedback loop (of the voltage regulator) can be closed during testing to enable structural testing without inductors. In one embodiment, a pair of digitally controlled current sources are coupled to voltage and mass sense inputs so that an I*R drop on the sensor lines (and/or optionally on small series resistors) has the effect of adding voltage to Vout.

In one embodiment, this voltage may have a periodic waveform, such as a square wave, which may be configured in frequency and amplitude. The response of Vout to this voltage (closed loop response) can be used to characterize the VR open loop transfer function. In one embodiment, the UGB is used to generate a copy of the compensator output Vfb for analog probing (without unnecessary loading of Vfb).

24 shows a pilot bridge 2400 according to an embodiment of the disclosure. It is noted that such elements of the 24 , which have the same reference numerals (or names) as elements in other figures, operate or function in a similar manner as described, but are not limited thereto.

In one embodiment, the pilot bridge 2400 is a small copy of a supply string, with the inductance replaced by a resistor (Ra+Rb). In one embodiment, resistors Ra prevent a short circuit between the NMOS and PMOS devices that couple to the resistor Rb. In one embodiment, resistor Rc is used to scale the pilot bridge output voltage vpilot by Rc/(Ra+Rb+Rc), but this is optional. In one embodiment, the scaling factor is 1/3. In another exemplary embodiment, the scaling factor can be chosen differently. In one embodiment, the capacitor Cfilter reduces the waves to vpilot, which is optional (since junction parasitic capacitances may be sufficient).

In one embodiment, the average of vpilot for a given PWM duty cycle D is given by vpilot=Vccin*D*(Rc/(Ra+Rb+Rc)). This is used for testing rather than an actual output voltage (Vccin*D) when inductors are not present or when the supply string is not active. In one embodiment, the outputs (of the pilot bridges) for all phases in a domain are coupled in parallel, so that vpilot is the average of all pilot bridge outputs of all phases.

25 shows a portion of a voltage regulation device 2500 with the differential type 3 compensator according to an embodiment of the disclosure. It is mentioned that such elements of the 25 with the same reference numerals (or names) as, but are not limited to, such elements of other figures operate or function in a similar manner as described.

In one embodiment, the device 2500 includes a bridge controller 105 ₁ , high-side switches MPs, low-side switches MNs while being part of 101 ₁ , a main inductor L1, a load capacitance C, an NLC unit 2502, override logic 2503, a comparator 108 ₁ , a compensator 2505, a load 2506, a remix resistor and a wave generator 106.

In one embodiment, the bridge controller 105 controls ₁ to turn on and/or turn off high-side and low-side switches (MPs and MNs) via gate control signals corresponding to np and nn. In one embodiment, the low-side switch is replaced by a diode. In a normal voltage regulation operation, the bridge controller 105 ₁ receives an output from the comparator 108 ₁ to determine when to turn on and/or turn off the high-side and low-side switches (MPs and MNs).

For example, the comparator 108 ₁ compares a modulated wave generated by the wave generator 106 with a reference voltage (eg, Vref_s) to generate a switching signal, the switching signal indicating when the modulated wave is above or below the reference voltage Vref_s. In normal operation, the override logic 2503 behaves like a buffer and passes the output of the comparator 108 ₁ to the bridge controller 105 ₁ . The term "normal operation" generally refers to a stable voltage and current drawn by the load 2506, that is, when the output voltage does not drop. Normal operation is different from a voltage drop situation when the load 2506 suddenly draws more current, causing a voltage drop in Vout.

In one embodiment, the high-side switch MPs and the low-side switch MNs form the bridge of the voltage regulator. In one embodiment, the low-side switch MNs is replaced by a diode. In such an embodiment, the bridge controller 105 ₁ effectively controls the output voltage by turning on and off the high-side switch MPs. In one embodiment, the bridge receives an input supply voltage Vin and produces a regulated output voltage Vout for the load 2506. In one embodiment, switching the current across the main inductor L1 and charging/discharging the capacitor C through the bridge leaves Vout stable.

In one embodiment, when a voltage drop occurs in Vout, the NLC unit 2502 detects the voltage drop relative to a reference voltage and generates a trigger signal (also referred to as an NLC fired signal). In one embodiment, confirmation of the trigger signal activates the override logic 2503 to bypass an output of the comparator 108 ₁ and directly controls the bridge controller 105 ₁ . In one embodiment, the override logic 2503 is coupled to the comparator 108 ₁ and the bridge controller 105 ₁ . In one embodiment, override logic 2503 performs an OR logic function on the outputs of comparator 108 ₁ and the trigger signal. In another embodiment, the override logic 2503 is an OR gate. In other embodiments, override logic 2503 is any logic gate configured to override the output of comparator 108 ₁ in response to an assertion of the trigger signal.

In one embodiment, when the trigger signal is asserted (ie, when a voltage drop in Vout is detected by the NLC unit 2502), the high-side switch MPs is turned on and the low-side switch MNs is turned off. In one embodiment, the trigger signal is a pulse signal with a pulse width that indicates a duration of the voltage drop. In one embodiment, the pulse width of the trigger signal is adjustable by a pulse adjuster (not shown). In such an embodiment, the high-side switch MPs is turned on and the low-side switch MNs is turned off for the duration of the pulse width of the trigger signal. In one embodiment, if the trigger signal is not asserted, the override logic 2503 allows the output of the comparator 108 ₁ to continue to control the bridge controller 105 ₁ . In one embodiment, the NLC unit 2402 is an alternating current (AC) coupled to Vout to generate the trigger signal.

In one embodiment, the output voltage Vout is received by the compensator 2505. In one embodiment, compensator 2505 scales reference voltage Vref as Vref_s for comparator 108 ₁ . In one embodiment, compensator 2505 includes a comparator 2409 that couples to passive units 2510 as shown. In an execution case game, the passive units 2510 receive the output voltage Vout. In one embodiment, compensator 2505 adjusts Vref_s in response to a voltage drop in Vout so that when the drop ends, override logic 2503 allows output from comparator 108 ₁ to control bridge controller 105 ₁ with Vout at its normal voltage level as stable as possible reached.

In one embodiment, the compensator 2505 provides feedback and transfer functionality necessary to stabilize the VR system such that nominal Vout is substantially equal to Vref while accounting for steady state load and low frequency transient load conditions. In one embodiment, the transfer function of the compensator 2505 is used to optimally set the transfer function of the VR loop.

In one embodiment, wave generator 106 generates a triangular wave for comparator 108 ₁ . The output of comparator 108 ₁ is a pulse width modulated (PWM) signal. In one embodiment, an Rmix resistor is used to subtract Iavg from Iphase, as described in other embodiments. In one embodiment, device 2505 includes circuitry for eliminating offset of comparator 108 ₁ . In one embodiment, an Rmix resistor is used to achieve phase current balancing for buck VRs. In one embodiment, current is injected or withdrawn from various points on a potentiometer (e.g., adjustable resistor); this shifts the average output voltage from wave generator 106 as seen by comparator 108 ₁ .

In order not to use the exemplary embodiment of the 6 To cover up, a bridge controller 105 ₁ , a set of high-side and low-side switches (MPs and MNs), and a main inductor L1 are shown. However, embodiments may be operated with multiple bridge controllers, each controlling its own set of bridges (ie, high-side and low-side switches) coupled to its own inductor or to a main inductor L1, ie, a multi-phase Buck VR. In such an embodiment, multiple comparators are used so that each comparator drives one bridge example or “phase”. In one embodiment, the output from each of the plurality of comparators 108 ₁ is received by override logic 2503, which is used to override the output of the comparators when the voltage drop has been detected by the NLC 2502. In such an embodiment, all of the bridge controllers turn their respective high -side switches on and turn off their low-side switches during the voltage drop of Vout. In this embodiment, the wave generator 106 generates multiple waves that are essentially identical except for a phase offset. In one embodiment, each phase is specially trimmed via Rmix.

In one embodiment, during low voltage operation of the device 2500 having multi-phase bridge drivers, where some of the phases are turned off to save power (e.g., such bridge drivers are not) and some phases are turned on to produce Vout with a low current demand when on When the voltage drop in Vout is detected by the NLC unit 2502, the bridges that are turned off (to save power) are forced on by the cancellation logic 2503 to alleviate the voltage drop effect. In one embodiment, not all of the switched off bridges are forced on, but rather the phases (i.e. bridges that generate the phases) that have already been activated are forced on.

26 is a smart device or a computer system or a SoC (system on a chip) 1600 with one or more circuits and methods as described in relation to 1 to 25 have been described, corresponding to an exemplary embodiment of the disclosure. It is noted that such elements of the 26 with the same reference numerals (or names) as such elements in other figures operate or may function in a similar manner as described, but are not limited thereto.

26 shows a block diagram of an embodiment of a mobile device in which flat surface interface connectors may be used. In one embodiment, computing device 1600 represents a mobile computer, such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, or other wireless mobile devices. It is to be understood that certain components are shown generally and not all components of such a device are shown in the computing device 1600.

In one embodiment, the computing device 1600 includes a first processor 1610 with one or more circuits and methods as described with respect to the embodiments of FIG 1-25 were described. Other blocks of the computing device 1600 may also be included with one or more circuits or methods as described with respect to the exemplary embodiments the 1 to 25 were described. The various embodiments of the present disclosure may also include a network interface, within 1670, such as a wireless interface, such that a system embodiment may be incorporated into a wireless device, such as a cell phone or personal digital assistant.

In one embodiment, processor 1610 (or processor 1690) may include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by the processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connections of the computing device 1600 to other devices. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, the computing device 1600 includes an audio subsystem 1620, which represents hardware (such as audio hardware or audio circuitry) and software (e.g., drivers, codecs) components associated with provided audio functions of the computing device. The audio functions may include speaker and/or headphone outputs, as well as microphone inputs. Devices for such functions may be integrated into the computing device 1600 or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by the processor 1610.

The display subsystem 1630 represents hardware (e.g., a display device) or software (e.g., driver) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. The display subsystem 1630 includes a display interface 1632 that particular display or the hardware device used to provide a display to the user. In one embodiment, the display interface 1632 includes logic separate from the processor 1610 to perform at least some processing-related steps related to the display. In one embodiment, the display subsystem 1630 includes a touchscreen (or touchpad) device that provides output and input to a user.

I/O controllers 1640 represent hardware devices and software components for interacting with a user. The I/O controller 1640 is designed to manage hardware that is part of the audio subsystem 1620 and/or the display subsystem 1630. Additionally, the I/O controller 1640 provides a connection point for additional devices that can be connected to the computing device 1600 through which a user can interact with the system. For example, devices connected to computing device 1600 may include a microphone device, speakers or stereo systems, video systems or other display devices, a keyboard, or keypad device, or other I/O devices for use in specific applications, such as a card reader or other devices.

As mentioned above, the I/O controller 1640 can interact with the audio subsystem 1620 and/or the display subsystem 1630. For example, input via a microphone or other audio device may represent input or instruction for one or more applications or functions of computing device 1600. Additionally, audio output may be provided instead of or in addition to the display output. In another example, the display subsystem 1630 includes a touch screen, the display device also serving as an input device that may be at least partially managed by the I/O controller 1640. Additional buttons or switches may also be provided on the computing device 1600 to provide I/O functions for managing the I/O controller 1640.

In one embodiment, the I/O controller 1640 manages devices such as accelerators, cameras, light sensors or other environmental sensors or other hardware that may be integrated into the computing device 1600. The input may be part of direct user interaction as well as providing environmental input to the system to influence its operations (such as filtering noise, adjusting displays for brightness detection, applying a flash to a camera, or other features). .

In one embodiment, computing device 1600 includes power management 1650 that manages battery power usage, manages battery charging, and manages features related to a power saving option. The storage subsystem 1660 includes storage devices for storing information in the computer system advises 1600. The memory may include non-volatile (the state does not change when the power to the memory is interrupted) and/or volatile (the state is no longer determined when the power to the memory is interrupted) storage devices. The storage subsystem 1660 may store application data, user data, music, photos, documents, and other data, as well as store system data (whether long-lived or temporary) related to executing applications and functions on the computing device 1600.

Elements of embodiments may also be provided as a machine-readable medium (e.g., memory 1660) for storing computer-readable instructions (e.g., instructions for implementing any method as previously discussed). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMS, DVD-ROMs, RAMs, EPROMS, EEPROMS, magnetic or optical cards, phase change memory (PCM), others Types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may also be downloaded as a computer program (e.g., BIOS) downloaded from a remote computer (e.g., a server) in response to a request from the computer (e.g., a client) using data signals over a communication link (e.g., a modem or a network connection).

The connection 1670 includes hardware devices (e.g., wireless and/or wired connectors and communications hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 may include separate devices, such as other computing devices, wireless access points or base stations, as well as peripheral devices such as a headset, printer, or other devices.

Network capability 1670 may also include several different types of network capability. In general, the computing device 1600 is shown having a mobile network capability 1672 and a wireless network capability 1674. The mobile network capability 1672 generally refers to a cellular network capability provided by a wireless carrier, such as over GSM (Global System of Mobile Communications) or Variations or derivatives thereof, CDMA (Code Divisional Multiple Access) or variations and derivatives thereof, TDM (Time Divisional Multiplexing) or variations or derivatives thereof, or other mobile service standards. A wireless networking capability (or a wireless interface) 1674 refers to a wireless networking capability that is non-cellular and, for example, a personal area network (such as Bluetooth or Near Field, etc.), local area network (such as Wi-Fi), and /or wide area networks (such as WiMax) or other wireless communication.

Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to enable peripheral connections. It is understood that the computing device 1600 may be both a peripheral device (“to” 1680) to other computing devices, as well as having peripheral devices (“from” 1682) connected to it. The computing device 1600 typically has a “docking” port for connecting to other computing devices for the purpose of managing (e.g., downloading and/or uploading, modifying and synchronizing) content on the computing device 1600. Additionally, a docking port may allow that the computing device 1600 is connected to certain peripheral devices that allow the computing device 1600 to control the content of the output, such as the audio visual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 may establish peripheral connections 1680 via common or standards-based connectors. Common types include a universal serial bus (USB) port (which may be included in any of different hardware interfaces), a display port including a MiniDisplayPort (MDP), high-resolution multimedia interfaces (HDMI), Firewire, or other types.

In the description, reference is made to “one embodiment,” “some embodiments,” or “other embodiments,” meaning that the particular features, structures, or characteristics described in connection with the embodiment are included in at least one other embodiment , but not necessarily in all embodiments. The different occurrences of “an embodiment,” or “some embodiments” do not necessarily refer to the same embodiments. If the description represents a component, feature, structure or characteristic by including "may", "could" or "may", this means that the particular component, feature, structure or characteristic is not necessarily included. If the description or claims refer to “one” element, this does not mean that only one element is present. If the description or claims refer to “an additional” element, this does not exclude the possibility that there are more than one additional element.

Additionally, the particular features, structures, functions, or characteristics may be combined in any desired manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment whenever the particular features, structures, or functions or characteristics associated with the two embodiments are not mutually exclusive.

While the disclosure has been described in connection with specific embodiments, it is apparent that many alternatives, modifications, or variations of such embodiments will be apparent to one skilled in the art in light of the foregoing description. For example, other memory architectures such as dynamic RAM (DRAM) may be used in the embodiments discussed. The exemplary embodiments of the disclosure are not intended to describe all possible alternatives, modifications and variations that fall within the broad scope of the appended claims.

Additionally, known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown in the illustrated figures to simplify illustration and discussion and not to obscure the disclosure. Additionally, arrangements are shown in block diagram form to avoid obscuring the disclosure and also for the reason that the specifics relating to the implementation of such block diagram arrangements are highly dependent on the platform within which the present disclosure is to be implemented ( i.e. such specifics should be within the discretion of an expert). Where specific details (e.g., circuits) have been set forth to describe an exemplary embodiment of the disclosure, it will be apparent to one skilled in the art that the disclosure may be embodied without or with variations of the specific details. The description should therefore be viewed as illustrative rather than limiting.

The following examples refer to further exemplary embodiments. Special features in the examples can be used in each of the exemplary embodiments mentioned. Any optional features of the device as described herein may also be implemented in terms of a method or process.

For example, in one embodiment, a device includes: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor of the plurality of inductors; and a plurality of current sensors, each coupled to a bridge for sensing current through a transistor of the bridge. In one embodiment, the device further comprises a circuit for generating an average current using the sampled current from each of the multiple current sensors. In one embodiment, the device further comprises: a wave generator for generating a plurality of wave signals; a plurality of comparators for generating a plurality of phase width modulated (PWM) signals; and a plurality of resistors, each of which is coupled to a comparator of the plurality of comparators and coupled to the wave generator.

In one embodiment, each resistor of the plurality of resistors is configured to generate a fault current from a difference of the average current and a corresponding sampled current of the bridge. In one embodiment, each resistor of the plurality of resistors is configured to generate a direct current (DC) voltage for adjusting a DC level of a wave signal among the plurality of wave signals. In one embodiment, each comparator is configured to adjust a duty cycle of its generated PWM signal according to the DC voltage generated by the resistor coupled to the comparator.

In one embodiment, the wave generator is designed to generate a plurality of wave signals, which are triangular waves. In one embodiment, the apparatus further includes circuitry for eliminating an input offset for each comparator of the plurality of comparators. In one embodiment, an overcurrent safety circuit is further included for receiving the average current and generating an overcurrent safety signal corresponding to the average current. In one embodiment, the device further comprises a power control unit (PCU) for obtaining the average current.

In one embodiment, the current sensor includes: a first current sensor for sensing the current through a high-side switch of the bridge; and a second current sensor for sensing the current through a low-side switch of the bridge. In one embodiment, the first and second current sensors include a common gate amplifier. In one embodiment, each of the first and second current sensors is configured to generate a corresponding differential current output.

In one embodiment, the device further includes a circuit for converting the corresponding differential current output into a corresponding single-ended current output. In one embodiment, the first current sensor is coupled to the second current sensor to generate a combined differential current output. In one embodiment, the device further includes circuitry for converting the combined differential current output into a single-ended current output.

In another example of an embodiment, a system includes: a storage device; a processor coupling to the memory device, the processor comprising: a plurality of inductors coupling to a capacitor and a load; and a plurality of bridges, each of which is coupled to a corresponding inductance of a plurality of the inductors; and a plurality of current sensors, each coupled to a bridge for sensing current through a transistor of the bridge; and a wireless interface for allowing the processor to communicate with other devices.

In one embodiment, the system further comprises a display unit. In one embodiment, the processor further comprises: a circuit for generating an average current using the sampled current from each of the plurality of current sensors; a wave generator for generating a plurality of wave signals; a plurality of comparators for generating a plurality of phase width modulated (PWM) signals; and a plurality of resistors, each coupled to one of the plurality of comparators, and coupled to the wave generator. In one embodiment, each of the plurality of resistors is configured to generate a fault current from a difference of the average current and a corresponding sampled current of the bridge.

In another example, in an embodiment, the current digital-to-analog converter (DAC) includes: a plurality of n-type devices (units), control contact terminals thereof coupled to a first control signal, wherein a Source terminal of each of the n-type devices is coupled to a ground; and a plurality of switches for coupling the sink terminals of some or all of the n-type devices together to generate a first current signal.

In one embodiment, the power DAC further comprises: a plurality of p-type devices, control contact terminals thereof coupled to a second control signal, the source terminal of each of the p-type devices coupled to a power supply; and a plurality of switches for coupling the drain terminals of some or all of the p-type devices to each other and generating a second output current. In one embodiment, the power DAC further includes: an output node for coupling the first and second power outputs.

In one embodiment, the plurality of p-type and n-type devices are controlled by digital signals to cause each of the plurality of p-type and n-type devices to be turned off or on. In one embodiment, the digital signals are a binary code, with the output node configured to produce a monotonic change in the stream corresponding to the binary code.

A summary is provided and will allow the reader to appreciate the nature and spirit of the technical disclosure. The summary is submitted with the understanding that it cannot be used to limit the scope or meaning of the claims. The following claims, which are hereby incorporated into the detailed description, stand alone and as separate embodiments.

Claims (4)

A current-to-digital-to-analog converter, DAC (1900), comprising: a plurality of n-type devices having gates coupled to a first bias voltage, the source of each of the n-type devices coupled to ground; a first plurality of switches operable to couple the drains of some or all of the n-type devices together to produce a first output current whose magnitude depends on the number of n-type devices electrically coupled together , a plurality of transistor devices, whose Gate terminals are coupled to a second bias voltage; and a second plurality of switches operable to couple the drains of some or all of the transistor devices together to produce a second output current, the magnitude of which depends on the number of the transistor devices electrically coupled together. Power DAC after Claim 1 which further comprises: an output node for coupling the first and second power outputs. Power DAC according to one of the Claims 1 or 2 , wherein the first and second pluralities of switches are controlled by digital signals. Power DAC after Claim 3 , where the digital signals are a binary code and where the output node produces a monotonic current change corresponding to the binary code.

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