DE102014014677B4 - Process for the generation of PWM-modulated signals for the supply of LEDs for lighting in vehicles - Google Patents

Abstract

Method for generating two, in particular n, PWM spread codes, in particular for use in a DC voltage supply and/or a DC/DC converter, in particular for supplying LEDs with electrical energy, in particular in motor vehicles, with n being a positive integer number and n>1, for generating a PDM output signal (PDMout) with an optimized PDM spectrum and with a specified PDM fill factor (fcycle), the abbreviation PDM being understood as pulse density modulation, comprising the steps a. generating a first PWM signal (PDM1) with a PWM period (TPDM) and the PWM fill factor (fcycle) andb. Generating at least one, in particular n-1, further PDM signals (PDM2, second PDM signal to PDMn, nth PDM signal), with n as a positive integer and n>1, in particular by delaying the first PDM Signals (PDMi), undi. wherein each ith PWM signal (PDM1) with 1<i≤n, if generated, is delayed relative to the first signal (PDM1) by a temporal ith offset (Toff_i) relative to the first PWM signal (PDM1), andii . each of the generated, in particular n, PDM signals (PDM1 to PDMn) representing one of the generated, in particular n, PDM spread codes.

Description

Introduction

The present application refers to the German prior application 10 2013 016 386.2 dated September 30, 2013, the contents of which are hereby made the subject of the present application in their entirety.

In the said German pre-registration DE 10 2013 016 386.2 describes, among other things, that the activation of consumers can be modulated with the help of spread codes, which are predefined and sequentially activate a switching element (M) with the help of a PWM output signal (PWM _out ) or a PWM output signal (PDM _out ). That in the pre-registration DE 10 2013 016 386.2 The method described has the advantage that the spectra of the PWM output signal (PWM _out ) or of the PWM output signal (PDM _out ) can be checked well. The disadvantage of the method is the immense storage space that the spread codes require in order to be able to hold available for all fill factors defined there if the PWM or PDM resolution is to be more than 4 bits. As can be easily understood, if the resolution is to be 1 bit, the memory requirement increases with the 1st power of 2.

The U.S. 8,129,924 B2 already discloses a current source for an LED which is controlled by a stochastic signal density modulator. The value of a signal density register is compared with the value of a stochastic state machine.

object of the invention

It is therefore the object of the invention described here to provide a simplified method for generating two or more PWM spread codes or PWM spread code signals for PWM modulation or two or more PWM spread codes or Specify PDM spreading code signals for PDM modulation that produce a spectrum that is as flat as possible and result in few peaks in the spectrum, so keeping your code table (CTAB) as in the disclosure DE 10 2013 016 386.2 can be omitted.

This object is achieved with the aid of methods according to claims 1 and 3.

Description of the invention

When examining suitable PWM spread codes for an application in the German patent application DE 10 2013 016 386 A1 The technique described on Pulse Width Modulation (PWM) has shown that some PWM spreading codes are more suitable than others to optimize the spectrum. The same applies to the application in the German patent application DE 10 2013 016 386 A1 described technique on pulse density modulation (PDM).

The disclosure content and technical content of the application DE102013016386.2 is an integral part of this application and is assumed here as part of the description of this disclosure. The claims are decisive for the claimed extent. The description is for explanation only.

The first part of the description goes into the generation of optimal PWM spread codes for pulse width modulation (PWM modulation), since this is easier for the reader to understand.

In a second part, the description goes into the generation of PDM spread codes for pulse density modulation (PDM modulation) and their use.

However, the statements of both parts refer to the PDM and PWM modulation at the same time and can be applied by analogous transfer.

First part: Generation of PWM spread codes and their application

The invention is based on the finding that good PWM spread codes, ie PWM spread codes that generate a very flat spectrum with few spikes, have certain symmetries.

It has been shown that in the simplest case, two PWM spread code signals (PWM ₁ , PWM ₂ ) are generated, each of which is a normal PWM signal with the common specified PWM period T _PWM . These two PWM signals, the first PWM signal (PWM ₁ ) and the second PWM signal (PWM ₂ ), preferably have the same fill factor, which means that their duty cycle (f _cycle ), typically given in % , is equal to. Typically, the first PWM signal (PWM ₁ ) is generated by a first PWM signal generator (PWMG ₁ ) and the second PWM signal (PWM ₂ ) is generated by a second PWM signal generator (PWMG ₂ ). The two PWM signals (PWM ₁ , PWM ₂ ) preferably have a fixed phase shift relative to one another. The period of the second PWM signal (PWM ₂ ) is shifted by a time, a second offset (T _{off_2} ) compared to the first PWM signal (PWM ₁ ). The two PWM signals (PWM ₁ , PWM ₂ ) otherwise chosen the same. The first PWM signal (PWM ₁ ) can thus be mapped to the second PWM signal (PWM ₂ ) by a time shift by said second offset (T _{off_2} ). The PWM output signal (PWM _out ) can then be formed by switching between these two PWM signals (PWM ₁ and PWM ₂ ), for example by means of a multiplexer (MUX) as a selection device. In this case, the selection device (MUX) is controlled by a selection signal (PWM _select ), the nature of which will be discussed in more detail later. For the sake of simplicity, it should first be assumed that the selection is random.

It has been shown as part of the investigations that led to the invention, that a delay of the second PWM signal (PWM ₂ ) compared to the first PWM signal (PWM ₁ ) by half the PWM period (T _PWM ) to a particularly favorable spectrum of the PWM output signal (PWM _out ).

• (1) Erzeugen eines ersten PWM-Signals (PWM₁) mit einer PWM-Periodendauer (T_PWM) und dem PWM-Duty-Cycle (f_cycle) und
• (2) Erzeugen eines zweiten PWM-Signals (PWM₂) durch Verzögerung des ersten PWM-Signals (PWM₁) beispielsweise in einer Verzögerungsstrecke (ΔT, ΔT₂) um vorzugsweise die Hälfte der PWM-Periode (T_PWM) wobei jedes der beiden erzeugten PWM-Signale (PWM₁, PWM₂) je einen der beiden erzeugten PWM-Spreiz-Codes als erstes bzw. zweites PWM-Spreiz-Code-Signal repräsentiert.

The method on which the invention is based for generating two PWM spread codes, the PWM signals (PWM ₁ , PWM ₂ ) for generating a PWM output signal (PWM _out ) with an optimized PWM spectrum and with a specified PWM duty -Cycle (f _cycle ), thus includes the steps

• (1) generating a first PWM signal (PWM ₁ ) with a PWM period (T _PWM ) and the PWM duty cycle (f _cycle ) and
• (2) Generate a second PWM signal (PWM ₂ ) by delaying the first PWM signal (PWM ₁ ), for example in a delay path (ΔT, ΔT ₂ ) by preferably half the PWM period (T _PWM ), each of the two generated PWM signals (PWM ₁ , PWM ₂ ) each represents one of the two generated PWM spread codes as the first or second PWM spread code signal.

The method can of course be generalized to n PWM spreading codes, where n is a positive integer greater than 1.

It has been shown that in this more general case, n PWM spread code signals (PWM ₁ to PWM _n ) are generated, each of which is a normal PWM signal with the common specified PWM period T _PWM . These n PWM signals, the first PWM signal (PWM ₁ ) to the nth PWM signal (PWM _n ), preferably again have the same fill factor, which means that their duty cycle (f _cycle ), typically given in %, equals. Typically, the first PWM signal (PWM ₁ ) is generated by a first PWM signal generator (PWMG ₁ ) and the n-1 further PWM signals (PWM ₂ to PWM _n ) are generated by further PWM signal generators (PWMG ₂ to PWMG _n ). . In this case, the n PWM signals again preferably have a fixed time phase shift relative to one another. The period of an i-th PWM signal (PWM _i ) with 2≤i≤n, which is one of the n-1 further PWM signals (PWM ₂ to PWM _n ), is by a time, an i Tenth offset (T _{off_i} ), compared to the first PWM signal (PWM ₁ ) shifted. Preferably, all n PWM signals (PWM ₁ to PWM _n ) are otherwise chosen to be the same. An i-th PWM signal (PWM _{1 ) can thus be mapped to the first PWM signal (PWM 1 )} by a time shift by said i-th offset (T _{off_i} ). The PWM output signal (PWM _out ) can then be formed again by switching between these n PWM signals (PWM ₁ to PWM _n ), for example using an n to 1 multiplexer (MUX) as a selection device. In this case, the selection device (MUX) is again controlled by the selection signal (PWM _select ), the nature of which will be discussed in more detail later. For the sake of simplicity, it should first be assumed here that the selection is random.

It has been shown within the scope of the investigations that led to the invention that a delay in an i-th PWM signal (PWM ₁ ) compared to the first PWM signal (PWM ₁ ) by a time that (i-1)/ n is the PWM period (T _PWM ), leads to a particularly favorable spectrum of the PWM output signal (PWM _out ).

• (1) Erzeugen eines ersten PWM-Signals (PWM₁) mit einer PWM-Periodendauer (T_PWM) und dem PWM-Duty-Cycle (f_cycle) und
• (2) Erzeugen von n-1 weiteren PWM-Signalen (PWM₂, zweites PWM-Signal bis PWM_n, n-tes-PWM-Signal), mit n als ganzer positiver Zahl und n>1, vorzugsweise durch Verzögerung in n-1 Verzögerungsstrecken (ΔT₂ bis ΔT_n) um vorzugsweise jeweils (i-1)/n der PWM-Periode (T_PWM), wobei i die Nummer des i-ten PWM-Signals (PWM₁) repräsentiert, aus diesen n-1 PWM-Signalen (PWM₂ bis PWM_n) wobei jedes der beiden erzeugten n PWM-Signale (PWM₁ bis PWM_n) je einen der n erzeugten PWM-Spreiz-Codes als erstes bis n-tes PWM-Spreiz-Code-Signal repräsentiert.

The method according to the invention is then a method for generating n PWM spread codes, with n being a positive integer and n>1, for generating a PWM output signal (PWM _out ) with an optimized PWM spectrum and with a predetermined PWM -Duty Cycle (f _cycle ). It then includes the steps

• (1) generating a first PWM signal (PWM ₁ ) with a PWM period (T _PWM ) and the PWM duty cycle (f _cycle ) and
• (2) Generate n-1 further PWM signals (PWM ₂ , second PWM signal to PWM _n , nth PWM signal), with n as a positive integer and n>1, preferably by delay in n- 1 delay sections (ΔT ₂ to ΔT _n ) by preferably (i-1)/n of the PWM period (T _PWM ), where i represents the number of the i-th PWM signal (PWM ₁ ), from these n-1 PWM signals (PWM ₂ to PWM _n ), each of the two generated n PWM signals (PWM ₁ to PWM _n ) representing one of the n generated PWM spread codes as the first to n-th PWM spread code signal .

This generation can return to the first, for example by delaying the first PWM signal (PWM ₁ ) in n-1 delay devices (ΔT ₂ to ΔT _n ) take place. Each of the n-1 PWM signals is typically delayed differently. In the following we speak of the i-th PWM signal (PWM _i ) when we mean one of the other PWM signals (PWM ₂ to PWM _n ). Thus, each ith PWM signal (PWM ₁ ) with 1<i≤n, if generated, is compared to the first PWM signal (PWM ₁ ) by a temporal ith offset (T _{off_i} ), which is specific to the respective i-th PWM signal (PWM ₁ ) is delayed compared to the first PWM signal (PWM ₁ ). In this case, each of the n PWM signals generated (PWM ₁ to PWM _n ) represents one of the n PWM spread codes generated and in the form of n PWM spread code signals.

In order to generate a PWM output signal (PWM _out ) from the PWM spread code signals defined in this way, the n PWM signals (PWM ₁ to PWM _n ), a selection device, typically an n to 1 multiplexer (MUX) , one of the n PWM signals (PWM ₁ to PWM _n ) as the kth PWM signal (PWM _k ) that is then converted to the PWM output signal (PWM _out ) by means of an output stage (PA). This output stage (PA) adjusts the level and possibly the signal form in such a way that the resulting PWM output signal (PWM _out ) is suitable for a subsequent switching device (M). at. It is typically a switching device (M) which is switched “on” and “off”, for example, by means of the kth PWM signal (PWM _k ).

The kth PWM signal (PWM _k ) is preferably selected from the n PWM signals (PWM ₁ to PWM _n ) as the current PWM spread code signal at the beginning of a PWM period of the first PWM signal (PWM ₁ ). Also preferably, the PWM spreading code is not changed during a PWM period having a PWM period duration T _PWM . This means that the next change takes place at the earliest after a PWM period (T _PWM ) or an integer positive multiple thereof. The factor is denoted by m below.

The first selection of a PWM signal (PWM ₁ to PWM _n ) as a PWM spread code in the form of the current spread code signal, the k-th PWM signal (PWM _k ), following the second, next selection of a PWM spread codes are thus preferably carried out at the beginning of a PWM period of the first PWM signal (PWM ₁ ) after m PWM periods (T _PWM ), with m being a positive integer.

The first selection of the spreading code signal from the PWM signals (PWM ₁ to PWM _n ) occurs at a first spreading code selection time (Tscsi), which is typically a time at the beginning of a PWM period of the first PWM signal ( PWM ₁ ) is. The following next selection of a PWM spread code then takes place at an immediately following second spread code selection time (T _SCS2 ) at the beginning of a PWM period of the first PWM signal (PWM1), which ends after m PWM periods (T _PWM ) follows the first selection time (Tscsi).

The selection is controlled by the selection device (MUX) as a function of the selection signal (PWM _select ). Typically, this is an analog and preferably a digital individual or bus signal that controls the selection device (MUX). This selection signal (PWM _select ) can be, for example, a random signal or a pseudo-random signal or a signal that is generated analogously and/or digitally by a finite state machine.

The following two paragraphs do not apply to pulse-density modulation, while the previous statements were transferrable.

In PWM modulation, the PWM signals (PWM ₁ to PWM _n ) are typically based on PWM pulses that have a predetermined pulse width (T _pulse ), where the following typically applies: f _cycle =T _pulse /T _PWM .

The pulse width (T _puls ) of the PWM signals (PWM ₁ to PWM _n ) is typically modulated on one side and/or on both sides as a function of the duty cycle (f _cycle ). One-sided modulation means that the position of an edge of the pulse of a PWM signal (PWM ₁ to PWM _n ) changes depending on the specified duty cycle (f _cycle ) while the other edge always changes from PWM period to PWM period has the same distance T _PWM . In the case of two-sided PWM modulation, both edges are changed and only one point within the pulse of the PWM signal always has the constant spacing of the PWM period (T _PWM ).

What is described in the previous section is not relevant for pulse density modulation. The following can also be applied analogously to the pulse density modulation.

It is obvious that it is favorable if each of the PWM signals (PWM ₁ to PWM _n ) is generated by a respective PWM generator (PWMG ₁ to PWMG _n ). In many cases, all of these PWM generators (PWMG ₁ to PWMG _n ) can be formed by a single PWM generator. A processor can also run a program that generates these PWM signals (PWM ₁ to PWM _n ) using the hardware.

The further PWM signals (PWM ₂ to PWM _n ) can be generated from a first PWM signal (PWM ₁ ) by n delay paths (ΔT ₂ to ΔT _n ). Typically, n-1 can equal such delay paths (ΔT) are connected in series, whereby the required n-1 further PWM signals (PWM ₂ to PWM _n ) are generated at their n-1 outputs.

Of course, it is also conceivable to generate one or more or all of the further PWM signals (PWM ₂ to PWM _n ) autonomously by means of one or more further PWM signal generators (PWMG ₂ to PWMG _n ), the further PWM signal generators ( PWMG ₂ to PWMG _n ) are synchronized with the first PWM signal generator (PWMG ₁ ).

As a result, the n-1 further PWM signals (PWM ₂ to PWM _n ) are obtained again, which are offset relative to the first PWM signal (PWM ₁ ) by a specific temporal i-th offset (T _{off_i} ) relative to the first PWM signal. Signal (PWM1) are delayed, where i stands for the respective number of the further PWM signal (PWM ₂ to PWM _n ) whose delay is currently being considered.

As already discussed, it is particularly favorable when the following applies: $${\text{T}}_{\text{off\_i}}={\text{T}}_{\text{PWM}}*\left(\text{i}-1\right)\text{/n}$$

All of these n PWM signals (PWM ₁ to PWM _n ) always represent one of the n PWM spread codes.

It has been found that in some cases it makes sense to first allow a number of spread code periods (T _PWM ) to elapse before the selection signal (PWM _select ) sends another PWM spread code in the form of another current spread code -Signals (PWM _k ) by means of the selection device (MUX) selects. It is therefore particularly preferred if the spread code selection signal (PWM _select ) has a periodicity with a spread code period (T _select ) to the effect that its value only changes at times that are multiple, for example an m-fold the PWM period, are, can change. For this spreading code period (T _select ), the following typically applies: $${\text{T}}_{\text{select}}=\text{m}*{\text{T}}_{\text{PWM}}$$

Where m is a positive integer greater than or equal to 1.

The selection device (MUX) thus selects a kth PWM signal (PWM _k ) as the current spread code signal from the generated n PWM signals (PWM ₁ to PWM _n ) as a function of a selection signal (PWM _select ) as PWM -Output signal (PWM _out ) typically at a time interval of m times the PWM period duration (T _PWM .) and generates the said PWM from this for the next selection period of a duration m times the PWM period (T _PWM ). -Output signal (PWM _out ).

This temporal processes is preferably realized by a controller (CTR), which is typically one of the PWM signal generators (PWMG ₁ to PWMG _n ), in particular the first PWM signal generator (PWMG1), synchronized and the selection of the kth PWM signal (PWM _k ) as the current PWM spread code by the selection signal (PWM _select ) at least for a period of time only at the beginning of a PWM period of the first PWM signal (PWM ₁ ) and during a PWM period (T _PWM ) from the start of the PWM period to its end and during the spread code period (T _select ) prevents a change in the current spread code signal (PWM _k ). As already explained, a spread code change is thus suppressed for m times a PWM period (T _PWM ), namely the spread code period (T _select ).

Of course, the selection signal (PWM _select ) can not only be impressed from the outside, but can also be generated by a selection signal generator (SG), which is then part of the device according to the invention. If the selection signal (PWM _selsct ) is to be a pseudo-random signal, it is conceivable, for example, to use a shift register fed back with a simple primitive polynomial as the selection signal generator (SG) or other devices that also generate a pseudo-random signal. However, the selection signal generator can also use other genuine random processes, for example noise etc., to generate the selection signal (PWM _select ). Finally, the selection signal generator can be a finite state machine that generates a selection sequence of the selection signal (PWM _select ) in a predetermined manner.

Finally, a few special cases for the generation of the spread code signal, particularly with regard to pulse density modulation (PDM), should be discussed.

Second part: Generation of PDM spread codes and their application

Most of what has been described so far can be applied to pulse density modulation (PDM).

If the terms PWM are replaced by PDM in the terminology, the analogous terminology for pulse density modulation (PDM) is obtained.

In this way, the n PWM signals (PWM ₁ to PWM _n ) become the n PWM signals (PDM ₁ to PDM _n ). The duty cycle (f _cycle ) is used to calculate the fill factor, also called f _cycle here, which indicates how many ones within a PDM period (T _PDM ) versus how many possible ones are actually set within a PDM period (T _PDM ).

The selected PWM signal (PWM _k ) becomes the selected PWM signal (PDM _k ). The i-th PWM signal (PWM ₁ ) becomes the i-th PWM signal (PDM _i ). This can now be carried out more or less analogously to all sizes and concepts.

With regard to the modulation, however, there are minor differences in a special form.

Preferably, all of the n PDM generators (PDMG ₁ to PDMG _n ) each generate one of the n PDM signals (PDM ₁ to PDM _n ). The n PDM generators (PDMG ₁ to PDMG _n ) generate their respective PDM signals (PDM ₁ to PDM _n ) in n-1 partial areas with a total length of (n-1)/n of the PDM period duration (T _PDM ) with a constant value. This constant value in these n-1 sub-ranges correspond to a 1 value or a 0 value. These PDM generators (PDMG ₁ to PDMG _n ) generate their PDM signals (PDM ₁ to PDM _n ) in a sub-area of length 1/n of the PDM period duration (T _PDM ) with a pulse density that is n times the modulo of fill factor (f _cycle ) times n.

In the case of n=2, it is conceivable to generate the first PWM signal (PDM ₁ ) in such a way that, if the duty cycle is below 50%, it consists of a first half that is filled with a pulse density-modulated pulse density signal is whose pulse density is twice the fill factor (f _cycle ). This means that the first half of the PDM signal (PDM ₁ ) defined in this way must be 100% filled with a fill factor (f _cycle ) of 50%.

The other half is then set to zero.

If the desired fill factor (f _cycle ) of the PDM signal is greater than 50%, the second half is filled completely and the first half only with a pulse density that corresponds to twice the difference between the duty cycle and 50%.

The second PWM signal (PDM 2 ) is obtained again by shifting by half a PWM period (T _PDM / ₂ ).

This can also be extended to n PDM signals (PDM ₁ to PDM _n ).

First, the case of a fill factor (f _cycle ) that is less than 100%/n is treated.

In this case it is conceivable to generate the first PWM signal (PWM ₁ ) in such a way that it consists of a first 1/n part of the PWM period if the fill factor (f _cycle ) is below 100%/n , which is filled with a pulse density modulated pulse density signal (PDM) whose pulse density is n times the fill factor (f _cycle ). This means that the first 1/n part of the PDM signal (PDM ₁ ) defined in this way must be 100% filled with a fill factor (f _cycle ) of 1/n.

The other following n-1 parts of a partial signal length of T _PWM /n are then set to zero.

Next, the case of a fill factor (f _cycle ) that is greater than 100%/n but less than 200%/n is treated.

If the desired fill factor (f _cycle ) is greater than 100%/n but less than 200%/n, the first part is completely filled and the second part only with a pulse density that is n times the difference between duty cycle and corresponds to 100%/n, filled and the third to the nth part set to zero.

This can be continued such that if the desired fill factor (f _cycle ) is greater than f* 100%/n, with n-1 ≥ f ≥ 1, then s the first part to the f th part complete be filled to 100% and the f+1-th part is only filled with a pulse density that corresponds to n times the Gauss bracket n times the fill factor (f _cycle ) and the f+2-th to the n- th part is set to zero. The Gaussian bracket denotes the largest integer that is less than or equal to the number in the Gaussian bracket. This is written as $$ƒ=\lfloor {ƒ}_{cycle}\ast n\rfloor$$

angegeben werden.Analogously, the number of partial areas to be filled with zero can be $$n-ƒ-1=n-\lfloor {ƒ}_{cycle}\ast n\rfloor -1$$

be specified.

How the values 0 and 1 are defined in this sense in relation to the effect on the switching device (M) depends on the application.

In this disclosure, it is assumed by way of example that the switching element is closed at 1 and open at 0. This can be reversed.

The i-th PDM signal (PDM _i ) from the first PDM signal (PDM ₁ ) is obtained again by shifting by a PDM period part (i*T _PDM /n).

The advantage of this method is that it is a mixture of PWM and PDM.

• 1a zeigt ein erstes PWM-Signal (PWM₁) mit einem Duty-Cycle von f_cycle=25% und einer PWM-Periode von T_PWM. In diesem Fall werden nur zwei Spreiz-Code-Signale (PWM₁ und PWM₂) erzeugt. Das zweite Spreiz-Code-Signal, das zweite PWM-Signal (PWM₂) entsteht aus dem ersten PWM-Signal (PWM₁) durch verschiebung um eine PEM-Periodendauer (T_PWM) geteilt durch die Anzahl der Spreiz-Code-Signale n. Da n hier zwei ist ist die Verschiebung T_PWM/2.
• 1b zeigt das erste und zweite PWM-Signal (PWM₁ und PWM₂) nun für einem Duty-Cycle von f_cycle=37,5% bei einseitiger PWM-Modulation.
• 2a zeigt das erste und zweite PWM-Signal (PWM₁ und PWM₂) nun für einem Duty-Cycle von f_cycle=75% bei einseitiger PWM-Modulation.
• 2b zeigt das erste und zweite PWM-Signal (PWM₁ und PWM₂) nun für einem Duty-Cycle von f_cycle=62,5% bei einseitiger PWM-Modulation.
• 3 zeigt nun die sich ergebenden PWM-Ausgangssignale (PWM_out) für die Signale der 1a, 1b, 2a und 2b.
• 3a zeigt das PWM-Ausgangssignal (PWM_out) für die PWM-Signale (PWM₁ und PWM₂) der 1a. Die schraffierten Flächen zeigen die zeitlichen Bereiche in denen das Auswahlsignal (PWM_select) das Ausgangssignal (PWM_out) moduliert. Ist das Auswahlsignal (PWM_select) ein Zufallssignal, so ist der Bereich der Blöcke innerhalb einer PWM-Auswahlperiode von m*T_PWM entweder für alle diese Flächen innerhalb der Spreiz-Code-Periode (T_select) gemeinsam beispielsweise 1 oder 0. Welcher Wert für alle diese Flächen innerhalb einer Spreiz-Code-Periode (T_select) angenommen wird ist bei einem Zufallssignal als Auswahlsignal (PWM_select) zufällig. Diese Zeitbereiche „rauschen“ also von Spreiz-Code-Periode (T_select) zu PWM- Spreiz-Code-Periode (T_select) als Gesamtheit. Zwischen diesen „rauschenden Bereichen ist das PWM-Ausgangssignal (PWM_out) Null. Es handelt sich also um die PWM eines Zufallssignals, wobei dieses durch die Spreiz-Code-Periode (T_select) nach oben hin bandbegrentz ist.
• 3b zeigt das PWM-Ausgangssignal für die PWM-Signale (PWM₁ und PWM₂) der 1b. Ansonsten sind die Verhältnisse ähnlich denen der 3a
• 3c zeigt das PWM-Ausgangssignal für die PWM-Signale (PWM₁ und PWM₂) der 2b mit einem Duty-Cycle (f_cycle) von mehr als 50%, nämlich 62,5%. Der Unterschied zur 3b ist der, dass nun zwischen den „rauschend“, als schraffiert markierten Bereichen das PWM-Ausgangssignal (PWM_out) in diesem Beispiel eins ist, statt wie zuvor Null. Dies liegt daran, dass der Duty-Cycle (f_cycle) von mehr als 50% verwendet wird.
• 3d zeigt das PWM-Ausgangssignal für die PWM-Signale (PWM₁ und PWM₂) der 2a mit einem Duty-Cycle (f_cycle) von 75% . Ansonsten sind die Verhältnisse ähnlich denen der 3c
• 4 zeigt ein beispielhaftes schematisches Beispiel für eine Vorrichtung zur Erzeugung eines optimierten PWM-Ausgangssignals. In diesem Fall ist im Gegensatz zu den vorhergehenden Figuren nicht n=2 sondern n=4 beispielhaft gewählt. Die vier PWM-Signale (PWM₁ bis PWM₄) werden von vier Signalgeneratoren (PWMG₁ bis PWMG₄) erzeugt. Dabei ist das zweite PWM-Signal (PWM₂) gleich dem ersten PWM-Signal (PWM₁) verzögert um ein Viertel der PWM-Periodendauer (T_PWM). Dabei ist das dritte PWM-Signal (PWM₃) gleich dem ersten PWM-Signal (PWM₁) verzögert um zwei Viertel der PWM-Periodendauer (T_PWM) und das vierte PWM-Signal (PWM₃) gleich dem ersten PWM-Signal (PWM₁) verzögert um drei Viertel der PWM-Periodendauer (T_PWM). Damit diese Verhältnisse bestehen bleiben, werden die PWM-Generatoren (PWMG₁ bis PWMG₄) durch ein Synchronisationssignal (Sync) synchronisiert. Dieses wird in diesem Beispiel von einer Kontrolleinheit (CTR) geliefert, die typischerweise auch den Systemtakt liefert und/oder den Systemtakt selbst benutzt. Die Kontrolleinheit (CTR) sorgt mittels einer ebenfalls eingezeichneten Steuerleitung dafür, dass der Auswahlsignalgenerator (SG) nur dann ein anderes PWM-Signal (PWM₁ bis PWM₄) als selektiertes PWM-Signal (PWM_k) mittels des Multiplexers (MUX) auswählt, wenn m PWM-Periodenvorüber sind, also die Spreiz-Code-Periode (T_select), vorüber ist. Das so ausgewählte PWM-Signal (PWM_k) wird durch eine Anpassvorrichtung (PA) an die Erfordernisse des zu steuernden Elements, hier eine Schaltvorrichtung (M) in Form eines MOS-Transistors, als PWM-Ausgangssignal (PWM_out) angepasst. Hierdurch wird die Last, hier eine LED (D), mit einem Strom bestromt, der durch die Drosselspule L geglättet wird. Freilaufdioden etc. sind zur Vereinfachung nicht eingezeichnet.
• 5 zeigt beispielhafte vier PWM-Signale (PWM₁ bis PWM₄) für einen beispielhaften Duty-Cycle (f_cycle) von 12,5% passend zur Vorrichtung entsprechend 4.
• 6 zeigt die Einteilung einer PWM-Periode in n, hier also beispielhaft 4, Zeitschlitze (SL1 bis SL4). Ansonsten entspricht die Figur der 5.
• 7 zeigt das erste PWM-Signal (PWM₁) für eine verschiedene Anzahl m von PWM-Perioden zwischen zwei Spreiz-Code Auswahlzeitpunkten (TSCS1, TSCS2) für die Dauer der Spreiz-Code-Periode (T_select) für eine erste Auswahl eines PWM-Signals (PWM₁ bis PWM_n) als PWM-Spreiz-Code in Form des aktuellen PWM-Spreiz-Code-Signals (PWM_k). Für m=1 ist die Spreiz-Code-Periode (T_select) identisch mit der PWM-Periodendauer (T_PWM).
• 8 zeigt nun einen Verwürfler (SCR), der die Zeitschlitze der n PWM-Signale, hier beispielhaft vier PWM-Signale (PWM₁ bis PWM₄), n verwürfelten PWM-Signalen, hier beispielhaft vier verwürfelten PWM-Signalen (PWM₁' bis PWM₄') zuordnet. Erst danach bildet die Auswahlvorrichtung (MUX) wie in 4 das ausgewählte PWM-Signal (PWM_k). Die Verwürfelung wird anhand von 9 erläutert.
• 9 zeigt das beispielhafte Ergebnis der Verwürfelung von hier beispielhaft 4 PWM-Signalen durch den Verwürfler (SCR) entsprechend 8 dar. Das erste verwürfelte PWM-Signal (PWM₁') entspricht im ersten Zeitschlitz (SL₁) dem ersten Zeitschlitz (SL₁) des ersten PWM-Signals (PWM₁). Das erste verwürfelte PWM-Signal (PWM₁') entspricht im zweiten Zeitschlitz (SL₂) dem zweiten Zeitschlitz (SL₂) des zweiten PWM-Signals (PWM₂). Das erste verwürfelte PWM-Signal (PWM₁') entspricht im dritten Zeitschlitz (SL₃) dem dritten Zeitschlitz (SL₃) des dritten PWM-Signals (PWM₃). Das erste verwürfelte PWM-Signal (PWM₁') entspricht im vierten Zeitschlitz (SL₄) dem vierten Zeitschlitz (SL₄) des vierten PWM-Signals (PWM₄). Das zweite verwürfelte PWM-Signal (PWM₂') entspricht im ersten Zeitschlitz (SL₁) dem ersten Zeitschlitz (SL₁) des zweiten PWM-Signals (PWM₂). Das zweite verwürfelte PWM-Signal (PWM₂') entspricht im zweiten Zeitschlitz (SL₂) dem zweiten Zeitschlitz (SL₂) des dritten PWM-Signals (PWM₃). Das zweite verwürfelte PWM-Signal (PWM₂') entspricht im dritten Zeitschlitz (SL₃) dem dritten Zeitschlitz (SL₃) des vierten PWM-Signals (PWM₄). Das zweite verwürfelte PWM-Signal (PWM₂') entspricht im vierten Zeitschlitz (SL₄) dem vierten Zeitschlitz (SL₄) des ersten PWM-Signals (PWM₁). Das dritte verwürfelte PWM-Signal (PWM₃') entspricht im ersten Zeitschlitz (SL₁) dem ersten Zeitschlitz (SL₁) des dritten PWM-Signals (PWM₃). Das dritte verwürfelte PWM-Signal (PWM₃') entspricht im zweiten Zeitschlitz (SL₂) dem zweiten Zeitschlitz (SL₂) des vierten PWM-Signals (PWM₄). Das dritte verwürfelte PWM-Signal (PWM₂') entspricht im dritten Zeitschlitz (SL₃) dem dritten Zeitschlitz (SL₃) des ersten PWM-Signals (PWM₁). Das dritte verwürfelte PWM-Signal (PWM₃') entspricht im vierten Zeitschlitz (SL₄) dem vierten Zeitschlitz (SL₄) des zweiten PWM-Signals (PWM₂). Das vierte verwürfelte PWM-Signal (PWM₄') entspricht im ersten Zeitschlitz (SL₁) dem ersten Zeitschlitz (SL₁) des vierten PWM-Signals (PWM₄). Das vierte verwürfelte PWM-Signal (PWM₄') entspricht im zweiten Zeitschlitz (SL₂) dem zweiten Zeitschlitz (SL₂) des ersten PWM-Signals (PWM₁). Das vierte verwürfelte PWM-Signal (PWM₄') entspricht im dritten Zeitschlitz (SL₃) dem dritten Zeitschlitz (SL₃) des zweiten PWM-Signals (PWM₂). Das vierte verwürfelte PWM-Signal (PWM₄') entspricht im vierten Zeitschlitz (SL₄) dem vierten Zeitschlitz (SL₄) des dritten PWM-Signals (PWM₃). Auf diese Weise werden durch zyklisches Vertauschen der Zeitschlitze neue verwürfelte PWM-Signal (PWM₁' bis PWM_n') aus den PWM-Signalen (PWM₁ bis PWM_n) gebildet, die typischerweise tiefer frequente Spektren zur Folge haben
• 10 zeigt die verwürfelten PWM-Signale (PWM₁' bis PWM₄') für einen Duty-Cycle (f_cycle) von 37,5%. Das erste verwürfelte PWM-Signal (PWM₁') ist hier permanent auf beispielhaft 1.
• 11 zeigt die verwürfelten PWM-Signale (PWM₁' bis PWM₄') für einen Duty-Cycle (f_cycle) von 62,5%. Das erste verwürfelte PWM-Signal (PWM₁') und das zweite verwürfelte PWM-Signal (PWM₂') sind hier permanent auf beispielhaft 1.
• 12 zeigt die verwürfelten PWM-Signale (PWM₁' bis PWM₄') für einen Duty-Cycle (f_cycle) von 87,5%. Das erste verwürfelte PWM-Signal (PWMi`)und das zweite verwürfelte PWM-Signal (PWM₂') und das dritte verwürfelte PWM-Signal (PWM₃') sind hier permanent auf beispielhaft 1.
• 13a zeigt eine alternative Möglichkeit zur Generierung zweier optimaler PWM-Spreiz-Codes. Auch hier ist statt n=2 eine andere ganze Zahl von n möglich. In diesem Fall wird das erste PWM-Signal (PWM₁) während einer Dauer von T_PWM/n also hier T_PWM/2 mit einer Pulsdichte-Modulation (PDM) mit einer Pulsdichte von 2* f_cycle moduliert. Hierbei hat f_cycle die Funktion des Füllfaktors (f_cycle), die die Menge der Einsen in Relation zu der Menge der möglichen Einsen ist. 13a zeigt die Verhältnisse bei f_cycle<1/n hier also f_cycle<50%. Das zweite PWM-Signal (PWM₂) erhält man wieder durch Verzögerung um T_PWM/n, hier also T_PWM/2.
• 13b entspricht 13a mit dem Unterschied, dass der Füllfaktor X nun über 50% liegt. Die in 13a modulierten Signalbereiche sind nun konstant auf beispielhaft 1, während die bisher auf beispielhaft 0 liegenden Teile nun mit einer Pulsdichtemodulation (PDM) moduliert werden. Die Anzahl f der Teilbereiche, die konstant auf beispielhaft 1 gelegt werden, ergibt sich als der abgerundete Wert f von f_cycle*n. Dieser wird typischerweise mit einer Gaußklammer [f_cycle*n] geschrieben. Es werden dann immer erst f Teilbereiche des ersten PWM-Signals (PWM₁) auf beispielhaft 1 gelegt und dann ein f+1-ter Bereich mit der besagten Pulsdichtemodulation versehen. Die Dichte dieser Pulsdichte-Modulation ist dabei n*(f_cycle-f/n). Da hier n=2 ist, ist hier die Dichte dieser Modulation 2*(f_cycle-1/2).
• 15 zeigt die Fourier-Transformierte eines Zufallsmodulierten Signals gemäß der US8129924 . Die Transformierte enthält relativ viele relativ hohe Spikes.
• 16 zeigt die Fourier-Transformierte eines erfindungsgemäßen PWM-Signals (PWM_out) mit einem Duty-Cycle (f_cycle) von 25% und m=1 ohne Verwürfelung. Der erste PWM-Spreiz-Code, das erste PWM-Signal (PWM₁), entspricht dabei einer Bit-Sequenz 1111000000000000. Der zweite PWM-Spreiz-Code, das zweite PWM-Signal (PWM₂), entspricht dabei einer Bit-Sequenz 0000000011110000.
• 17 zeigt die Fourier-Transformierte eines erfindungsgemäßen PWM-Signals (PWM_out) mit einem Duty-Cycle (f_cycle) von 25% und m=2 ohne Verwürfelung. Der erste PWM-Spreiz-Code, das erste PWM-Signal (PWM₁), entspricht dabei einer Bit-Sequenz 1100000011000000. Der zweite PWM-Spreiz-Code, das zweite PWM-Signal (PWM₂), entspricht dabei einer Bit-Sequenz 0000110000001100.
• 18 zeigt die Fourier-Transformierte eines erfindungsgemäßen PWM-Signals (PWM_out) mit einem Duty-Cycle (f_cycle) von 25% und m=2 ohne Verwürfelung. Der erste PWM-Spreiz-Code, das erste PWM-Signal (PWM₁), entspricht dabei einer Bit-Sequenz 1000100010001000. Der zweite PWM-Spreiz-Code das zweite PWM-Signal (PWM₂), entspricht dabei einer Bit-Sequenz 0010001000100010.
• 19 zeigt die Fourier-Transformierte eines erfindungsgemäßen PWM-Signals (PWM_out) nach Verwürfelung durch die Verwürfelungseinheit (SC) mit einem Duty-Cycle (f_cycle) von 25% und m=1. Der erste PWM-Spreiz-Code, das erste PWM-Signal (PWM₁), entspricht dabei einer Bit-Sequenz 1111000000000000. Der zweite PWM-Spreiz-Code, das zweite PWM-Signal (PWM₂), entspricht dabei einer Bit-Sequenz 0000000011110000. Der erste verwürfelte PWM-Spreiz-Code, das erste verwürfelte PWM-Signal (PWM₁'), entspricht dabei einer Bit-Sequenz 1111000011110000. Der zweite verwürfelte PWM-Spreiz-Code, das zweite verwürfelte PWM-Signal (PWM₂'), entspricht dabei einer Bit-Sequenz 0000000000000000.
• 20 zeigt die Fourier-Transformierte eines erfindungsgemäßen PWM-Signals (PWM_out) nach Verwürfelung durch die Verwürfelungseinheit (SC) mit einem Duty-Cycle (f_cycle) von 25% und m=2. Der erste PWM-Spreiz-Code, das erste PWM-Signal (PWM₁), entspricht dabei einer Bit-Sequenz 1100000011000000. Der zweite PWM-Spreiz-Code, das zweite PWM-Signal (PWM₂), entspricht dabei einer Bit-Sequenz 0000110000001100. Der erste verwürfelte PWM-Spreiz-Code, das erste verwürfelte PWM-Signal (PWM₁'), entspricht dabei einer Bit-Sequenz 1100110011001100. Der zweite verwürfelte PWM-Spreiz-Code, das zweite verwürfelte PWM-Signal (PWM₂'), entspricht dabei einer Bit-Sequenz 0000000000000000.
• 21 zeigt die Fourier-Transformierte eines erfindungsgemäßen PWM-Signals (PWM_out) nach Verwürfelung durch die Verwürfelungseinheit (SC) mit einem Duty-Cycle (f_cycle) von 25% und m=4. Der erste PWM-Spreiz-Code, das erste PWM-Signal (PWM₁), entspricht dabei einer Bit-Sequenz 1000100010001000. Der zweite PWM-Spreiz-Code, das zweite PWM-Signal (PWM₂), entspricht dabei einer Bit-Sequenz 0010001000100010. Der erste verwürfelte PWM-Spreiz-Code, das erste verwürfelte PWM-Signal (PWM₁'), entspricht dabei einer Bit-Sequenz 1010101010101010. Der zweite verwürfelte PWM-Spreiz-Code, das zweite verwürfelte PWM-Signal (PWM₂'), entspricht dabei einer Bit-Sequenz 0000000000000000.

The invention is explained in more detail below with reference to the attached drawings.

• 1a shows a first PWM signal (PWM ₁ ) with a duty cycle of f _cycle =25% and a PWM period of T _PWM. In this case only two spreading code signals (PWM ₁ and PWM ₂ ) are generated. The second spread code signal, the second PWM signal (PWM ₂ ) results from the first PWM signal (PWM ₁ ) by shifting it by a PEM period (T _PWM ) divided by the number of spread code signals n Since n is two here, the shift is T _PWM /2.
• 1b shows the first and second PWM signal (PWM ₁ and PWM ₂ ) now for a duty cycle of f _cycle =37.5% with one-sided PWM modulation.
• 2a shows the first and second PWM signal (PWM ₁ and PWM ₂ ) now for a duty cycle of f _cycle =75% with one-sided PWM modulation.
• 2 B shows the first and second PWM signal (PWM ₁ and PWM ₂ ) now for a duty cycle of f _cycle =62.5% with one-sided PWM modulation.
• 3 now shows the resulting PWM output signals (PWM _out ) for the signals of 1a , 1b , 2a and 2 B .
• 3a shows the PWM output signal (PWM _out ) for the PWM signals (PWM ₁ and PWM ₂ ) of the 1a . The hatched areas show the time ranges in which the selection signal (PWM _select ) modulates the output signal (PWM _out ). If the selection signal (PWM _select ) is a random signal, then the area of the blocks within a PWM selection period of m*T _PWM is either 1 or 0 for all these areas within the spreading code period (T _select ) together, for example. Which value is assumed for all of these areas within a spreading code period (T _select ) is random in the case of a random signal as the selection signal (PWM _select ). These time ranges therefore "noise" from spread code period (T _select ) to PWM spread code period (T _select ) as a whole. Between these "noisy" areas, the PWM output signal (PWM _out ) is zero. It is therefore a question of the PWM of a random signal, with this being band-limited upwards by the spread code period (T _select ).
• 3b shows the PWM output signal for the PWM signals (PWM ₁ and PWM ₂ ) of 1b . Otherwise the conditions are similar to those of 3a
• 3c shows the PWM output signal for the PWM signals (PWM ₁ and PWM ₂ ) of 2 B with a duty cycle (f _cycle ) of more than 50%, namely 62.5%. The difference to 3b is that now between the "noisy" areas marked as hatched, the PWM output signal (PWM _out ) is one in this example instead of zero as before. This is because the duty cycle (f _cycle ) of more than 50% is used.
• 3d shows the PWM output signal for the PWM signals (PWM ₁ and PWM ₂ ) of 2a with a duty cycle (f _cycle ) of 75%. Otherwise the conditions are similar to those of 3c
• 4 shows an exemplary schematic example of a device for generating an optimized PWM output signal. In this case, in contrast to the previous figures, not n=2 but n=4 is chosen as an example. The four PWM signals (PWM ₁ to PWM ₄ ) are generated by four signal generators (PWMG ₁ to PWMG ₄ ). The second PWM signal (PWM ₂ ) is equal to the first PWM signal (PWM ₁ ) delayed by a quarter of the PWM period (T _PWM ). The third PWM signal (PWM ₃ ) is equal to the first PWM signal (PWM ₁ ) delayed by two quarters of the PWM period (T _PWM ) and the fourth PWM signal (PWM ₃ ) is equal to the first PWM signal ( PWM ₁ ) delayed by three quarters of the PWM period duration (T _PWM ). In order for these conditions to remain, the PWM generators (PWMG ₁ to PWMG ₄ ) are synchronized by a synchronization signal (sync). In this example, this is supplied by a control unit (CTR), which typically also supplies the system clock and/or uses the system clock itself. The control unit (CTR) uses a control line that is also shown to ensure that the selection signal generator (SG) only selects another PWM signal (PWM ₁ to PWM ₄ ) as the selected PWM signal (PWM _k ) using the multiplexer (MUX) if when m PWM periods are over, i.e. the spreading code period (T _select ), is over. The PWM signal (PWM _k ) selected in this way is adapted by an adaptation device (PA) to the requirements of the element to be controlled, here a switching device (M) in the form of a MOS transistor, as a PWM output signal (PWM _out ). As a result, the load, here an LED (D), is supplied with a current that is smoothed out by the choke coil L. Freewheeling diodes etc. are not shown for the sake of simplicity.
• 5 FIG. 12 shows example four PWM signals (PWM ₁ through PWM ₄ ) for an example Duty cycle (f _cycle ) of 12.5% appropriate to the device accordingly 4 .
• 6 shows the division of a PWM period into n, here by way of example 4, time slots (SL1 to SL4). Otherwise the figure corresponds to 5 .
• 7 shows the first PWM signal (PWM ₁ ) for a different number m of PWM periods between two spread code selection times (TSCS1, TSCS2) for the duration of the spread code period (T _select ) for a first selection of a PWM Signals (PWM ₁ to PWM _n ) as a PWM spread code in the form of the current PWM spread code signal (PWM _k ). For m=1, the spreading code period (T _select ) is identical to the PWM period (T _PWM ).
• 8th now shows a scrambler (SCR) that uses the time slots of the n PWM signals, here as an example four PWM signals (PWM ₁ to PWM ₄ ), n scrambled PWM signals, here as an example four scrambled PWM signals (PWM ₁ 'to PWM ₄ ') assigns. Only then does the selection device (MUX) form as in 4 the selected PWM signal (PWM _k ). The scrambling is based on 9 explained.
• 9 shows the exemplary result of the scrambling of 4 PWM signals by the scrambler (SCR) accordingly 8th represents. The first scrambled PWM signal (PWM ₁ ') corresponds in the first time slot (SL ₁ ) to the first time slot (SL ₁ ) of the first PWM signal (PWM ₁ ). The first scrambled PWM signal (PWM ₁ ') corresponds in the second time slot (SL ₂ ) to the second time slot (SL ₂ ) of the second PWM signal (PWM ₂ ). The first scrambled PWM signal (PWM ₁ ') corresponds in the third time slot (SL ₃ ) to the third time slot (SL ₃ ) of the third PWM signal (PWM ₃ ). The first scrambled PWM signal (PWM ₁ ') corresponds in the fourth time slot (SL ₄ ) to the fourth time slot (SL ₄ ) of the fourth PWM signal (PWM ₄ ). The second scrambled PWM signal (PWM ₂ ') corresponds in the first time slot (SL ₁ ) to the first time slot (SL ₁ ) of the second PWM signal (PWM ₂ ). The second scrambled PWM signal (PWM ₂ ') corresponds in the second time slot (SL ₂ ) to the second time slot (SL ₂ ) of the third PWM signal (PWM ₃ ). The second scrambled PWM signal (PWM ₂ ') corresponds in the third time slot (SL ₃ ) to the third time slot (SL ₃ ) of the fourth PWM signal (PWM ₄ ). The second scrambled PWM signal (PWM ₂ ') corresponds in the fourth time slot (SL ₄ ) to the fourth time slot (SL ₄ ) of the first PWM signal (PWM ₁ ). The third scrambled PWM signal (PWM ₃ ') corresponds in the first time slot (SL ₁ ) to the first time slot (SL ₁ ) of the third PWM signal (PWM ₃ ). The third scrambled PWM signal (PWM ₃ ') corresponds in the second time slot (SL ₂ ) to the second time slot (SL ₂ ) of the fourth PWM signal (PWM ₄ ). The third scrambled PWM signal (PWM ₂ ') corresponds in the third time slot (SL ₃ ) to the third time slot (SL ₃ ) of the first PWM signal (PWM ₁ ). The third scrambled PWM signal (PWM ₃ ') corresponds in the fourth time slot (SL ₄ ) to the fourth time slot (SL ₄ ) of the second PWM signal (PWM ₂ ). The fourth scrambled PWM signal (PWM ₄ ') corresponds in the first time slot (SL ₁ ) to the first time slot (SL ₁ ) of the fourth PWM signal (PWM ₄ ). The fourth scrambled PWM signal (PWM ₄ ') corresponds in the second time slot (SL ₂ ) to the second time slot (SL ₂ ) of the first PWM signal (PWM ₁ ). The fourth scrambled PWM signal (PWM ₄ ') corresponds in the third time slot (SL ₃ ) to the third time slot (SL ₃ ) of the second PWM signal (PWM ₂ ). The fourth scrambled PWM signal (PWM ₄ ') corresponds in the fourth time slot (SL ₄ ) to the fourth time slot (SL ₄ ) of the third PWM signal (PWM ₃ ). In this way, new scrambled PWM signals (PWM ₁ 'to PWM _n ') are formed from the PWM signals (PWM ₁ to PWM _n ) by cyclically exchanging the time slots, which typically result in lower-frequency spectra
• 10 shows the scrambled PWM signals (PWM ₁ ' to PWM ₄ ') for a duty cycle (f _cycle ) of 37.5%. The first scrambled PWM signal (PWM ₁ ') is here permanently set to 1, for example.
• 11 shows the scrambled PWM signals (PWM ₁ ' to PWM ₄ ') for a duty cycle (f _cycle ) of 62.5%. The first scrambled PWM signal (PWM ₁ ') and the second scrambled PWM signal (PWM ₂ ') are here permanently set to 1, for example.
• 12 shows the scrambled PWM signals (PWM ₁ ' to PWM ₄ ') for a duty cycle (f _cycle ) of 87.5%. The first scrambled PWM signal (PWMi`) and the second scrambled PWM signal (PWM ₂ ') and the third scrambled PWM signal (PWM ₃ ') are here permanently set to 1, for example.
• 13a shows an alternative way to generate two optimal PWM spreading codes. Here, too, instead of n=2, another whole number of n is possible. In this case, the first PWM signal (PWM ₁ ) is modulated with a pulse density modulation (PDM) with a pulse density of 2* f _cycle for a period of T _PWM /n, ie here T _PWM /2. Here, f _cycle has the function of the fill factor (f _cycle ), which is the set of ones in relation to the set of possible ones. 13a shows the ratios at f _cycle <1/n, in this case f _cycle <50%. The second PWM signal (PWM ₂ ) is obtained again by delaying by T _PWM /n, in this case T _PWM /2.
• 13b corresponds 13a with the difference that the fill factor X is now over 50%. In the 13a The modulated signal areas are now constant at 1, for example, while the parts that were previously at 0, for example, are now modulated with pulse density modulation (PDM). The number f of sub-areas, which is kept constant at 1, for example, results as the rounded-down value f of f _cycle *n. This is typically written with a Gaussian bracket [f _cycle *n]. In this case, first f partial areas of the first PWM signal (PWM ₁ ) are set to 1, for example, and then an f+1-th area is provided with the said pulse density modulation. The density of this pulse density modulation is n*(f _cycle -f/n). Since n=2 here, the density of this modulation is 2*(f _cycle -1/2).
• 15 shows the Fourier transform of a random modulated signal according to FIG US8129924 . The transform contains a relatively large number of relatively high spikes.
• 16 shows the Fourier transform of a PWM signal (PWM _out ) according to the invention with a duty cycle (f _cycle ) of 25% and m=1 without scrambling. The first PWM spread code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence 1111000000000000. The second PWM spread code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence 0000000011110000.
• 17 shows the Fourier transform of a PWM signal (PWM _out ) according to the invention with a duty cycle (f _cycle ) of 25% and m=2 without scrambling. The first PWM spread code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence 1100000011000000. The second PWM spread code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence 0000110000001100.
• 18 shows the Fourier transform of a PWM signal (PWM _out ) according to the invention with a duty cycle (f _cycle ) of 25% and m=2 without scrambling. The first PWM spread code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence 1000100010001000. The second PWM spread code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence 0010001000100010 .
• 19 shows the Fourier transform of a PWM signal (PWM _out ) according to the invention after scrambling by the scrambling unit (SC) with a duty cycle (f _cycle ) of 25% and m=1. The first PWM spread code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence 1111000000000000. The second PWM spread code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence 0000000011110000. The first scrambled PWM spread code, the first scrambled PWM signal (PWM ₁ '), corresponds to a bit sequence 1111000011110000. The second scrambled PWM spread code, the second scrambled PWM signal (PWM ₂ ' ), corresponds to a bit sequence 0000000000000000.
• 20 shows the Fourier transform of a PWM signal (PWM _out ) according to the invention after scrambling by the scrambling unit (SC) with a duty cycle (f _cycle ) of 25% and m=2. The first PWM spread code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence 1100000011000000. The second PWM spread code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence 0000110000001100. The first scrambled PWM spread code, the first scrambled PWM signal (PWM ₁ '), corresponds to a bit sequence 1100110011001100. The second scrambled PWM spread code, the second scrambled PWM signal (PWM ₂ ' ), corresponds to a bit sequence 0000000000000000.
• 21 shows the Fourier transform of a PWM signal (PWM _out ) according to the invention after scrambling by the scrambling unit (SC) with a duty cycle (f _cycle ) of 25% and m=4. The first PWM spread code, the first PWM signal (PWM ₁ ), corresponds to a bit sequence 1000100010001000. The second PWM spread code, the second PWM signal (PWM ₂ ), corresponds to a bit sequence 0010001000100010. The first scrambled PWM spread code, the first scrambled PWM signal (PWM ₁ '), corresponds to a bit sequence 1010101010101010. The second scrambled PWM spread code, the second scrambled PWM signal (PWM ₂ '), corresponds to a bit sequence 0000000000000000.

Like the 16 until 21 can be seen, in contrast to US8129924 the spectrum can be influenced over a wide range by the choice of the parameters n and m.

Reference List

ctr

Steering. The control is preferably with at least one of the PWM signal generators (PWMG ₁ to PWMG _n ), in particular the first PWM signal generator (PWMG1), or with at least one of the PWM signal generators (PDMG ₁ to PDMG _n ), in particular the first PDM signal generator _{(PDMG1), synchronizes and lets the selection signal (PWM select , PDM select} ) at least for a period of time only at the beginning of a PWM period of the first PWM signal (PWM ₁ ) or only at the beginning of a PWM period of the first PWM signal (PDM ₁ ). In another embodiment of the invention, the controller allows a next selection again, which is based on a first selection at a first spread code selection time (Tscsi) at the time at the beginning of a PWM period of the first PWM signal (PWM ₁ ) or at the time at the beginning of a PWM period of the first PWM signal (PDM ₁ ). This approval of a new selection of a new spread code signal only occurs at an immediately following second spread code selection time (T _SCS2 ) at the beginning of a PWM period of the first PWM signal (PWM ₁ ) or at the beginning of a PWM Period of the first PWM signal (PDM ₁ ) after m PWM periods (T _PWM ) or after m PWM periods (T _PDM ) again. The controller thus suppresses a change in the spreading code signal for the duration of a spreading code period (Tselect).

ΔT

delay element. The delay element preferably delays a signal by the PWM period (T _PWM ) divided by the number n of PWM signals or by the PWM period (T _PDM ) divided by the number n of PWM signals.

ΔT2

Delay element that delays the first PWM signal (PWM ₁ ) by the first offset (T _{off_1} ) to the second PWM signal (PWM ₂ ) or that the first PWM signal (PDM ₁ ) by the first offset (T _{off_1} ) delayed to the second PDM signal (PDM ₂ ).

ΔT3

Delay element that delays the first PWM signal (PWM ₁ ) by the third offset (T _{off_3} ) to the third PWM signal (PWM ₃ ) or that the first PWM signal (PDM ₁ ) by the third offset (T _{off_3} ) delayed to the third PDM signal (PDM ₃ ).

ΔT4

Delay element that delays the first PWM signal (PWM ₁ ) by the fourth offset (T _{off_4} ) to the fourth PWM signal (PWM ₄ ) or that the first PWM signal (PDM ₁ ) by the fourth offset (T _{off_4} ) delayed to the fourth PDM signal (PDM ₄ ).

ΔTn

Delay element that delays the first PWM signal (PWM ₁ ) by the nth offset (T _{off_n} ) to the nth PWM signal (PWM _n ) or that the first PWM signal (PDM ₁ ) by the nth th offset (T _{off_n} ) to the n-th PDM signal (PDM _n ).

D

LED or load

fcycle

PWM duty cycle with PWM modulation in % or fill factor with PDM modulation in %

L

choke coil

M

Switching device, in particular a transistor

MUX

selection device. The selection device selects the kth PWM signal (PWM _k ) or the kth PWM signal (PDM _k ) as the current spread code signal from the generated n PWM signals (PWM ₁ to PWM _n ) or from the generated n PDM signals (PDM ₁ to PDM _n ) depending on a selection signal (PWM _select , PDM _select ) as a PWM output signal (PWM _out ) or as a PWM output signal (PDM _out ).

n

Number of PWM spread codes with PWM modulation or number of PDM spread codes with PWM modulation

m

PWM modulation: Number of PWM periods between two spread code selection times (Tscsi, T _SCS2 ) for a first selection of a PWM signal (PWM ₁ to PWM _n ) as a PWM spread code in the form of the current PWM spread code signal (PWM _k ). PDM modulation: Number of PWM periods between two spread code selection times (T _SCS1 , T _SCS2 ) for a first selection of a PWM signal (PDM ₁ to PDM _n ) as a PDM spread code in the form of the current PWM Spreading Code Signal (PDM _k ).

PA

Adjustment device for adjusting the result to the useful element (here the switching device (M)); PWM modulation: The PWM signal (PWM _k ) selected by the selection device (MUX) is adapted by the adaptation device (PA) to the requirements of the element to be controlled, here a switching device (M) in the form of a MOS transistor. PWM modulation: The PWM signal (PDM _k ) selected by the selection device (MUX) is adapted by the adaptation device (PA) to the requirements of the element to be controlled, here a switching device (M) in the form of a MOS transistor.

PDM

Pulse Density Modulation

PDM1

first PDM signal of the first PDM generator (PDMG ₁ )

PDM2

second PDM signal of the second PDM generator (PDMG ₂ )

PDM3

third PDM signal of the third PDM generator (PDMG ₃ )

PDM4

fourth PWM signal of the fourth PWM generator (PDMG ₄ )

PDM1'

first scrambled PDM signal

pdm2'

second scrambled PDM signal

pdm3'

third scrambled PDM signal

pdm4'

fourth scrambled PDM signal

PDMi

i-th PWM signal of the i-th PWM generator (PDMG _i ), with 1≤i≤n

PDMk

current PDM spreading code signal or k-th PDM signal of the i-th PDM generator (PDMG _i ), with 1≤k≤n. The k-th PWM signal is the signal that is currently selected as a function of the current status of the selection signal (PDM _select ) and is therefore essentially associated with the PWM output signal (PDM _out ) for the duration of this selection, typically up to level and some delay, agrees.

PDMn

nth PDM signal of the nth PDM generator (PDMG _n )

PDMout

PWM output signal of the device according to the invention

PDMselect

selection signal

PDMG1

first PDM signal generator for generating the first PDM signal (PDM ₁ )

PDMG2

second PWM signal generator for generating the second PWM signal (PDM ₂ ). The second signal generator generates the second PWM signal (PDM ₂ ) typically by a second offset (T _{off_2} ) in time with respect to the first PWM signal (PDM ₁ ). It is preferably a first PWM signal (PDM ₁ ) delayed by this second offset (T _{off_2} ).

PDMGi

i-th PWM signal generator (1≤i≤n) for generating the i-th PWM signal (PDM _i ). The i-th signal generator generates the i-th PWM signal (PDM _i ) typically offset in time by an i-th offset (T _{off_i} ) relative to the first PWM signal (PDM _i ). It is preferably a first PWM signal (PDM ₁ ) delayed by this i-th offset (T _{off_i} ). The i-th signal generator is one, namely the i-th, of the n signal generators (PDMG ₁ to PDMG _n ).

PDMGk

k-th PWM signal generator (1≦k≦n) for generating the k-th PWM signal (PDM _k ) which is the currently selected spreading code signal. The k-th signal generator generates the k-th PWM signal (PDM _k ) typically by a k-th offset (T _{off_k} ) in time with respect to the first PWM signal (PDM ₁ ). It is preferably a first PWM signal (PDM ₁ ) delayed by this kth offset (T _{off_k} ). The kth signal generator is one, namely the kth, of the n signal generators (PDMG ₁ to PDMG _n ).

PDMGn

nth PWM signal generator n for generating the nth PWM signal (PDM _n ). The nth signal generator generates the nth PWM signal (PDM _n ) typically by an nth offset (T _{off_n} ) in time with respect to the first PWM signal (PDM ₁ ). It is preferably a first PWM signal (PDM ₁ ) delayed by this nth offset (T _{off_i} ).

PWM

Pulse Width Modulation

PWM1

first PWM signal of the first PWM generator (PWMG ₁ )

PWM2

second PWM signal of the second PWM generator (PWMG ₂ )

PWM3

third PWM signal of the third PWM generator (PWMG ₃ )

PWM4

fourth PWM signal of the fourth PWM generator (PWMG ₄ )

PWM1'

first scrambled PWM signal

PWM2'

second scrambled PWM signal

PWM3'

third scrambled PWM signal

PWM4'

fourth scrambled PWM signal

PWMi

i-th PWM signal of the i-th PWM generator (PWMG _i ), with 1≤i≤n

PWMk

current PWM spreading code signal or k-th PWM signal of the i-th PWM generator (PWMG _i ), with 1≤k≤n. The k-th PWM signal is the signal that is currently selected as a function of the current status of the selection signal (PWM _select ) and is therefore essentially connected to the PWM output signal (PWM _out ) for the duration of this selection, typically up to level and some delay, agrees.

PWMs

nth PWM signal of the nth PWM generator (PWMG _n )

PWMont

PWM output signal of the device according to the invention

PWMselect

selection signal

PWMG1

first PWM signal generator for generating the first PWM signal (PWM ₁ )

PWMG2

second PWM signal generator for generating the second PWM signal (PWM ₂ ). The second signal generator generates the second PWM signal (PWM ₂ ) typically by a second offset (T _{off_2} ) in time with respect to the first PWM signal (PWM ₁ ). It is preferably a first PWM signal (PWM ₁ ) delayed by this second offset (T _{off_2} ).

PWMGi

i-th PWM signal generator (1≤i≤n) for generating the i-th PWM signal (PWM _i ). The i-th signal generator generates the i-th PWM signal (PWM _i ) typically by an i-th Offset (T _{off_i} ) offset in time with respect to the first PWM signal (PWM _i ). It is preferably a first PWM signal ( _PWM i ) delayed by this i-th offset (T _{off_i} ). The ith signal generator is one, namely the ith, of the n signal generators (PWMG ₁ to PWMG _n ).

PWMGk

k-th PWM signal generator (1≦k≦n) for generating the k-th PWM signal (PWM _k ), which is the currently selected spreading code signal. The k-th signal generator generates the k-th PWM signal (PWM _k ) typically by a k-th offset (T _{off_k} ) in time with respect to the first PWM signal (PWM ₁ ). It is preferably a first PWM signal (PWM ₁ ) delayed by this kth offset (T _{off_k} ). The kth signal generator is one, namely the kth, of the n signal generators (PWMG ₁ to PWMG _n ).

PWMGn

nth PWM signal generator n for generating the nth PWM signal (PWM _n ). The nth signal generator generates the nth PWM signal (PWM _n ) typically by an nth offset (T _{off_n} ) in time with respect to the first PWM signal (PWM ₁ ). It is preferably a first PWM signal (PWM ₁ ) delayed by this nth offset (T _{off_i} ).

SCR

scrambler

SG

selection signal generator. PWM modulation: The selection signal generator generates the selection signal (PWM _select ), on the basis of which the selection device (MUX) generates the current spread code signal (PWM _k ), which represents the current PWM spread code, from the n PWM signals ( PWM ₁ to PWM _n ). PDM modulation: The selection signal generator generates the selection signal (PDM _select ), on the basis of which the selection device (MUX) generates the current spread code signal (PDM _k ), which represents the current PWM spread code, from the n PDM signals ( PDM ₁ to PDM _n ).

Toff_2

Delay of the second PWM signal (PWM ₂ ) compared to the first PWM signal (PWM ₁ ) or delay of the second PWM signal (PDM ₂ ) compared to the first PWM signal (PDM ₁ )

Toff_3

Delay of the third PWM signal (PWM ₃ ) compared to the first PWM signal (PWM ₁ ) or delay of the third PWM signal (PDM ₃ ) compared to the first PWM signal (PDM ₁ )

Toff_4

Delay of the fourth PWM signal (PWM ₄ ) compared to the first PWM signal (PWM ₁ ) or delay of the fourth PWM signal (PDM ₄ ) compared to the first PWM signal (PDM ₁ )

Toff_i

Delay of the i-th PWM signal (PWM ₁ ) compared to the first PWM signal (PWM ₁ ) or delay of the i-th PWM signal (PDM ₁ ) compared to the first PWM signal (PDM ₁ )

Toff_k

Delay of the kth PWM signal (PWM _k ), the currently selected PWM spread code signal, compared to the first PWM signal (PWM ₁ ) or delay of the kth PWM signal (PDM _k ), of the currently selected PDM spread code signal compared to the first PDM signal (PDM ₁ )

Toff_n

Delay of the nth PWM signal (PWM _n ) compared to the first PWM signal (PWM ₁ ) or delay of the nth PWM signal (PDM _n ) compared to the first PWM signal (PDM ₁ )

Tpuls

PWM pulse width

TPDM

PDM period duration

TPWM

PWM period duration

Tselect

Spreading Code Period. The spreading code period is an m-times period of the PWM period (T _PWM ) or an m-times period of the PWM period (T _PDM ).

TSCS1

PWM modulation: first spread code selection time for a first selection of a PWM signal (PWM ₁ to PWM _n ) as a PWM spread code in the form of the current PWM spread code signal (PWM _k ); PDM modulation: First spread code selection time for a first selection of a PDM signal (PDM ₁ to PDM _n ) as a PDM spread code in the form of the current PDM spread code signal (PDM _k ).

TSCS2

PWM modulation: second spread code selection time for a PWM signal (PWM ₁ to PWM _n ) as a PWM spread code in the form of the current PWM spread code signal (PWM _k ) following the first selection second selection of the same; PDM modulation: second spread code selection time for a PDM signal (PDM ₁ to PDM _n ) as PDM spread code in the form of the current PDM spread code signal (PDM _k ) following the first selection second choice of the same.

Vbat

exemplary supply voltage

Claims (10)

Method for generating two, in particular n, PWM spread codes, in particular for use in a DC voltage supply and/or a DC/DC converter, in particular for supplying LEDs with electrical energy, in particular in motor vehicles, with n being a positive integer number and n>1, for generating a PWM output signal (PDM _out ) with an optimized PWM spectrum and with a specified PWM fill factor (f _cycle ), the abbreviation PDM being understood as pulse density modulation, comprising the steps a. generating a first PWM signal (PDM ₁ ) with a PWM period (T _PDM ) and the PWM fill factor (f _cycle ) and b. Generating at least one, in particular n-1, further PWM signals (PDM ₂ , second PWM signal to PDM _n , nth PWM signal), with n as a positive integer and n>1, in particular by delaying the first one PDM signal (PDMi), and i. where each i-th PWM signal (PDM ₁ ) with 1<i≤n, if generated, compared to the first signal (PDM ₁ ) by a temporal i-th offset (T _{off_i} ) compared to the first PWM signal (PDM ₁ ) is delayed and ii. wherein each of the generated, in particular n, PDM signals (PDM ₁ to PDM _n ) represents one of the generated, in particular n, PDM spread codes. procedure after claim 1 characterized in that the offset (T _{off_} i) of one, in particular all, the i-th PDM signals (PDM ₁ ) is multiplied as a PDM period (T _PDM ) by the number (i-1) divided by two, in particular multiplied by the number (i-1) divided by the number n of PDM spreading codes. Method for generating a PDM spread code modulated PWM output signal (PDM _out ) in particular for use in a DC voltage supply and/or a DC/DC converter in particular for supplying LEDs with electrical energy in particular in motor vehicles based on two, in particular n, PWM spreading codes, with n being a positive integer and n>1, and a spreading code sequence of m consecutive PWM spreading codes of these n PWM spreading codes, with m being a positive one , integer and m≥1 and a spreading code period (T _select ), for generating an optimized PWM spectrum of the PWM output signal (PDM _out ), comprising the steps a. Generating a first PWM signal (PDM ₁ ) with a PWM period and a PWM period duration (T _PDM ) and a fill factor (f _cycle ) and b. Generating one, in particular n-1, further PDM signals (PDM ₂ , second PDM signal to PDM _n , nth PDM signal) by respective delaying of the first PDM signal (PDM ₁ ) and/or generation a respective delayed first PWM signal (PDM ₁ ) and i. where each i-th PWM signal (PDM ₁ ) generated in this way with 1≤i≤n offsets the first signal (PDM ₁ ) by a temporal i-th offset (T _{off_i} ) relative to the first PWM signal (PDM ₁ ) is delayed and ii. each of the n PDM signals (PDM ₁ to PDM _n ) representing one of the n PDM spreading codes. c. Selecting a k-th PDM signal (PDM _k ) as the current PDM spread code signal from the n PDM signals (PDM ₁ to PDM _n ) depending on a selection signal (PDM _select ). procedure after claim 3 characterized in that the offset (T _{off_} i) of one, in particular all, the i-th PDM signals (PDM ₁ ) is multiplied as a PDM period (T _PDM ) by the number (i-1) divided by two, in particular divided by the number n of PDM spreading codes. procedure after claim 3 or 4 characterized in that the k-th PWM signal (PDM _k ) is selected as the current PWM spread code signal at the beginning of a PWM period of the first PWM signal (PDM ₁ ). Method according to one or more of the claims 3 until 5 characterized in that the response to a first selection of a PWM signal (PDM ₁ to PDM _n ) as a PWM spread code in the form of the current PWM spread code signal (PDM _k ) at a first spread code selection time ( Tscsi) at the time at the beginning of a PWM period of the first PWM signal (PDM ₁ ) following the next selection of a PWM spread code at an immediately following second spreading code selection time (T _SCS2 ) at the beginning of a PWM period of the first PWM signal (PDM ₁ ) after m PDM periods (T _PDM ), which corresponds to the spreading code period (T _select ), takes place. procedure after claim 6 characterized in that the selection signal (PDM _select ) is a random signal. Method according to one or more of the preceding claims, characterized in that a. that the PDM signals (PDM ₁ to PDM _n ) in n-1 partial areas with a total length of (n-1)/n of the PDM period duration (T _PDM ) assume a constant value which in $\lfloor {ƒ}_{cycle}\ast n\rfloor$

sub-areas corresponds to a 1 value and in $n-\lfloor {ƒ}_{cycle}\ast n\rfloor -1$

partial areas corresponds to a 0 value and b. that the PDM signals (PDM ₁ to PDM _n ) are modulated in a sub-area of length 1/n of the PDM period (T _PDM ) with a pulse density which corresponds to n times the modulus of the fill factor (f _cycle ) times n. Method according to one or more of the claims 3 until 8th characterized by the steps a. Division of a PDM period of the PDM period length (T _PDM ) into time slots (SL ₁ to SL _n ) in particular by a scrambler (SCR) and b. Formation of n scrambled PDM signals (PDM ₁ 'to PDM _n ') by interchanging (scrambling) signal sections of the PDM signals (PDM ₁ to PDM _n ) each of a time slot of the time slots (SLi to SL _n ) with one another, in particular by a Scrambler (SCR). procedure after claim 9 characterized in that the swapping scheme is changed cyclically from time slot to time slot, in particular by a scrambler (SCR) during the spreading code period (T _select ).

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