DE102013210814A1 - Method for producing a transistor with high electron mobility - Google Patents

Abstract

A method of manufacturing a high electron mobility transistor (100), comprising the steps of:
a) providing a HEMT structure (10);
b) applying a dielectric layer (20) to the HEMT structure (10);
c) applying a gate protection layer (30) to the dielectric layer (20) in a region provided for the gate (70);
d) opening the first dielectric layer (20) and forming ohmic contacts (40) in the regions of source (80) and drain (90);
e) depositing and patterning passivation layers (50, 60), wherein patterning is performed by dry etching with etch stop on the gate protective layer (30);
f) forming a structure for the gate (70) by patterning the passivation layers (50, 60) and selectively removing the gate protection layer (30); and
g) depositing and patterning terminal metallizations of all the electrodes (70, 80, 90) of the power transistor (100).

Description

The invention relates to a method for producing a transistor with high electron mobility. The invention further relates to a transistor with high electron mobility.

State of the art

Conventional high electron mobility transistors (HEMT) are formed by epitaxially depositing GaN / AlGaN heterostructures on sapphire, silicon carbide, or silicon substrates. The most cost-effective variant is given here in particular by the choice of silicon. A spontaneous formation of a two-dimensional electron gas (2DEG) at the GaN / AlGaN interface leads to very high mobilities (μe> 2000 cm ² / Vs) and carrier densities (n> 10 ¹³ cm ^-2 ) in the channel region. These properties offer the potential to realize transistors with extremely low conduction and switching losses. These devices are self-conducting due to the presence of the conductive channel without applied electrical gate voltage.

The pamphlets US 2011/0101370 A1 . US 2006/0099781 A1 and US 6,818,061 B2 disclose such transistors.

In conventional HEMT transistors, the gate electrode is a Schottky contact (e.g., Ni). However, this has the disadvantage that, especially at high voltages in the blocking case, the leakage currents and thus the losses of the device are very high. Furthermore, Schottky gate components in the maximum gate voltage are very limited, which in particular severely impairs dynamic performance of the components.

A simultaneous solution to these problems can be achieved by using a metal-insulator-semiconductor (MIS) structure as a gate electrode. Such devices are referred to as MIS HEMTs. However, this approach poses a number of technological challenges, in particular the quality of the semiconductor-insulator interface and the dielectric layer is very critical to the performance of the device.

Disclosure of the invention

It is thus the object of the present invention to provide an alternative method of manufacturing a high electron mobility transistor.

• a) Bereitstellen einer HEMT-Struktur;
• b) Aufbringen einer dielektrischen Schicht auf die HEMT-Struktur;
• c) Aufbringen einer Gateschutzschicht auf die dielektrische Schicht in einem für das Gate vorgesehenen Bereich;
• d) Öffnen der ersten dielektrischen Schicht und Ausbilden von Ohmschen Kontakten in den Bereichen von Source und Drain;
• e) Abscheiden und Strukturieren von Passivierungsschichten, wobei das Strukturieren mittels Trockenätzens mit Ätzstopp auf der Gateschutzschicht durchgeführt wird;
• f) Ausbilden einer Struktur für das Gate durch Strukturieren der Passivierungsschichten und selektives Entfernen der Gateschutzschicht; und Abscheiden und Strukturieren von Anschlussmetallisierungen aller Elektroden des Leistungstransistors.

The object is achieved with a method for producing a transistor with high electron mobility, comprising the steps:

• a) providing a HEMT structure;
• b) applying a dielectric layer to the HEMT structure;
• c) applying a gate protection layer to the dielectric layer in a region provided for the gate;
• d) opening the first dielectric layer and forming ohmic contacts in the regions of source and drain;
• e) depositing and patterning passivation layers, wherein structuring is performed by dry etching with etch stop on the gate protective layer;
• f) forming a structure for the gate by patterning the passivation layers and selectively removing the gate protective layer; and depositing and patterning terminal metallizations of all the electrodes of the power transistor.

It provides an alternative fabrication process for a high electron mobility transistor having improved metal-insulator-semiconductor structure quality. In particular, a higher-quality insulator layer of said structure is processed. The insulating layer advantageously prevents damage to the surface in a dry etching process. Early separation of a gate protection layer allows the use of very clean materials and equipment. As a result, an interface of semiconductor gate insulation becomes very high in quality, which increases a performance of a power transistor produced according to the present invention.

According to a second aspect, the object is achieved with a transistor with high electron mobility, comprising:
a metal-insulator-semiconductor HEMT structure characterized in that a region between a gate and a first dielectric layer of the metal-insulator-semiconductor HEMT structure is substantially not exposed in a manufacturing process of the power transistor.

Advantageous embodiments of the method and the power transistor are the subject of dependent claims.

An advantageous development of the method according to the invention provides that in step f) the gate protection layer is not completely removed. In this way, advantageously, a first alternative embodiment of the power transistor is provided in which the gate protection acts as a gate electrode and is thus actively used. The advantage of this variant is the best quality Realized boundary layer between gate protection and gate insulation.

A further advantageous development of the method according to the invention provides that, in step e), an opening of the first passivation layer is not carried out in the active gate area. In this way, a second alternative embodiment of the power transistor is advantageously realized. This variant has the advantage that the entire surface of the gate dielectric is protected during the deposition and structuring of the ohmic contacts, as well as their alloying.

A further advantageous embodiment of the method according to the invention provides that a layout of the structure for the gate is performed with defined geometry parameters. In this way, a field distribution can be advantageously influenced by the specific definition of the geometry parameters.

A further advantageous embodiment of the method according to the invention provides that in step b) a plurality of dielectric layers having a defined layer sequence are applied to the HEMT structure. In this way, a threshold voltage of the transistor can be selectively influenced by means of a deliberately selected layer sequence.

A further advantageous embodiment of the method according to the invention provides that in step f) a T-shaped structure is formed for the gate. In this way, a targeted influencing of the electric field is possible. The T-shape is thus an advantageous structure that can be represented in a simple manner by means of the method according to the invention.

A further advantageous embodiment of the power transistor according to the invention provides that the gate has at least partially a layer with a high temperature stability. In this way, an effective protection of the underlying gate insulation layer can be provided in a temperature process, so that the gate insulation layer remains as uninfluenced as possible, which advantageously supports a high-quality formation of the two-dimensional electron gas.

A further advantageous embodiment of the power transistor according to the invention provides that the layer is at least one of highly doped poly Si, SiGe, metal. By a suitable choice of different materials can be achieved in this way a sufficient temperature stability. An advantage of this is that no interaction with the layers below is effected during subsequent temperature steps.

The invention will be described in detail below with further features and advantages with reference to several figures. All described or illustrated features, alone or in any combination form the subject matter of the invention, regardless of their summary in the claims or their dependency, as well as regardless of their formulation or representation in the description or in the figures. The figures are primarily intended to illustrate the principles essential to the invention.

In the figures shows:

1 a basic structure of a HEMT structure;

2 a gate insulation layer and a gate protection on said HEMT structure;

3 the opened gate insulation and deposited and alloyed ohmic contacts;

4 a deposited and patterned first passivation layer on the HEMT structure;

5 a deposited and patterned second passivation layer on the HEMT structure;

6 a representation of metallizations of all electrodes of the power transistor;

7 a first alternative embodiment of the power transistor according to the invention;

8th a second alternative embodiment of the power transistor according to the invention; and

9 a basic sequence of an embodiment of the method according to the invention.

Embodiments of the invention

A gate-first process, in which a gate insulator is deposited first, is in principle preferable for the production of an MIS HEMT from the point of view of the quality of the semiconductor-insulator interface and prevention of possible contamination. However, this approach is very difficult to combine with the conventional process flow, since the necessary thicker field passivation on the thin and sensitive gate insulation must be selectively opened.

On the one hand, the selectivity of the process between the materials used for gate and field insulation is usually not given, and on the other hand, with, for example, dry etching with damage to the surface of the gate insulation count and thus with a degradation of the electrical properties.

According to the invention, therefore, an improved manufacturing process of a MIS-HEMT power transistor is proposed, which is explained below with reference to figures.

1 shows a basic structure of a so-called HEMT structure 10 , The HEMT structure 10 has a substrate 1 (For example, silicon) on, by means of MOCVD (English metal-organic chemical vapor deposition) a buffer layer 2 , a channel layer 3 (For example, a crystalline GaN layer in the nm range) and a barrier layer 4 (Eg AlGaN) are deposited epitaxially. The channel layer 3 and the barrier layer 4 form in this way a so-called heterostructure, being at an interface of the two layers 3 . 4 due to physical effects, a channel is formed which has electrons in a high concentration and with a high mobility. This two-dimensional electron gas 5 can only be two-dimensional in the lateral direction along the interface between the two layers 3 . 4 move.

2 shows that now a dielectric layer 20 ("Gate Isolation Layer") on the HEMT structure 10 is deposited on the in a region corresponding to the later gate electrode, a gate protective layer 30 is deposited. The dielectric layer 20 is preferably formed as a very thin (a few nm thick) dielectric layer and is formed, for example by means of in-situ or ex-situ deposition of SiN, SiO ₂ , Al ₂ O ₃ , etc. Optionally, an ex situ deposition of a second or third dielectric layer can also be carried out. The layer sequence is thereby preferably chosen so that the threshold voltage of the transistor can be influenced. The gate protection layer 30 For example, it may be PolySi or SiGe, which is patterned. The gate protection layer 30 should be sufficiently temperature stable, because a high temperature budget is required for the subsequent formation of ohmic contacts and a reaction of gate protection layer 30 should be avoided with the underlying semiconductor structure.

3 Fig. 10 shows in principle a result of opening the gate insulation layer, depositing ohm metal, and alloying at a high temperature (typically between about 600 ° C and about 900 ° C). Due to the presence of the gate protection layer 30 can advantageously no impurities on the surface of the dielectric layer in the said formation of the ohmic contacts 20 deposit.

4 shows a deposition of a first passivation layer 50 (For example, SiN or SiO ₂ ), for example, with a thickness between about 10 nm and about 100 nm. Thereafter, a structuring of the first passivation layer 50 For example, by means of a dry etching process with an etch stop on the gate protective layer 30 , Geometric parameters L1, L2, L3 are suitably selected by considering the electric field distribution, where L1 is a length of the effective gate protection and L2 and L3 are lengths for suitable formation of the T-structure for the gate 70 represent.

Due to the fact that the first passivation layer 50 dry structured, the gate area must also be exposed. However, during this exposure, the etching process can not be stopped in a completely defined manner, so that overetching or modification of the surface typically takes place in areas to the left and right of the gate protection layer 30 is exaggerated by rounded areas. This means that in this case an attack of the dielectric layer 20 takes place.

5 shows a selective removal of the gate protective layer 30 for example by means of a wet-chemical method or by means of a highly selective, plasmaless dry etching method (eg by means of ClF ₃ ). Then a second passivation layer 60 made of the same or different material as the first passivation requirement 50 deposited. It can be seen that the thickness of this second passivation layer 60 and the parameters L1, L2, L3 are selected such that an optimal "T-gate structure" is formed. Suitable numerical values for this can be determined, for example, by a two-dimensional simulation.

6 shows deposition and patterning of the gate metallization for the gate 70 (for example, by vapor deposition or sputtering) and deposition of power metallization for Source 80 and drain 90 of the power transistor (for example by means of electroplating in the micron range). Preferred materials for metallization are Cu or Al. 7 shows a first alternative embodiment of the power transistor according to the invention 100 , In this variant, the gate protection layer 30 deposited only after the formation of the ohmic contacts. This requires the gate protection layer 30 not advantageous particularly stable to temperature, because the rest of the process no longer has a high temperature budget. It can be used in this case, therefore, a metallic layer, such as aluminum or a layered structure of titanium and aluminum.

This can either according to the in the 4 to 6 shown process steps be further processed or used directly as gate metallization. In this case, therefore, the gate protection layer becomes advantageous 30 a functional use as a gate 70 fed. In this way, a quality of an interface between the gate protective layer 30 and the dielectric layer 20 be carried out as possible because the said interface was exposed to any atmosphere or any aggressive environments during an etching process.

8th shows a second alternative embodiment of the line transistor according to the invention 100 , It can be seen that in this variant, a deposition of the first passivation layer 50 followed by an opening of this first passivation layer 50 is performed in the ohmic contacts, but not in the active gate region.

This is followed by a deposition and alloying of the ohmic contacts, after which a further processing according to the in the 4 to 6 shown process steps is performed. This variant has the advantage that the entire surface of the gate dielectric is protected during the deposition and structuring of the ohmic contacts, as well as their alloying. Thus, advantageously, the incorporation of possible contaminants can be avoided very effectively. This variant requires an additional mask layer.

9 shows a basic sequence of an embodiment of the method according to the invention.

In a first step S1 becomes an HEMT structure 10 provided,

In a second step S2, a deposition of a dielectric layer is performed 20 on the HEMT structure 10 carried out.

In a third step S3, a gate protection layer is formed 30 on the dielectric layer 20 in one for the gate 70 applied area provided.

In a fourth step S4, an opening of the first dielectric layer 20 and forming ohmic contacts 40 in the areas of Source 80 and drain 90 carried out.

In a fifth step S5, deposition and patterning of passivation layers takes place 50 . 60 wherein the patterning by means of dry etching with etch stop on the gate protective layer 30 is carried out.

In a sixth step S6, a structure for the gate 70 by structuring the passivation layers 50 . 60 and selectively removing the gate protective layer 30 educated.

Finally, in a seventh step S7, deposition and patterning of terminal metallizations of all electrodes takes place 70 . 80 . 90 of the power transistor 100 ,

In summary, the invention proposes a method for producing a MIS-HEMT power transistor, which has a very good transition region between the gate electrode and the gate insulation layer. In this way, the two-dimensional electron gas can advantageously be formed very well. In addition, as early as possible application of the gate protective layer to the gate insulating layer is made possible by the deposition of the gate insulating layer. This is done at a time when no metals have yet been processed, so that materials and tools with a high degree of purity can be used.

The invention thus proposes an alternative process by means of which a quality of the MIS structure can be improved. A quality of the semiconductor-insulator interface advantageously contains very few defects, as a result of which a high performance of the power semiconductor can be achieved. Compared to conventional MIS-HEMT transistors with high electron mobility, in which first the first passivation layer is deposited, which is opened and only then the gate insulation layer is deposited, a substantially higher purity of said transition region gate-gate insulation layer can be achieved by the inventive method.

Although the invention has been disclosed in terms of specific embodiments, it is by no means limited thereto. In particular, it is possible to use the method according to the invention for other suitable materials from the III-V group.

The person skilled in the art will thus modify the features of the invention in a suitable manner and / or combine them with one another, without departing from the essence of the invention.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 2011/0101370 A1 [0003]
• US 2006/0099781 A1 [0003]
• US 6818061 B2 [0003]

Claims (9)

Method for producing a transistor ( 100 ) with high electron mobility, comprising the steps: a) providing an HEMT structure ( 10 ); b) applying a dielectric layer ( 20 ) on the HEMT structure ( 10 ); c) applying a gate protection layer ( 30 ) on the dielectric layer ( 20 ) in one for the gate ( 70 ) area; d) opening the first dielectric layer ( 20 ) and forming ohmic contacts ( 40 ) in the areas of Source ( 80 ) and drain ( 90 ); e) depositing and structuring of passivation layers ( 50 . 60 ), wherein structuring by dry etching with etch stop on the gate protective layer ( 30 ) is carried out; f) forming a structure for the gate ( 70 ) by structuring the passivation layers ( 50 . 60 ) and selective removal of the gate protection layer ( 30 ); and g) depositing and structuring terminal metallizations of all electrodes ( 70 . 80 . 90 ) of the power transistor ( 100 ). The method of claim 1, wherein in step f) the gate protective layer ( 30 ) is not completely removed. Method according to claim 1 or 2, wherein in step e) an opening of the first passivation layer ( 50 ) is not performed in the active gate area. Method according to one of claims 1 to 3, wherein a layout of the structure for the gate ( 70 ) is performed with defined geometry parameters (L1, L2, L3). Method according to one of the preceding claims, wherein in step b) the HEMT structure ( 10 ) a plurality of dielectric layers are applied with a defined sequence of layers. Method according to one of the preceding claims, wherein in step f) a T-shaped structure for the gate ( 70 ) is formed. Transistor ( 100 ) with high electron mobility, comprising: a metal-insulator-semiconductor HEMT structure ( 10 . 20 . 70 . 80 . 90 ), characterized in that an area between a gate ( 70 ) and a first dielectric layer ( 20 ) of the metal-insulator-semiconductor HEMT structure ( 10 . 20 . 70 . 80 . 90 ) in a manufacturing process of the power transistor ( 100 ) is not substantially exposed. Transistor ( 100 ) according to claim 7, characterized in that the gate ( 70 ) at least partially a layer ( 30 ) having a high temperature stability. Transistor ( 100 ) according to claim 8, characterized in that the layer ( 30 ) at least one of: highly doped poly Si, SiGe, metal.

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