DE102013210624A1 - Method for producing a semiconductor structure with an implantation of ions in a channel region - Google Patents

Abstract

A method for manufacturing a semiconductor structure comprises implanting ions through an opening in a dielectric structure into a channel region of an active region. The active region is formed in a crystalline semiconductor material and comprises a source region, a drain region and the channel region. The dielectric structure covers the source region and the drain region. At least part of the channel region is amorphized by the implantation of the ions. The opening is filled with an elastically tensioned material. The channel region is recrystallized in the presence of the elastically strained material in the opening.

Description

The present invention relates generally to the fabrication of integrated circuits, and more particularly to integrated circuits comprising transistors having a resiliently strained channel region.

Integrated circuits include a large number of circuit elements, particularly including field effect transistors. A field effect transistor includes at least one gate electrode separated from and electrically isolated from a channel region by a gate insulating layer. Next to the canal area there is a source area and a drain area. The channel region, the source region and the drain region are formed in a semiconductor material, wherein the doping of the channel region differs from the doping of the source region and the drain region. Between the source region and the channel region as well as between the channel region and the drain region, there can be a pn junction in each case.

By an electric voltage applied to the gate electrode, the transistor between a switched-on state in which a relatively high electrical conductivity between the source region and the drain region is present, and a switched-off state in which between the source region and the drain region, a relatively low electrical conductivity exists, be switched.

To improve the electrical conductivity between the source region and the drain region in the on state and to increase the switching speed of a transistor, the semiconductor material in the channel region can be elastically clamped. Due to the elastic strain, the mobility of the charge carriers in the channel region can be influenced. An elastic compressive stress can improve the mobility of holes in silicon, while an elastic tensile stress can improve the mobility of electrons in silicon. Therefore, for p-channel transistors in which the conductivity of the channel region in the on state depends on the mobility of the holes, an elastic compressive stress in the channel region is advantageous, while for n-channel transistors in which the conductivity of the channel region in the on state of the mobility of the Electrons depends, an elastic tensile stress is beneficial.

There are several techniques to achieve the elastic strain of the channel region. For example, a layer of an elastically strained dielectric material, such as a layer of elastically strained silicon nitride, may be deposited over a transistor, or portions of a transistor, such as sidewall spacers disposed adjacent the gate electrode, may be fabricated from an elastically strained dielectric material. The presence of the elastically strained dielectric material may affect the conductor material of the channel region to be under an elastic strain.

Other techniques for achieving elastic strain use the stress memory of materials such as silicon. Such techniques are often referred to by the English term "stress memorization". In this case, the material to be clamped, which may be silicon in the source and drain regions of the transistor, is amorphized and in the presence of an elastically strained material layer, which is typically a layer deposited over the transistor of a dielectric material such as silicon nitride, recrystallized. During the recrystallization, the crystal structure of the recrystallized material is influenced by the elastically strained material layer in such a way that an intrinsic elastic strain is obtained, which can at least partially persist even after the removal of the elastically strained material layer.

In the 45 nanometer technology node and below, the so-called high-k + metal gate technique (HKMG technique) is often used. In this technique, the gate insulating layer is wholly or partly made of a material having a larger dielectric constant k than silicon dioxide, for example, hafnium oxide and / or hafnium silicon oxynitride. The gate electrode is made of a metal, wherein different metals can be used for p-channel transistors and n-channel transistors in order to adapt the work function of the gate electrode to the respective doping of the channel region.

In transistors made by the HKMG technique, the metal of the gate electrode can be made with an elastic strain. The elastic voltage state of the gate electrode may affect the elastic voltage of the channel region of the transistor. The elastic strain of the metal of the gate electrode can be achieved by the use of suitable parameters of a deposition process used in the deposition of the metal of the gate electrode. The use of elastically strained metal gate electrodes may be advantageous in highly miniaturized field effect transistors according to the 45 nanometer technology node and below, as other techniques for creating elastic strain on the channel region, such as For example, elastically strained layers that are formed over the transistor or can lose voltage memory techniques at very small feature sizes.

Methods for providing elastically strained channel regions of field-effect transistors according to the prior art are, for example, in CY Kang, et. al., "A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFETs utilizing Si (110) Channel for Both N and PMOSFETs", Proceedings of the Electron Devices Meeting, 2006, IEDM '06 International, pp. 1-4 ; CY Kang et. al., "Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate / High-k Dielectric SOI FinFETs", IEEE Electron Devices Letters, Vol. 5, May 2008, pp. 487-490 ; and K.-M. Tan, "Diamond-Like Carbon (DLC) Liner: A New Stressor for P-Channel Multiple-Gate Field-Effect Transistor", IEEE Electron Device Letters, Vol. 7, July 2008, pp. 750-752 described.

A disadvantage of the known techniques for producing elastically strained channel regions of transistors by means of elastically strained metal gate electrodes is that the strength of the elastic strain that can be achieved is limited.

An object of the present invention is to provide a technique with which a stronger elastic strain of the channel region is achieved.

A method of fabricating a semiconductor structure according to the invention comprises implanting ions through an opening in a dielectric structure into a channel region of an active region. The active region is formed in a crystalline semiconductor material and includes a source region, a drain region, and the channel region. The dielectric structure covers the source region and the drain region. At least part of the channel region is amorphized by the implantation of the ions. The opening is filled with an elastically strained material and the channel region is recrystallized in the presence of the elastically strained material in the opening.

Due to the amorphization of the channel region occurring during the implantation of the ions through the opening in the dielectric structure, the crystalline order of the semiconductor material in the channel region is lost. Upon recrystallization of the channel region, the crystalline order of the semiconductor material in the channel region is restored. However, the elastic stress of the elastically strained material in the opening, which is located above the channel region, acts on the semiconductor material. As a result, an intrinsic elastic strain of the semiconductor material in the channel region can be effected. The elastic strain achieved in this way can be stronger than the elastic strain that can be achieved if, as described above, only one elastically strained gate electrode is arranged above the channel region without amorphization and recrystallization of the channel region being carried out.

The dielectric structure may be configured to reduce at least an implantation of ions into the source region and the drain region such that the source region and the drain region still have a crystalline order immediately after the implantation of the ions. As a result, the amorphization and the recrystallization can be carried out selectively in the channel region, so that the elastic strain can be provided specifically in the channel region.

The dielectric structure may include a sidewall spacer adjacent the opening and an interlayer dielectric. Thereby, the method can be well integrated into a process for manufacturing a semiconductor structure in which a gate electrode containing a metal is manufactured by an exchange gate method. The elastically strained material may contain a metal.

In some embodiments, the elastically strained material forms a gate electrode in the opening. Thereby, the filling of the opening with the elastically strained material in the manufacture of a gate electrode can be performed with an exchange gate method, so that no additional material deposition processes are required to fill the opening with the elastically strained material. Prior to filling the opening with the elastically strained material, a gate insulating layer of a high dielectric constant material may be formed at least at the bottom of the opening.

In other embodiments, after recrystallization of the channel region, the elastically strained material may be removed from the opening and a gate electrode may be formed in the opening. Forming the gate electrode may include filling the opening with a gate electrode material after removing the elastically strained material from the opening. This can be used to generate the elastic strain of the channel region, which takes place in the recrystallization of the channel region, a first material which is particularly well suited for generating the elastic strain of the channel region, for example because it has a suitable strength of the strain and / or the right Type of tension (compressive stress or tensile stress) for the provides the type of transistor to be manufactured. The gate electrode may be formed of another material that has particularly advantageous properties in terms of controlling the current flow through the transistor, for example, a well-fitting work function.

Prior to filling the opening with the elastically strained material, in such embodiments, a gate insulating layer may be formed at least at the bottom of the opening, the gate insulating layer at least partially remaining at the bottom of the opening upon removal of the elastically strained material and the gate electrode formed over the gate insulating layer. The gate insulating layer may include a high-dielectric-constant material, and the gate-electrode material may include a metal.

The recrystallization of the channel region may include performing a heat treatment. The heat treatment may include irradiation of the semiconductor structure with electromagnetic radiation. A duration of the heat treatment may be shorter than 100 ms and / or the heat treatment may be performed at a temperature of 1000 ° C or more. By a short-term heat treatment at a relatively high temperature, undesired diffusion of dopants, in particular dopants in the source region and in the drain region of the active region, can be substantially avoided or at least reduced. As a result, a change in doping profiles, in particular in the transition region between the source region and the channel region and in the transition region between the drain region and the channel region, which could have effects on the electrical properties of the transistor, can be substantially avoided or at least reduced.

In the channel region, ions of a semiconductor material, in particular silicon ions, or ions of a noble gas, in particular xenon ions, can be implanted through the opening in the dielectric structure. By implanting such ions, an effective amorphization of the channel region can be achieved without substantially changing the electrical properties of the channel region, in particular its doping.

The method may include forming a source contact structure that electrically contacts the source region, a drain contact structure that electrically contacts the drain region, and a gate contact structure that electrically contacts the gate electrode. Thereby, the transistor produced in the process can be connected to other circuit elements.

A method of fabricating a semiconductor structure according to the present invention may include providing a semiconductor structure having a first active region, a second active region, and a dielectric structure. The active regions are formed in a semiconductor substrate and have a crystalline order. Each of the active regions includes a source region, a channel region, and a drain region. The source region and the drain region of the first active region are p-doped, and the source region and the drain region of the second active region are n-doped. The dielectric structure has a first opening over the channel region of the first active region and a second opening over the channel region of the second active region. At the first active area and at the second active area, a method is performed with some or all of the features described above. Thereby, suitable elastic strains of the channel region can be provided in a p-channel transistor formed on the basis of the first channel region and in an n-channel transistor formed on the basis of the second channel region.

The implantation of ions through the first opening and the implantation of ions through the second opening may be performed in a common ion implantation process. Thus, only one ion implantation process is required for amorphizing the channel regions of the first active region and the second active region, which may in particular comprise irradiation of the entire semiconductor structure with ions.

The recrystallization of the channel region of the first active region and the recrystallization of the channel region of the second active region can be carried out in a common heat treatment, so that only one heat treatment is required for recrystallization of the channel region of the first active region and the channel region of the second active region, in particular may be a heat treatment of the entire semiconductor structure.

The elastically strained material with which the first opening is filled may have an elastic tensile stress, and the elastically strained material with which the second opening is filled may have an elastic compressive stress. Due to the elastic tensile stress of the material with which the first opening is filled, an elastic compressive stress in the channel region of the first active region can be achieved, and by the elastic compressive stress of the elastically strained material in the second opening, an elastic tensile stress in the channel region of the second active Area can be achieved. Thus, for a p-channel transistor based on the first for an n-channel transistor which is fabricated based on the second active region, one respective elastic strain suitable for improving the mobility of the respective majority carriers in the channel region is provided.

Providing the semiconductor structure may include forming a first gate structure over the first active region and a second gate structure over the second active region. Each of the gate structures may include a dummy gate electrode and a sidewall spacer located adjacent to the dummy gate electrode. The source region and the drain region of the first active region are formed adjacent to the first gate structure, and the source region and the drain region of the second active region are formed adjacent to the second gate structure. An interlayer dielectric is deposited and a polishing process is performed. In the polishing process, a surface of the interlayer dielectric is planarized and the dummy gate electrodes of the first and second gate structures are exposed. The first and second openings are formed by removing the exposed dummy gate electrodes.

Embodiments of the invention will be described with reference to the figures. Show it:

1 to 4 schematic cross-sectional views of a semiconductor structure in stages of a manufacturing process according to an embodiment; and

5 and 6 schematic cross-sectional views of a semiconductor structure in stages of a manufacturing process according to another embodiment.

1 shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of a method according to the invention for producing a semiconductor structure according to the present invention.

The semiconductor structure 100 includes a substrate 101 , In some embodiments, the substrate may be 101 a solid semiconductor substrate, for example, a wafer or chip of a semiconductor material such as silicon. In other embodiments, the substrate 101 a semiconductor on insulator substrate (often also referred to with the term "semiconductor-on-insulator substrate"), which comprises a layer of a semiconductor material, such as silicon, which is arranged above a carrier substrate and from this by an electrically insulating Layer of a dielectric material, such as silicon dioxide, is separated. The carrier substrate may be a wafer or chip made of a semiconductor material, for example silicon.

The substrate 101 includes a first active area 102 and a second active area 103 , The active areas 102 . 103 are through an isolation trench structure 104 from each other and from other circuit elements (not shown) of the semiconductor structure 100 outside the in 1 represented part of the semiconductor structure 100 can be located, electrically isolated. The isolation trench structure 104 may be a shallow trench isolation, the trenches in the substrate 101 which are filled with an electrically insulating material such as silicon dioxide.

The first active area 102 includes a source region 105 , a canal area 106 and a drainage area 107 , where the channel area 106 between the source area 105 and the drainage area 107 located. The source area 105 and the drainage area 107 can, as in 1 shown include a source extension and a drain extension, respectively, extending under the sidewall spacers 123 extend and may have a smaller depth than the rest of the source region 105 and the drainage area 107 , The source area 105 and the drainage area 107 can also silicide areas 111 . 112 include.

Over the active area 102 there is a gate structure 115 , The gate structure 115 includes a dummy gate electrode 117 , which may contain polysilicon, for example. The dummy gate electrode 117 is over the canal area 106 of the active area 102 and from this through a dummy gate insulating layer 119 , which may contain, for example, silica, separated. Above the dummy gate electrode 117 can be a topcoat 126 may contain, for example, silicon nitride. Next to the dummy gate electrode 117 can be a sidewall spacer 123 located, which may contain, for example, silicon nitride. Between the dummy gate electrode 117 and the sidewall spacer 123 can become an intermediate layer 121 are using a different material than the material of the sidewall spacer 123 contains, for example, silicon dioxide.

Similar to the active area 102 includes the active area 103 a source area 108 , a canal area 109 and a drainage area 110 , where the channel area 109 between the source area 108 and the drainage area 110 located. The source area 108 and the drainage area 110 may include a source extension or a drain extension, as in FIG 1 shown.

Above the canal area 109 there is a gate structure 116 , The gate structure 116 includes a dummy gate insulating layer 120 , a dummy gate electrode 118 , a topcoat 127 a sidewall spacer 124 and an intermediate layer 122 , The parts of the gate structure 116 may contain substantially the same materials as the corresponding parts of the gate structure 115 , In the source area 108 and in the drainage area 110 can silicic areas 113 . 114 are located.

About the active areas 102 . 103 and the gate structures 115 . 116 there is an interlayer dielectric 125 containing a dielectric material, for example silicon dioxide.

In the in 1 shown stage of the manufacturing process, the active areas 102 . 103 contain a crystalline semiconductor material. In particular, the source regions 105 . 108 , the channel areas 106 . 109 and the drainage areas 107 . 110 have a crystalline order. In a crystalline order, the arrangement of the atoms of the material has a long-range order, wherein deviations from an ideal long-range order such as lattice defects and / or grain boundaries may be present. In some embodiments, the substrate may be 101 or at least the part of the substrate 101 in which are the active areas 102 . 103 (For example, the semiconductor layer of a semiconductor on insulator structure in embodiments in which the substrate 101 a semiconductor on insulator substrate) is substantially a single crystalline structure having a continuous, uniform and / or homogeneous crystal lattice.

The active areas 102 . 103 may be doped, with the doping of the source regions 105 . 108 and the drainage areas 107 . 110 from the doping of the channel region 106 . 109 of the respective active area.

In the active area 102 can the source area 105 and the drainage area 107 be p-doped and the channel region 106 may be n-doped, corresponding to the doping of the source, drain and channel regions in a p-channel transistor. In the active area 103 can the source area 108 and the drainage area 110 be n-doped, and the channel region 109 may be p-doped, corresponding to the doping of the source, drain and channel regions in an n-channel transistor. The dopant concentrations in the source regions 105 . 108 , the drainage areas 107 . 110 and the channel areas 106 . 109 may correspond to common values of dopant concentrations in active regions of field effect transistors.

In the 1 illustrated semiconductor structure 100 can be prepared as follows.

The substrate 101 may be provided in the form of a bulk silicon substrate or a semiconductor on insulator substrate. In the substrate 101 can the isolation trench structure 104 be formed by methods for producing a shallow trench isolation, which may include in particular photolithography processes, etching processes, oxidation processes and deposition processes. Subsequently, the active areas 102 . 103 doped with the aid of ion implantation processes, wherein the doping of the active regions produced in these ion implantation processes 102 . 103 essentially the desired doping of the channel regions 106 . 109 equivalent. In the doping of the active area 102 can be the active area 103 covered with a mask, for example a photoresist mask (not shown), and in the doping of the active region 103 can be the active area 102 covered with a mask.

After that, the gate structures can 115 . 116 be formed. For this purpose, layers of the materials of the dummy gate insulating layers 119 . 120 , the dummy gate electrodes 117 . 118 and the cover layers 126 . 127 deposited and patterned using photolithography processes and etching processes. Thereafter, layers of materials of the intermediate layers 121 . 122 and the sidewall spacer 123 . 124 be deposited.

The sidewall spacers 123 . 124 can be formed by means of an anisotropic etching process, for example, a dry etching process, wherein the layer of the material of the intermediate layers 121 . 122 can be used as an etch stop layer. The anisotropic etch process may be terminated as soon as the portions of the sidewall spacer material layer 123 . 124 over substantially horizontal parts of the semiconductor structure 100 , such as the surfaces of the source regions 105 . 108 , the drainage area 107 . 110 and the cover layers 126 . 127 while portions of the layer are on the sidewalls of the dummy gate electrodes 117 . 118 stand still and the sidewall spacers 123 . 124 form. After that, those can not be removed from the sidewall spacers 123 . 124 covered parts of the layer of the material of the intermediate layers 121 . 122 be removed by an etching process.

Thereafter, ion implantation processes for doping the source regions 105 . 108 and the drainage areas 107 . 110 be performed. In the implantation of dopants in the source region 105 and the drainage area 107 of the active area 102 can be the active area 103 covered with a mask, such as a photoresist mask, and the active area 102 may be during the implantation of ions into the source region 108 and the drainage area 110 of the active area 103 covered with a mask to the source and Drain areas of the active area 102 and the active area 103 to dope differently.

In embodiments where, as described above, under the sidewall spacers 123 . 124 Source and drain extensions are located with a doping corresponding to the doping of the respective adjacent source and drain regions, they can by additional ion implantation processes, after the formation of the dummy gate electrodes 117 . 118 and before the formation of the sidewall spacers 123 . 124 be formed.

After implantation of dopants in the source regions 105 . 108 and the drainage areas 107 . 110 For example, a heat treatment may be performed to activate the introduced dopants.

Thereafter, the silicide areas 111 . 112 . 113 . 114 by forming a layer of a metal such as tungsten, nickel and / or titanium over the semiconductor structure 100 deposited and a heat treatment is performed to a chemical reaction between the metal and the semiconductor material of the source regions 105 . 108 and the drainage areas 107 . 110 trigger. Excess metal that has not reacted with the semiconductor material can be removed by an etching process. Formation of silicide in the dummy gate electrodes 117 . 118 which, as stated above, may contain polysilicon, may pass through the cover layers 126 . 127 , the intermediate layers 121 . 122 and the sidewall spacers 123 . 124 prevents contact between the metal and the dummy gate electrodes 117 . 118 prevent.

In some embodiments, activation of the dopants in the source regions 105 . 108 and the drainage areas 107 . 110 and the formation of silicide areas 111 . 112 . 113 . 114 be performed with a heat treatment, while in other embodiments, two successive heat treatments can be performed.

After the formation of silicide areas 111 . 112 . 113 . 114 may be the interlayer dielectric 125 be deposited. In some embodiments, where the interlayer dielectric 125 For this purpose, a chemical vapor deposition (CVD) or a plasma enhanced chemical vapor deposition (PECVD) process can be carried out using a reaction gas containing tetraethyl orthosilicate (TEOS).

2 shows a schematic cross-sectional view of the semiconductor structure 100 at a later stage of the manufacturing process.

After the deposition of the interlayer dielectric 125 a polishing process can be carried out. The polishing process may be a chemical-mechanical polishing process in which the semiconductor structure 100 is moved relative to a surface of a polishing pad, and an interface between the semiconductor structure 100 and a polishing agent is supplied to the polishing pad. The polishing agent may be chemicals that interfere with the materials on the surface of the semiconductor structure 100 react, contain. Products of such chemical reactions may be due to the friction between the semiconductor structure 100 and the polishing pad and / or abrasives contained in the polishing agent are removed.

In the polishing process, a surface of the interlayer dielectric 125 be planarized, so that, for example, the in 1 shown mound of the interlayer dielectric 125 , which are involved in the deposition of the interlayer dielectric 125 over the gate structures 115 . 116 can be removed, and one has a substantially planar surface of the semiconductor structure 100 receives. In addition, in the polishing process, the outer layers 126 . 127 on the dummy gate electrodes 117 . 118 and parts of the sidewall spacers 123 . 124 and the intermediate layers 121 . 122 located above the dummy gate electrodes 117 . 118 and next to the cover layers 126 . 127 be removed. As a result, the dummy gate electrodes are after the polishing process 117 . 118 at the surface of the semiconductor structure 100 free. The after the polishing process in the semiconductor structure 100 remaining parts of the interlayer dielectric 125 , the side wall spacer 123 . 124 and the intermediate layers 121 . 122 form a dielectric structure 203 containing the exposed dummy gate electrodes 117 . 118 encloses annularly in each case.

After the polishing process, the exposed dummy gate electrodes 117 . 118 be removed. For this purpose, an etching process adapted to the material of the dummy gate electrodes may be performed 117 . 118 relative to the materials of the dielectric structure 203 ie, the materials of the interlayer dielectric 125 , the intermediate layer 121 . 122 and the sidewall spacer 123 . 124 selectively remove. In embodiments in which the intermediate layers 121 . 122 and the interlayer dielectric 125 Containing silica, the sidewall spacers 123 . 124 Silicon nitride and the dummy gate electrodes 117 . 118 Contain polysilicon, can be used to remove the dummy gate electrodes 117 . 118 an etching process adapted to selectively etch polysilicon relative to silicon dioxide and silicon nitride may be used. The etching process may be a wet etching process or a Be dry etching process. In the etching process, the dummy gate insulating films 119 . 120 serve as Ätzstoppschichten, causing damage to the channel areas 106 . 109 active areas 102 . 103 avoided by chemicals used in the etching process, or at least reduced in their effects.

By removing the dummy gate electrodes 117 . 118 be openings 201 . 202 in the dielectric structure 203 formed in the same places of the semiconductor structure 100 are as before the dummy gate electrodes 117 . 118 , Thus, the opening is 201 the dielectric structure 203 over the canal area 106 of the active area 102 , and the opening 202 the dielectric structure 203 is located above the canal area 109 of the active area 103 ,

After removing the dummy gate electrodes 117 . 118 may be the dummy gate insulating layers 119 . 120 can be removed, which can be done by another etching process, which may be a wet or dry etching process. In other embodiments, the dummy gate insulating layers 119 . 120 first at the bottom of the openings 201 . 202 remain and only after the ion implantation process 204 and before the formation of final gate insulating layers 301 . 302 (please refer 3 ), which are described in more detail below, are removed.

Through the openings 201 . 202 the dielectric structure 203 can ions in the channel areas 106 . 109 active areas 102 . 103 be implanted. For this purpose, an ion implantation process may be carried out in 2 schematically by arrows 204 is shown. In the ion implantation process 204 can simultaneously ions through the opening 201 and through the opening 202 be implanted. Thus, the ion implantation process 204 a common ion implantation process, in which an implantation of ions through the opening 201 and implantation of ions through the opening 202 be performed.

In the ion implantation process 204 For example, the semiconductor structure may be irradiated with ions of an element which, when present in the semiconductor material of the active regions 102 . 103 is substantially no doping of the semiconductor material causes. In some embodiments, the semiconductor structure 100 in the ion implantation process 204 be irradiated with silicon ions. In other embodiments, ions of semiconductor material other than silicon, such as germanium ions, may be used. In other embodiments, ions of a noble gas, such as xenon ions, may be used.

The energy of the ion implantation process 204 The ions used may be in the range of about 5 keV to about 30 keV, and the dose of ions may be in the range of about 5 x 10 ¹³ atoms / cm ² to about 2 x 10 ¹⁵ atoms / cm ² .

Ions passing through the openings 201 . 202 can be implanted in the canal areas 106 . 109 that are at the bottom of the openings 201 . 202 are located, penetrate and with atoms of the channel areas 106 . 109 , interact. As a result, atoms of the semiconductor material of the channel regions 106 . 109 be removed from their places in the crystal lattice, whereby the originally existing crystalline order of the semiconductor material can be destroyed. The in the ion implantation process 204 applied ion dose can be chosen such that at least in parts of the channel regions 106 . 109 the crystalline order of the atoms of the semiconductor material is substantially lost, and the semiconductor material is amorphized. This forms amorphous areas 205 . 206 in which essentially no remote ordering of the atoms of the semiconductor material is no longer present, but a certain order of proximity of the atoms may still be present.

In some embodiments, the amorphous region 205 the entire canal area 106 of the active area 102 included and the amorphous area 206 can the entire channel area 109 of the active area 103 contain. In other embodiments, only parts of the channel regions 106 . 109 be amorphized, for example, parts of the channel areas 106 . 109 near the bottom of the openings 201 . 202 located surfaces of the channel areas 106 . 109 , In other embodiments, the amorphous regions 205 . 206 next to the channel areas 106 . 109 also other parts of the active areas 102 . 103 as the channel areas 106 . 109 include. For example, the amorphous region 205 Parts of the source area 105 and the drainage area 107 included, and the amorphous area 206 can be parts of the source area 108 and the drainage area 110 of the active area 103 contain. This can be achieved by the ions in the ion implantation process 204 obliquely on the semiconductor structure 100 be directed so that ions in areas of active areas 102 . 103 under the sidewall spacers 123 . 124 can penetrate.

Ions that are involved in the ion implantation process 204 on the dielectric structure 203 can impinge on the dielectric structure 203 be absorbed. This allows the source areas 105 . 108 and the drainage areas 107 . 110 , or at least parts of the source areas 107 . 108 and the drainage areas 107 . 110 at a distance to the openings 201 . 201 be protected from ion irradiation, or at least the dose of the ions be reduced so far that no amorphization of the relevant parts of the source regions 105 . 108 and the drainage areas 107 . 110 takes place and the crystalline order of the semiconductor material is substantially retained therein.

3 shows a schematic cross-sectional view of the semiconductor structure 100 at a later stage of the manufacturing process.

After the ion implantation process 204 can in the opening 201 the dielectric structure 203 a gate insulating layer 301 and a gate electrode 303 be formed. In the opening 202 the dielectric structure 203 may be a gate insulating layer 302 and a gate electrode 304 be formed.

The gate insulating layers 301 . 302 can essentially have the same composition. In embodiments, the gate insulating layers 301 . 302 a material with a high dielectric constant, in particular a larger dielectric constant than that of silicon dioxide. The dielectric constant of the gate insulating layers 301 . 302 can be greater than 4 In some embodiments, the gate insulating layers 301 . 302 one or more of the materials include hafnium oxide, zirconia, alumina, tantalum oxide, hafnium silicon oxynitride, and zirconium silicon oxynitride, which have a relatively high dielectric constant. In some embodiments, the gate insulating layers 301 . 302 comprise a layer of silicon dioxide directly on the semiconductor material of the channel regions 106 . 109 and a layer of high-dielectric-constant material located on the layer of silicon dioxide. In further embodiments, the gate insulating layers 301 . 302 also contain more than two partial layers of different materials or a single substantially homogeneous material layer.

The gate electrodes 303 . 304 can contain different materials. In particular, the gate electrode 303 a metal having a workfunction suitable for use as a gate electrode material in a p-channel transistor. The metal may be, for example, aluminum, aluminum nitride and / or titanium nitride.

The gate electrode 304 may include a metal having a work function suitable for a gate electrode of an n-channel transistor. In particular, the gate electrode 304 Lanthanum, lanthanum nitride and / or titanium nitride.

The metals of the gate electrodes 303 . 304 can each have an elastic strain, wherein the elastic stresses of the materials of the gate electrodes 303 . 304 can differ from each other. In particular, the metal of the gate electrode 303 have an intrinsic elastic tensile stress, and the metal of the gate electrode 304 may have an intrinsic elastic compressive stress. In other embodiments, the metals of the gate electrodes 303 . 304 have an elastic tension of the same type but different thickness. For example, the metals of the gate electrodes 303 . 304 each having a compressive stress, wherein the metal of the gate electrode 303 is weaker than the metal of the gate electrode 304 , Alternatively, the metals of the gate electrodes 303 . 304 each having a tensile stress, wherein the metal of the gate electrode 303 is more strained than that of the gate electrode 304 , In further embodiments, the metal may be from one of the two gate electrodes 303 . 304 be substantially unstressed and the metal of the other gate electrode may have a tensile stress or compressive stress.

For the preparation of the gate insulating layers 301 . 302 For example, techniques for depositing materials such as chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition techniques such as sputtering may be used.

After deposition of a layer of the material of the gate insulating layers 301 . 302 that initially essentially covers the entire surface of the semiconductor structure 100 can cover a layer of the metal of one of the gate electrodes 303 . 304 are deposited, for example, a layer of the metal of the gate electrode 303 , For this purpose, methods of chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition and / or atomic layer deposition (ALD, the abbreviation stands for "Atomic Layer Deposition") can be used.

The elastic strain of the metal of the gate electrode 303 can be controlled by adjusting the parameters of the deposition process used. For example, in the deposition of a metal by sputtering, the elastic strain of the metal may be affected by the magnitude of the DC voltage applied to the sputtering target and / or the density and / or temperature and / or composition of the plasma used to produce the sputtering ions.

In a deposition by a chemical vapor deposition method, the elastic strain of the metal by adjusting the composition of the reaction gas, as well as other parameters of the reaction gas, for example Pressure and temperature, to be controlled. In a plasma enhanced chemical vapor deposition process deposition, parameters such as the magnitude of an applied DC voltage and a radio frequency AC voltage through which the plasma is generated may be controlled in addition to the parameters previously associated with chemical vapor deposition.

In deposition by atomic layer deposition, parameters of the deposition process such as gas flows, pressures, temperature and duration of the phases of the deposition process can be controlled to adjust the elastic strain of the metal.

In other embodiments, the elastic strain of the metal may be affected by controlling the thickness of the deposited metal layer. When the thickness of the metal layer is smaller than the depth of the recess 201 For example, a layer of another material, such as amorphous silicon or polycrystalline silicon, may be deposited over the metal layer around the recess 201 to fill completely.

After the deposition of the metal of the gate electrode 303 can be the active area 102 by a mask, such as a photoresist mask or a hard mask, and an etching process may be performed to remove portions of the layer of the material of the gate electrode 303 over the active area 103 and, if present, the layer of the other material formed above it. Thereafter, the mask can be removed and it can be a layer of the metal of the gate electrode 304 over the semiconductor structure 100 be deposited. Similar to the deposition of the layer of the metal of the gate electrode 303 can the elastic strain of the layer of the metal of the gate electrode 304 be controlled by adjusting the parameters of the deposition process and / or the thickness of the layer. In embodiments in which the thickness of the layer is less than the depth of the recess 202 is, can over the layer of the metal of the gate electrode 304 a layer of another material, such as amorphous or polycrystalline silicon, are deposited around the recess 202 to fill completely.

Thereafter, portions of the layer of the metal of the gate electrode 303 and the layer of the metal of the gate electrode 304 , as well as parts of the layer of the material of the gate insulating layers 301 . 302 , and, if present, additional layers of material over the metal layers outside the openings 201 . 202 the dielectric structure 203 are removed by a polishing process, such as a chemical-mechanical polishing process removed.

In other embodiments, first, a layer of the metal of the gate electrode 304 can be deposited, then parts of the layer of the material of the gate electrode 304 over the active area 102 can be removed and it can be a layer of the metal of the gate electrode 303 be deposited. Thereafter, portions of the layers of the metals of the gate electrodes 303 . 304 and the layer of the material of the gate insulating layers 301 . 302 that are outside the openings 201 . 202 were removed, removed by a polishing process.

In some embodiments, the layer of metal may be the gate electrode 303 and the layer of the metal of the gate electrode 304 Titanium nitride (TiN) included. A TiN layer with an intrinsic elastic compressive stress can be obtained, for example, by deposition by means of atomic layer deposition, wherein the strength of the elastic stress can be influenced inter alia by the choice of the thickness of the titanium nitride layer. For example, a titanium nitride layer having a relatively small thickness of about 3 nm may have a greater compressive stress than a titanium nitride layer having a somewhat larger thickness of about 20 nm. By manufacturing by atomic layer deposition, particularly good conformability of the layer may be advantageously achieved. In a deposition of a titanium nitride layer by a chemical vapor deposition or a plasma enhanced chemical vapor deposition, the intrinsic elastic stress of the layer may be a compressive stress or a tensile stress, depending on the parameters of the deposition process.

After forming the gate electrodes 303 . 304 may be a recrystallization of the channel areas 106 . 109 active areas 102 . 103 be performed. In this case, the elastically strained materials of the gate electrodes 303 . 304 in the opening 201 or in the opening 202 present and can be an elastic strain of the channel areas 106 . 109 cause.

The recrystallization of the channel areas 106 . 109 may include performing a heat treatment, what in 3 schematically by arrows 305 is shown. In the heat treatment 305 can the channel areas 106 . 109 be recrystallized, so that the heat treatment 305 a common heat treatment for the recrystallization of the channel region 106 and the recrystallization of the channel region 109 is.

In the heat treatment 305 can the semiconductor structure 100 be exposed to a relatively high temperature for a relatively short time. Heat treatment at a relatively high temperature and with a relatively short duration can be compared to recrystallization of the channel regions 106 . 109 which is carried out with a heat treatment at a lower temperature and with a longer duration, a lower diffusion of the dopants in the source regions 105 . 108 and in the drainage areas 107 . 110 cause. Thus, heat treatment at a relatively high temperature and with a relatively short duration may help smear the doping profiles of the source regions 105 . 108 and the drainage areas 107 . 110 essentially prevent or at least reduce it.

In some embodiments, the heat treatment 305 an irradiation of the semiconductor structure 100 with electromagnetic radiation, in particular with light, which may be visible, ultraviolet and / or infrared light include. The irradiation of the semiconductor structure 100 can be done using a laser and / or one or more flashlamps.

In some embodiments, the duration of the heat treatment, in particular the length of the period during which the semiconductor structure is 100 is irradiated with the electromagnetic radiation, shorter than 100 ms. For example, the heat treatment 305 have a duration in the range of a few milliseconds, in particular a duration in the range of 1 ms to 10 ms. The heat treatment may be performed at a temperature of 1000 ° C or more, wherein at least a near-surface portion of the semiconductor structure 100 in which are the active areas 102 . 103 be reached, the temperature at which the heat treatment is performed reaches. In some embodiments, the heat treatment may be performed at a temperature in the range of 900 ° C to about 1250 ° C, for example, a temperature of 1200 ° C.

In the recrystallization of the channel areas 106 . 109 can the semiconductor material in the amorphous areas 205 . 206 caused by the ion implantation process 204 again assume a crystalline order, so that the atoms of the semiconductor material in the channel areas 106 . 109 again have a long distance order.

During recrystallization, the semiconductor material of the channel region becomes 106 by the elastic strain of the material of the gate electrode 303 influenced, so that the atoms of the semiconductor material of the channel region 106 at intervals that are different from the natural lattice constants of the semiconductor material, indicating an intrinsic elastic strain of the material of the channel region 106 equivalent. In particular, with an intrinsic elastic tensile stress of the material of the gate electrode 303 an intrinsic elastic compressive stress of the semiconductor material of the channel region 106 to be obtained. After recrystallization of the channel region 106 can the intrinsic elastic stress of the semiconductor material in the channel region 106 "Frozen", ie it would at least partially continue to exist when the gate electrode 303 would be removed.

Accordingly, the channel area becomes 109 at its recrystallization by the intrinsic elastic stress of the material of the gate electrode 304 affected. At an intrinsic elastic compressive stress of the material of the gate electrode 304 can in the channel area 109 an intrinsic elastic tensile stress can be obtained.

The active area 102 and the gate electrode 303 can be a p-channel transistor with an intrinsic elastic compressive stress in the channel region 106 form, and the active area 103 and the gate electrode 304 can be an n-channel transistor with an intrinsic elastic tensile stress in the channel region 109 form. Due to the elastic tension in the channel area 106 Can the mobility of the holes in the canal area 106 , from which the conductivity between the source region 105 and the drainage area 107 of the p-channel transistor in the on state depends increased. Due to the intrinsic elastic compressive stress in the channel area 109 of the n-channel transistor, the mobility of the electrons in the channel region 109 , from which the electrical conductivity between the source region 108 and the drainage area 110 of the n-channel transistor in the on state depends increased.

4 shows a schematic cross-sectional view of the semiconductor structure 100 at a later stage of the manufacturing process.

After recrystallization of the channel areas 106 . 109 , can over the semiconductor structure 100 an interlayer dielectric 401 be deposited. In embodiments, the interlayer dielectric 401 essentially the same composition as the interlayer dielectric 125 For example, it may contain silica. The interlayer dielectric 401 can be formed using techniques of chemical vapor deposition and / or plasma enhanced chemical vapor deposition, in embodiments where the interlayer dielectric 401 Contains silica, a reaction gas containing tetraethyl orthosilicate, can be used.

After the deposition of the interlayer dielectric 401 can over the active area 102 a source contact structure 402 that the source area 105 electrically contacted, a gate contact structure 404 that the gate electrode 303 electrically contacted and a drain contact structure 405 that the drain area 107 electrically contacted, are formed. Correspondingly, over the active area 103 a source contact structure 406 , a gate contact structure 407 and a drain contact structure 408 be formed. The source, gate and drain contact structures 402 . 404 . 405 . 406 . 407 . 408 can be achieved by forming contact openings in the interlayer dielectrics 125 . 401 , which can be done by techniques of photolithography and etching, and filling the contact openings with an electrically conductive material, such as a metal, are formed. For filling the contact openings with the metal, a metal layer over the semiconductor structure 100 can be deposited and parts of the metal layer outside the contact openings can be removed by a chemical-mechanical polishing process.

The invention is not limited to embodiments in which, as described above, an elastic strain of the channel regions 106 . 109 by elastically strained materials in the openings of the dielectric structure 203 which form the final gate electrodes of the transistors is effected. In other embodiments, in the openings 201 . 202 the dielectric structure 203 before recrystallizing the channel regions 106 . 109 elastically stressed materials are introduced after recrystallization of the channel areas 106 . 109 be removed again and replaced by the final gate electrodes of the transistors. Hereinafter, such embodiments will be described with reference to FIGS 5 and 6 described.

5 shows a schematic cross-sectional view of a semiconductor structure 500 at a stage of a method according to the invention. Some features of the semiconductor structure 500 in the 5 illustrated stage, features of the semiconductor structure described above 100 in the above with reference to 3 correspond to the described stage. For the sake of simplicity are in the 3 and 5 corresponding elements of the semiconductor structures 100 . 500 denoted by the same reference numerals. Unless expressly stated otherwise below, properties of elements of the semiconductor structure 500 those of elements of the above with respect to the 1 to 4 described semiconductor structure 100 , which are denoted by like reference numerals, correspond, and elements of the semiconductor structures 100 . 500 , which are denoted by like reference numerals, can be manufactured by the same or similar methods.

The semiconductor structure 500 includes a substrate 101 in which active areas 102 . 103 formed by an insulating trench structure from each other 104 separated and electrically isolated. The active area 102 includes a source region 105 and a drainage area 107 , which may be p-doped, and a channel region 106 that can be n-doped. The active area 103 includes a source region 108 and a drainage area 110 which may be n-doped and a channel region 109 that can be p-doped. In the source areas 105 . 108 and the drainage areas 107 . 110 can silicide areas 111 . 112 . 113 . 114 be formed. In the active area 102 there is an amorphous area 205 who is the channel area 106 or at least parts of it, and in the active area 103 there is an amorphous area 206 who is the channel area 109 or at least parts of it.

About the active areas 102 . 103 there is a dielectric structure 203 with an opening 201 over the canal area 106 of the active area 102 and an opening 202 over the canal area 109 of the active area 103 , In the opening 201 There is a gate insulation layer 301 and a first elastically strained material 501 , In the opening 202 There is a gate insulation layer 302 and a second elastically strained material 502 , Next to the opening 201 There is a sidewall spacer 123 and an intermediate layer 121 , Next to the opening 202 There is a sidewall spacer 124 and an intermediate layer 122 , Except the sidewall spacers 123 . 124 and the intermediate layers 121 . 122 includes the dielectric structure 203 an interlayer dielectric 125 ,

The elastically strained materials 501 . 502 in the openings 201 . 202 the dielectric structure 203 can have different intrinsic elastic stresses. In particular, the elastically tensioned material 501 have an intrinsic elastic tensile stress and the elastically strained material 502 may have an intrinsic elastic compressive stress. In some embodiments, the elastically strained materials 501 . 502 each containing a metal, wherein the elastically strained materials 501 . 502 In some embodiments, they may contain the same metal and, in other embodiments, may contain different metals. In other embodiments, the elastically strained materials 501 . 502 also contain non-metallic materials and / or electrically non-conductive materials.

For example, in some embodiments, one or both of these may be elastic strained materials 501 . 502 strained silicon, in particular polysilicon included. In some embodiments, one or both of the elastically strained materials may include diamond-like carbon (DLC, which stands for Diamond Like Carbon). Diamond-like carbon can have a high intrinsic compressive stress, and can be obtained, for example, with the products of Tan et. al. and the techniques described therein. In other embodiments, one or both of the elastically strained materials 501 . 502 elastically strained silicon dioxide and / or elastically strained silicon nitride. In such embodiments, prior to depositing the respective elastically strained material, a thin etch stop layer of another material, relative to which the elastically strained material is selectively etchable, may be deposited to damage the dielectric structure 203 to avoid at a later removal of the elastically strained material. In depositing silicon nitride using plasma enhanced chemical vapor deposition, the intrinsic elastic strain can be adjusted by adjusting the parameters of the deposition process over a wide range of tensile and compressive stresses. In some embodiments similar deposition processes may be used to fabricate elastically strained silicon nitride layers as in the initially described fabrication of elastically strained dielectric material layers via prior art transistors.

Generally, for the deposition of elastically strained materials 501 . 502 Methods of chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition and / or atomic layer deposition can be used. The intrinsic elastic stress of elastically strained materials 501 . 502 can be controlled by adjusting parameters of the deposition method used, similar to the above for the gate electrodes 303 . 304 the semiconductor structure 100 described.

To the elastically strained materials 501 . 502 with different intrinsic elastic strain in the openings 201 . 202 the dielectric structure 203 For example, methods of photolithography and etching can be applied, similar to the above for the gate electrodes 303 . 304 the semiconductor structure 100 described. For example, first, a layer of one of the elastically strained materials over the semiconductor structure 500 by photolithography and etching of one of the two active regions 102 . 103 be removed. Subsequently, a layer of the other of the elastically strained materials 501 . 502 can be deposited, and excess material can be removed by a chemical mechanical polishing process.

After filling the openings 201 . 202 with the elastically strained materials 501 . 502 can the channel areas 106 . 109 active areas 102 . 103 be recrystallized, for example by performing a heat treatment 305 , Characteristics of heat treatment 305 can feature the above with respect to 3 described heat treatment 305 correspond.

Upon recrystallization of the channel regions 106 . 109 can, similar to above with regard to 3 described an intrinsic elastic strain of the recrystallization again a crystalline order having channel regions 106 . 109 to be obtained. The intrinsic elastic stress is in the semiconductor material of the channel regions 106 . 109 "Frozen", so that they are at least partially independent of the presence of elastically strained materials 501 . 502 over the channel areas 106 . 109 persists.

6 shows a schematic cross-sectional view of the semiconductor structure 500 at a later stage of the procedure.

After recrystallization of the channel areas 106 . 109 which, as above with respect to 5 described in the presence of elastically strained materials 501 . 502 in the openings 201 . 202 the dielectric structure 203 was performed, the elastically strained materials 501 . 502 from the openings 201 . 202 be removed. For this purpose, an etching process, in particular a wet etching process or dry etching process, can be carried out, in which the semiconductor structure 500 an etchant designed to hold the elastically strained materials 501 . 502 relative to the materials of the dielectric structure 203 selectively etch. The gate insulating layers 301 . 302 can serve as Ätzstoppschichten and at least partially at the bottom of the openings 201 . 202 the dielectric structure 203 remain.

After removing the elastically strained materials 501 . 502 can in the opening 201 the dielectric structure 203 over the canal area 106 of the active area 102 a gate electrode 601 be formed and in the opening 202 the dielectric structure 203 over the canal area 109 of the active area 103 can be a gate electrode 602 be formed. The gate electrodes 601 . 602 may be formed wholly or partly of metal, wherein the gate electrodes 601 . 602 may contain different metals. In particular, the gate electrode 601 a metal with one for use containing in a p-channel transistor suitable work function and the gate electrode 602 may include a metal having a work function suitable for use in an n-channel transistor. For the preparation of the gate electrodes 601 . 602 may use appropriate techniques as above for the preparation of the gate electrodes 303 . 304 the semiconductor structure 100 described, applied, and for the gate electrodes 601 . 602 For example, the same or similar materials may be used as above for the gate electrodes 303 . 304 described.

As the intrinsic elastic strain of the channel areas 106 . 109 even before the manufacture of the gate electrodes 601 . 602 by recrystallizing the channel regions 106 . 109 in the presence of the elastically strained materials 501 . 502 has been provided, and this is at least partially retained after removing the elastically strained materials, the gate electrodes 601 . 602 not necessarily one to the desired elastic strain of the channel areas 106 . 109 have matched intrinsic elastic strain. For example, the gate electrodes 601 . 602 be essentially unstrung. This results in a greater freedom in the choice of the gate electrodes 601 . 602 used materials and the processes used for their preparation, whereby, for example, a better adaptation of the work functions of the gate electrodes 601 . 602 and / or the resistivity of the gate electrodes.

After forming the gate electrodes 601 . 602 can, as above with respect to 4 described, an interlayer dielectric over the semiconductor structure 500 can be deposited and source contact structures, drain contact structures and gate contact structures can be formed.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited non-patent literature

• CY Kang, et. al., "A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFETs Utilizing Si (110) Channel for Both N and PMOSFETs", Proceedings of the Electron Devices Meeting, 2006, IEDM '06 International, pp. 1-4 [0009 ]
• CY Kang et. al., "Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate / High-k Dielectric SOI FinFETs", IEEE Electron Devices Letters, Vol. 5, May 2008, pp. 487-490 [0009]
• K.-M. Tan, "Diamond-Like Carbon (DLC) Liner: A New Stressor for P-Channel Multiple-Gate Field-Effect Transistor", IEEE Electron Device Letters, Vol. 7, July 2008, p. 750-752 [0009]

Claims (19)

Method for producing a semiconductor structure with: Implanting ions through an opening in a dielectric structure into a channel region of an active region, wherein the active region is formed in a crystalline semiconductor material and includes a source region, a drain region and the channel region, the dielectric structure covers and at least one of the source region and the drain region Part of the channel region is amorphized by the implantation of the ions; Filling the opening with an elastically strained material; and Recrystallizing the channel region in the presence of the elastically strained material in the opening. The method of claim 1, wherein the dielectric structure is configured to reduce implantation of ions into the source region and the drain region at least to such an extent that the source region and the drain region still have a crystalline order immediately after the implantation of the ions. The method of any one of the preceding claims, wherein the dielectric structure comprises a sidewall spacer adjacent the opening and an interlayer dielectric. Method according to one of the preceding claims, wherein the elastically stressed material contains a metal. The method of claim 4, wherein the elastically strained material forms a gate electrode in the opening. The method of claim 5, further comprising forming a gate insulating layer of high-dielectric-constant material at least at the bottom of the opening prior to filling the opening with the elastically-strained material. Device according to one of claims 1 to 4, additionally comprising: Removing the elastically strained material from the opening after recrystallization of the channel region; and Forming a gate electrode in the opening, wherein forming the gate electrode comprises filling the opening with a gate electrode material after removing the elastically strained material from the opening. The method of claim 7, further comprising forming a gate insulating layer at least at the bottom of the opening prior to filling the opening with the elastically strained material, wherein the gate insulating layer at least partially remains at the bottom of the opening upon removal of the elastically strained material and the gate electrode is formed over the gate insulating layer , A method according to claim 7 or 8, wherein the gate insulating layer contains a high dielectric constant material and the gate electrode material contains a metal. The method of any one of the preceding claims, wherein the recrystallization of the channel region comprises performing a heat treatment. The method of claim 10, wherein the heat treatment comprises irradiating the semiconductor structure with electromagnetic radiation, and a duration of the heat treatment is shorter than 100 ms. The method according to claim 11, wherein the heat treatment is carried out at a temperature of 1000 ° C or more. Method according to one of the preceding claims, wherein ions of a semiconductor material, in particular silicon ions, or ions of a noble gas, in particular xenon ions are implanted through the opening in the channel region. The method of claim 1, further comprising: forming a source contact structure that electrically contacts the source region, a drain contact structure that electrically contacts the drain region, and a gate contact structure that electrically contacts the gate electrode. Method for producing a semiconductor structure with: Providing a semiconductor structure having a first active region, a second active region and a dielectric structure, wherein the active regions are formed in a semiconductor substrate and have a crystalline order, each of the active regions comprises a source region, a channel region and a drain region, the source region and the drain region of the first active region are p-doped, and the source region and the drain region of the second n-doped in active region; and wherein the dielectric structure comprises a first opening over the channel region of the first active region and a second opening over the channel region of the second active region; and Performing a method according to any one of the preceding claims on the first active area and on the second active area. The method of claim 15, wherein the implantation of ions through the first opening and the implantation of ions through the second opening are performed in a common ion implantation process. A method according to claim 15 or 16, wherein the recrystallization of the channel region of the first active region and the recrystallization of the channel region of the second active region are carried out in a common heat treatment. A method according to any one of claims 15 to 17, wherein the elastically strained material with which the first opening is filled has an elastic tensile stress and the elastically strained material with which the second opening is filled has an elastic compressive stress. The method of any one of claims 15 to 18, wherein providing the semiconductor structure comprises: Forming a first gate structure over the first active region and a second gate structure over the second active region, each of the gate structures comprising a dummy gate electrode and a sidewall spacer located adjacent to the dummy gate electrode; Forming the source region and the drain region of the first active region adjacent to the first gate structure; Forming the source region and the drain region of the second active region adjacent to the second gate structure; Depositing an interlayer dielectric; Performing a polishing process in which a surface of the interlayer dielectric is planarized and the dummy gate electrodes of the first and second gate structures are exposed; and Forming the first and second openings by removing the exposed dummy gate electrodes.

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