DE102013104019B4 - Method and structure for increasing the performance and reducing the negative bias temperature instability (NBTI) of a MOSFET - Google Patents

Abstract

A method of forming a p-type field effect transistor (100) structure, the method comprising: forming a mask layer (118) on a semiconductor substrate (110), the mask layer (118) having an opening (120) defining a semiconductor region Exposing (114a) the semiconductor substrate (110) within the opening (120); Forming an n-type well (n-well) (122) in the semiconductor region (114a) by applying an ion implantation of n-type dopants to the semiconductor substrate (110) through the opening (120) of the mask layer (118); and applying a germanium (Ge) channel implant to the semiconductor substrate (110) through the opening (120) of the mask layer (118), thereby forming a Ge channel implant region (124) in the n-well (122).

Description

background

Integrated circuits have evolved into advanced technology products with smaller device sizes, such as 32 nm, 28 nm, and 20 nm. Of these advanced technology products, field effect transistors (FETs) comprise three-dimensional transistors, each having a fin-like FET structure (FinFET) for improved device performance. In the FETs, gate stacks include metal for metal electrodes and high k dielectric materials for gate dielectrics. However, the existing methods and structures have several disadvantages in terms of device performance and reliability. For example, charge scattering is a factor limiting the mobility and scalability of FETs in sub-40nm technologies in conjunction with metal electrodes and high-k gate dielectrics. In addition, a three-dimensional FinFET structure is complex and expensive, for example, in terms of cost and performance. Other examples include a deficient short channel effect as well as mismatches and lack of variability due to dopant fluctuations.

The DE 10 2010 064 280 B4 describes a method for forming a field effect transistor structure in which a plurality of layers with different Ge doping are grown to form a Ge-doped region in a recess of a semiconductor substrate. The DE 100 29 659 A1 describes a similar process in which several implantation steps are used to form different FET structural elements.

There is therefore a need for a structure and method for a FET device which overcomes the aforementioned disadvantages to improve its performance and reduce manufacturing costs.

Brief description of the drawings

Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice in industry, various components are not drawn to scale. In fact, the dimensions of various elements may be arbitrarily increased or decreased to clarify the discussion.

The 1 - 4 12 are cross-sectional views of a semiconductor structure fabricated according to one or more embodiments at various stages of fabrication.

The 5 FIG. 10 is a flowchart of a method for manufacturing a semiconductor structure according to FIG 4 , which is constructed according to an embodiment according to various aspects of the present disclosure.

Precise description

It should be understood that the following disclosure represents a plurality of different embodiments or examples of implementation of different elements of the various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. These repetitions are for the sake of simplicity and clarity, and themselves do not suggest a relationship between the discussed embodiments and / or configurations. Moreover, the formation of a first element over a second element in the description below may include embodiments in which the first and second elements are in direct contact with each other, and further embodiments in which additional elements may be formed between the two first and second members are arranged such that the first and second members are not in direct contact with each other.

The 1 - 4 FIG. 15 are cross-sectional views of a semiconductor structure. FIG 100 at various stages of manufacture according to one or more embodiments. In one embodiment, the semiconductor structure comprises 100 one or more field effect transistors (FET).

Regarding 1 includes the semiconductor structure 100 a semiconductor substrate 110 , The semiconductor substrate 110 includes silicon. Alternatively, the substrate comprises germanium, silicon germanium or other suitable semiconductor materials. In another embodiment, the semiconductor substrate comprises 110 a hidden layer of dielectric material for isolation purposes, formed by any suitable technology, such as by a technology called Separation-By-Implanted-Oxygen (SIMOX). In some embodiments, the substrate may be 110 a semiconductor on insulator, such as a silicon on insulator (SOI).

Various shallow-trench isolation elements (STI) 112 are in the semiconductor substrate 110 trained and defined different Semiconductor regions (or active regions) 114 , such as the semiconductor regions 114a and 114b , The semiconductor areas 114 are about the STI elements 114 separated and isolated. For example, the surface of the semiconductor substrate 110 and the surface of the STI element 112 be arranged coplanar, so that there is a common surface. In one embodiment, the formation includes the STI elements 114 forming a hardmask having openings defining the regions of the STI elements; the etching of the semiconductor substrate 110 through the openings of the hard mask to form trenches; depositing dielectric material to fill the trenches; and performing a chemical mechanical polishing (CMP) process. For example, the depth of the STI elements is illustrative 112 between about 30 nm and about 250 nm.

In one embodiment, the formation includes the STI elements 112 Continue to remove the hardmask after the CMP step. In another embodiment, the hardmask comprises a silicon oxide layer by thermal oxidation and a silicon nitride layer on the silicon oxide layer by chemical vapor deposition (CVD). In yet another embodiment, the hardmask is removed after the CMP process.

In another embodiment, the deposition of the dielectric material further comprises the thermal oxidation of the trenches and then the filling of the trenches with the dielectric material, such as silicon oxide, by means of CVD. For example, the trench fill CVD process includes a high density plasma (HDPCVD) CVD process.

In one embodiment, the semiconductor region is 114a for a p-type FET (pFET) and the semiconductor region 114b for an n-type FET (nFET).

Continue with reference to 1 becomes a mask layer 118 on the semiconductor structure 100 formed and with one or more openings 120 structured for one or more wells of the n-type (n-well) to be in some semiconductor areas 114 to be trained. In the present embodiment, an n-well in the semiconductor region 114a be formed. The mask layer 118 resists ion implantation such that ion implantation occurs only on the semiconductor region (s) within the aperture 120 the mask layer 118 is applied.

In one embodiment, the mask layer is 118 a hard mask and it comprises a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON) or a combination of these. For example, the hardmask comprises a silicon oxide thermal layer deposited on the substrate 110 is formed, and a SiN layer formed on the thermal silicon oxide layer. In addition to the example, the thermal silicon oxide layer is formed by means of a thermal oxidation process and the SiN layer by means of a CVD process. Further, the hard mask is patterned around the openings by a process including a lithography and an etching process 120 train. In the present embodiment, a patterned photoresist layer is formed on the hardmask using a photolithography process, including photoresist coating, pre-cure, exposure, post exposure (PEB), develop, and through cure. Subsequently, the hard mask is etched through the openings of the patterned photoresist layer, whereby a patterned hard mask is formed by means of the etching process. The patterned photoresist layer may then be removed using a suitable process such as wet stripping or plasma ashing. In one example, the etching process includes applying a dry etch (or a plasma etch) to remove the hard mask within the opening of the patterned photoresist layer. In another example, the etching process includes applying a plasma etch to remove the SiN layer within the opening of the patterned photoresist layer, and wet etching with a hydrogen fluoride (HF) solution to remove the SiO layer within the opening of the patterned photoresist layer.

In another embodiment, the mask layer comprises 118 a photoresist material wherein a patterned photoresist layer is used directly as an implantation mask. Photoresist material is sensitive to photons, but is resistant to ion implantation (alternatively or additionally, it may be resistant to etching when used as an etch mask). In this case, the mask layer is 118 a structured photoresist layer. The formation of the patterned photoresist layer is similar to that of the previously described photoresist layer for the structuring of the hard mask.

In the present embodiment of the lithographic process, a photomask is used. The mask includes a pattern having different elements and defining different areas for one or more n-wells. The photomask and the corresponding lithography process may use a suitable technology. By way of example, the photomask is a binary photomask comprising a transparent substrate (for example made of cast quartz) and an opaque layer (for example made of Chromium) disposed on the transparent substrate. The opaque layer is patterned to define the areas for the n-wells. In other examples, the photomask may include a phase shift mask (PSM) or other suitable photomask.

In another embodiment, a lithography process may employ other suitable technologies, such as an electron beam (e-beam), to form a patterned photoresist layer. In this case, the photoresist material is sensitive to electrons. The photomask is removed and the photoresist layer is exposed in a direct e-beam write mode according to a pattern stored in a data memory. Other lithography processes alternatively used may include ion lithography or molecular printing.

Regarding 2 becomes an n-tub 122 in one or more semiconductor regions 114 educated. The n-tub 122 comprises an n-type dopant, such as phosphorus (P), which is distributed in an active region in which a pFET is to be formed. The n-type dopant becomes the n-well 122 through the opening 120 the mask layer 118 registered by means of a suitable doping process, for example by means of one or more ion implantation steps. Because the mask layer 118 is stable to ion implantation, the ions from the mask layer 118 held and only in the semiconductor regions within the openings of the mask layer 118 entered. In the present example for illustrative purposes, the n-well becomes 122 in the semiconductor region 114a educated. For example, the n-well 122 have a corresponding doping concentration between about 10 ¹⁶ and 10 ¹⁸ cm ^-3 . In another example, the n-well 122 have a thickness between about 0.5 microns and 2 microns.

Continue with reference to 2 For example, a germanium (Ge) channel implantation process is applied to Ge in the substrate 110 using the same mask layer 118 enter, creating one or more channel implantation areas 124 in the semiconductor substrate 110 arise. Because the Ge channel implantation process using the same mask layer 118 is executed, which for the formation of the n-well 122 is used, the channel implantation area 124 in the corresponding semiconductor region, where the n-well 122 is formed, formed. In other words, the Ge channel implantation area becomes 124 in the n-tub 122 educated.

The Ge channel implantation area 124 is formed by means of one or more ion implantation steps. Ge becomes in the semiconductor substrate 110 inside the opening 120 the mask layer 118 entered. After diffusion and then diffusion caused by the annealing, the doped Ge is in the corresponding n-well 122 distributed from the surface to a certain depth (Ge depth). For example, the Ge channel implantation area extends 124 from the surface of the semiconductor substrate 110 up to the n-tub 122 , where the Ge depth is between about 6 nm and about 12 nm. In particular, the Ge doping profile is in the vertical direction (the direction perpendicular to the surface of the semiconductor substrate 110 ) In the Ge doping concentration profile in the vertical direction, the maximum doping concentration is about half the Ge depth. The Ge doping concentration decreases from the highest doping concentration with reaching the surface of the semiconductor substrate and reaching the Ge depth. In one embodiment, the average Ge doping concentration is between about 4 × 10 ¹⁴ and about 10 ¹⁶ cm ^-3 . In particular, the Ge atomic concentration is in the Ge channel implantation region 124 less than about 3%.

The doped Ge becomes the Ge channel implant area 124 entered by means of an ion implantation process. In one embodiment, the Ge implantation dose at the Ge implantation region is between about 5 × 10 ¹⁴ and about 10 ¹⁶ cm ^-2 . In another embodiment, the Ge channel implant area becomes 124 formed by an ion implantation process at a plasma energy between about 2 keV and about 15 keV.

The Ge channel implantation area 124 is configured to alter the composition of the channel region of the pFET such that the corresponding work function is tuned to provide improved device performance, such as to provide a reduced threshold voltage of the pFET. The Ge doping concentration is designed taking into account the appropriate work function for the channel region. Since Ge is introduced by ion implantation instead of epitaxial growth, the manufacturing cost is reduced. In particular, the same mask layer becomes 118 as an implantation mask during the formation of the n-wells 122 and also used as an implant mask in the Ge channel implant area, with no further lithography processes and other process steps. The corresponding manufacturing process is kept simple and the lead time of the manufacturing process is reduced.

Regarding 3 can after the training of the n-tub 122 as well as the Channel implant region 124 the mask layer 118 be removed by a suitable process, such as wet etching.

Other operations close to forming other elements of the pFET in the semiconductor region 114a and will be described below with reference to the 4 described. For simplicity, only the semiconductor region becomes 114a illustrated.

A gate stack 130 will be on the semiconductor area 114a educated. The gate stack 130 includes a gate dielectric element 132 that on the semiconductor substrate 110 is arranged, as well as a gate electrode 134 which is disposed on the gate dielectric. The semiconductor structure 100 can still be gate spacers 136 exhibit on sidewalls of the gate stack 130 are arranged.

The gate dielectric element 132 includes a gate dielectric material, such as silicon oxide or a suitable dielectric material, having a higher dielectric constant (a high-k dielectric material). In the present embodiment, the gate dielectric element comprises 132 more than one dielectric material layer. For example, the gate dielectric element comprises 132 a dielectric barrier layer, such as silicon oxide, as well as a high-k dielectric layer on the barrier layer. The gate electrode 134 comprises a conductive material layer, such as doped polysilicon, a metal, a metal alloy and / or metal silicides. In an embodiment, the gate electrode comprises 134 more than one conductive material layer. For example, the gate electrode comprises 134 a first conductive layer providing a suitable work function on the gate dielectric element 132 and a second conductive layer on the first conductive layer. By way of example, the first conductive layer comprises tantalum nitride or titanium nitride. As another example, the second conductive layer comprises aluminum, tungsten, copper, doped polysilicon, or combinations thereof. The gate spacers 136 are formed by deposition and anisotropic etching (such as dry etching). The gate spacers 136 comprise a dielectric material, such as silicon oxide, silicon carbide, silicon nitride or silicon oxynitride.

In various embodiments, the gate stack becomes 130 formed by a gate-first process or by a gate-load process. In the gate first process, a gate dielectric layer is formed on the semiconductor substrate 110 and depositing a gate electrode layer on the gate dielectric layer using a method including a lithography process and an etching process to pattern the gate dielectric layer and the gate electrode layer to form the gate stack. In the gate-load process, a dummy gate stack is formed by deposition and patterning; an interlayer dielectric material (ILD) is formed on the dummy gate stack by means of deposition and polishing, such as chemical mechanical polishing (CMP); and the dummy gate is removed, as well as the gate stack 130 by means of a suitable method, for instance by means of a method comprising deposition and CMP. In extension of the gate-load process, in the case where the dummy gate is removed, either the dummy gate stack including the corresponding gate dielectric and the gate electrode is completely or only partially removed (for example, only the gate Electrode be removed).

Continue with reference to 4 For example, a source and a drain in the n-well are formed by one or more ion implantation steps of p-type dopants, such as boron (B). In the present embodiment, the source and the drain include lightly doped drain elements (LDD). 138 as well as heavily doped source and drain elements (S / D) 140 , In one embodiment, the LDD elements become 138 formed by ion implantation; the gate spacers 136 are formed on the sidewalls of the gate stack (the gate stack 130 in the gate first process or the dummy gate stack in the gate load process); then heavily doped S / D elements 140 formed by a further ion implantation step. The heavily doped S / D elements 140 are through the gate spacers 136 to the LDD elements 138 staggered. A thermal annealing process may be followed by activation. A channel area 142 is in the Ge channel implant area 124 set between the source and the drain. In particular, the channel area 142 between the LDD elements 138 arranged. The channel area 142 is Ge-doped and therefore also as a Ge-doped channel region 142 designated.

The in the semiconductor area 114a formed pFET therefore includes the n-well 122 , the Ge Canal area 142 , the source as well as the drain and the gate stack 130 , The different embodiments may have various advantages. In one embodiment, by means of the Ge channel implantation, the work function of the channel region 142 adjusted to achieve improved component performance. In another embodiment, the short channel effect is reduced or eliminated by means of the Ge channel implantation. In yet another embodiment, it has been found experimentally that by means of the Channel implantation, the Dotandenflktuation is reduced and, accordingly, the variation of the device performance from transistor to transistor is reduced. In yet another embodiment, Negative Bias Temperature Instability (NBTI) is substantially reduced wherever the NBTI has caused reliability problems in the pFET. In yet another embodiment, charge scattering is reduced due to Ge channel implantation. Accordingly, the charge carrier mobility in the pFET is increased. In yet another embodiment, the effective drain current I _deff and the source I _soff deactivated current are also improved due to Ge channel implantation. In addition, the disclosed pFET and method enhance the scalability of the pFET structure and extend the planar FET structure for advanced technology nodes (such as in sub-40 nm FET technology with high k dielectrics and a metal gate ).

Other elements can be formed by means of appropriate steps. For example, an ILD material may be formed by a deposition process, such as chemical vapor deposition (CVD), as well as by polishing (using CMP to planarize the surface). In another embodiment, a connection structure is formed having various conductive elements (such as metal lines, contact elements and vias) configured to interconnect various components to form a functional circuit.

5 is a flowchart of a method 100 for forming a pFET constructed according to the various aspects of the present disclosure in one or more embodiments. The procedure 150 includes a step 152 in which a semiconductor substrate 110 is provided, such as a silicon wafer.

The procedure 150 includes a step 154 in which a plurality of STI elements are formed to define different semiconductor regions separated from each other via the STI elements. For example, the STI elements are formed in a process flow that includes forming a patterned mask layer on the semiconductor substrate, etching the semiconductor substrate to form trenches through the openings of the patterned mask, depositing a dielectric material to fill the trenches; and planarizing the surface using CMP.

The procedure 150 includes a step 156 in which a mask layer is formed which is patterned to have one or more openings so that the underlying semiconductor substrate is exposed within the openings. The masking layer is used as an ion implantation mask for subsequent ion implantation steps. In one embodiment, the mask layer is a hard mask having a dielectric material and is formed by a method that includes deposition, a lithography process, and etching. For example, a dielectric material layer (silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof) is deposited, forming a patterned photoresist layer on the dielectric material layer, and an etch process is employed to remove the dielectric material layer within the aperture of the photoresist layer. The patterned photoresist layer is then removed. The patterned photoresist layer is formed by a photolithography process which includes coating, exposure and development. In another embodiment, the mask layer comprises a patterned photoresist layer.

The procedure 150 includes a step 158 , performing a first ion implantation on the semiconductor substrate to form an n-well using the mask layer as an ion implantation mask. The first ion implantation uses an n-type dopant, such as phosphorus.

The procedure 150 includes a step 160 by performing a second ion implantation (or a Ge channel implantation process) on the semiconductor substrate to form a Ge channel implant region in the n-well using the same mask layer as an ion implantation mask. The second ion implantation uses a Ge dopant. The Ge channel implantation process is used to introduce Ge into the N-well, resulting in a Ge channel implantation region in the N-well. In particular, the Ge channel implantation process is performed using the same mask layer that was used to form the n-well.

According to one example, the Ge channel implantation region extends from the surface of the semiconductor substrate to the n-well, at a Ge depth of between about 6 nm and about 12 nm. In particular, the Ge doping profile is in the vertical direction (orthogonal to the direction the surface of the semiconductor substrate) is not uniform. The Ge doping concentration profile in the vertical direction is the maximum Doping concentration at about half the Ge depth. The Ge doping concentration decreases with reaching the surface of the semiconductor substrate and with reaching the Ge depth of the highest doping concentration.

In one embodiment, the average Ge doping concentration is between about 4 × 10 ¹⁴ and about 10 ¹⁶ cm ^-2 . In particular, the Ge atomic concentration in the Ge channel implantation region is less than about 3%.

In another embodiment, the GE implantation dose in the Ge implantation process is tuned in a range of between about 5 × 10 ¹⁴ and about 10 ¹⁶ cm ^-2 . In yet another embodiment, the Ge channel implantation region is formed by ion implantation at a plasma energy between about 2 keV and about 15 keV.

In one embodiment, the method 150 have an operation for removing the mask layer after the first and the second ion implantation. In another embodiment, the method comprises 150 an operation to form a gate stack on the n-well. The gate stacks include a gate dielectric layer and a gate electrode layer. The formation of the gate stacks comprises the deposition and structuring, which furthermore comprises a lithography process and an etching step. The gate stack may include high-k dielectric material and a metal electrode formed in a gate-first process or a gate-load process according to various examples. In another embodiment, the method comprises 150 an operation to form a source and a drain with p-type dopants in the n-well. For example, the source and drain include lightly doped drain elements (LDDs) and heavily doped source and drain (S / D) elements formed by various ion implantation processes. Thus, the formed pFET comprises the n-well, the source, and the drain and the gate stack. In particular, the pFET comprises a channel region which is localized.

Other manufacturing steps may be performed before, during or after the operations of the process. In one embodiment, a dielectric interlayer (ILD) is formed on the semiconductor substrate. The ILD layer includes silicon oxide, low-k dielectric material, other suitable dielectric materials, or combinations thereof. The ILD layer is formed by a suitable method, such as CVD. For example, high density plasma CVD can be used to form the ILD layer.

In another embodiment, the method includes a workflow for forming various connectors configured to interconnect various components (including the pFET) to form a functional circuit. The connectors include vertical connections such as contacts and vias, as well as horizontal connections such as metal lines. The various connectors may use various conductive materials including copper, tungsten and silicide. For example, a demasking process is used to form copper-based multilayer interconnect structures. In another embodiment, tungsten is used to form tungsten stretchers in the contact holes. In another example, silicide is used to form various contacts on source and drain regions to achieve reduced contact resistance.

The present disclosure may be used in various applications, such as logic circuits, dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, flash memories, or image sensors. As an illustrative example, an inverter ring oscillator may be constructed by the method 150 comprise formed pFET structure.

The present disclosure thus provides a method for forming a p-type field effect transistor structure (pFET). The method includes forming a mask layer on a semiconductor substrate, the mask layer having an opening exposing a semiconductor region of the semiconductor substrate within the opening; forming an n-type well (n-well) in the semiconductor region by performing an ion implantation process with n-type dopants on the semiconductor substrate through the opening of the mask layer; and performing germanium channel implantation on the semiconductor substrate through the opening of the mask layer and forming a Ge channel implantation region in the n-well.

In an embodiment, the method further comprises forming a plurality of shallow trench isolation (STI) elements in the semiconductor substrate, whereby the semiconductor regions are defined separately from other regions by means of the STI elements.

In another embodiment, the method further comprises removing the Mask layer after forming the n-well and performing the GE channel implantation.

In still another embodiment, the method further comprises forming a gate stack on the semiconductor substrate and within the semiconductor region; and forming p-type dopant source and drain elements in the n-type well, with the gate stack interposed therebetween. The gate stack may include a gate dielectric comprising a high-k dielectric material and a gate electrode comprising a metallic material. The gate stack can be formed by means of a gate-first process as well as by means of a gate-load process.

In still another embodiment, the mask layer comprises a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof. In still another embodiment, the mask layer comprises a photoresist material.

In yet another embodiment, forming the mask layer includes depositing a mask material layer on the semiconductor substrate; and patterning the mask material layer by means of a lithography process to form a mask layer having the opening.

In yet another embodiment, performing the Ge channel implantation comprises performing a Ge ion implantation process having Ge dopants at an energy between about 2 keV and about 15 keV.

In yet another embodiment, performing the Ge channel implantation comprises performing a Ge ion implantation process using Ge dopants at a doping dose of between about 5 × 10 ¹⁴ / cm ² and about 10 ¹⁶ / cm ² .

The present disclosure also provides another embodiment of a method for forming a pFET structure. The method includes forming a plurality of shallow trench isolation (STI) elements in a semiconductor substrate, thereby defining a semiconductor region of the semiconductor substrate which is separated from other semiconductor regions via the STI elements; forming a mask layer on the semiconductor substrate, the mask layer being patterned to have an opening exposing the semiconductor region within; performing a first ion implantation of n-type dopants into the semiconductor substrate through the opening of the mask layer, thereby forming an n-type well (n-well) in the semiconductor region; and performing a second ion implantation of germanium (Ge) in the semiconductor substrate through the opening of the mask layer, thereby forming a Ge channel implantation region in the n-well.

In one embodiment, the method includes forming a gate stack on the semiconductor substrate and within the semiconductor region, and further comprising forming source and drain regions of a p-type dopant in the n-well, between which the gate and gate regions Stack is arranged. The gate stack may comprise a gate dielectric comprising a high-k dielectric material and a gate electrode comprising a metallic material.

In yet another embodiment, forming the mask layer includes depositing a mask material on the semiconductor substrate; and patterning the mask material using a lithography process to form a mask layer having the opening. The mask material may comprise either a dielectric material or a photoresist material.

In yet another embodiment, the Ge channel implantation comprises performing a Ge ion implantation process using Ge dopants having an energy between about 2 keV and about 15 keV at a doping dose of between about 5 × 10 ¹⁴ / cm ² and about 10 ¹⁶ / cm ² .

The present disclosure also includes an embodiment of a p-type field effect transistor (pFET) structure having an n-well of n-type dopant formed in a semiconductor substrate; a channel region formed in the n-well; a gate stack formed on the channel region; Source and drain elements formed in the n-well and between which the channel region is formed; wherein the channel region comprises germanium (Ge) with an atomic concentration of less than about 3%.

In one embodiment, the channel region comprises a non-uniform Ge doping concentration in a direction perpendicular to the semiconductor substrate, with a maximum Ge doping concentration remote from a surface of the semiconductor substrate; and wherein an average Ge doping concentration is between about 4 × 10 ²⁰ / cm ³ and about 1.5 × 10 ²² / cm ³ .

In another embodiment, the gate stack includes a high-k dielectric material layer and a metal layer on the high-k dielectric material layer.

The foregoing disclosure has represented elements of various embodiments. One skilled in the art will appreciate that he may readily use the present disclosure as a basis for developing or modifying other processes and structures for carrying out the same purposes and / or for achieving the same advantages as the embodiments described herein.

Claims (20)

Method for forming a field effect transistor structure ( 100 ) of the p-type (pFET), the method comprising: forming a mask layer ( 118 ) on a semiconductor substrate ( 110 ), the mask layer ( 118 ) an opening ( 120 ) having a semiconductor region ( 114a ) of the semiconductor substrate ( 110 ) within the opening ( 120 ) uncovered; Forming an n-type well (n-well) ( 122 ) in the semiconductor sector ( 114a by applying an ion implantation of n-type dopants to the semiconductor substrate (US Pat. 110 ) through the opening ( 120 ) of the mask layer ( 118 through; and applying a germanium (Ge) channel implant to the semiconductor substrate ( 110 ) through the opening ( 120 ) of the mask layer ( 118 ), whereby a Ge channel implantation region ( 124 ) in the n-tub ( 122 ) is formed. The method of claim 1, further comprising forming a plurality of shallow trench isolation (STI) elements ( 112 ) in the semiconductor substrate ( 110 ), whereby it is determined that the semiconductor region ( 114a ) about the STI elements ( 112 ) of other semiconductor areas ( 114b ) is separated. The method of claim 1 or 2, further comprising removing the mask layer (16). 118 ) after forming the n-well ( 122 ) and after applying the Ge channel implant. Method according to one of the preceding claims, further comprising: forming a gate stack ( 130 ) on the semiconductor substrate ( 110 ) and within the semiconductor region ( 114a ); and forming a source and a drain element ( 138 . 140 ) from a p-type dopant in the n-type well ( 122 ), between which the gate stack ( 130 ) is arranged. Method according to Claim 4, in which the gate stack ( 130 ) a gate dielectric ( 132 ) comprising a high-k dielectric material and a gate electrode ( 134 ) with a metallic material. Method according to Claim 4 or 5, in which the gate stack ( 130 ) is formed by either a gate first process or a gate load process. Method according to one of the preceding claims, in which the mask layer ( 118 ) comprises a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and a combination thereof. Method according to one of the preceding claims, in which the mask layer ( 118 ) has a photoresist material. Method according to one of the preceding claims, in which the formation of the mask layer ( 118 ): deposition of a mask material layer on the semiconductor substrate ( 110 ); and patterning the mask material layer in a lithography process to form a mask layer ( 118 ) forming the opening ( 120 ) having. The method of claim 1, wherein performing the Ge channel implantation comprises performing a Ge ion implantation process using Ge dopants having an energy between about 2 keV and about 15 keV. The method of claim 1, wherein performing the Ge channel implantation comprises performing a Ge ion implantation process using Ge dopants at a doping dose of between about 5 × 10 ¹⁴ / cm ² and about 10 ¹⁶ / cm ² . A method comprising: forming a plurality of shallow trench isolation (STI) elements ( 112 ) in a semiconductor substrate ( 110 ), whereby a semiconductor region ( 114a ) of the semiconductor substrate ( 110 ), which of other semiconductor areas ( 114b ) about the STI elements ( 112 ) is separated; Forming a mask layer ( 118 ) on the semiconductor substrate ( 110 ), the mask layer ( 118 ) is structured so as to have an opening which contains in itself the semiconductor region ( 114a ) uncovered; Applying a first ion implantation of an n-type dopant to the semiconductor substrate ( 110 ) by the opening ( 120 ) of the mask layer ( 118 ), whereby an n-type well (n-well) ( 122 ) in the semiconductor substrate ( 110 ) is formed; and applying a second ion implantation of germanium (Ge) onto the semiconductor substrate ( 110 ) through the opening ( 120 ) of the mask layer ( 118 ), whereby a Ge channel implantation region ( 142 ) in the n-tub ( 122 ) is formed. The method of claim 12, further comprising: forming a gate stack ( 130 ) on the semiconductor substrate ( 110 ) and within the semiconductor region ( 114a ); and forming a source and a drain element ( 138 . 140 ) from a p-type dopant in the n-type well ( 122 ) between which the gate stack (between 130 ) is arranged. The method of claim 13, wherein the gate stack ( 130 ) a gate dielectric ( 132 comprising a high-k dielectric material and a gate electrode ( 134 ) with a metallic material. Method according to Claim 13 or 14, in which the formation of the mask layer ( 118 ): deposition of a mask material on the semiconductor substrate ( 110 ); and patterning the mask material by means of a lithography process to form a mask layer ( 118 ) forming the opening ( 120 ) having: A method according to any one of claims 12 to 15, wherein the mask material comprises either a dielectric material or a photoresist material. The method of claim 12, wherein performing the Ge channel implantation comprises performing a Ge ion implantation process comprising Ge dopants having an energy between about 2 keV and about 15 keV and a doping dose between about 5 × 10 ^14. cm ² and about 10 ¹⁶ / cm ² . Field effect transistor structure ( 100 ) of the p-type (pFET), comprising: an n-well ( 122 ) of an n-type dopant contained in a semiconductor substrate ( 110 ) is trained; a channel implantation area ( 124 ) in the n-tub ( 122 ) is trained; a channel area ( 142 ) located in the canal implantation area ( 124 ) is fixed; a gate stack ( 130 ) located on the channel area ( 142 ) is trained; a source and a drain element ( 140 ) in the n-tub ( 122 ) and between which the channel region ( 142 ) is arranged; and wherein the channel area ( 142 ) Germanium (Ge) having an atomic concentration of less than about 3%. The pFET structure of claim 18, wherein the channel region ( 142 ) a non-uniform Ge doping concentration in a direction perpendicular to the semiconductor substrate ( 110 ), wherein: a maximum Ge doping concentration is spaced from a surface of the semiconductor substrate ( 110 ) is present; and an average Ge doping concentration is between about 4 × 10 ²⁰ / cm ³ and about 1.5 × 10 ²² / cm ³ . The pFET structure according to claim 18 or 19, wherein the gate stack ( 130 ) a dielectric material layer ( 132 ) with a high k value and a metal layer ( 134 ) on the dielectric material layer ( 132 ) having a high k value.

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