DE102013021709A1 - STENCIL THEN COVER PATH PICTURE SHARING WITH COMMON EDGES - Google Patents

Abstract

One embodiment of the present invention includes techniques for rasterizing primitives that contain edges that are common to paths. For each edge, a raster unit applies a scanning rule made up of several scanning rules. If the edge is common, then the selected sampling rule causes the group of coverage samples associated with a single color sample to be deemed to be either completely inside or completely outside the edge. As a result, merge artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel can be reduced. In conventional techniques, reducing such blending artifacts typically involves increasing the number of color samples per pixel to be equal to the number of coverage samples per pixel. Advantageously, the disclosed techniques enable imaging using algorithms that reduce the ratio of color samples to coverage samples, thereby reducing memory consumption and memory bandwidth without introducing merge artifacts associated with common edges.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to United States provisional patent application Ser. No. 61 / 799,948, filed Mar. 15, 2013. The subject matter of this related application is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Field of the invention

Embodiments of the present invention generally relate to graphical processing, and more particularly to common-edge stencil-then-masking path modeling.

Description of the Related Art

Path imaging is one type of resolution-independent 2-dimensional imaging, often referred to as "vector graphics," which is the basis of a number of important imaging standards. These standards include PostScript, Java 2D, Apple's Quartz 2D, OpenVG, PDF, TrueType fonts, OpenType fonts, PostScript fonts, HTML 5 Canvas, Scalable Vector Graphics (SVG), Microsoft Silverlight and Adobe Flash for interactive web experiences, Microsoft XML Specification (XPS), Drawings in Office File Format with PowerPoint, Adobe Illustrator Appearances and More.

In path building, typically, a software application specifies a scene as a sequence of resolution-independent outlines, known as paths, that can be painted with constant colors, linear or radial gradients, or images. Many graphical processing units (GPUs) support the imaging of such paths through a two-pass imaging process known as "stencil-then-mask". First, in the path template pass, the CPU generates a template buffer indicating which samples (i.e., positions in each pixel) are covered by the path. Second, in a path coverage pass, the GPU creates the coverage geometry for the path and shadows the coverage geometry with the template check enabled. Typically, the GPU implements the coverage geometry with some sort of conservative delimiting geometry, such as a bounding box (i.e., two triangles), a convex hull, or the like. Since the template check is enabled during the path coverage pass, the GPU discards any fragments not covered by the path and writes the remaining fragments as processed graphics data into the color buffer.

In some of the template-then-masking path generation procedures, the GPU maintains N coverage scans per pixel and M color scans per pixel, where N is greater than M. In operation, the GPU determines the coverage of the path at N coverage scans per pixel. During the path coverage pass, before the GPU performs the blend and the color-write operations, the GPU then reduces the number of coverage scans to the number of color scans. Note that during this reduction, the GPU selects a set of N / M coverage samples associated with a single color scan and produces an opacity value for the color scans based on the fraction of N / M coverage scans that are covered. A limitation of this imaging solution is that reducing the groups of multiple coverage scans to single color scans may introduce merged image errors on edges that are common to different paths. In particular, the process of reduction merges the Boolean concept of coverage with a non-integer value of impermeability.

Assume, for example, that there are 4 coverage scans, each corresponding to a color scan (N = 4 and M = 1), that the background color is blue, and that the GPU is formed, Yin-Yang symbol - the Yin region first, to create. It is further assumed that the yin area of the symbol is yellow, the yang area of the symbol is green, and that the yin and yang areas have an edge in common at the boundary between the two areas. Finally, assume that two of the coverage samples associated with a particular color scan are covered by the yellow yin region of the symbol, and that two of the coverage samples associated with the particular color scan are from the green yang area of the symbol Symbols are covered. When imaging the yin area of the symbol, the GPU would assign a bluish intermediate color to the special color sample - a mixture of 50% of the yellow color associated with the yin region of the symbol and 50% of the blue color associated with linked to the background. When imaging the Yang portion of the symbol, the GPU would subsequently assign a different bluish color to the special color sample - a blend of 50% of the green color belonging to the yang portion of the symbol and 50% of the intermediate bluish color. Such impoverishment of Background color would affect the quality of the displayed image. Specifically, part of the blue background color becomes visible at the boundary between the yin region and the yang region of the yin-yang symbol (as if there were a gap between the yin region and the yang region of the yin-yang symbol .)

In one approach to reducing blurring artifacts associated with common edges between different paths, the number of color scans is increased to match the number of blanking scans. In such implementations, the coverage is maintained separately for each color scan as a Boolean value and is not merged with opacity. Consequently, when imaging scenes containing edges that coexist between different paths, no blur image errors are introduced that can be traced back to these common edges. However, increasing the number of color samples increases both the memory consumption and the memory bandwidth used by the color buffer. Since both the local storage capacity of GPUs and the associated memory bandwidth are limited, an increase in both memory usage and memory bandwidth is generally undesirable.

Therefore, what is needed in the art is a more effective way to create edges that are common to different paths.

OVERVIEW OF INVENTION

An embodiment of the present invention provides a method for rasterizing graphic primitives. The method comprises: determining a halftone state associated with a first edge of a primitive, selecting a first sweep rule from a plurality of sweep rules based on halftone state, determining whether a first blanket sweep must be considered to be within the first edge; Based on the first scan rule, and determining whether to consider the first coverage scan as being covered by the graphics primitive based on whether the first coverage scan is considered to be within the first edge.

An advantage of the disclosed approach is that a processing unit can perform memory efficient path imaging operations without introducing merging image errors associated with edges that are common between different paths. Since the rasterizer unit considers each group of coverage samples associated with a particular color scan either as completely within or as completely outside each common edge, the number of coverage scans per pixel may exceed the number of color scans without any depletion of the background in the image caused image is produced. Consequently, the processing unit does not effect the increased memory overhead and bandwidth associated with known techniques in which the number of color samples is increased to match the number of coverage samples.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to indicate the manner in which the above-mentioned features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, will be provided with reference to embodiments, some of which are illustrated in the attached drawings , It should be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

1 Figure 13 is a block diagram illustrating a computer system configured to implement one or more aspects of the present invention;

2 FIG. 12 is a block diagram of a parallel processing unit that operates in the parallel processing subsystem. FIG 1 is included, according to an embodiment of the present invention;

3 FIG. 12 is a conceptual view of a graphics processing pipeline that is in the parallel processing unit. FIG 2 according to an embodiment of the present invention can be realized;

4 Figure 12 is a conceptual view showing a path template pass and a path cover pass into which the parallel processing unit is made 2 can be configured for implementation according to an embodiment of the present invention;

5 is a concept view that shows a triangle fan for the graphics processing pipeline 3 can be configured to generate it as an image according to an embodiment of the present invention;

6 FIG. 11 is a conceptual view showing a scanning group and scanning edge rules to which Implementation of the grid unit 2 can be configured according to an embodiment of the present invention;

7 Fig. 10 is a conceptual view showing an index buffer according to an embodiment of the present invention;

8A - 8B give a flowchart of method steps for rasterizing triangles according to an embodiment of the present invention; and

9 FIG. 10 is a flowchart of process steps for image formation of paths according to an embodiment of the present invention. FIG.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, those skilled in the art will recognize that the present invention may be practiced without one or more of these specific details.

System Overview

1 is a block diagram showing a computer system 100 which is configured to implement one or more aspects of the present invention. As shown, the computer system includes 100 without restriction, a central processing unit (CPU) 102 and a system memory 104 that with a parallel processing subsystem 112 over a memory bridge 105 and a communication path 113 connected is. The memory bridge 105 is also provided with an I / O (input / output) bridge 107 via a communication path 106 connected, and the I / O bridge 107 is in turn with a switch or a switching device 116 connected.

In operation is the I / O bridge 107 formed, a user input information from input devices 108 (for example, a keyboard, a mouse, a video / image recorder, etc.) and input information to the CPU 102 for processing via the communication path 106 and the memory bridge 105 forward. The desk 116 is formed connections between the I / O bridge 107 and other components of the computer system 100 such as a network adapter 118 and various additional cards 120 and 121 to provide.

As further shown, the I / O bridge is 107 with a system diskette 114 which is adapted to content and applications and data for use by the CPU 102 and the parallel processing subsystem 112 save. Generally, the system diskette 114 non-volatile memory for applications and data, and may include stationary or removable hard disk drives, flash memory devices and CD-ROM (compact disk read only memory), DVD-ROM (digital versatile disk ROM), Blu-ray, HD-DVD (high definition DVD) or other magnetic, optical or semiconductor memory devices. Although not explicitly shown, other components such as a universal serial bus or other port connections, compact disk drives, digital versatile floppy disk drives, film recording devices, and the like may also be used with the I / O bridge 107 be connected.

In various embodiments, the memory bridge 105 be a northbridge chip, and the I / O bridge 107 may be a southbridge chip. Furthermore, the communication paths 106 and 113 as well as other communication paths in the computer system 100 may be established using any of the technically-appropriate protocols, including, without limitation, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

In some embodiments, the parallel processing subsystem comprises 112 a graphical subsystem that sends pixels to a display device 110 which may be a conventional cathode ray tube, a liquid crystal display, a light emitting diode display, or the like. In such embodiments, the parallel processing subsystem includes 112 a circuit optimized for graphics and video processing, including, for example, a video output circuit. As explained in more detail below with reference to 2 Such a circuit may be provided across one or more parallel processing units (PPUs) included in the parallel processing subsystem 112 are included. In other embodiments, the parallel processing subsystem includes 112 a circuit optimized for general purpose and / or computational processing. Again, such a circuit may be integrated over one or more PPUs included in the parallel processing subsystem 112 are included and are adapted to perform such operations for general purposes and / or calculations. In still other embodiments, the one or more PPUs included in the parallel processing subsystem 112 may be configured to perform graphic processing, general purpose processing, and arithmetic processing operations. The system memory 104 Contains at least one device driver 103 who is trained, the Processing operations of the one or more PPUs in the parallel processing subsystem 112 manage. The system memory 104 also includes a software application 125 that in the CPU 102 is executed and can issue commands that control the operation of the GPUs.

In various embodiments, the parallel processing subsystem 112 in one or more of the other elements 1 be integrated to form a single system. For example, the parallel processing subsystem 112 with the CPU 102 and other interconnect circuitry may be integrated on a single chip to form a system-on-a-chip (SoC).

It should be noted that the system shown herein is illustrative only and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of CPUs 102 and the number of parallel processing subsystems 112 can be modified as needed. For example, in some embodiments, the system memory could 104 with the CPU 102 directly instead of the memory bridge 105 and other devices could be connected to the system memory 104 over the memory bridge 105 and the CPU 102 communicate. In other alternative topologies, the parallel processing subsystem 112 with the I / O bridge 107 or directly with the CPU 102 instead of the memory bridge 105 be connected. In still other embodiments, the I / O bridge 107 and the memory bridge 105 be integrated into a single chip rather than being present as single or multiple discrete components. Finally, in certain embodiments, one or more of the in 1 shown components are not present. For example, the switch could 116 be omitted, and the network adapter 118 and the additional cards 120 . 121 could be directly with the I / O bridge 107 be connected.

2 is a block diagram of a parallel processing unit (PPU) 202 in the parallel processing subsystem 112 out 1 according to an embodiment of the present invention. Even though 2 a single PPU 202 As previously indicated, the parallel processing subsystem may be shown 112 any number of PPUs 202 contain. As shown, the PPU is 202 with a local parallel processing (PP) memory 204 connected. The PPU 202 and the PP memory 204 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASIC), or memory devices, or may be implemented in any other technically feasible manner.

In some embodiments, the PPU includes 202 a graphics processing unit (GPU) that may be configured to implement a graphics processing pipeline to perform various operations associated with the generation of pixel data based on graphics data provided by the CPU 102 and / or system memory 104 be related, related. When graphics data is processed, the PP memory may 204 may be used as graphics memory containing one or more conventional block buffers and, if desired, also containing one or more rendering targets. Among other things, the PP memory 204 can be used to store and update pixel data and final pixel data or display blocks to the display device 110 for the display. In some embodiments, the PPU 202 also be designed for processing for general purposes and arithmetic operations.

During operation, the CPU is 102 the parent processor of the computer system 100 to control and coordinate the function of other system components. In particular, the CPU gives 102 Commands out the operation of the PPU 202 Taxes. In some embodiments, the CPU writes 102 a stream of commands for the PPU 202 into a data structure (neither in 1 still in 2 explicitly shown) stored in the system memory 104 in which PP memory 204 or may be located at a different location to which both the CPU 102 as well as the PPU 202 can access. A pointer to the data structure is written to a shift buffer to initiate processing of the stream of instructions in the data structure. The PPU 202 reads instruction streams out of the shift buffer and then executes instructions asynchronously to the operation of the CPU 102 out. In embodiments where multiple shift buffers are generated, execution priorities for each shift buffer may be determined by an application program through the device driver 103 to control the scheduling of the different shift buffers.

As further shown, the PPU includes 202 an I / O (input / output) unit 205 that with the rest of the computer system 100 over the communication path 113 and the memory bridge 105 communicates. The I / O unit 205 generates packets (or other signals) for transmission on the communication path 113 and further receives all incoming packets (or other signals) from the communication path 113 to get the incoming packets to appropriate components of the PPU 202 forward. For example, commands related to processing tasks may become one Main interface 206 while commands that read memory operations (for example, read from the PP memory 204 or store in the same), to an intersection unit 210 can be directed. The main interface 206 reads each shift buffer and sends the instruction stream stored in the shift buffer to a front area 212 ,

As previously in connection with 1 may be mentioned, the connection of the PPU 202 with the rest of the computer system 100 also be different. In some embodiments, the parallel processing subsystem is 112 that at least one PPU 202 contains, as an add-in card, implemented in an expansion slot of the computer system 100 can be introduced. In other embodiments, the PPU 202 along with a bus bridge, such as the memory bridge 105 or the I / O bridge 107 be integrated on a single chip. Again, in still other embodiments, some or all of the elements of the PPU 202 together with the CPU 102 be contained in a single integrated circuit or a system-on-a-chip (SoC).

During operation, the front area transmits 212 Processing tasks coming from the main interface 206 to be received to a work distribution unit (not shown) in the task / work unit 207 , The work distribution unit receives pointers to processing tasks that are encoded as task metadata (TMD) and stored in the memory. The pointers to the TMD are contained in a command stream stored as a sliding buffer and by the front-end unit 212 from the main interface 206 Will be received. Processing tasks that may be encoded as TMD include indexes associated with the data being processed, as well as state parameters and commands that determine how the data is to be processed. For example, the state parameters and commands may specify the program to execute on the data. The tasks / work unit 207 receives tasks from the front area 212 and make sure the GPCs 208 are configured to a valid state before the processing tasks specified by the TMD are initiated. You can specify a priority for the TMD that will be used to schedule the execution of the processing tasks. Processing tasks can also be taken from the processing cluster array 230 be received. Optionally, the TMD may include a parameter that controls whether the TMD is added to the front part or the back part of a list of processing tasks (or a list of pointers to the processing tasks), thereby providing another level of controllability besides the execution priority.

The PPU 202 advantageously implements a highly parallel processing architecture based on a processing cluster array 230 that is a group of C general processing clusters (GPCs) 208 contains, where C ≥ 1. Every GPC 208 is able to process a large number (for example, hundreds or thousands) of strands simultaneously, with each strand being an instance of a program. Different applications can use different GPCs 208 for processing different types of programs or for performing different types of calculations. The assignment of GPCs 208 can change depending on the workload that occurs for each type of program or calculation.

The storage interface 214 Contains a group of D partition units 215 where D≥1. Each partition unit 215 is with one or more Dynamic Random Access Memories (DRAM) 220 connected in the PP memory 204 lie. In one embodiment, the number of partition units 215 equal to the number of DRAM 220 , and each partition unit 215 is with another DRAM 220 connected. In other embodiments, the number of partition units may vary 215 from the number of DRAM 220 differ. The person skilled in the art recognizes that a DRAM 220 can be replaced by any other suitable technical storage device. During operation, various imaging targets, such as texture maps and block buffers, may be inserted into the DRAM 220 be stored so that the partition units 215 Describe regions of each imaging destination in parallel to efficiently estimate the available bandwidth of the PP memory 204 exploit.

A given GPC 208 can process data in one of the DRAM 220 in the PP memory 204 to write. The crossing unit 210 is trained, the output of each GPC 208 the input of a partition unit 215 or another GPC 208 for further processing. The GPCs 208 communicate with the memory interface 214 over the crossing unit 210 to various DRAMs 220 to read or describe. In one embodiment, the intersection unit 210 a connection to the I / O unit 205 in addition to a connection to the PP memory 204 via the memory interface 214 , thus providing the processing cores in the different GPCs 208 are able to with the system memory 104 or with a memory that is not local to the PPU 202 is to communicate. In the embodiment of 2 is the crossing unit 210 directly with the I / O unit 205 connected. In various Embodiments may be the intersection unit 210 Use virtual channels to control traffic flows between the GPCs 208 and the partition units 215 to separate.

The GPCs 208 can be programmed to perform processing tasks involving a variety of applications including, without limitation: linear and non-linear data transformations, filtering of video and / or audio data, modeling operations (e.g., application of physical laws to determine position, velocity, and other attributes of objects), image rendering operations (e.g., tiling shading, vertex shading, geometry shading, and / or pixel / fragment shading), general computational operations, etc. In operation, the PPU 202 trained, data from the system memory 104 and / or the PP memory 204 to transfer to one or more on-chip storage devices, process the data and return the result data back to the system memory 104 and / or the PP memory 204 to write. The result data can then be accessed by other system components, including the CPU 102 , another PPU 202 in the parallel processing subsystem 112 or another parallel processing subsystem 112 in the computer system 100 belong.

As indicated previously, any number of PPUs 202 in a parallel processing subsystem 112 be included. For example, several PPUs 202 may be provided in a single add-on card, or multiple add-on cards may communicate with the communication path 113 or one or more of the PPUs 202 can be integrated in a bridge chip. The PPUs 202 in a multi-PPU system can be identical or different to each other. For example, different PPUs 202 a different number of processing cores and / or different sizes of PP memory 204 exhibit. In embodiments where multiple PPUs 202 In addition, these PPUs can operate in parallel to process data at a higher throughput than a single PPU 202 it is possible. Systems containing one or more PPUs 202 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, mobile computers, personal computers in the form of handheld devices or other handheld devices, service providers' computers, workstations, game consoles, embedded systems, and the like.

Architecture of the graphics pipeline

3 is a conceptual view of a graphics processing pipeline 350 that in the PPU 202 out 2 according to an embodiment of the present invention can be realized. As shown, the graphics processing pipeline includes 350 without limitation a primitive distribution unit (PD) 355 ; a vertex attribute collection unit (VAF) 360 ; a vertex, tiling, geometry processing unit (VTG) 365 ; a viewport scaling, selection and cutting unit (VPC) 370 ; a tile unit 375 , a setup unit (set up) 380 , a grid unit (grid) 385 ; a fragment processing unit, also called a pixel shading unit (PS) 390 and a raster operation unit (ROP) 395 ,

The PD 355 collects vertex data associated with higher-order surfaces, graphical primitives, and the like from the front 212 and sends the vertex data to the VAF 360 ,

The VAF 360 receives vertex attributes associated with each of the incoming vertices from the shared memory and stores the vertex data along with the associated vertex attributes in the shared memory.

The VTG 365 is a programmable execution unit configured to execute vertex shader programs, tiling programs, and geometry programs. These programs process the vertex data and vertex attributes that come from the VAF 360 and generates graphical primitives for further processing in the graphics processing pipeline 350 , Although not explicitly shown, the VTG 365 in some embodiments, one or more of: a vertex processing unit, a tiling initialization processing unit, a task generation unit, a task distribution unit, a topology generation unit, a tiling processing unit, and a geometry processing unit.

The vertex processing unit is a programmable execution unit that is configured to execute vertex shader programs, lighting, and the transformation of vertex data as indicated by the vertex shader programs. For example, the vertex processing unit may be programmed to transfer the vertex data from the object-based coordinate representation (object space) to an alternative-based coordinate system, such as a world space or a space with normalized device coordinates (NDC). to transform. The vertex processing unit may read vertex data and vertex attributes stored in the shared memory from the VAF and may process the vertex data and vertex attributes. The vertex processing unit stores processed vertices in the shared memory.

The tiling initialization processing unit is a programmable execution unit configured to execute tiling initialization shading programs. The tiling initialization processing unit processes vertices generated by the vertex processing unit and generates graphic primitives known as stains. The tiling initialization processing unit also generates various stain attributes. The tiling initialization processing unit then stores the stain data and stain attributes in the shared memory. In some embodiments, the tiling initialization shader may be referred to as wrap shading or tiling control shading.

The task generation unit retrieves data and attributes for vertices and patches from the shared memory. The task generation unit generates tasks for processing the vertices and patches for processing by later stages in the graphics processing pipeline 350 ,

The task distribution unit distributes the tasks generated by the task generation unit. The tasks created by the various instances of the vertex shader program and the tiling initialization program can be clearly separated between a graphical processing pipeline 350 and another one. The task distribution unit distributes these tasks such that each graphics processing pipeline 350 has about the same workload during later pipeline stages.

The topology generation unit retrieves tasks distributed by the task distribution unit. The topology generation unit indexes the vertices, including vertices associated with patches, and computes (U, V) coordinates for tiling vertices and the indices connecting the vertices partitioned into a parquet to form graphic primitives. The topology generation unit then stores the indexed vertices in the shared memory.

The tiling processing unit is a programmable execution unit configured to execute tiling shading programs. The tiling processing unit reads input data from the shared memory and writes output data thereto. The output data in the shared memory is sent to the next shading stage, i. H. the geometry processing unit, passed as input data. In some embodiments, the tiling shader may be referred to as a range shading or as a tiling weighting control.

The geometry processing unit is a programmable execution unit that is configured to execute geometry shader programs, thereby transforming graphical primitives. Vertices are grouped to construct graphical primitives for processing, with graphic primitives including triangles, line segments, points, and the like. For example, the geometry processing unit may be programmed to subdivide the graphical primitives into one or more new primitives and to calculate parameters, such as level equation coefficients, used to divide the new primitives into a grid.

The geometry processing unit sends the parameters and vertices that indicate the new graphical primitives to the VPC 370 , The geometry processing unit may read out data stored in the shared memory for use in processing the geometry data. The VPC 370 performs pruning, selection, and transformation of the viewport to determine which graphical primitives are potentially visible in the final rendered image and which graphical primitives are potentially invisible. The VPC 370 then sends the processed graphic primitives to the tiling unit 375 ,

The tile unit 375 is a unit for sorting graphic primitives that exist between a world space pipeline 352 and a screen space pipeline 354 is arranged as described hereinafter. Graphical primitives will be in the world-space pipeline 352 processed and then to the tiling unit 375 Posted. The screen space is cached, with each cache tile associated with a portion of the screen space. For each graphic primitive, the tile unit determines 375 the set of cache tiles intersecting the graphics primitive, this process being referred to as "tile ordering" herein. After the tiling of a certain number of graphic Basic elements are processed by the tiling unit 375 the graphical primitives based on a cache tile, where graphic primitives belonging to a particular cache tile become the device entity 380 be sent. The tile unit 375 sends graphical primitives to the setup unit 380 one at a time for a single cache tile. Graphical primitives that intersect multiple cache tiles are typically once in the world space pipeline 352 processed, but then several times to the screen space pipeline 354 Posted.

Such a technique improves the locality of the cache memory during processing in the screen space pipeline 354 when multiple memory operations associated with a first cache tile access one area of the L2 cache, or another technically feasible cache memory that persists during screen space processing of the first cache tile is. Once the graphical primitives associated with the first cache tile from the screen space pipeline 354 are processed, the area of L2 cache associated with the first cache tile is flushed, and the tile unit may transmit graphic primitives associated with a second cache tile. Multiple memory operations associated with a second cache tile may then access the area of the L2 caches that is permanently maintained during screen space processing of the second cache tile. Therefore, all memory traffic to the L2 caches and to the imaging targets can be reduced. In some embodiments, the computation in world space is done once for a given primitive, regardless of the number of cache tiles in the screen space intersecting the primitive.

The setup unit 380 receives vertex data from the VPC 370 about the tiling unit 375 and calculates parameters associated with the primitives, including, without limitation, the color values, surface normal vectors, and transmittance values at each vertex of the primitive. The setup unit 380 then sends processed graphic primitives to the rasterizer 385 ,

The grid unit 385 converts the new graphic primitives and sends fragments and coverage data to the pixel shader 390 , Furthermore, the raster unit 385 be configured to make a z-selection and other z-based optimizations.

The pixel shading unit 390 is a programmable execution unit that is configured to execute fragment shader programs, thereby removing fragments from the rasterizer 385 are received, as indicated by the fragment shader programs. The fragment shader programs can shade fragments at pixel level resolution, such shader programs being referred to as pixel shader programs. Alternatively, fragment shader programs may shade fragments at a scan-plane resolution, where each pixel contains multiple scans, and each scan represents a portion of a pixel. Alternatively, fragment shader programs can shade fragments at any other technically feasible resolution, depending on the programmed sampling rate.

In various embodiments, the fragment processing unit 460 be programmed to perform operations such as perspective correction, texture mapping, shading, blending, and the like to create shaded fragments that are applied to the ROP unit 395 be sent. The pixel shading unit 390 can read data stored in the shared memory.

The ROP unit 395 is a processing unit that performs raster operations such as stenciling, z-checking, mixing, and the like, and the pixel data as processed graphics data for storage in graphics memory via the memory interface 214 The graphics memory is typically constructed as one or more imaging targets. The processed graphics data may be stored in the graphics memory in the parallel processing memory 204 or in the system memory 104 for display on the display device 110 or for further processing by the CPU 102 or the parallel processing subsystem 112 get saved. In some embodiments, the ROP unit is 395 formed to compress z or color data written in the memory, and to decompress z or color data read from the memory. In various embodiments, the ROP unit 395 in the memory interface 214 in the GPCs 208 in the processing cluster array 230 outside the GPCs or in a separate unit (not shown) in the PPUs 202 be arranged.

The graphics processing pipeline 350 may be due to one or more of the processing elements within the PPU 202 will be realized. For example, a data stream multiprocessor (not shown) in one of the GPCs 208 out 2 be configured to perform the functions of one or more of the VTG 365 and the pixel shading unit 390 perform. The functions of the PD 355 , the VAF 360 , the VPC 450 , the tiling unit 375 , the furnishing unit 380 , the raster unit 385 and the ROP unit 395 may also be from processing elements within a particular GPC 208 in conjunction with a corresponding partition unit 215 be executed. Alternatively, the graphics processing pipeline 350 be implemented using specific processing elements with a specified function for one or more of the aforementioned functions. In various embodiments, the PPU 202 be formed, one or more graphics processing pipelines 350 to implement.

In some embodiments, the graphics processing pipeline may 350 in a world space pipeline 352 and a screen space pipeline 354 be split. The world space pipeline 352 processes graphical objects in 3D space, where the position of each graphical object is known with respect to other graphical objects and with respect to a 3D coordinate system. The screen room pipeline 354 Processes graphical objects projected from the 3D coordinate system onto a flat 2D surface representing the surface of the display device 110 represents. For example, the world space pipeline could 352 Pipeline stages in the graphics processing pipeline 350 from the PD 355 up to the VPC 370 contain. The screen room pipeline 354 could pipeline stages in the graphics processing pipeline 350 starting from the set-up unit 380 up to the ROP unit 395 contain. The tile unit 375 would be on the final stage of the world space pipeline 352 that is, on the VPC 370 , consequences. The tile unit 375 would before the first stage of the screen space pipeline 354 that is the setup unit 380 , lie.

In some embodiments, the world space pipeline may 352 be further divided into an alpha-phase pipeline and a beta-phase pipeline. For example, the alpha-phase pipeline could be pipeline stages in the graphics processing pipeline 350 starting from the PD 355 up to the task generation unit. The beta-phase pipeline could be pipeline stages in the graphics processing pipeline 350 from the topology generation unit to the VPC 370 contain. The graphics processing pipeline 350 performs a first set of operations during processing in the alpha-phase pipeline and performs a second set of operations during processing in the beta-phase pipeline. As used herein, a group of operations is defined as one or more instructions that are executed by a single thread, by a thread group or by several thread groups that work together.

In a system with multiple graphics processing pipelines 350 For example, the vertex data and vertex attributes associated with a set of graphical objects can be split up into each graphics processing pipeline 350 has about the same amount of work in the alpha phase. The alpha phase processing can significantly increase the amount of vertex data and vertex attributes such that the amount of vertex data and vertex attributes generated by the task generation unit is significantly larger than the amount of vertex data and vertex attributes used by the PD 355 and the VAF 360 were generated. Furthermore, the task generation unit, which can be used with a single graphics processing pipeline 350 to generate a significantly larger amount of vertex data and vertex attributes than the task generation unit that is connected to another graphics processing pipeline 350 even in cases where the two graphics processing pipelines are linked 350 handle the same set of attributes at the beginning of the alpha-phase pipeline. In such cases, the task distribution unit redistributes the attributes generated by the alpha-phase pipeline such that each graphics processing pipeline 350 has about the same workload at the beginning of the beta-phase pipeline.

It should be noted that references herein to shared memory refer to one or more arbitrary technically feasible memory, including but not limited to: a local memory shared by one or more data stream multiprocessors, or memory accessed by the one or more data stream multiprocessors memory interface 214 can be accessed, such as a cache memory, the parallel processing memory 204 or the system memory 104 , It should also be noted that, as used herein, references to a cache memory refer to one or more arbitrary technically feasible memory, including, without limitation, an L1 cache, an L1.5 cache, and the L2 cache. cache memory.

Path imaging

The software application 125 out 1 can the graphics processing pipeline 350 to configure various operations related to the generation of pixel data based on graphics data provided by the CPU 102 and / or system memory 104 be performed. In particular, the software application 125 the graphics processing pipeline 350 configure to perform operations related to path building. As noted hereinbefore, path imaging is the basis for a number of important imaging standards, such as HTML 5 Canvas and SVG. In operation, the PPU implements 202 a template kidney-then- Covering path mapping with N coverage scans per pixel and M color scans per pixel, where N is greater than M. In general, the software application defines 125 a path and configures the PPU 202 to execute the stencil-then-masking path generation as two sequentially executed imaging passes - the Path Masking Pass and the Path Cover Pass.

4 is a conceptual view showing a path template pass 485 and a path coverage pass 495 shows in which the PPU 202 out 2 can be configured for implementation according to an embodiment of the present invention. As previously disclosed herein, the PPU 202 configured to perform the stencil-then-masking path generation. First, the PPU performs 202 the path template pass 485 from, resulting in template data from the stenciling pass 445 be generated. Subsequently, the PPU initiates 202 the path cover pass 495 , whereby a path generated as an image 455 is produced.

In operation, the software application specifies 125 out 1 a path and initiates the path template pass 485 , Upon receipt of the path specification, the PPU generates 202 a path geometry 403 that represents the path. As shown, process the VPC unit 370 , the grid unit 385 , the PS unit 390 and the ROP unit 395 the path geometry 403 , whereby the template data for the stenciling pass 445 be generated in a template buffer. In other embodiments, the PPU may process the path geometry in any technically feasible manner using any available processing units in any combination. The values in the template buffer indicate which coverage scans are covered by the path. As disclosed hereinbefore, the PPU maintains 202N Coverage scans per pixel and M color scans per pixel, where N is greater than M. During the path stenciling pass 485 the coverage scans are updated, but the color scans are not updated.

After generating the template data from the template pass 445 generates the PPU 202 a cover geometry 405 that conservatively covers the path. As shown, process the VPC unit 370 , the grid unit 385 , the PS unit 390 and the ROP unit 395 the cover geometry 405 whereby the covered pixels are shaded and thereby the path created as an image 455 is produced. In other embodiments, the PPU may process the coverage geometry in any technically feasible manner using any available processing units in any combination. During this process, the PPU reduces 202 the number of coverage scans on the number of color scans. In some implementations, the PPU determines for each color scan 202 a group of N / M coverage samples pertaining to the color scan and produces an opacity value for the color scan based on the proportion of N / N coverage scans that are covered. For example, if the number of coverage scans per pixel 16 and the number of color scans per pixel 4 is then linked to the PPU 202 Groups of 4 coverage scans with a respective color scan, and the possible opacity values are 0, 0.25, 0.5, 0.75, and 1.0. It should be noted that the PPU 202 the template data from the template pass 455 used in the template buffer are used to discard fragments and coverage scans that are not covered by the path. The PPU 202 then writes the remaining fragments in the color buffer as the image generated path 455 ,

As previously disclosed herein, typical known PPUs determine that a color scan is only partially covered by a primitive at a common edge. Consequently, the PPUs could introduce merge image errors at the common edges. In contrast, the PPU determines 202 in that each color scan is either completely covered or completely uncovered by the graphic primitive, and this applies to each common edge. However, the PPU can 202 determine that a particular color scan is only partially covered by a primitive on a non-shared edge. Therefore, the techniques disclosed herein allow the PPU 202 efficiently generates paths using more coverage scans than color scans, while ensuring that the image generated paths do not contain merge image errors associated with shared edges.

5 is a concept view that has a triangle fan 500 for which it produces the graphics processing pipeline 350 out 3 according to an embodiment of the present invention can be configured. As previously disclosed herein, the PPU 202 trained, the path geometry 403 and the cover geometry 405 as part of the template-then-masking path generation. The triangular fan 500 can in one or both, ie in the path geometry 403 and the cover geometry 405 to be included.

As shown, the triangle fan is 500 a group of connected triangles that share a single vertex. As further shown is the triangle fan contains 500 common edges 510 , not common edges 520 and internal edges 530 , In particular, each of the common edges 510 also included in another path (not shown). For example, each of the common edges 510 also be included in another graphic primitive. In contrast, the non-common edges 520 and the internal edges 530 not included in other paths. The common edges 510 can be determined by any technically feasible manner. For example, the software application 125 out 1 explicitly the common edges 510 as part of the path specification. Furthermore, the device driver may 103 out 1 common edges 510 as part of the processing of path specification.

As shown, the internal edges are 530 such edges that are inside the triangle fan 500 lie. Each of the internal edges 530 is common for connected triangles that are in the triangle fan 500 are included. The internal edges 530 can be determined by any technically feasible manner. For example, the internal edges 530 based on the specification of the triangle fan 500 be determined.

In one embodiment, the PPU determines 202 during the path template pass 485 the cover with regard to the common edges 510 unlike the cover for the non-common edges 520 and the internal edges 530 , Subsequently, the PPU determines 202 during the path coverage pass 495 the cover with regard to the internal edges 530 unlike the cover with regard to the common edges 510 and the non-common edges 520 , In alternative embodiments, the PPU may be configured to determine any number of other edge properties and subsequently modify the imaging process based on those edge properties. For example, in some other embodiments, the PPU does not distinguish between common edges, non-common edges, and internal edges during the path coverage pass when the coverage is detected.

As those skilled in the art will recognize, the triangle fan is 501 an example of a special graphical primitive for which the graphics processing pipeline 350 is designed to perform an image formation. Other graphic primitives, such as triangular stripes, can also share edges 510 , not common edges 520 and internal edges 530 exhibit. Such graphic primitives are provided by the PPU 202 processed in a similar way.

6 is a concept view, which is a sampling group 610 and scanning edge rules showing the rasterizer unit 385 out 3 can implement, according to an embodiment of the present invention. As previously explained herein, the PPU supports 202 N coverage scans per pixel and M color scans per pixel, where N is greater than M. As shown, the PPU determines 202 for each color scan the sample group 610 from N / M coverage samples belonging to the color scan. Further, the PPU designates 202 one of the coverage samples included in the sample group 610 is included as a primary scan 617 , and the rest of the coverage samples included in the sample group 610 are included as secondary scans 615 designated.

As shown, presents 6 the sampling group 610 as a dotted square, where the primary scan 617 is shown as a bold outlined dot and the secondary scans 615 are shown as slightly outlined dots. Further shows 6 covered samples as filled and uncovered samples as unfilled. As further shown, each of the sample groups includes 610 a single primary scan 617 and three secondary scans 615 , The computer system 100 can detect the position of the coverage scans and the lower coverage scans 617 in any technical way mark. For example, the device driver may be 103 determine the positions of the coverage samples and may determine the first coverage scan that is in each scan group 610 is included as the primary coverage scan 617 mark. However, selects for each sample group 610 the computer system 100 the corresponding primary scan 617 deterministic and consistent across the paths. In other embodiments, the sample group may include any number, including zero to secondary samples.

Advantageously, in one embodiment, the raster unit 385 configured to select between scan edge rules based on properties associated with a respective edge. Note that the scan edge rules, also referred to herein as "scan rules," are rasterizer results that can be applied to a coverage scan to determine if the coverage scan is considered to be within an edge. For each edge applies the grid unit 385 the selected scan edge rule on the edge to the coverage of the coverage scans that are in the scan group 610 are to be determined. The scan edge rules include, without limitation, individual scan edge rules 455 , a primary scan edge rules 465 and any scan edge rule 475 , As in conventional Grid division hierarchy or determines the grid unit 385 the coverage of the scanning group 610 with respect to a particular primitive, by determining the intersection or union of the coverage results associated with each edge of the primitive.

When using the individual scanning edge rule 455 determines the grid unit 385 the coverage of each of the coverage samples included in the scan set 610 regardless of other coverage samples included in the sample group 610 are included. In particular, the grid unit determines 385 the cover of the primary scan 617 based on the position of the primary scan 617 relative to the edge. Similarly, the rasterizer determines 385 for each of the secondary scans 615 the coverage of the secondary scan 615 based on the position of the secondary scan 615 relative to the edge.

As shown, the grid unit applies 385 the individual scanning edge rule 455 on two scanning group 610 on, which are arranged on an edge of a triangle. For the left sampling group 610 determines the grid unit 385 that the position of one of the secondary scans 615 is within the edge of the triangle, and therefore covered. For the right scanning group 610 determines the grid unit 385 in that the positions of the primary scan 617 and two of the three secondary scans 615 lie within the edge of the triangle and are thus covered.

Broad application of the primary scanning edge rule 465 determines the grid unit 385 the coverage of all coverage samples that are in the scan set 610 are included, based on the position of the primary scan 617 relative to the edge. Consequently, the raster unit determines 385 in that either all coverage samples included in the sample group 610 are included, or that all coverage scans that are in the scan group 610 are not covered. Advantageously, the determination of the coverage in this way ensures that for the color scanning associated with the scanning group 610 the cover is not fused with opacity during the reduction of (N / M) coverage scans to a single color scan.

As shown, the grid unit applies 385 the primary scan edge rule 465 on two scanning groups 610 on, which are arranged on an edge of a triangle. For the left sampling group 610 determines the grid unit 385 that the position of the primary scan 617 is outside the edge of the triangle, and thus the primary scan 617 and all secondary scans 615 are not covered. For the right scanning group 610 determines the grid unit 385 that the position of the primary scan 617 lies within the edge of the triangle and thus the primary scan 617 and all secondary scans 615 are covered.

When applying any scanning edge rule 475 the grid unit 385 determines that the position of the primary scan 617 or one of the secondary scans 615 within the primitive relative to the edge, then the rasterizer determines 385 in that all coverage scans are covered. Determining the coverage in this way ensures that for each color scan that matches the scan group 610 the cover is not fused with opacity during the reduction of (N / M) coverage scans to a single color scan. It should be noted that the arbitrary scanning edge rule 475 more conservative than the individual scanning edge rule 455 and the primary scanning edge rule 465 is.

As shown, the grid unit applies 385 the arbitrary scanning edge rule 465 on two scanning groups 610 which lie on one edge of a triangle. For the left sampling group 610 determines the grid unit 385 in that the position of one of the four coverage samples is within the edge of the triangle and thus the primary scan 617 and all secondary scans 615 are covered. For the right scanning group 610 determines the grid unit 385 in that the positions of three out of four coverage scans are within the edge of the triangle, and therefore the primary scan 617 and all secondary scans 615 are covered.

Again, the grid unit 385 be adapted to apply different Abtastkantenregeln on the edges of a primitive based on properties of the edge. Furthermore, the raster unit 385 be configured to select different edge rules based on whether the PPU 202 the path template pass 485 or the path coverage pass 495 performs. Although in conjunction with the 6 described examples show a cover relative to a single edge, determines the raster unit 385 the coverage of the scanning group 610 relative to a particular primitive by determining the intersection of the coverage results pertaining to each edge of the primitive.

In one embodiment, the rasterizer employs 385 during the path template pass 485 the individual scanning edge rule 455 on not common edges 520 and the internal edges 530 at. In contrast, the grid unit applies 385 the primary scan edge rule 465 on the common edges 510 at. Because the grid unit 385 determines that each sample group 610 either completely covered or completely uncovered is relative to the common edges 510 , blurring artifacts associated with common edges in the prior art can be reduced.

During the path coverage pass 495 applies the grid unit 385 the arbitrary scanning edge rule 475 on the non-common edges 520 and the common edges 510 and applies the primary scanning edge rule 465 on the internal edges 530 at. Again, the grid unit 385 determines that each sample group 610 either completely covered or completely uncovered is relative to the common edges 510 , blurring artifacts associated with common edges in known techniques can be reduced. By applying the primary scanning edge rule 465 on the internal edges 530 further avoids the raster unit 385 a double rasterization during the path coverage pass 495 ,

In some embodiments of the present invention, the computer system 100 the PPU 202 to efficiently configure the primary scan edge rules 465 apply based on path to path. Especially if the computer system 100 determines that one of the edges contained in a path has a common edge 510 is, then the computer system 100 the PPU 202 configure the coverage of the entire scan group 610 based on the position of the primary scan 617 to determine.

In one embodiment, the device driver 102 out 1 determines that a path has common edges 510 contains, then makes the device driver 103 the positions of the coverage samples that are in each of the sample groups 610 are included, the same if the path is divided into rasters. Especially before the grid unit 385 If a primitive divides into rasters associated with such a path, the device driver changes 103 the positions of all secondary scans 615 so that they match the position of the associated primary scan 617 to match. Consequently, assigns for each sample group 610 the grid unit 385 all cover scans a single position. After the grid unit 385 The basic element is rasterized by the device driver 103 the positions of the secondary scans 615 again according to the originally assigned positions. The skilled artisan recognizes that operations that equalize the positions and restore the positions of the secondary scans 615 can be reduced if the PPU 202 a sequence of primitives that all share common edges 510 contain.

In another embodiment, if the computer system 100 determines that a path has common edges 510 contains, configures the computer system 100 the PS unit 390 to assign a single output cover to all samples in the sample group 510 are included, this is done via a sampling mask. In operation, the PS unit selects 390 the output coverage of the primary scan 617 off, assigns the selected coverage to each of the associated secondary scans 615 and writes the corresponding sampling mask.

7 is a concept view that contains an index buffer 760 according to an embodiment of the present invention. As is well known, the index buffer 760 can be used to reduce the memory used to store graphical primitives as part of indexed geometry imaging.

In operation, a graphic primitive may be represented by a sequence of entries 750 in the index buffer that is in the index buffer 760 are represented. As shown, each index buffer entry contains 750 an edge mark 752 and a vertex index 754 , Generally, each index buffer entry contains 750 a total of N bits, of which the most significant M bits are the edge mark 752 and the remaining (N-M) bits the vertex buffer index 754 to save. As in conventional indexed geometry imaging, the vertex index is 754 an index in the vertex buffer (not shown) containing data per vertex. However, in known approaches, typically all N bits in each index buffer entry are allocated for storage of the vertex index. By reallocating the most significant bits of each index buffer entry 750 for displaying the edge mark 752 may advantageously be any index buffer entry 750 Data per edge, in addition to the data per vertex, is stored over the vertex index 754 can be accessed. In contrast, conventional techniques typically duplicate the vertex data for each edge.

For example, as shown, the triangle 705-0 in the clockwise direction 720 through the three vertices 715-0 . 715-1 and 715-2 To be defined. As further shown, the triangle 705-1 in the order of clockwise 720 through the three vertices 715-3 . 715-0 and 715-2 To be defined. Further, the edge is the vertex 715-0 and the vertex 715-2 connects, together for multiple paths. As shown, the index buffer represents 760 the two triangles 705-0 and 705-1 using 8-bit index buffer entries 750 . where the most significant bit is the edge mark 752 and the remaining 7 bits the vertex index 754 to save. In particular, a value of "1" indicates the edge mark 752 that the edge of the graphical primitive, which is made up of the corresponding vertex index 754 yields one of the common edges 510 is.

To further optimize memory usage, the semantics of the Kantemarke can change 752 depending on the imaging pass. In the example of the index buffer 760 is the PPU 202 trained, the path stenciling pass 485 to realize, and an activated edge mark 752 gives the original vertex 715 a special common edge 510 at. If, in contrast, the PPU 202 is formed, the path cover pass 495 to realize, then gives the activated edge mark 752 the original vertex 715 a special internal edge 530 at.

In other embodiments, an arbitrary number of bits may be reserved for the tag, and the edge tag may represent any data associated with edges. In some embodiments, the rasterizer unit may be configured to select between two scan edge rules based on the edge mark. In other embodiments, the edge mark may represent several different properties of the edge, such as common to common and internal to external. Those skilled in the art will understand that embodiments of the invention include any techniques that redesign bits included in the index buffer to determine the selection of the scan edge rules during the rasterization.

8A - 8B 12 show a flowchart of method steps for grid division of triangles according to an embodiment of the present invention. Although the process steps related to the systems of the 1 - 7 Those skilled in the art will recognize that any system suitable for carrying out the process steps in any order is within the scope of the present invention.

As shown, a procedure begins 800 in step 802 in which the grid unit 385 a simple triangle as part of the path template pass 485 receives. In step 804 selects the grid unit 385 a special sampling group 610 to coverage samples and initializes an associated primary coverage value and associated secondary coverage values of value "1". The primary coverage value and each of the secondary coverage values represents whether the associated coverage scan is considered covered by the entrance triangle. As disclosed hereinbefore, the PPU maintains 202 N coverage scans per pixel and M color scans per pixel, where N is greater than M. Each scan group 610 is associated with a special color scan. Further, one of the (N / M) coverage samples is in the sample group 610 the primary scan 617 and the remaining coverage scans are the secondary scans 615 , The computer system 100 can be the primary scan 617 select in any technically feasible way. However, for each color scan, the computer system chooses the corresponding primary scan 617 for the paths in a deterministic and consistent way. Note that the number of secondary coverage values equals the number of secondary scans 615 is.

In step 806 selects the grid unit 385 a first edge contained in the input triangle. In step 808 rates the grid unit 385 the primary scan 617 in relation to the selected edge. If the raster unit 385 determines that the position of the primary scan 617 within the input triangle with respect to the selected edge, then sets the rasterizer 385 the primary coverage value for the edge is "1". On the other hand, if the grid unit 385 determines that the position of the primary scan 617 is outside the input triangle with respect to the selected edge, then sets the rasterizer 385 the primary coverage value for the edge is "0". Generally, the primary edge coverage value represents whether the primary scan 617 is considered to be within the selected edge of the input triangle. When in step 810 the grid unit 385 determines that the selected edge is not one of the common edges 510 is, then the procedure goes 800 to the step 812 further. The grid unit 385 can determine in any technically feasible manner whether the selected edge is one of the common edges 510 is. For example, in some embodiments, the rasterizer 385 a read operation on the edge mark 752 to determine if the edge mark 702 50 is activated. In step 812 applies the grid unit 385 the individual scanning edge rule 455 to the selected edge. In operation, the grid unit sets 385 for each of the secondary scans 615 the corresponding secondary edge coverage value based on whether the location of the secondary scan 615 within the input triangle with respect to the selected edge. Generally, the secondary edge coverage value represents whether the secondary scan 615 is to be considered within the selected edge of the input triangle. The procedure 800 then go to the step 816 further.

When in step 810 the grid unit 385 determines that the selected edge is one of the common edges 510 is, then the procedure goes 800 continue to step 814 , In step 814 applies the grid unit 385 the primary scan edge rule 465 to the selected edge. During operation, the raster unit sets 385 for each of the secondary scans 615 Set the appropriate secondary edge coverage value to match the primary edge coverage value. By determining that the sample group 610 either completely covered or completely uncovered by the entrance triangle, may advantageously be the raster unit 385 a Boolean concept for covering color scans with common edges 510 are linked.

In step 816 leads the grid unit 385 a logical AND operation between the primary edge coverage value and the primary coverage value. In this way, the grid unit sets 385 the coverage of the selected edge coincides with previous edge coverage values. In step 818 leads the grid unit 385 for each secondary edge coverage value, a logical AND operation between the secondary edge coverage value and the secondary coverage value. In step 820 then goes, if the grid unit 385 determines that the selected edge is not the third edge contained in the input triangle, the rasterizer 385 continue to step 822 ,

In step 822 selects the grid unit 385 the next edge contained in the input triangle and the method 800 returns to the step 808 back. The grid unit 385 cycles through the steps 808 to 823 , where edge rules for each edge are selected and applied until the raster unit 385 has processed all three edges contained in the input triangle. In other embodiments, the input triangle may be replaced by another input primitive, and the rasterizer 385 cycles through the steps 808 to 823 until the grid unit 385 has processed all the edges contained in the initial primitive. When in step 820 the selected edge is the third edge contained in the input triangle, then the primary coverage value and the secondary coverage value represent the coverage of the scan group 610 with regard to the entrance triangle. In other embodiments, the raster unit 385 process several scanning groups or edges in parallel. In some other embodiments, the rasterizer unit 385 select any one of the rasterization rules based on any technically feasible criteria, such as other marks included in the index buffer entry 750 are included.

9 FIG. 10 is a flowchart of method steps for generating paths in accordance with an embodiment of the present invention. FIG. Although the process steps related to the systems of the 1 - 7 Those skilled in the art will recognize that any system suitable for carrying out the process steps in any order is within the scope of the present invention.

As shown, a procedure begins 900 in step 902 in which the software application 125 specifies a path. As part of the definition of the path, the software application identifies 125 any common edges 510 , In step 904 determines the device driver 103 whether the path has common edges 510 contains. The device driver 102 can share edges 510 detect in any technically feasible way contained in the path. For example, the device driver may be 103 some common edges 510 determine based on explicit commands issued by the software application 121 can be issued, and may have other common edges 510 while creating path geometries.

When in step 906 the device driver 103 determines that the path has one or more common edges 510 contains, then goes the procedure 900 continue to step 908 , In step 908 changes the device driver 103 for each color scan, the coverage samples included in the associated scan group 610 are included so that they have the same positions. In particular, the device driver sets 103 for each sample group 610 the positions of all secondary scans 615 so firm that they match the position of the primary scan 617 to match. In alternative embodiments, the device driver may re-program the location of the coverage scans in any technically feasible manner. In step 910 processes the grid unit 385 the path. Because each sample group 610 is associated with a single position, advantageously determines the raster unit 685 in that each color scan is either completely covered by the graphics primitive or completely uncovered. In step 912 represents the device driver 103 the positions of the secondary scans 615 that in each scanning group 610 are included, restored and the procedure 900 continue to step 916 , In step 916 complete the PS unit 390 and the ROP unit 395 the imaging pass and method 900 ends then. In alternative embodiments, the PS unit performs 390 and the ROP unit 395 the step 916 which completes the imaging pass before the device driver 103 the step 912 executing in which the positions of the secondary scans 615 be restored.

When in step 906 the device driver 103 determines that the path has no common edge 510 contains, then goes the procedure 900 continue to step 914 , In step 914 processes the grid unit 385 the path. In particular, the raster unit maintains 385 N differently arranged coverage scans per pixel and M color scans per pixel while the path is being processed. The procedure 900 then go to the step 916 further. In step 916 finish the PS unit 390 and the ROP unit 395 the imaging pass, and the method 900 ends then.

In summary, in one case, the rasterizer applies different edge rules to the edges of a primitive based on properties associated with the path. In particular, in the Path Stenciling pass, the rasterizer selects which edge rules to apply to which edge based on whether the edge is common to different paths. If the edge is common to different paths, then the rasterizer applies a primary scan edge rule to the edge. In applying the primary scan edge rule to the edge, the rasterizer determines whether a group of coverage scans associated with a single color scan are collectively located inside or outside the edge, based on the location of a single coverage scan - the primary scan. In contrast, if the edge is not common, then the rasterizer applies an independent scan edge rule to the edge. By applying the independent scan edge rule to the edge, the rasterizer determines whether each coverage scan is inside or outside the edge, based on the position of the coverage scan. Subsequently, for each coverage scan, the rasterizer unit then determines, when the rasterizer unit determines that the coverage scan within each edge associated with the primitive is that the coverage scan is covered by the primitive.

Similarly, in the path coverage pass, the rasterizer selects which edge rule to apply to which edge of the primitive, based on whether the edge is an inner edge of the primitive. If the edge is within the primitive, then the rasterizer applies the primary scan edge rule to the edge. On the other hand, if the edge is not within the primitive, then the rasterizer applies any scan edge rule to the edge. In applying the arbitrary scan edge rule to the edge, if the rasterizer determines that the position of a coverage scan associated with a color scan is within the edge, then the rasterizer determines that all coverage scans associated with the color scan are within the boundary Edge lie. If the rasterizer determines that the coverage scan is within for all edges associated with the particular primitive, then, for each coverage scan, the rasterizer determines that the coverage scan is covered by the primitive.

In a second case, when creating an indexed geometry, the device driver changes the purpose of the most significant bits contained in an index buffer entry to store edge marks. In general, a series of sequential index buffer entries contained in an index buffer defines a primitive. For example, a series of three sequential index buffer entries defines a primitive in the form of a triangle. The device driver allocates N bits of an N-bit index buffer entry to store edge flags, and (N-M) bits of the index buffer entry are always used to store a vertex index. As is well known, the vertex index is an index for a vertex buffer containing vertex data. In path imaging, the semantics of the edge marks change depending on the imaging pass. During the path template pass, an activated most significant bit in a particular index buffer entry indicates that the edge of the primitive resulting from the associated vertex index is common to two or more paths. During path coverage traversal, an activated most significant bit in a particular index buffer entry indicates that the edge of the primitive resulting from the associated vertex index is an internal edge of the primitive.

In a third case, the device driver may reprogram the positions of secondary coverage scans based on properties associated with the path. The device driver performs such reprogramming before the rasterizer processes the paths as part of the path template pass or as part of the path coverage pass. In particular, before dividing into a raster of a particular path, if the device driver determines that a particular path contains one or more edges common to multiple paths, then the device driver changes the coverage scan positions associated with each color scan such that they are the same. During operation, the device driver for each coverage scan group programs the secondary scan positions to match the primary scan position. After the rasterizer has performed operations involving path template creation or path coverage traversal, the device driver restores the secondary scans to their original locations.

An advantage of the above approach is that blurring image errors associated with edges that are common between different paths are reduced. In particular, for each common edge, the rasterizer sets each group of coverage scans associated with a particular color scan to either be completely covered by the primitive or completely uncovered. Thus, the rasterization of primitives containing common edges does not create a partial coverage that would cause depletion of the background if image formation were performed using more coverage scans per pixel than color scans per pixel. Further, imaging using more coverage scans than color scans reduces memory consumption and memory bandwidth compared to known techniques in which the number of color scans is increased to match the number of coverage scans. In one aspect of the foregoing approaches, memory consumption is further optimized by redirecting bits included in the index buffer to store edge tags. Thus, the disclosed approaches allow for memory efficient path imaging without creating blended image errors for shared edges typically associated with known techniques.

An embodiment of the invention may be implemented as a program product for use in a computer system. The program (s) of the program product define functions of the embodiments (including the methods described herein) and may be included in a variety of computer-readable storage media. Illustrative computer readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices in a computer, such as CD-ROM disks readable from a CD-ROM drive, flash memory, ROM Chips or other type of nonvolatile semiconductor memory) on which information is permanently stored; and (ii) recordable storage media (eg floppy disks in a floppy disk drive or hard disk drive or other type of random access semiconductor memory) having changeable information stored thereon.

The invention has been described with reference to specific embodiments. However, those skilled in the art will recognize that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The foregoing description and drawings are therefore to be considered as illustrative and not restrictive.

Therefore, the scope of the present invention is defined by the following claims.

Claims (10)

A computer-implemented method of rasterizing graphical primitives, the method comprising: Determining a rasterization state associated with a first edge of a graphical primitive; Selecting a first scan rule from a plurality of scan rules based on the rasterization state; Determining whether a first coverage scan is considered to be within the first edge based on the first scan rule; and Determining whether the first coverage scan is deemed to be covered by the graphical primitive based on whether the first coverage scan is considered to be within the first edge. The method of claim 1, wherein the primitive comprises a path, and wherein the rasterization state indicates that the first edge is a common edge of the path. The method of claim 1, wherein the primitive comprises a path, and wherein the rasterization state indicates that the first edge is a non-common edge of the path. The method of claim 1, wherein the primitive comprises a path, and wherein the rasterization state indicates that the first edge is an external edge of the path. The method of claim 1, wherein determining if the first coverage scan is considered to be within the first edge comprises: calculating if the position of the first coverage scan is within the graphical primitive relative to the first edge. The method of claim 1, wherein the graphical primitive comprises a triangle. The method of claim 6, wherein determining whether the first coverage scan is deemed to be covered by the graphical primitive comprises: determining whether the first coverage scan is considered to be within all three edges of the graphical traffic Base element is considered, including the first edge, a second edge belonging to a third edge. The method of claim 1, further comprising: composing a color value for a first color scan based on whether the first coverage scan is deemed to be covered by the graphics primitive. A computing device which is designed to divide graphic primitives into a grid, wherein the computation device comprises: a memory; a processing unit coupled to the memory and configured to implement at least a portion of a graphics processing pipeline, the at least one portion of the graphics processing pipeline being configured to: determine a rasterization state associated with a first edge of a graphical primitive; select a first scan rule from a plurality of scan rules based on the rasterization state; determine whether a first coverage scan is considered to be within the first edge based on the first scan rule; and determine whether the first coverage scan is deemed to be covered by the graphics primitive based on whether the first coverage scan is considered to be within the first edge. A processing unit configured to implement at least a portion of a graphics processing pipeline that includes a rasterizer, wherein the at least a portion of the graphics processing pipeline is configured to perform the steps of: Parsing a first index associated with a first vertex of the primitive; Determining a first edge tag included in the first index and a first vertex index included in the vertex index; Accessing a vertex buffer based on the first vertex index to read data associated with the first vertex; and Performing a rasterization on a first edge of the primitive based on the first edge mark and the data associated with the first vertex, the first edge extending from the first vertex.

Images