DE102012217881A1 - Sensor arrangement and manufacturing method - Google Patents

Abstract

A sensor arrangement comprises a plurality of sensor elements which are arranged two-dimensionally in a plane, spacer elements on the underside of the sensor arrangement in order to define a cavity under the sensor elements and a plurality of electrical lines for the individual connection to each sensor element, the lines being integrated with the spacer elements are.

Description

The present invention relates to a sensor arrangement with a plurality of sensor elements. In particular, the invention relates to a sensor arrangement with thermal sensor elements for determining spatially resolved temperatures. Furthermore, the invention relates to a method for producing the sensor arrangement.

A large number of sensors require a certain independence from the ambient temperature for their function. Some sensors are based on a functional principle according to which a physical or chemical quantity to be detected in the form of introduced energy slightly changes the temperature of the sensor. A sensor element of such a sensor is typically fabricated on a membrane to ensure thermal decoupling of the sensor element from an environment or from an adjacent sensor element. Typical applications include chemical sensors for measuring conversion energy or thermal sensors for radiation measurement. The radiation measuring sensors may in particular comprise thermopiles based on the thermoelectric effect, bolometers based on the thermoresistive effect or pyrosensors based on the pyroelectric effect.

If the sensor comprises more than just one sensor element, then a larger number of information can be sampled simultaneously, the sensor elements generally being arranged next to one another, so that each sensor element is assigned to one measurement location. If the number of sensor elements is large enough, an imaging process can make use of the values sampled simultaneously. To increase the resolution of the image provided, the largest possible number of sensor elements with the smallest possible dimensions is required.

For example, infrared spectroscopy or infrared imaging can be performed by means of such a sensor. Microbolometer assemblies are commercially available for thermography and for night vision devices in passenger cars. However, a sensor arrangement with a large number of sensor elements, a high sensitivity and preferably low crosstalk between the individual sensor elements is complex and requires a complex production, which can be very costly. Often, the need to cool the sensor increases the complexity of a sensor array, power consumption, and cost, such as with cooled quantum detectors.

The invention has for its object to provide a sensor array with a plurality of sensor elements, which can be produced at a reduced cost. Another object of the invention is to specify a manufacturing method for the sensor arrangement. The invention solves these objects by means of a sensor arrangement and a method having the features of the independent claims. Subclaims give preferred embodiments again.

A sensor arrangement according to the invention comprises a plurality of sensor elements arranged two-dimensionally in a plane, spacer elements on the underside of the sensor arrangement to define a cavity below the sensor elements and a plurality of electrical lines for individual connection to each sensor element, the lines being integrated with the spacer elements are executed.

According to the invention, it is possible to lead the lines of the sensor elements away from the sensor elements outside the plane in which they are arranged. An available area in the plane can thus be used to a reduced extent for cables. The sensor elements can thus be increased or their number per area in the plane (fill factor) increased. The diameter of the spacers may be reduced so that less heat can be passed over the spacers, which may increase the sensitivity of the sensor elements.

Furthermore, a mean line length, which lies between a sensor element and an evaluation device, can be reduced. A deviation of line lengths from the average line length can be kept small at the same time. In addition, the arrangement of the line ends of an arrangement of individually associated with the sensor elements evaluation can be facilitated. The structure of the sensor arrangement can be independent of a number of comprehensive sensor elements, so that a simple construction of the sensor is possible. The sensor arrangement can be produced with reduced effort and reduced costs. As a result, new commercial applications can be developed for which a highly integrated sensor arrangement was previously too expensive.

In a preferred embodiment, the lines of the sensor elements run along spacer elements, which adjoin the respective sensor element. Thus, at least each sensor element be assigned a spacer element, in or on which a line of the sensor element extends. The cavity below the sensor arrangement can be subdivided into a plurality of cavities, so that, for example, a cavity exists in each case under a predetermined number of sensor elements. The arrangement of the spacer elements may reflect the arrangement of the sensor elements of the sensor arrangement. Accordingly, the arrangement of line ends can correspond to the arrangement of the sensor elements. A connection of the lines with an evaluation circuit can be simplified thereby.

In a particularly preferred embodiment, the lines run through the spacer elements. As a result, the lines can be laterally insulated over the full length of the spacer elements. In addition, the lines can contribute to the stability of the spacer elements.

In a particularly preferred embodiment, the sensor elements are arranged regularly in the plane. Surfaces of the sensor elements may, for example, be hexagonally shaped, the arrangement of the sensor elements being honeycomb-shaped. In another embodiment, the surfaces of the sensor elements may be rectangular or square and the sensor elements may be arranged in a matrix-like manner in rows and columns. In any case, can be made possible by the inventive leadership of the lines along the spacer elements, that along virtually linearly independent directions in the plane virtually any number of sensor elements are arranged, the number of which is not limited by the lines leading to the sensor elements. The regular arrangement can simplify a further processing of measurement results of the individual sensor elements.

In one embodiment, the sensor elements are mounted on membranes lying in the plane. The membranes may reduce thermal coupling of each sensor element to an adjacent sensor element or along a spacer. The sensitivity of the sensor elements can thereby be increased.

In a preferred embodiment, the spacer has a height to width ratio of at least 10 to 1. Thereby, the cavities below the sensor elements can be dimensioned sufficiently large to ensure the thermal decoupling of the sensor elements, while at the same time the individual sensor elements can be attached to the sensor arrangement with high density.

In one embodiment, the sensor arrangement additionally comprises a semiconductor substrate, which is electrically connected to the spacer elements, wherein an evaluation circuit for signals of the sensor elements is arranged on the semiconductor substrate.

Thus, a particularly high integration of the individual sensor elements with individual or summary evaluation elements can be provided. A contacting of the lines with the semiconductor substrate can be carried out in a simplified manner within a manufacturing process of the sensor arrangement. The line ends can easily be individually contacted independently of their number.

In a variant, structures of the evaluation circuit can be produced by means of similar processes as the sensor elements of the sensor arrangement. A manufacturability of the entire sensor arrangement can thereby be improved and production costs can be reduced.

Each sensor element can be assigned two lines insulated from one another, wherein the lines run in different spacing elements. In particular, the spacer elements can adjoin the sensor element. The spacer elements can run parallel to different edges of the sensor element and enclose an angle in the plane with each other. As a result, the lines of each sensor element can be guided relatively far apart and also relatively far away from lines of other sensor elements.

The sensor elements can be set up in particular for the provision of electrical signals as a function of the temperatures of the sensor elements. The temperatures may be variable, for example, based on radiation or a chemical effect. As a result, the sensor arrangement may be suitable for a multiplicity of applications which require a temperature measurement at several locations in one plane. In particular, the sensor arrangement may be suitable for imaging measurement methods.

An area of the spacers in the plane may be less than 25% to 30% of the total area of the sensor elements in the plane. As a result, an increased density of sensor elements in the plane can be achieved. A local resolution of the sensor elements in the plane can be increased while the Nevertheless, individual sensor elements still have sufficiently large surfaces to show a sensitive measurement behavior.

A method according to the invention for producing a sensor arrangement having a multiplicity of sensor elements arranged two-dimensionally in a plane comprises steps of providing semiconductor material having a lower and an upper surface, introducing plated-through holes which electrically connect points to different surfaces of the semiconductor material, applying the sensor elements to the top surface such that the sensor elements are each in electrical contact with at least one of the vias, and removing semiconductor material at the bottom surface in areas between the vias.

As a result of this production method, the spacer elements which lie between adjacent sensor elements are formed by leaving portions in the region of the plated-through holes during the removal of semiconductor material from the lower surface. As a result, the lines associated with the individual sensor elements can be formed simply and reliably.

In one embodiment, the introduction of vias into the semiconductor material includes steps of inserting vias into the semiconductor material, passivating walls of the vias, and filling the vias with liquified conductive material.

By doing so, it is also possible to fill via holes whose length in relation to their diameter comprises a ratio of 10 to 1 and more. Other methods, such as sputtering or electroplating, may not be able to ensure complete filling of such a via without the inclusion of non-conductive regions. The procedure is relatively simple and allows an almost error-free filling of through holes with almost any ratios of length to diameter with conductive material.

In one embodiment, filling the through-holes with liquefied conductive material includes injecting a molten conductor by overpressure and then cooling the conductor until it solidifies in the through-holes. The passage opening produced in this way can be particularly low-error and mechanically or electrically highly resilient.

In one embodiment, the through-holes are introduced by means of a photo-assisted electrochemical etching process. While with conventional dry etching technology, for example by means of the Bosch process, ratios of length to diameter of about 10 to 1 to about 15 to 1 can be achieved with a diameter of a few micrometers, significantly higher ratios of up to 200 to 1 means a wet chemical etching process can be achieved. In particular, the etching process may include a photo assisted electrochemical etch (PAECE). For example, a through hole having a diameter of about 3 μm and a length of about 350 μm may be introduced into the semiconductor material without causing variations in diameter along the through hole. With a suitable choice of the operating point of the photo-assisted electrochemical etching process, distances between adjacent through-holes of a few 10 μm, in particular about 40 to 60 μm, may be possible.

The passivation of the walls of the through holes can be effected in particular by means of thermal oxidation. In order to be able to completely passivate a through hole with a high ratio of length to diameter, the thermal oxidation can have advantages over other passivation possibilities. In addition, thermal oxidation can provide a highly uniform passivation layer with low defect density.

Brief description of the figures

The above-described characteristics, features and advantages of this invention, as well as the manner in which they are achieved, will become clearer and more clearly understood in connection with the following description of exemplary embodiments which will be described in detail in conjunction with the accompanying drawings, in which:

1 a sensor arrangement;

2 the sensor arrangement 1 in a further embodiment, and

3 Steps of a method for producing a sensor arrangement according to one of 1 or 2 represents.

1 shows a sensor arrangement 100 , The sensor arrangement 100 includes a plurality of sensor elements 105 that in a plane 110 are arranged. The sensor elements 105 are designed to determine a temperature in the region of their respective surfaces. In this case, the temperature is determined with high accuracy, so that the sensor arrangement 100 For example, for the radiation measurement of electromagnetic radiation, in particular infrared radiation, or may be suitable for measuring conversion energy in a chemical process. For example, the sensor arrangement 100 Part of an imaging thermography system for spatially resolved scanning of infrared radiation.

The sensor elements 105 preferably have surfaces of the same shape and size and are regularly arranged by spacing between adjacent sensor elements 105 are the same size. In the illustrated exemplary embodiment, the sensor elements 105 each have a square surface and are in a matrix of rows 115 and columns 120 arranged, wherein a row direction is perpendicular to a column direction. The sensor elements 105 are machined from a flat semiconductor material whose top in 1 is recognizable.

For thermal isolation is below each sensor element 105 a cavity 125 intended. The cavities 125 are defined by spacers 130 which the sensor elements 105 at a predetermined distance above the surface of an underlying semiconductor substrate 135 or other support material, which is not necessarily part of the sensor array 100 is.

Each sensor element 105 is with at least two wires 140 electrically connected, wherein perpendicular to the plane extending portions of the lines 140 in the presentation of 1 are not recognizable. These sections are preferably integrated with the spacers 130 formed, with a relative position of a line 140 to the spacer 130 can be performed differently.

Optionally, the lines 140 on the surface of the semiconductor substrate 135 be continued horizontally. Preferably, the lines lead 140 to contact points 145 on the semiconductor substrate 135 , The wires 140 or the contact points 145 can in particular to an evaluation circuit 150 lead, which on the semiconductor substrate 135 or in a deeper layer in the semiconductor substrate 135 can be arranged.

To a thermal isolation of the sensor elements 105 concerning the spacers 130 can improve a contact surface between a sensor element 105 and the surrounding semiconductor material by introducing a slot 155 be downsized. In the illustrated embodiment, at each sensor element 105 four slots 155 provided parallel to the edges of the sensor elements 105 run and preferably are so long that a connection between the sensor element 105 and the surrounding semiconductor material only in the region of the corners of the sensor element 105 he follows. The slots 155 However, in other embodiments may be shaped differently or omitted entirely.

2 shows the sensor arrangement 100 out 1 in a further embodiment. The representation is made in a section along the direction of the lines 115 or the columns 120 through the spacers 130 ,

Between two adjacent sensor elements 105 here is a spacer 130 provided, the two sensor elements 105 at a predetermined distance above the surface of the semiconductor substrate 135 holds. The semiconductor substrate 135 is not necessarily part of the sensor arrangement 100 and in other embodiments, the lower ends of the spacers may be 130 also on a different surface than the semiconductor substrate 135 to be appropriate. In the illustrated embodiment, the lines run 140 completely inside the spacers 130 so that they are in their vertical sections laterally completely through material of the spacer 130 are covered. Here are the vertical sections of the lines 140 laterally through the material of the spacers 130 electrically isolated. At their upper ends lead the lines 140 each to a sensor element 105 , here by way of example to an upper side or a lower side of the sensor element 105 , At their bottom ends the lines 140 at contact points 145 of the semiconductor substrate 135 , Preferably, the contact points 145 set up with the wires 140 to be electrically and mechanically connected, for example by means of a soldering process.

The in the 1 and 2 illustrated embodiments of the sensor arrangement 100 can combine features that combine the versatility and high quality of the sensor assembly 100 far above known sensor arrangements, as can be seen by the following features: typ. range prefers Size sensor element 20 .mu.m-100 .mu.m ~ 40 .mu.m-60 .mu.m Number of sensor elements 1000000-10000000 ~ 2000000 rel. surface 60% -90% ~ 75% -80% Wide spacers 3 .mu.m-10 .mu.m ~ 5 microns (Table 1)

3 shows steps of a procedure 300 for producing a sensor arrangement 100 after one of the 1 or 2 , steps 305 to 335 are different stages of the sensor array 100 shown in their preparation. All representations correspond to a longitudinal section through the sensor arrangement 100 analogous to the representation of 2 ,

In one step 305 the procedure begins 300 with that a semiconductor material 340 , in particular silicon (Si), which is an upper side 345 and a bottom 350 having. Preferably, a thickness of the semiconductor material 340 constant. In the semiconductor material 340 become through holes 355 introduced, which between points on different surfaces 345 . 350 of the semiconductor material 340 run. These points preferably face each other in pairs. The through holes 355 are usually as long as the semiconductor material 340 is thick and preferably much longer than its diameter. A length to diameter ratio is preferably at least 10: 1, more preferably more than 15: 1 and can achieve ratios of about 200: 1 and more. This is the diameter of the through holes 355 typically in the range of about 1 to 5 microns.

To a through hole 355 with a high length to diameter ratio in the semiconductor material 135 To introduce a conventional silicon dry etching technology, such as the Bosch process can be used. Preferably, however, a wet-chemical etching process, in particular with light assistance, is used. Preferably, the photo-assisted electrochemical etching process (PAECE) is used. With this method, the through holes can 355 For example, have a diameter of about 3 microns, while the thickness of the semiconductor material 340 is about 350 microns.

In step 310 become walls of through-holes 355 passivated and it becomes a membrane 360 on the top 345 of the semiconductor material 340 deposited. These two processes can be combined with each other by the membrane 360 consists of a layer sequence with a non-conductive insulation layer 365 starts. The insulation layer 365 may in particular comprise silicon dioxide (SiO ₂ ). The insulation layer 365 is preferably thermally applied to coat well the vertical surfaces in the through holes well. Alternatively, another known method may be used, for example, chemical vapor deposition (CVD).

The membrane 360 For example, it may be formed as an oxide-nitride-oxide (ONO) film. In this case, a first, lowermost layer of SiO ₂ , a second, overlying layer approximately of Si ₃ N ₄ and a third, final layer again of SiO ₂ . The first layer can in particular with the insulating layer 365 fall together.

In step 315 become one or more functional layers 370 on the membrane 360 deposited, which provide a conversion of a physical quantity, in particular a heating or a temperature into a voltage. For example, the functional layer 370 comprise a pyroelectric. In the illustrated embodiment, the only functional layer used is 370 on its underside with a lower electrode 375 and at its top with an upper electrode 375 Mistake. For this purpose, preferably the lower electrode 375 , then the functional layer 370 and finally the upper electrode 375 applied.

In step 320 become the through holes 355 with a conductive material 380 filled. Has the through hole 355 a ratio of length to diameter of 15: 1 or smaller, so can a conventional methods such as sputtering or electroplating are used. At ratios of about 15: 1 or greater, a liquid-filling method may preferably be performed.

For this purpose, in a vacuum chamber, a bath with conductive material 380 provided and the prepared semiconductor material 340 is placed in the chamber. The chamber is evacuated so that an atmospheric pressure is below about 1 millibar. The semiconductor material 340 and the conductive material 380 are heated until the conductive material 340 melts and becomes liquid. The conductive material may comprise, for example, a solder, in particular based on tin, copper or aluminum.

Then the semiconductor material becomes 340 lowered into the bath and the atmospheric pressure in the vacuum chamber is raised, preferably to a value above one bar. Depending on the conductive material used 380 and diameter of the through hole 355 The pressure can be determined for a complete injection without air pockets in the through holes 355 is required. In one embodiment, the pressure may reach values of about 8 bar and more. The pressure becomes the liquid conductive material 380 in the through holes 355 pressed so that the through holes 355 continuously with the molten conductive material 380 are filled.

Subsequently, the semiconductor material 340 lifted out of the bath and allowed to cool until the conductive material 380 is frozen. The pressure in the vacuum chamber can then be lowered back to a common ambient value and the plated-through semiconductor material 340 be removed. In the places of the through holes 355 there are now vias ("visa").

In the following step 325 become the conductive materials 380 different through holes 355 with different electrodes 375 connected, which may include, for example, platinum (Pt). This can be exemplified another insulation layer 365 be applied, on which a conductive layer 385 is deposited.

In step 330 can optionally have a slot 155 are introduced, which later the membrane 360 partly from the spacer 130 separates. Preferably, the remaining webs of the membrane 360 between or next to the slots 155 designed to be the membrane 360 in the region of the sensor element 105 keep under mechanical tension.

In step 335 a deep etching takes place from the underside 350 of the semiconductor material 340 , This will cause the sensor elements 105 exposed and the spacers 130 on different sides of cavities 125 educated. The semiconductor material 320 is preferably completely from the back of the sensor element 105 removed, leaving the sensor element 105 only from the membrane 360 is worn, the contact with the spacers 130 has, and the bottom of the membrane 360 directly to the cavity 125 borders. Laterally the spacers 130 can still semiconductor material 340 remain stationary to ensure stability of the sensor arrangement 100 to increase.

In an optional step, the semiconductor material becomes 340 still on the semiconductor substrate 135 or another carrier material applied. The application can be carried out by means of a soldering or another method and comprises an electrical connection of the lines 140 and preferably also a mechanical fixation of the semiconductor material 340 on the semiconductor substrate 135 , Before or after application, structures may be formed on the semiconductor substrate 135 be attached, the evaluation of the electrically provided signals of the sensor elements 105 include. Preferably, prior to application, contact elements 145 on the semiconductor substrate 135 Designed to fit with the lower ends of the wires 140 to get in electrical contact.

Although the illustrated embodiment of the sensor assembly 100 from 1 resembles, in the two spacers 130 with a predetermined gap between sensor elements 105 can lie next to each other, can also only a spacer 130 between the adjacent sensor elements 105 lie, such as in the 2 illustrated embodiment.

Although the invention has been further illustrated and described in detail by the preferred embodiment, the invention is not limited by the disclosed examples, and other variations can be derived therefrom by those skilled in the art without departing from the scope of the invention.

Claims (15)

Sensor arrangement ( 100 ), comprising: - a plurality of sensor elements ( 105 ), which are in one level ( 110 ) are arranged two-dimensionally; - spacers ( 130 ) on the bottom ( 350 ) of the sensor arrangement ( 100 ) to a cavity ( 125 ) under the sensor elements ( 105 ) define; A plurality of electrical lines ( 140 ) for individual connection to each sensor element ( 105 ), - the lines ( 390 ) with the spacer elements ( 130 ) are integrated. Sensor arrangement ( 100 ) according to claim 1, wherein the lines ( 390 ) of the sensor elements ( 105 ) along spacers ( 130 ), which are connected to the respective sensor element ( 105 ). Sensor arrangement ( 100 ) according to claim 1 or 2, wherein the lines ( 390 ) by the spacer elements ( 130 ) pass through. Sensor arrangement ( 100 ) according to one of the preceding claims, wherein the sensor elements ( 105 ) in the plane ( 110 ) are arranged regularly. Sensor arrangement ( 100 ) according to one of the preceding claims, wherein the sensor elements ( 105 ) on membranes ( 360 ), which are in the plane ( 110 ) lie. Sensor arrangement ( 100 ) according to one of the preceding claims, wherein the spacer element ( 130 ) has a height to width ratio of at least 10: 1. Sensor arrangement ( 100 ) according to one of the preceding claims, further comprising a semiconductor substrate ( 135 ) electrically connected to the spacer elements ( 130 ), wherein on the semiconductor substrate ( 135 ) an evaluation circuit ( 150 ) for signals of the sensor elements ( 105 ) is arranged. Sensor arrangement ( 100 ) according to one of the preceding claims, wherein each sensor element ( 105 ) two insulated lines ( 390 ) and the lines ( 390 ) in different spacers ( 130 ). Sensor arrangement ( 100 ) according to one of the preceding claims, wherein the sensor elements ( 105 ) for providing electrical signals as a function of temperatures of the sensor elements ( 105 ) are set up. Sensor arrangement ( 100 ) according to one of the preceding claims, wherein a surface of the spacer elements ( 130 ) in the plane ( 110 ) less than 30% of the total area of the sensor elements ( 105 ) in the plane ( 110 ) is. Method for producing a sensor arrangement ( 100 ) with a plurality of sensor elements ( 105 ), which are in one level ( 110 ) are arranged two-dimensionally, comprising the following steps: 305 ) of semiconductor material ( 340 ) with a lower ( 350 ) and an upper surface ( 345 ); - introduction ( 305 . 310 . 320 ) of vias ( 355 . 365 . 380 ), which points on different surfaces ( 345 . 350 ) of the semiconductor material ( 340 ) electrically connect to each other; - application ( 315 ) of the sensor elements ( 105 ) on the upper surface ( 345 ) such that the sensor elements ( 105 ) each in electrical contact with at least one of the vias ( 355 . 365 . 380 ), and - Remove ( 335 ) of semiconductor material ( 340 ) on the lower surface ( 350 ) in areas between the vias ( 355 . 365 . 380 ). Procedure ( 300 ) according to claim 11, wherein the introduction of vias ( 355 . 365 . 380 ) in the semiconductor material ( 340 ) comprises the following steps: - introduction ( 305 ) of through holes ( 355 ) in the semiconductor material ( 340 ); - Passivate ( 310 ) of walls of the through holes ( 355 ), and - filling ( 320 ) of the through holes ( 355 ) with liquefied conductive material ( 380 ). Procedure ( 300 ) according to claim 12, wherein the through holes ( 355 ) under pressure with a molten conductor ( 380 ) and the ladder ( 380 ) is then cooled until it is in the through holes ( 355 ) stiffens. Procedure ( 300 ) according to claim 12 or 13, wherein the through holes ( 355 ) is introduced by means of a photo-assisted electrochemical etching process ( 305 ) become. Procedure ( 300 ) according to one of claims 12 to 14, wherein the walls of the through-holes ( 355 ) passivated by thermal oxidation ( 310 ) become.

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