DE102012107351A1 - Driver circuit for display device e.g. LCD device of electronic devices, has driver supporting modes in response to control signals and controlling bus with data that is not related to locked- or unlocked states of clock signal - Google Patents

Abstract

The circuit has a multifunction driver (25) designed such that the driver supports two operation modes in response to two control signals. The driver controls a bus (CB) with an output signal (FDATA) with a value, which indicates locked- or unlocked states of a clock signal. The driver controls the bus with data i.e. multi-bit data stream, that is not related to the locked- or unlocked states of the clock signal. The data stream comprises same header and footer-bit strings. The driver and another multifunction driver are electrically coupled with a backward channel signal line. An independent claim is also included for a method for operating a display device.

Description

Reference to priority application

This application claims priority under 35 USC § 119 of 23 September 2011 Korean Patent Application No. 10-2011-0096478 the disclosure of which is hereby incorporated by reference herein.

TECHNICAL AREA

The present invention relates to integrated circuit devices and methods for operating the same, and more particularly to integrated display circuit devices and methods for operating integrated display circuit devices.

BACKGROUND

Display devices such. For example, liquid crystal display (LCD) devices and plasma display panel (PDP) devices may include a display driver IC (DDI). A display device may include a plurality of source driver chips (eg, source drivers) having a DDI configuration. Each source driver may include driver source lines (eg, data lines) of a field based on display data of a timing controller. As the return signal line, a shared return channel (SBC) may be used as the associated bus for transferring a soft-fail signal output from any of the source drivers to a timing controller. Here, the soft-fail signal may indicate an unlocked state of a clock recovery unit or indicate whether settings have been changed by electrostatic discharge (ESD). When a clock is latched, the soft-fail signal can be set to a logical high level by a power-down operation of a split back channel driver in the source driver. When a clock is unlocked, the soft-fail signal can be set to a logical low level by a power-on of the divided back channel driver in the source driver. Examples of display driver ICs are in the US patents US 7,259,742 by Chang et al. and US 7,737,939 by Shin et al. , the disclosures of which are incorporated herein by reference.

SHORT VERSION

Display driver circuits according to embodiments of the invention include a first multi-function driver configured to support at least first and second modes of operation. The first multi-function driver supports the first mode of operation in response to a first control signal by controlling a bus with a first output signal. This first output signal has a value indicative of a locked or unlocked state of a first clock signal therein. The first multi-function driver also supports the second mode of operation in response to a second control signal by controlling the bus at first data not associated with the locked or unlocked state of the first clock signal. This first data may be a multi-bit data stream. A second multi-function driver may also be provided. This second multi-function driver is configured to support the first mode of operation in response to a third control signal by controlling the bus with a second output signal having a value indicative of a locked or unlocked state of a second clock signal therein. The second multi-function driver is configured to support the second mode of operation in response to a fourth control signal by controlling the bus with second data not coupled to the locked or unlocked state of the second clock signal. The first and second control signals may be provided as inactive and active states of a first read enable signal, or vice versa, and the third and fourth control signals may be provided as inactive and active states of a second read enable signal, or vice versa.

According to some embodiments of the invention, the bus may operate as a split back channel signal line and the first and second multi-function drivers may be configured to control the split back channel signal line with the first and second output signals during the first mode of operation, respectively. In addition, the first and second multi-function drivers may be electrically coupled to the split return channel signal line in a wired-OR configuration. In still other embodiments of the invention, the first multi-function driver may be configured to support the second mode of operation by controlling the split back channel signal line with a data stream that is related to at least one of the touch sensor data, ambient light sensor data, temperature sensor data, and bit error count data refers.

A timing control may also be provided. This controller is configured to provide a first training clock to the first multi-function driver in response to receiving the first output signal with a value indicating an unlocked state of the first clock signal. In particular, the timing controller may be configured to provide the respective first and second training clocks to the first and second multi-function drivers during the first mode of operation in response to detecting a signal on the shared one Return channel signal line reflecting an unlocked state of any one of the first and second clock signals.

According to further embodiments of the invention, a display driver circuit is provided with a plurality of drivers. These drivers have respective output terminals electrically coupled to each other with a divided back channel signal. The plurality of drivers are configured to respond to a first jointly provided supervisory command by informing the shared back channel signal line of the state of a signal or device therein. The plurality of drivers is further configured to individually respond to a separately provided read command by controlling the shared back channel signal line with respective read data. The display driver circuit may also include a receiver electrically coupled to the split return channel signal line and a plurality of transmitters. The plurality of transmitters are configured to control the plurality of drivers side by side with the first monitor command during a monitor mode of operation to determine when respective clock signals within the plurality of drivers have been latched. The scheduler may also be configured to provide a training clock during the monitoring mode of operation for the plurality of drivers.

A display driver circuit according to other embodiments of the invention may include a plurality of drivers having respective first terminals electrically coupled to each other with a shared return channel signal line through a wired-OR configuration. The drivers are configured to support a training clock mode of operation by controlling the split back channel signal line with a first signal that supports an unlocked state of at least one clock within the plurality of drivers. The drivers are also configured to support individual data read modes of operation by controlling the shared back channel signal line with respective data streams during non-overlapping time intervals. Each of these data streams may have equal header and footer bit sequences.

According to still further embodiments of the invention, a method of operating a display device includes providing a training clock of a first multi-function driver circuit in response to detecting an unlocked state of a first clock generated therein over a shared bus coupled to an output of first multi-function driver circuit is coupled. The method further includes providing a first active read control signal of the first multi-function driver circuit in response to detecting a locked state of the first clock over the shared bus. In response to the first active read control signal, the first multi-function driver transmits first read data to the shared bus.

The methods further include providing a training clock for a second multi-function driver circuit in response to detecting an unlocked state of at least one of a second clock generated therein and the first clock over a shared bus coupled to an output of the second bus second multi-function driver circuit is coupled. A second active read control signal for the second multi-function driver circuit may be provided in response to detecting a locked state of the first and second clocks over the shared bus. Second read data may be transmitted from the second multi-function driver circuit to the shared bus in response to the second active read control signal. The provision of the first active read control signal and the provision of the second active read control signal can only be performed individually. Providing the training clock for the second multi-function driver circuit may also include first and second training clocks for the first and second multi-function driver circuits, respectively.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features will become apparent from the following description with reference to the following figures, wherein like reference characters refer to like parts throughout the several figures, unless otherwise specified.

The 1A - 1B 12 are block diagrams of multi-function driver circuitry according to embodiments of the inventive concept.

The 2 FIG. 10 is a block diagram illustrating a plurality of drivers electrically coupled to a shared bus in accordance with an embodiment of the inventive concept. FIG.

The 3A FIG. 12 is an electrical diagram illustrating a plurality of source drivers electrically coupled by a split bus to a timing control circuit in accordance with an embodiment of the present invention. FIG.

The 3B is an electrical schematic of a plurality of source drivers of 3A with distant selective components to the operation of the source driver during a monitor mode of operation.

The 3C FIG. 12 is an electrical schematic of the plurality of source drivers of FIG 3A with remote selective components to illustrate the operation of one of the source drivers during a read data mode of operation.

The 3D is a timing diagram showing a timing of signals RD1, RD2 and SBC of 3C during operation to train a plurality of source drivers followed by an operation to read data from a second source driver.

The 3E is a timing diagram showing a timing of signals RD1, RD2 and SBC of 3C during operation to train a plurality of source drivers followed by an operation to read data from a second source driver during an ESD overvoltage event.

The 4 FIG. 12 is a block diagram schematically illustrating a plurality of source drivers and a timing control according to an embodiment of the inventive concept. FIG.

The 5 is a flowchart illustrating several operating modes of the source driver and timing of 4 illustrated according to an embodiment of the invention.

The 6 is a detailed flowchart showing several modes for the operation of the source driver and timing of 4 illustrated according to an embodiment of the invention.

The 7A FIG. 12 is an electrical schematic diagram illustrating a plurality of source drivers coupled electrically to a timing control circuit by a shared bus in accordance with an embodiment of the present invention. FIG.

The 7B is an electrical schematic of a plurality of source drivers of 7A with selected components removed to illustrate the operation of the source drivers during a monitor mode of operation.

The 8A FIG. 12 is an electrical schematic of the plurality of source drivers of FIG 7A with selected components removed to illustrate operation of one of the source drivers during a data read mode of operation.

The 8B is a timing diagram showing a timing of signals RD1, RD2 and SBC of 8A during an operation to train a plurality of source drivers followed by an operation to read data from a second source driver.

The 8C is a timing diagram showing a timing of signals RD1, RD2 and SBC of 8A during an operation to train a plurality of source drivers followed by an operation to read data from a second source driver during an ESD overvoltage event.

The 9 FIG. 12 is a block diagram schematically illustrating a display device according to an embodiment of the inventive concept. FIG.

The 10 FIG. 16 is a block diagram schematically showing a connection between a communication device and a display device of FIG 9 illustrated.

The 11 is a block diagram that schematically shows an internal circuit of 4 illustrated according to an embodiment of the inventive idea.

The 12 Figure 12 is a block diagram of an application of the inventive idea applied to various display devices.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive idea will be described below with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are illustrated. However, this inventive idea may be embodied in many different forms and should not be interpreted as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive idea to those skilled in the art. In the drawings, the size and relative sizes of regions may be exaggerated for purposes of illustration. The same numbers refer to the same elements throughout.

It should be understood that although the terms first, second, third, etc. are used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions do not these terms are limited. These terms are used only to distinguish an element, a component, an area, a layer or Part of another area, layer or subarea. Therefore, a first element, a first component, a first region, a first layer, or a first subregion discussed below may be referred to as a second element, a second component, a second region, a second layer, or a second subregion without departing from the teaching of the inventive idea.

Spatially related terms such. "Lower," "below," "below," "below," "above," "upper," and the like, may be used herein to facilitate the description to describe one element or the ratio of one feature to another element (s) ) or function (s) as shown in the figures. It will be understood that the spatially related terms are intended to encompass different orientations of the device in use or operation in addition to orientation as illustrated in the figures. If z. For example, as the devices on the figures are rotated, elements described as "below" or "below" or below other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" may delineate both an up and down orientation. The device may also be otherwise oriented (rotated 90 degrees or in a different orientation) and the spatially relative terms used herein may be construed accordingly. Moreover, it is also to be understood that when a layer is described as being "between" two layers, it may be the only layer between the two layers or, moreover, one or more intermediate layers may be present.

The terminology used herein has the sole purpose of describing particular embodiments and is not intended to limit the inventive concept. As used herein, the singular forms "a / a" and "the" should also include the plural forms unless the context clearly indicates otherwise. In addition, it is to be understood that the terms "he / she / it indicates" and / or "having" when used in this specification indicate the presence of particular characteristics, integers, steps, operations, elements, and / or components. but do not exclude the presence or addition of one or more other properties, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of one or more of the listed listed terms.

It will be understood that when an element or layer is described as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it directly contacts, connects, couples, or adjoins to another element or layer, or intervening elements or layers may be present. In contrast, when an element is described as "directly on," "directly connected to," "directly coupled to," or "immediately adjacent" to another element or layer, there are no intervening elements or layers.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these inventive concepts pertain. Furthermore, it is understood that terms such. For example, those defined in standard dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant technique and / or description and is not construed in an idealized and overly formal sense, unless explicitly stated herein so defined.

The 1A - 1B 13 are block diagrams of multi-function driver circuits according to embodiments of the inventive concept. Regarding the 1A can be a driver 25 by a control unit 220 be controlled and coupled to a shared bus CB. The driver 25 may have an input terminal IN. The driver 25 may include a first mode of operation or a second mode of operation according to a read enable signal RE applied to a line L20. The first mode of operation may be assigned to a monitoring or training mode, and the second mode of operation may be assigned to a data read mode. When the first operation mode is executed in response to an inactive state of the read enable signal RE, a soft-fail signal may appear on the divided bus CB as a first output capable of forming a divided return channel. This first output signal may have a logical high value or a logical low value. When the second operation mode is executed in response to an active state of the read enable signal RE, a data output read from various internal circuits may occur on the divided bus as the first data FDATA. The first data FDATA can z. B. be a data stream with a format according to a clock signal. The driver 25 which drives the divided bus CB may have at least two operation modes according to a state of the read enable signal RE. Because of this, the driver may be 25 as a multi-function driver be designated. In a case where a driver 25 is provided, a local bus LB may be the shared bus CB. In the case where a plurality of drivers are provided, a shared bus CB may be coupled to a plurality of local buses LB. For example, as in the 1B presented driver 25-1 and 25-2 by a control unit 220 be controlled and coupled to a shared bus CB. Each of these drivers 25-1 and 25-2 can each have inputs IN1 and IN2. Each of these drivers 25-1 . 25-2 may include a first mode of operation or a second mode of operation according to a read enable signal RE1 (or RE2) applied via a line L20 (or L30) as shown. The first operating mode may be referred to as a monitoring or training mode, and the second operating mode may be referred to as a data read mode. When the first operation mode is executed in response to an inactive state of the read enable signal RE, a soft-fail signal may occur on the split bus CB as a first (or second) output capable of a divided return channel to become. This first (or second) output signal may have a logical high value or a logical low value. When the second operation mode is executed in response to an active state of the read enable signal RE, a read-out data output from various internal circuits on the shared bus may occur as first data FDATA (or second data SDATA) including a data stream in accordance with a clock signal generated format.

The 2 is a block diagram of drivers according to another embodiment of the inventive concept. Regarding the 2 can be a first driver 25-1 be coupled to a shared bus CB via a first local bus LB1, and a second driver 25-2 can be coupled to the shared bus CB via a second local bus LB2. A shared receiver 224 can read first data from the first driver 25-1 or second read data from the second driver 25-2 exhibit. This read data is transmitted over the split bus CB, which can be held "lightly" at a voltage logic level of 1 (eg, Vdd) by a pull-up resistor R. As shown in more detail below, this resistor may be implemented as a PMOS pull-up transistor with gate and drain terminals shorted together. When a first enable signal RE1 is set in an inactive state, a second read enable signal RE2 may be independently activated. In this case, a second data output (eg, second read data) may be from the second driver 25-2 to the shared receiver 224 be transmitted over the split bus CB, which operates as a shared return channel. On the other hand, when the second activated read signal RE2 is in an inactive state, the first enable signal RE1 may be independently activated. In this case, the first data output (eg, first read data) may be from the first driver 25-1 on the shared receiver 224 be transmitted via the shared bus CB. As described in more detail below, each driver may support two modes of operation, but may be applied to the shared bus CB only one at a time in an active read mode of operation.

The 3A is a schematic diagram of a plurality of source drivers 250-1 . 250-2 , ..., 250-n containing a corresponding plurality of driver circuits 25-1 and 25-2 as in 2 has shown. As described more fully below, the driver circuits 25-1 and 25-2 have two modes of operation and can be controlled by the timing 220 to be controlled. Regarding the 3A can be a first driver circuit 25-1 three MOS transistors and two sorters (eg multiplexer). The first driver circuit 25-1 for data transmission may comprise a first MOS transistor N1 having a drain coupled to the split bus CB via the node ND1, a grounded source and a gate coupled to receive a first input signal RD1. A second MOS transistor N2 is also provided having a drain coupled to the split bus CB via the node ND1 and having a grounded source. A third PMOS transistor P1 is provided having a drain connected to the split bus CB via the node ND1 and having a source coupled to a supply voltage (eg, Vdd). A first sorter / multiplexer S1 is provided which selects a first input and a second input according to a state of a read control signal RC1. The first sorter S1 has an output which is coupled to a gate terminal of the third PMOS transistor P1. This read control signal RC1 may correspond to the externally applied read enable signal RE1, which is for the timing control 220 is provided. A second sorter / multiplexer S2 is provided which selects one of a third input and a fourth input according to a state of the read control signal RC1. This second sorter S2 has an output coupled to a gate of the second MOS transistor N2.

In the 3A For example, the first input to the first sorter S1 and the third input to the second sorter S2 may be the same signal (eg, both may be RD1). This same signal RD1 may be treated as a soft-fail signal (the locked or unlocked state of an internal clock) or as a read-out data signal depending on the mode of operation. The first and second MOS transistors N1 and N2 can n- Channel MOS field effect transistors and the third MOS transistor P1 may be a p-channel MOS field effect transistor. However, the inventive idea is not limited thereto, and these transistor types can be changed accordingly. In addition, in the case where the second input to the first sorter S1 is set to a first logical state (eg, a logic 1 = Vdd), the fourth input to the second sorter S2 may be set to a second logical state (eg, a logical 0 = ground), however, alternative fixed states may be used in accordance with further embodiments of the invention. The second driver circuit 25-2 and all other driver circuits may have the same configuration as the first driver circuit as shown 25-1 exhibit.

The operation of the multi-function driver circuit according to the 3A will now be described. Each of the read control signals RC1 and RC2, at the selected terminals of the sorters / multiplexers S1, S2 in the first and second drivers 25-1 . 25-2 can be disabled during a monitor mode of operation and can be independently enabled individually during a data read mode of operation. When the read control signal RC1 is inactivated during the monitoring mode, the first sorter S1 in the first driver circuit 25-1 select the second input, thereby setting the gate of the third MOS transistor P1 in a high signal state (eg, Vdd), thereby setting the third MOS transistor P1 in an "off" state. In addition, the second sorter S2 in the first driver circuit 25-1 select the third input and thereby pass a soft-fail signal input to the gate of the second MOS transistor N2. Consequently, when the input signal RD1 is logically low during the monitoring operation mode, the first and second MOS transistors N1 and N2 may be turned off together with the third MOS transistor P1, making it possible to connect the node ND1 (and a split bus CB). " weak "at a pre-charged voltage level by an always-on PMOS pull-up transistor PU1 having a relatively high resistance (or other type of resistor R).

Thus, in the case where one clock of a clock recovery unit in the first source driver 250-1 is locked (eg, correctly synchronized), the input signal RD1 has a logic low level, which means that first data having a logical high state is held at a precharged level on the divided bus CB. On the other hand, when the input signal RD1 is logic high, the first and second MOS transistors N1 and N2 will be turned on. In this case, a potential is pulled down (eg, discharged) from the node ND1 to a ground potential (eg, Gnd), which means that first data having a logic low state is applied to the divided bus CB. As will be described in more detail below, in the event that a clock having a clock recovery unit is not latched (eg, out of synchronization), the corresponding input signal RD1 may have a logic high level, meaning that the first data is tied to the first logic low state are transferred to the divided bus CB, thereby the unlocked state of the clock in the first source driver 250-1 reflect. In addition, when the first data of a logical low state is provided on the divided return channel during the monitoring mode, a timing control unit may be provided 220 with the shared receiver 224 therein detect the clock as unlocked, and may (or continue to provide) provide a training clock to a corresponding source driver. Thus, during the first mode of operation, a stall condition signal may be transmitted over the split bus CB indicating a locked / unlocked state of a clock recovery unit in the source driver.

In contrast, when the read control signal RC1 is activated during a data read operation mode (eg, the second operation mode), the first sorter S1 may select and apply the first input (eg, the signal RD1) output the gate of the third MOS transistor P1. The third MOS transistor P1 can be turned on or off according to a logic state of the first input RD1. The first and third MOS transistors N1 and P1 may constitute a CMOS inverter INV. The second sorter S2 may also select the fourth input (eg, a logic low level) and output it to the gate of the second MOS transistor N2. Accordingly, the second MOS transistor N2 can be turned off. Accordingly, when the input signal RD1 is logic low, the first MOS transistor N1 can be turned off while the third MOS transistor P1 can be turned on. This may mean that the node ND1 is set to a potential of power supply by the PMOS transistor Plauf (eg, Vdd), so that second data having a logical high state may occur on the divided bus CB. However, when the input signal RD1 is logic high, the first MOS transistor N1 may be turned on while the third MOS transistor P1 may be turned off. Thereby, the node ND1 will be pulled to a logic zero voltage level (eg, Gnd) because the pull-down strength of the first MOS transistor N1 is greater than the pull-up strength of the PMOS pull-up Transistor PU1. Thus, during the data read mode of operation of the shared receiver 224 in the Timing control 220 the second data as an inverted version of the first input RD1 of the selected driver (e.g. 25-1 . 25-2 , ..., 25-n ) over the shared bus (eg shared return channel SBC). This second data may be bit error rate (BER) test data, touch panel data, brightness data, temperature data, or other data stored in the corresponding source driver.

In addition, to achieve a smooth transition from the second mode of operation (eg, data read mode) to the first mode of operation (eg, monitoring / training mode), the pull down drive capacity of the second MOS Transistor N2 in a non-selected driver 25-n that receives an inactive read control signal RCn (eg, an inactive read enable signal REn) may be greater than the combined (eg, parallel) pull-up strengths of the split PMOS pull-up transistor PU1 and the PMOS pull-up transistor P1 in a selected driver providing read data to the split bus CB in response to an active read control signal. As a result, as described more fully below with respect to the timing diagram of FIG 3E even if the PMOS pull-up transistor P1 drives the divided bus CB with a logical 1 data, an unselected driver is described 25-n with an unlocked clock therein, overwriting and maintaining the logical 1 data value by lowering the split bus CB to a logic 0 voltage level until a new training clock operation is performed to reset the clock in the unselected driver 25-n to lock.

The 3B illustrates components of a display driver circuit according to further embodiments of the invention during a first monitor mode of operation when each of the source drivers 250-1 . 250-2 , ..., 250-n receives a corresponding training cycle. These training clocks support the synchronization of clock signals in the source drivers 250-1 . 250-2 , ..., 250-n , In contrast to the embodiment of 3A is the timing control 220 from 3B with a shared receiver 224 an input terminal electrically coupled to the split bus (CB) operating as a divided return channel SBC and a plurality of transmitters 221-1 . 221-2 , ..., 221-n illustrated. These transmitters are electrically connected to an input bus 210 coupled input terminals and output terminals coupled to the respective signal lines L40, L42, ..., L44, the respective read enable signals RE1, RE2, ..., REn to the source drivers 250-1 . 250-2 , ..., 250-n provide. Like in the 3B shown are elements of the driver 25-1 . 25-2 , ..., 25-n from 3A have been omitted from the view which are inactive in response to inactive read enable signals (e.g., RC1, RC2, ..., RCn = 0). Each of the input signals RD1, RD2, ..., RDn is provided to a corresponding pair of NMOS pull-down transistors N1, N2, which means that the divided bus CB is pulled low from a "light" precharged logic 1 voltage level Whenever one (or more) of the input signals RD1, RD2, ..., RDn is set to a logical value of 1, the latched state of the clock is asserted in a corresponding source driver 250-1 . 250-2 , ..., 250-n to reflect. Maintaining a sustained logic 0 voltage level on the shared bus CB during the monitor mode of operation (eg, when RE1, RE2, ..., REn = 0) will result in delayed generation of a training clock at each of the source drivers, FIGS the divided bus CB is reset to a logical 1 voltage level. This return to a logical 1 voltage level will occur when all input signals RD1, RD2, ..., RDn are switched to logic 0 voltage levels, thereby causing the NMOS pull-down transistors N1, N2 in each of the drivers 25-1 . 25-2 , ..., 25-n turn off and show that all corresponding clocks in the source drivers ( 250-1 . 250-2 , ..., 250-n ) have been successfully trained (eg synchronously).

The 3C represents how that in relation to the 3B described training clock operation, an operation for reading data (eg, bit error rate (BER) test data, touch panel data, brightness data, temperature data, etc.) from the second driver 25-2 in the second source driver 250-2 simultaneously with monitoring a state of a clock in the first source driver 250-1 (and other source drivers) can follow. These modes of operation may be accomplished by controlling the first source driver 250-1 can be achieved with an inactive read enable signal RE1, which results in an inactive read control signal RC1 in the first source driver 250-1 can be converted while at the same time the second source driver 250-2 is driven with an active read enable signal RE1, which is to an active read control signal RC2 in the second source driver 250-2 can be converted. This active read control signal RC2 will enable the operation of an inverter (eg PMOS pull-up transistor P1 and NMOS pull-down transistor N1), because the active read control signal RC2 will pass the input signal RD2 through the selector / multiplexer S1 to the gate terminal of the PMOS transistor P1 (while simultaneously holding an NMOS pull-down transistor N2 in an off state by passing a logic 0 voltage signal (e.g., Gnd) to the sorter / multiplexer S2 (not in FIG 3C shown) is maintained). Accordingly, as long as the input signal RD1 in the first source driver 250-1 is held at a logic 0 voltage level to thereby reflect a continuous synchronization of a clock therein, the input terminal of the shared receiver 224 in the timing control 220 with read data of the second source driver 250-2 (eg CB = / RD2).

The 3D to 3E 2 are timing diagrams illustrating the operating timings discussed above with respect to FIG 3C during which read data (/ RD2) from the second source driver 250-2 to the shared return channel SBC (eg, the shared bus CB) in response to an active read enable signal RB2. Just like that 3D are shown are the source drivers 250-1 . 250-2 , ..., 250-n are responsible for respective training strokes during a monitor mode of operation when the read enable signals RE1, RE2, ..., REn are held at logic 0 voltage levels (eg, inactive). In response to these training clocks, internal clock signals (eg, PLL clock signals) in the source drivers are synchronized. Once the last of the internal clock signals is synchronized, the divided return channel SBC switches from a logic 0 voltage level to a logical 1 voltage level due to the pull-up of the PMOS pull-up transistor PU1 and the fact that all input signals RD1, RD2, ..., RDn have been set to logic 0 voltage levels, thereby including the NMOS pull-down transistors N1, N2 in the drivers 25-1 . 25-2 , ..., 25-n off. Thereafter, after activating the read enable signal RE2 during a time interval T21, a data read operation starts from the second driver 25-2 during the time interval T0 (eg, from a time t1 to a time t4). During this data read operation, header information (Start), data (Read_Data) and footer information (End) are provided on the shared return channel SBC at times t1, t2 and t3, respectively. The header and footer information is provided as a relatively short alternating sequence of logical 1 and logical 0 data bits to timing control 220 to allow the start and stop of a valid data read interval (T0) associated with the active read enable signal RE2 to be asserted. However, the retained logical 0 value on the divided return channel SBC during the time interval T0 is timed out 220 (eg due to alternate logical 1 and logical 0 data bits having missing footing) are correctly interpreted as false data, as indicated by the 0 to 1 transition of signal RD1 during a time interval T0 in 3E when a faulty event (eg, an ESD overvoltage) occurs in any of the clocks in the source drivers 250-1 . 250-2 , ... 250-n that get out of hand results. In response to the missing footer area line during the time interval from time t3 to time t4, the timing control becomes 220 resume a monitor mode of operation during which a previously enabled read enable signal is inactivated (eg, RE1, RE2, ..., REn = 0). During this monitoring mode of operation, respective training cycles again become the source drivers 250-1 . 250-2 , ..., 250-n is provided until all clocks are resynchronized and the shared return channel SBC is reset to a logical 1-voltage level.

The 4 FIG. 12 is a block diagram schematically illustrating a source driver and a timing controller according to an embodiment of the inventive concept. FIG. Regarding the 4 can be a timing control 220 a plurality of broadcasters 221-1 to 221-n and a shared receiver 224 exhibit. The timing control 220 can with a system control unit 210 be coupled. The majority of source drivers 250-1 to 250-n can with a plurality of senders 221-1 to 221-n in the timing control 220 be coupled. An interface for transmitting display data from the time control unit 220 to the source driver 250-1 to 250-n can be referred to as an intra-panel interface. The intra-panel interface may be used as a reduced signal swing (RSDS) differential signaling using a multi-drop method or using a point-to-point differential signaling (PPDS) interface that is point-to-point Point method used.

The source driver 250-1 may be a shared return channel driver circuit 25-1 , a clock recovery unit 26-1 , an internal circuit 28-1 and a display panel control unit 29-1 exhibit. As a clock restoring circuit, the clock recovery unit 26-1 a DLL or PLL circuit and may output a soft-fail signal indicating whether a clock is unlocked or latched therein. The internal circuit 28-1 may be a circuit for outputting readout data via a line LC and may be in the 11 illustrated circuit (s). This may mean that bit error rate check data, touch panel data, brightness data, or temperature data, etc., through the split back channel driver circuit 25-1 can be controlled to be transferred to the shared bus CB. The driver unit 29-1 may be a circuit for controlling source lines of a panel and may be controlled by a timer 220 to be controlled.

The split bus CB, which operates as a return channel signal line, can be timed 220 provide a soft error signal in a first mode of operation. For example, in a case where a clock recovery unit is unlocked or set values by Electrostatic discharge (ESD) can be changed, the source driver 250-1 to 250-n set a split bus CB to a logical low state. The shared bus CB may be a shared return channel SBC originating from the source drivers 250-1 to 250-n shared. In the 4 an embodiment is illustrated in which the timing control 220 and the source drivers 250-1 to 250-n coupled in a multi-drop manner. However, the inventive idea is not limited to this. For example, the shared return channel SBC may be between the timing 220 and the source driver 250-1 to 250-n be connected in a chain. The shared return channel SBC may use an Enhanced-Reduced Differential Signaling (eRVDS) method to achieve a consistent signal interface.

The 5 FIG. 10 is a flowchart for describing a data transmission method according to an embodiment of the inventive concept. FIG. During operation S50, a check is made to determine if a first mode of operation is desired. If so, the operation S51 is performed to execute the first operation mode. Regarding the second source driver 250-2 of the 4 For example, during the first mode of operation, a second read enable signal RE2 may be transmitted via a second transmitter 221-2 is applied to the source driver 250-2 be applied via a line L42. This second read enable signal RE2 can be set to an inactive state. Accordingly, as described above, when the second read control signal RC2, which is the same signal as the second read enable signal RE2, is inactivated, a third MOS transistor P1 in a driver circuit 25-2 turned off. In addition, in case of a clock of a clock recovery unit 26-2 is locked, the input signal RD2 are set to a logical low level, so that first data will occur with a logic high level on the split bus CB. However, if the clock in the clock recovery unit 26-2 unlocked, first data with a logic low level occur on the shared bus CB. When the first data is received at a logic low level via a shared return channel SBC during the first mode of operation (eg, a monitor mode), timing control may be enabled 220 with the included shared receiver 224 determine that a clock within at least one source driver is unlocked.

Referring again to the 5 If the operation S50 determines that the first mode is not desired, the process proceeds to step S52. During operation S52, a check is made to determine if a second mode of operation has been selected. If so, then an operation is performed at S53 to execute the second mode. Referring again to the source driver 250-2 of the 4 This can be done by the second transmitter 221-2 generated second read enable signal RE2 to the source driver 250-2 be applied via the line L42. Accordingly, as above with respect to the 3A - 3E when the second read control signal RC2, which is the same signal as the second read enable signal RE2, is activated, a first sorter S1 within the driver circuit is activated 25-2 select the first input RD2 and output it to a gate of a third MOS transistor P1. Thus, the signal RD2 can be inverted by the CMOS inverter defined by the first and third MOS transistors N1 and P1. A second MOS transistor N2, which is turned off, can not participate in one operation during the second operation mode. Based on this activation of the second driver 25-2 For example, when the input signal RD2 is logic low (high), the data will appear on the split bus CB with a second logical high (low) state.

During this second operating mode, the timing control 220 receive the second data as an inverted version of the first input RD2 via the split return channel SBC. The second data can be z. B. bit error rate test data, touch panel data, brightness data, color data or temperature data. If the drivers 25-1 . 25-3 , ..., 25-n working in the first mode of operation, a second driver 25-2 operate independently in the second mode of operation to transmit the second data in a fixed format over the split bus CB. The data having the designated format may include start data indicating a start of a data transfer (eg, a header area), data read out to be transferred, and end data indicating an end of a data transfer (eg, a packet footer line). Show. In the case that is the decision in the operation step S52 of the 5 shows that the second mode of operation is not active, the step S54 may be performed to thereby perform another mode of operation instead of the first or second mode of operation. Finally, as indicated by step S55 in the 5 shown a test performed to end operations when the previously selected operating mode has been completed.

The 6 is a detailed flowchart referring to the flowchart of FIG 5 refers. In the 6 For example, a monitor mode of operation is a primary mode of operation until a data read mode is to be periodically executed. During this data read mode, an operation may be performed to cope with error generation when data is sent via a shared return channel be transmitted. As by the block S60 in 6 an initialization (training) operation may be performed during its training signals to the source drivers 250-1 . 250-2 , ..., 250-n to be provided. The training signals may be training clocks used for a clock latching operation of a respective clock recovery unit. In particular, a clock recovery unit 26-1 . 26-2 , ..., 26-n perform a procedure to lock an internal clock to the appropriate training clock to thereby enable data synchronization in the corresponding source driver. In the situation where a clock is disabled, a source driver may normally source lines of a display panel 280 control according to input display data, as described in the 9 is shown.

As in step S61 in the 6 5, a check is made to see if the first data in the divided return channel SBC is at a logical low level or a logical high level. If the first data on the shared return channel SBC is judged to have a logical low level, a clock may be judged to be unlocked, meaning that training procedures must be continued (see, for example, block S60). However, if the first data of the split return channel SBC is judged to be a high logic level, all clocks in the source drivers may be considered latched and a monitor mode will continue as a primary mode of operation (see, for example, block S62). In this normal operating mode, the source drivers 250-1 . 250-2 , ..., 250-n Source lines of the display panel 280 control and the timing control 220 can continue to monitor whether all clocks remain latched across the split return channel SBC.

In addition, in the case that the system control unit 210 from 4 a read request associated with internal data of a panel via an external test device (or internal data associated with a panel in the system controller 210 itself), the operation S63 of FIG 6 be performed to confirm that a data read mode has been requested. If a data read mode has been requested, the process proceeds to step S64. Operation S64 may include applying an active read control signal to the selected source driver 250-2 which means that a first input RD2 of the second driver 25-2 read data from an internal circuit 28-2 from 4 while a first input RD1 of the first driver 25-1 a latch output from a clock recovery unit 26-1 can be.

Accordingly, as above with respect to 3D described the first input RD2 of the second driver 25-2 occur as data having a fixed format, the start data (indicating a start of the data transmission), data read out as data to be transmitted and end data (indicating an end of the data transmission). This second data may be an inverted version of data of the first applied data RD2 due to an inverter function in the second driver 25-2 exhibit. As a result, second data read during the second operation mode can be read from the internal circuit 28-2 via the shared return channel SBC in step S65 and a shared receiver 224 can receive the second data. In operation S66, the timing control 220 Check that the data entry is via the shared receiver 224 is faulty. The reception of erroneous data can be detected because the transmitted second data packet has a fixed format (eg header, data, footer area line). When the data input through the shared receiver 224 is judged to be faulty, the data transfer must be re-executed, and such a situation must be timed out 220 be recognized. The data transfer error can be generated when the second source driver 250-2 the second data on the divided return channel SBC transmits and a release state of a clock in the first source driver 250-1 is produced. Like in the 3E For example, when a high input in the waveform RD1 is generated upon transmission of the second data, an abnormal waveform SBC may occur on the divided return channel SBC although the first input RD2 of the second driver 25-2 has valid data. Consequently, the timing control 220 does not receive an accurate end signature (eg, an alternate 0-1 footer sequence). In response to this, the timing control 220 detect a transmission error of the second data during the period T0. If an error is detected in the data transfer in operation S66, the process returns to step S60, but if no error in the data transfer is detected, the process proceeds to operation S67. In step S67 of 6 it can be judged whether the execution of the data read mode has been completed. If the data read mode has not yet ended, the process returns to step S64. However, when the data read mode is ended, a monitor mode may be executed, wherein the first mode of operation is executed.

The 7A is a circuit diagram of a plurality of source drivers 250-1 . 250-2 , ..., 250-n containing a corresponding plurality of driver circuits 25-1 and 25-2 has, as in 2 is shown. The driver circuits 25-1 and 25-2 may have two modes of operation and at least in part by the timing control 220 to be controlled. Regarding the 7A can be a first driver circuit 25-1 three MOS transistors and two sorters (eg multiplexer). The first driver circuit 25-1 for data transmission, may comprise a first MOS transistor N1 having a drain coupled to the split bus CB via the node ND1 and a local bus LB1, having a grounded source and a gate coupled to it a first Input signal RD1 receives. A second MOS transistor N2 is also provided which has a drain coupled to the split bus CB via the node ND1 and a grounded source. A third PMOS transistor P1 is provided which has a drain coupled to the split bus CB via the node ND1 and a source coupled to a supply voltage (eg, Vdd). A first sorter / multiplexer S11 is provided which selects one of the first inputs and selects a second input according to a status of a first read control signal RC11. The first sorter S11 has an output which is connected to a gate terminal of the third PMOS transistor P1. This first read control signal RC12 may correspond to the externally applied read enable signal RE1 generated by the timing control 220 provided. A second sorter / multiplexer S12 is also provided, which selects one of third inputs FCDR1 and selects a fourth input according to a status of the second read control signal RC12, which respectively correspond to the applied read enable signal RE1. This second sorter S12 has an output coupled to the gate of the second MOS transistor N2.

In the 7A For example, the signal RD1 may be considered as a readout data signal and the signal FCDR1 may be considered as a soft error signal indicating a locked or unlocked status of an internal clock. The first and second MOS transistors N1 and N2 may be n-channel MOS field effect transistors, and the third MOS transistor P1 may be a p-channel MOS field effect transistor. In addition, in the case that the second input of the first sorter S11 is set to a first logic level (eg, a logic 1 = Vdd), the fourth input to the second sorter S12 may be set to a second logic level (e.g. B. a logical 0 = ground), however, alternative fixed states may be used in accordance with further embodiments of the invention.

A second driver circuit 25-2 for data transmission may include a first MOS transistor N1 having a drain coupled to the split bus CB via the node ND2 and a local bus LB2, having a grounded source and having a gate coupled to a direct input signal RD2 to recieve. A second MOS transistor N2 is also provided, having a drain coupled to the split bus CB via the node ND2, and a grounded source. A third PMOS transistor P1 is provided having a drain coupled to the split bus CB via node ND2 and a source coupled to a supply voltage (eg, Vdd). A first sorter / multiplexer S21 is provided which selects one of the first inputs and selects a second input according to a state of a read control signal RC21. The first sorter S21 has an output coupled to a gate terminal of the third PMOS transistor P1. This read control signal RC21 may correspond to the externally applied read enable signal RE1 generated by the timing control unit 220 provided. A second sorter / multiplexer S22 is also provided which selects one of third inputs FCDR2 and selects a fourth input according to a state of the read control signal RC22 corresponding to the applied read enable signal RE1. This second sorter S22 has an output coupled to the gate of the second MOS transistor N2. In the 7A For example, signal RD2 may be considered a readout data signal, and signal FCDR2 may be considered a soft error signal indicating a locked or unlocked state of an internal clock.

The operation of the multi-function driver circuit of 7A will now be described. Each of the read control signals RC11, RC12, RC21, RC22, the selected terminals of the sorters / multiplexers S11, S12, S21, S22 in the first and second drivers 25-1 . 25-2 can be disabled, respectively, during a monitor mode of operation, and can be independently enabled one at a time during a data read mode of operation. When the read control signals RC11, RC12 are inactivated during a monitoring mode, the first sorter S11 may be in the first driver circuit 25-1 select the second input and thereby pass a high level signal (eg, Vdd) to the gate of the third MOS transistor P1, thereby holding the third MOS transistor P1 in an "off" state. In addition, the second sorter S12 in the first driver circuit 25-1 select the third input and therefore pass a soft error signal to the gate of the second MOS transistor N2. Consequently, when the input signals RD1 and FCDR1 are logically low during the monitoring operation mode, the first and second MOS transistors N1 and N2 may be turned off together with the third MOS transistor P1, allowing the node ND1 (and divided bus CB ) "Weak" on a preloaded Voltage level is maintained by a PMOS pull-up transistor PU1. Thus, in the case that a clock with a clock recovery unit in the first source driver 250-1 is latched (eg, correctly synchronized), the input signals RD1 and FCDR1 have logic low levels, meaning that first data having a logic high level is held at a precharged level on the split bus CB. On the other hand, when the input signal FCDR1 is logic high, the second MOS transistor N2 (regardless of the value of RD1) will be turned on. In this case, a potential of the node ND1 will be pulled down (eg, discharged) to a ground potential level (eg, Gnd), which means that first data having a logic low level will appear on the divided bus CB. As described in more detail below, in the case that a clock of a clock recovery unit is unlocked (for example, not synchronized), the corresponding input signal FCDR1 may have a logic high level, so that the first data having the logical low level is set to the logic low divided bus CB, thereby the unlocked state of the clock in the first source driver 250-1 reflect. In addition, when the first data of a logical low level is provided on the split return channel during a monitor mode, timing control may be performed 220 with the shared receiver 224 therein detect the clock as unlocked, and may provide (or relay) a training clock to a corresponding source driver / drivers. Thus, during the first mode of operation, a lock state signal indicative of a locked / unlocked state of a clock recovery unit in the source driver may be transmitted via the split bus CB.

In contrast, when the read control signals RC11 and RC12 are activated during a data read operation mode (eg, the second operation mode), the first sorter S11 may select the first input (eg, the signal RD1) and it to the gate of the third MOS transistor P1 forward. The third MOS transistor P1 may be on or off according to a logic state of the first input RD1. The first and third MOS transistors N1 and P1 may constitute a CMOS inverter INV. The second selector S12 may also select the fourth input (eg, a logic low level) and pass it to the gate of the second MOS transistor N2. Accordingly, the second MOS transistors N2 can be turned off. Accordingly, when the input signal RD1 is logic low, the first MOS transistor N1 can be turned off while the third MOS transistor P1 can be turned on. This may mean that the node ND1 is driven to a power supply (eg, Vdd) through the PMOS transistor P1 so that second high logic level data may occur on the split bus CB. However, when the input signal RD1 is logic high, the first MOS transistor N1 may be turned on while the third MOS transistor P1 may be turned off. Thereby, the node ND1 will be pulled to a logical 0 voltage level (eg Gnd) because the pull-down strength of the first MOS transistor N1 is greater than the pull-up strength of the PMOS pull-up transistor PU1. Thus, during the data read mode of operation, the shared receiver 224 in the timing control 220 the second data as an inverted version of the first input RD1 of the selected driver (e.g. 25-1 . 25-2 , ..., 25-n ) over the shared bus (eg shared return channel SBC). This second data may be bit error rate (BER) test data, touch panel data, brightness data, temperature data, or other data stored in the corresponding source driver.

The 7B illustrates components of a display driver circuit according to further embodiments of the invention during a first monitor mode of operation when each of the source drivers 250-1 . 250-2 , ..., 250-n receives a corresponding training cycle. These training clocks support the clock synchronization of clock signals in the source driver 250-1 . 250-2 , ..., 250-n , In contrast to the embodiment of 7A becomes the timing control 220 from 7B so illustrated that they are a shared receiver 224 having an input terminal electrically coupled to the split bus (CB) operating as a divided return channel SBC, and having a plurality of transmitters 221-1 . 221-2 , ..., 221-n having. These transmitters are electrically connected to an input bus 210 coupled input terminals and output terminals coupled to the respective signal lines L40, L42, ..., L44, the respective read enable signals RE1, RE2, ..., REn the source drivers 250-1 . 250-2 , ..., 250-n provide. How through the 7B Illustrated are elements of the drivers 25-1 . 25-2 , ..., 25-n from 7A which have been inactive in response to inactive read control signals (eg, RC11, RC12, RC21, RC22, ... = 0) have been omitted from the illustration. Each of the input signals FCDR1, FCDR2,..., Is provided to the NMOS pull-down transistor N2, which means that the divided bus CB is pulled low from a "weakly" precharged logic 1 voltage level when one (or several) of the input signals FCDR1, FCDR2, ..., is set to a logic 1 value to the unlocked state of a clock in a corresponding source driver 250-1 . 250-2 , ..., 250-n to reflect. Maintaining a sustained 0 logic voltage level on the split bus CB during the monitor mode of operation (eg, when RE1, RE2, ..., REn = 0) becomes one delayed generation of a training clock for each of the source drivers until the shared bus CB is pulled back to a logical 1 voltage level. This return to a logic 1 voltage level will occur when all input signals FCDR1, FCDR2, ..., FCDRn are switched to a logic 0 voltage level, thereby causing the NMOS pull-down transistor N2 in each of the drivers 25-1 . 25-2 , ..., 25-n turn off and show that all corresponding clocks in the source drivers ( 250-1 . 250-2 , ..., 250 N ) have been sufficiently trained (eg synchronously).

The 8A illustrated like that with respect to the 7B training clock operation described a data read operation (eg, bit error rate (BER) test data, touch panel data, brightness data, temperature data, etc.) from the second driver 25-2 in the second source driver 250-2 simultaneously with monitoring a state of a clock in the first source driver 250-1 (and other source drivers) can follow. These modes of operation may be achieved by controlling the first source driver 250-1 be achieved with an inactive read enable signal RE1, as inactive read control signals RC11, RC12 in the first source driver 250-1 can be transmitted while simultaneously the second source driver 250-2 be controlled with an active read enable signal RE1, as the active read control signals RC21, RC22 in the second source driver 250-2 can be transmitted. The active read control signal RC21 will enable operation of an inverter (eg, the PMOS pull-up transistor P1 and NMOS pull-down transistor N1) since the read active control signal RC21 passes the input signal RD2 will assist the sorter / multiplexer S21 to the gate terminal of the PMOS transistor P1 (while at the same time holding an NMOS pull-down transistor N2 in an off state by passing a logic zero voltage signal (e.g., Gnd) through the gate Sorter / Multiplexer S22 (not in the 8A shown) is maintained). Accordingly, as long as the input signal FCDR1 in the first source driver 250-1 is held at a logic 0 voltage level to thereby reflect a current synchronization of the clock, the input terminal of the shared receiver 224 in the timing control 220 with read data from the second source driver 250-2 (eg CB = / RD2).

8B - 8C are timing diagrams showing the timing of the above-described operations in relation to the 8A during which read data (/ RD2) from the second source driver 250-2 on the shared return channel SBC (eg, the shared bus CB) in response to an active read enable signal RE2. As the 8B shows are the source drivers 250-1 . 250-2 , ..., 250-n responsive to respective training clocks during a monitor mode of operation when the read enable signals RE1, RE2, ..., REn are held at a logic 0 voltage level (eg, inactive). In response to these training clocks, internal clock signals (eg, PLL clock signals) are synchronized to the source driver. Once the last of the internal clock signals is synchronized, the divided return channel SBC switches from a logic 0 voltage level to a logical 1 voltage level due to the pull-up of the PMOS pull-up transistor PU1 and the fact that all input signals RD1, RD2, ..., RDN, FCDR1, FCDR2, ..., FCDRn have been set at a logic 0 voltage level to thereby cause the NMOS pull-down transistors N1 and N2 in the drivers 25-1 . 25-2 , ..., 25-n off. Thereafter, after the assertion of the read enable signal RE2 during the time interval T21, during the time interval T0, a data read operation from the second driver begins 25-2 (eg, from time t1 to time t4). During this data read operation, header information (Start), data (Read_Data) and footer information (End) are provided on the shared return channel SBC at times T1, T2 and T3, respectively. The header and footer information is provided as a relatively short alternating sequence of logical 1 and logical 0 data bits to enable timing control 220 Begin and completion of a valid data read interval (T0), which is associated with the active read enable signal RE2. However, as indicated by the 0-to-1 transition of the signal FCDR1 during the time interval T0 in FIG 8C is shown when a faulty event (eg, ESD overvoltage) occurs, which results in every clock in the source drivers 250-1 . 250-2 , ..., 250-n from synchronization, the persistent logic value 0 on the split return channel SBC during the time interval T0 will properly be invalid data by the timing control 220 (for example due to missing footer information with alternating logical 1 and logical 0 data bits). In response to the missing footer information during the time interval from the time t3 to the time t4, the timing control becomes 220 re-establish a monitor mode of operation during which a previous read enable signal is inactivated (eg, RE1, RE2, ..., REn = 0). During this monitoring mode of operation, corresponding training clocks again become the source drivers 250-1 . 250-2 , ..., 250-n until all clocks are synchronized and the divided return channel SBC is reset to a logical 1 voltage level.

The 9 Fig. 10 is a block diagram schematically showing a display device according to an embodiment of the inventive concept illustrated. Regarding the 9 can be a display device 200 a system control unit 210 , a timing control 220 , a gate driver 240 , a source driver 250 , a gamma voltage generator 260 and a display field 280 exhibit. A power supply 230 can with the system control unit 210 be coupled via a line L12 and may be different voltages P1, P2 and P3 for the display device 200 produce. As will be understood by those skilled in the art, the system controller may 210 the timing control 220 with vertical and horizontal synchronization signals Vsync and Hsync, a clock signal DCLK, a data enable signal DE, data (RGB data values), etc. The power supply 230 may raise or lower a voltage of 3 volts to thereby generate a voltage (s) applied to the display panel 280 be provided. The power supply 230 may perform a DC / DC conversion, and may generate a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, a control power voltage, and a common voltage VCOM.

The display field 280 can be realized as a liquid crystal display device and having a plurality of liquid crystal cells CLC, which are arranged at the intersections of the data lines D1 to Dn and gate lines G1 to Gm. A TFT data transistor (DT) of each liquid crystal cell Clc may provide a corresponding liquid crystal cell Clc with a data signal supplied from a corresponding data line in response to a sense signal from a gate line Gi. A storage capacitor Cst may be formed at each liquid crystal cell Clc. The storage capacitor Cst may be formed between a pixel electrode of the liquid crystal cell Cls and a gate line of a front stage or between a pixel electrode of the liquid crystal cell Cls and a divided electrode line, thereby keeping a voltage of the liquid crystal cell Clc constant.

Alternatively, the display field 280 z. Example, be an organic light-emitting panel or a plasma screen. The timing control 220 may include a gate control signal GCS and a data control signal DCS for controlling the gate driver 240 and the source driver 250 generate by the vertical and horizontal synchronization signals Vsync and Hsync, the clock signal DCLK and the data enable signal DE of the system control unit 210 used. Here, the gate control signal GCS may be for controlling the gate driver 240 a gate start pulse GSP, a gate change clock GSC and a gate output enable signal GOE. The data control signal DCS for controlling the source driver 250 may include a source start pulse SSP, a source switching clock SSC, a source output enable signal SOE, and a polarity signal POL. The timing control 220 can match data (eg RGB data) sent by the system controller 210 be provided to the source driver 250 via a data line L16 output.

The gamma voltage generator 260 can be a gamma voltage with a control voltage from the power supply 230 generate it to the source driver 250 provide. The source driver 250 may perform a control operation in response to the data control signal DCS from the timing controller 220 carry out. The source driver 250 may output different gamma voltage levels according to a gradation value of the data input via a line L16. Consequently, a current value can be determined according to a gradation value of data, and the specified current value can be provided on the data lines D1 to Dn as an analog signal.

The gate driver 240 Sequentially, a sampling pulse, that is, a gate high voltage VGH on the gate lines G1 to Gm in response to the gate control signal GCS from the timing control 220 provide. Accordingly, if a horizontal line of the display panel 280 is selected, an image on the display panel 280 according to applied over a vertical line data are displayed.

In one embodiment, a soft error signal and data read from an internal circuit block may be transmitted backwards over a split return channel, referred to as a shared bus CB between the source driver 250 and the timing control 220 is working. Accordingly, in the case that the system control unit 210 coupled to an external test device, bit error rate test data or read touch panel data read from an internal circuit block are transmitted to the external test device. Further, if the timing control 220 temperature data output from a temperature sensor or brightness data output from a color sensor via the split return channel, then compensation for color positions or brightnesses are suitably controlled.

The 10 FIG. 12 is a block diagram schematically showing a connection relationship between a communication device and a display device of FIG 9 illustrated. Regarding the 10 can be a display device 200 with a communication device 100 be coupled via a system bus L1. The communication device 100 can z. As a DVD player, a computer, a set-top box (STB), a slot machine, a digital camcorder or a processor of a mobile phone. In the case that the display device 200 a monitor is and the communication device 100 is a computer, data provided from the memory of the computer can be displayed on the monitor. The memory can be used to store data information with various data formats, such as: As text, graphics, software code, etc. to save. The memory can z. An electrically erasable programmable flash memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM) called Ovonic Unified Memory (OUM), a resistor RAM (RRAM or ReRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano-floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, an insulator resistance changing memory, or the like.

The computer may include a CPU, a RAM, a user interface, a baseband chipset modem, and a storage system. The CPU of the computer can be constructed as a kind of multi-processor. In this case, it is possible to bypass installation of the RAM in each processor. Accordingly, the RAM may have a multi-port and a shared memory area so as to be shared among processors. Although not shown in the figures, the computer may further include an application chipset, a camera image processor (CIS), a mobile DRAM, etc. A memory and / or memory controller of the memory system may be packaged using various enclosures, such as a personal computer. Package-to-Package (PoP), ball-grid arrays (BGAs), chip-scale packages (CSP), plastic-leaded-chip-carriers (PLCC), plastic-dual-in-line packages (SOIC) In-Waffle Pack, Die-in-Wafer Form, Chip-On-Board (COB), Ceramic Dual-In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP ), Thin-Quad-Flatpack (TQFP), Small-Outline (SOIC), Shrink-Small-Outline-Package (SSOP), Thin-Small-Outline (TSOP), System-In-Package (SIP), Multi-Chip Package (MCP), Wafer Level Fabricated Package (WFP), Wafer Level Processed Stack Package (WSP), etc.

In the 10 can if the communication device 100 as a test device for checking the display device 200 is used, a computer of the communication device 100 Bit error rate check data or touch panel data from a control unit of the display device 100 receive. Furthermore, the computer of the communication device 100 occasionally receive temperature data output from a temperature sensor, or brightness data output from a color sensor.

The 11 is a block diagram that schematically shows an internal circuit of 4 illustrated according to an embodiment of the inventive idea. Regarding the 11 can be an internal circuit 28-1 a circuit 280 which outputs bit error rate (BER) check data, a circuit 282 that produces touch panel data from a touch screen of a panel, a circuit 284 which outputs brightness data from a color sensor and a circuit 286 that outputs temperature data detected by a temperature sensor. When a control unit sends the BER test data from the circuit 280 It can transmit the received data to an external test device. The external test device may perform a BER test on a display device without the use of separate channels. When the control unit releases the touch panel data from the circuit 282 It can transmit the received data to the external test equipment. The external test device may perform a test operation associated with a touch panel on a display device without separate channels.

A touch system that is capable of acting on a front-stage of the circuit 282 can be installed, a touch-screen panel having a plurality of detection units and a signal processing unit that generates touch data in response to a change in capacitance of a sensor unit of the touch-screen panel. A parasitic capacitance component may be present at the detection units of the touch-screen panel. Such parasitic capacitance components may include a horizontal capacitance component generated between detection units and having a vertical capacitance component generated between a sensor unit and a display panel. When the parasitic total capacitance value is large, a capacitance change due to a touch with a finger or a touch pen compared to the parasitic capacitance may be relatively small. If z. For example, as a finger or touch pen approaches a sensor unit, a capacitance value of the sensor unit may increase. Although the sensor unit is a relatively large parasitic capacitance value, its sensitivity can be reduced. A variation of a divided electrode voltage VCOM provided on a cover plate of a display panel may cause generation of a sampling noise of a touch function over a vertical parasitic capacitance. Accordingly, in the case that a check is made (eg, by an external tester) to determine whether a touch system is normal or abnormal, one may Data transmission according to an embodiment of the inventive idea be advantageous. If the control unit the brightness data coming from the circuit 284 output, it is possible to compensate the brightness by comparison with brightness data. When the control unit receives the temperature data from the circuit 286 receives, it is possible to compensate for color coordinates according to a temperature change related to a temperature characteristic table.

The 12 Figure 12 is a block diagram of an application of the inventive idea applied to various display devices. Regarding the 12 can be a display device 200 z. B. on a mobile phone 1310 , an LCD or PDP TV 130 , an ATM device 1330 , an elevator 1340 , a ticket machine 1350 , a PMP 1460 , an e-book 1370 , a navigation system 1380 be applied. For all applications that require a user interface, the display device may 200 have a system with a touch screen. In particular, in the case of a mobile phone, introduction of the touch-screen system may be effective.

The display device 200 may transmit a soft error signal and readout data generated in a split back channel timing control apparatus. Since a control unit of a device receives panel check data and internal data generated by an internal circuit via a split return channel without adding separate lines, appropriate control can be made. For example, when coupled to an external test device, the controller may receive BER test data received from an internal circuit block or touch panel data over the shared return channel for transmission to a tester. Further, it is possible to compensate color coordinates or magnitudes when the control unit receives temperature data output from a temperature sensor or receives brightness data output from a color sensor.

The above-disclosed subject matter is considered to be illustrative and not restrictive and the appended claims are intended to cover all modifications, improvements, and other embodiments that fall within the scope and spirit of the inventive idea. Consequently, to the fullest extent permitted by law, the broadest permissible interpretation of the following claims and their equivalents shall be construed and shall not be limited or limited by the foregoing detailed description. A split return channel, a data transfer mode, a data transfer format may e.g. B. be changed or changed in many ways.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• KR 10-2011-0096478 [0001]
• US 7259742 [0003]
• US 7737939 [0003]

Claims (21)

Display device driver circuit comprising: a first multi-function driver ( 25-1 ) configured to support a first mode of operation in response to a first control signal (RE1) by controlling a bus (CB) having a first output signal (FDATA) having a value indicating a locked or unlocked state of a first one Clock signal therein and further configured to support a second mode of operation in response to a second control signal (RE2) by controlling the bus (CB) at first data not associated with the locked or unlocked state of the first clock signal. The display driver circuit of claim 1, wherein the first data is a multi-bit data stream. A display driver circuit according to claim 1, further comprising: a second multi-function driver ( 25-2 ) configured to support the first mode of operation in response to a third control signal by controlling the bus (BC) with a second output signal (SDATA) having a value indicating a locked or unlocked state of a second clock signal therein and further configured to support the second mode of operation in response to a fourth control signal by controlling the bus (BC) with second data not associated with the locked or unlocked state of the second clock signal. A display driver circuit according to claim 3, wherein said bus (CB) comprises a split back channel signal line (SBC); and wherein the first and second multi-function drivers ( 25-1 . 25-2 ) are configured to control the split back channel signal line (SBC) with the first and second output signals (FDATA, SDATA) respectively during the first mode of operation. A display device driver circuit according to claim 4, wherein said first and second multi-function drivers ( 25-1 . 25-2 ) are electrically coupled to the split return channel signal line (SBC) in a wired OR configuration. A display device driving circuit according to claim 3, wherein the first and second control signals are provided as inactive and active states of a first read enable signal or vice versa, and wherein the third and fourth control signals are provided as inactive and active states of a second read enable signal or vice versa. Display device driver circuit according to claim 4, wherein the first multi-function driver ( 25-1 ) is configured to support the second mode of operation by controlling the split back channel signal line (SBC) with the first data. Display device driver circuit according to claim 5, wherein said first multi-function driver ( 25-1 ) is configured to support the second mode of operation by controlling the split back channel signal line (SBC) with the first data. Display device driver circuit according to claim 7, wherein the first multi-function driver ( 25-1 ) is configured to support the second mode of operation by controlling the split back channel signal line (SBC) with a data stream relating to at least one of touch sensor data, ambient light sensor data, temperature sensor data, and bit error count data. A display device driver circuit according to claim 1, further comprising a timing controller (10). 220 ) configured to issue a first training clock to said first multi-function driver ( 25-1 ) in response to receiving the first output signal (FDATA) having a value indicative of an unlocked state of the first clock signal. A display device driver circuit according to claim 4, further comprising a timing controller (10). 220 configured to transmit the respective first and second training cycles to said first and second multi-function drivers ( 25-1 . 25-2 ) during the first mode of operation in response to detecting a signal on the split back channel signal line (SBC) reflecting an unlocked state of any one of the first and second clock signals. A display device driver circuit comprising: a plurality of drivers ( 25-1 . 25-2 . 25-n ) having respective output terminals electrically coupled to a shared return channel signal line (SBC), the plurality of drivers ( 25-1 . 25-2 . 25-n ) is configured to respond to a first jointly provided supervisory command, which is jointly provided by informing the shared back channel signal line (SBC) of the state of a signal or device therein, and further configured to be customized to one The read command is provided sequentially by controlling the divided back channel signal line (SBC) with respective read data. The display driver circuit of claim 12, further comprising: a receiver electrically coupled to the split back channel signal line (SBC) ( 224 ); and a plurality of transmitters ( 221-1 . 221-2 . 221-n ) configured to receive said plurality of drivers (15) 25-1 . 25-2 . 25-n ) during an operation monitoring mode side by side with the first monitoring command to determine when respective clock signals within said plurality of drivers ( 25-1 . 25-2 . 25-n ) all have been locked. Display device driver circuit according to claim 13, wherein said timing control ( 220 ) is configured to perform a training cycle for said plurality of drivers during the monitoring mode of operation ( 25-1 . 25-2 . 25-n ). A display driver circuit according to claim 12, wherein said plurality of drivers ( 25-1 . 25-2 . 25-n ) is configured to respond to the first monitoring command by controlling the split back channel signal line (SBC) with a signal having a value indicating a locked or unlocked state of a clock signal therein. A display device driver circuit comprising: a plurality of drivers ( 25-1 . 25-2 . 25-n ) having respective first terminals electrically coupled to each other with a split return channel signal line (SBC) through a wired-OR configuration, the plurality of drivers (16) 25-1 . 25-2 . 25-n ) is configured to support a training clock mode of operation by controlling the split back channel signal line (SBC) with a first signal having an unlocked state of at least one clock within said plurality of drivers (12). 25-1 . 25-2 . 25-n ) and further configured to support individual data read modes of operation by controlling the split back channel signal line (SBC) with respective data streams during non-overlapping time intervals. The display driver circuit of claim 16, wherein each of said data streams has equal header and footer bit sequences. A method of operating a display device, comprising: providing a training clock for a first multi-function driver circuit ( 250-1 ) in response to detecting an unlocked state of a first clock generated therein across a shared bus (BC) coupled to an output of the first multi-function driver circuit (BC). 250-1 ) is coupled; Providing a first active read control signal (RC11) for the first multi-function driver circuit ( 250-1 in response to detecting a locked state of the first clock over the shared bus (BC), and transmitting first read data from the first multi-function driver circuit (12). 250-1 ) to the split bus (BC) in response to the first active read control signal (RC11). The method of claim 18, further comprising: providing a training clock for a second multi-function driver circuit ( 250-2 ) in response to detecting an unlocked state of at least one of a second clock generated therein and the first clock via a split bus (BC) coupled to an output of the second multi-function driver circuit (BC). 250-2 ) is coupled; Providing a second active read control signal (RC21) for the second multi-function driver circuit ( 250-2 in response to detecting a locked state of the first and second clocks over the divided bus (BC), and transmitting second data from the second multi-function driver circuit (14). 250-2 ) to the split bus (BC) in response to the second active read control signal (RC21). The method of claim 19, wherein said providing the first active read control signal (RC11) and providing the second active read control signal (RC21) are performed only one at a time. The method of claim 19, wherein said providing a training clock for a second multi-function driver circuit ( 250-2 ) providing respectively first and second training clocks for the first and second multi-function driver circuits ( 250-1 . 250-1 ) having.

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