DE102012105764A1 - Housing stack structure for wireless mobile phone, has intermediate housing terminals to transfer data signals and address/control signals and to provide power supply voltage for address/control circuit and data circuit, respectively - Google Patents

Abstract

The structure (100a) has upper and lower housings (105U, 105L) comprising upper and lower housing substrates (110U, 110L) and upper and lower semiconductor devices (150U, 150L) e.g. dynamic RAM and microprocessor, respectively. The lower housing is coupled with the upper housing by a set of first, second, third and fourth intermediate housing terminals (190A, 190B). The first and second terminals transfer data signals and address/control signals, respectively. The third and fourth terminals provide power supply voltage for an address/control circuit and a data circuit, respectively.

Description

BACKGROUND

1. Technical area

Embodiments of the inventive concept relate to semiconductor devices, package substrates, semiconductor packages, package packaging structures, and electronic systems having functionally asymmetric conductive elements.

2. State of the art

In the field of mobile electronic systems, small, thin and light electronic components have become more and more in demand. This is particularly true for newer mobile devices such as cell phones or tablet PCs, since these devices today have only a small space for their components.

SUMMARY

In one embodiment, a housing stack structure includes an upper housing having an upper housing substrate having a first edge and a second edge opposite the first edge, the upper housing substrate having a first area near the first edge and a second area near the second edge, wherein the upper case has a first upper semiconductor device covering the upper case substrate; a lower housing having a lower housing substrate and a lower semiconductor device, wherein the lower housing is coupled to the upper housing by a plurality of intermediate housing terminals. The inter-chassis terminals include first inter-chassis terminals configured to transmit data signals; second inter-chassis terminals configured to transmit address / control signals; third inter-package terminals configured to provide a power supply for an address / control circuit; fourth inter-package terminals configured to provide a supply reference voltage for a data circuit. A plurality of the first and second intermediate case terminals are arranged in the first area, and a plurality of the third intermediate case terminals are arranged in the second area.

BRIEF DESCRIPTION OF THE FIGURES

The above and other features and advantages of the inventive concepts will become more apparent in light of the more particular description of preferred embodiments of the inventive idea as illustrated in the attached figures in which like reference characters refer to like parts in the several views. The figures are not necessarily to scale, the emphasis instead being on illustrating the principles of inventive ideas. To the figures:

The 1A to 1D 10 are schematic plan views illustrating arrangements of input / output (I / O) elements of semiconductor devices according to some embodiments of the inventive concept;

The 2A to 2D FIG. 12 is a top view schematically illustrating a method of redistributing input / output (I / O) elements of a semiconductor device according to some embodiments of the inventive concept and cross-sectional views along the line II 'of FIG 2A illustrated;

The 3A to 3I FIG. 4 is an exploded perspective view illustrating package stack structures according to various embodiments of the inventive concept; FIG.

The 3J FIG. 11 is a plan view illustrating the package stack structure of FIG 3A illustrated in accordance with an embodiment of the inventive idea;

The 4A and 4B Figure 11 is a side sectional view and longitudinal sectional views of the upper cases according to various embodiments of the inventive concept;

The 5A to 5J are side sectional, longitudinal and partial exploded views of housing stack structures, such. For example, one-chip-system (SOC) or package-on-package (POP) stack structures according to various embodiments of the inventive concept;

The 6A to 6K FIG. 13 is an exploded perspective view of the package stack structures according to various embodiments of the inventive concept; FIG.

The 7A to 7H Fig. 12 are schematic views of the upper cases according to the various embodiments of the inventive idea;

The 8A to 8I Figure 4 is side, longitudinal and partial exploded views of the lower housings according to some embodiments of the inventive concept;

The 9A to 9H FIG. 15 are cross-sectional views of package stacks according to various embodiments of the inventive concept; FIG.

The 10 FIG. 12 is a conceptual plan view illustrating an arrangement of bonding pads of a semiconductor device according to some embodiments of the inventive concept; FIG.

The 11A and 11B 12 are side, longitudinal, and partial exploded views of semiconductor packages according to some embodiments of the inventive concept;

The 12A to 12J 13 are side sectional and longitudinal sectional views of housing stack structures according to various embodiments of the inventive concept;

The 13A to 13D FIG. 12 is schematic side sectional views of the upper cases according to some embodiments of the inventive concept; FIG.

The 14A to 14U Fig. 4 are side sectional and longitudinal sectional views of package stack structures of the various embodiments of the inventive concept;

The 15A to 15D 13 are schematic views of inter-body terminals according to various embodiments of the inventive concept;

The 16A and 16B 13 are schematic views of a package according to some embodiments of the inventive idea, and FIG

The 17 FIG. 12 is a block diagram of an electronic system according to some embodiments of the inventive concept. FIG.

The 18 FIG. 12 is a schematic view of an electronic system using the semiconductor device or package stack structure according to some embodiments of the inventive concept; FIG.

The 19 Fig. 12 is a schematic view of a mobile phone in which the electronic system according to an embodiment of the inventive concept is used;

The 20A FIG. 10 is a block diagram of an exemplary master semiconductor chip according to an embodiment of the inventive concept; FIG.

The 20B FIG. 12 is a block diagram of an exemplary slave semiconductor chip according to another embodiment of the inventive concept; and FIG

The 20C FIG. 12 is a block diagram of an exemplary semiconductor package according to yet another embodiment of the inventive concept.

DETAILED DESCRIPTION

Various exemplary embodiments will now be described in more detail with reference to the accompanying figures, in which some example embodiments are illustrated. These However, inventive idea may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive idea to a person skilled in the art. In the figures, the sizes and relative sizes of layers and regions may be exaggerated for purposes of illustration. The same numbers refer to the same elements throughout.

Embodiments of the inventive concept are described herein with reference to cross-sectional diagrams that are schematic illustrations of idealized embodiments of the inventive idea. As such, deviations from the forms of the representations are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the inventive idea are not to be construed as limited to the particular shapes of areas presented herein, but are to be interpreted as deviations in form, e.g. B. caused by the production. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a portion of a device and are not intended to limit the scope of the inventive idea.

In the present description, like reference numerals may refer to components having the same function. That is, components labeled with the same reference numerals may take different forms.

In the present specification, data signals may refer to electrical signals having effective information transmitted and received between a memory device and a memory controller.

In the present specification, reference voltages (or power supplies) for a data circuit may refer to the maximum voltage Vddq of the data signal, the minimum voltage Vssq thereof, or an intermediate voltage Vrefq required for determining an effective value. The reference voltages for a data circuit may be independently determined in various ways according to the characteristics of a memory device.

In the present specification, address / control signals may refer to signals for controlling information regarding the location of a cell in which information related to a storage device is written and related to operations of the storage device.

In the present specification, reference voltages (or power supplies) for an address / control circuit may refer to the maximum voltages Vdd or minimum voltage Vss of the address / control signals. The reference voltages for the address / control circuit can be independently determined in various ways according to the characteristics of a memory device.

In the present specification, reference voltages (or power supplies) for a data circuit and reference voltages (or power supplies) for an address / control circuit may have different voltage levels and be designed as voltages provided by conductive components that differ from one another.

In the present specification, the terms a first side, a first side surface, and a left side may be interpreted as synonymous with each other. Also, the terms a second page, a second page area, and a right page may be interpreted as synonymous with each other. The first and second sides may be arranged opposite to each other or may be arranged close to each other at right angles. That is, although the first and second sides may be upper and lower sides or left and right sides, the first and second sides may alternatively be upper and left (or right) sides or lower and left (or right) sides. Therefore, the first and second sides or the first and second side surfaces can be considered as different characteristics.

In the present specification, the term "near" may be interpreted as "relatively close to". For example, near a first page may be interpreted as closer to a first page than to a second page.

The 1A to 1D 12 are schematic plan views of arrangements of input / output (I / O) elements (bonding pads) of semiconductor devices according to some embodiments of the inventive concept.

Regarding the 1A may be a semiconductor device 1A According to some embodiments of the inventive idea, first bond pads 11 , second bond islands 12 and fourth bond islands 14 having on a region A1 near a first side (or first edge) S1a of a surface 3A are arranged thereof. The semiconductor device 1A can third bond islands 13 which are disposed on a region B1 thereof near a second side (or second edge) S2a. The semiconductor device 1A According to the present embodiments, functionally asymmetric bonding pads may be used 11 . 12 . 13 and or 14 exhibit. For example, the first and second bonding pads 11, 12 for transmitting signals and the fourth bonding pads 14 for providing power supplies or reference voltages Vddq / Vssq for a data circuit may be arranged asymmetrically on the region A1. In addition, the third bond islands 13 for providing power supplies (or reference voltages) for an address / control circuit to be arranged asymmetrically in the area B1. In the present specification, the term "asymmetry" may be interpreted as "non-equivalent" or non-symmetric, or interpreted relative to a given center axis that divides a planar surface area of a substrate. In addition, asymmetric placement of components may be considered to comprise a concentration of the components over a particular range, e.g. Arranged on a region near the first edge or on a first edge region, or interpreted as disposition of the components in other regions.

The first and second bond islands 11 and 12 may be arranged in at least one column or block or may not be arranged uniformly in the area A1. The region A1 may be near the first side (or the first edge) S1a of the semiconductor device 1A be arranged. In other words, the first and second bond islands 11 and 12 may be functionally asymmetrical near the first side S1a of the semiconductor device 1A be arranged. In the 1 According to an embodiment of the inventive concept and provided that the first side S1a is a left side view, the first and second bonding pads 11 and 12 near the left side of the semiconductor device 1A or functionally asymmetrically disposed on a left half L. The region B1 may be disposed near a second side S2a opposite to the first side S1a. The third Bond Islands 13 may be arranged in at least one discrete column or block, or arranged unevenly in the region B1. In the 1A can, provided that the second side S2a is a right side, the third and fourth bonding islands 13 and 14 near the right side of the semiconductor device 1A or functionally asymmetrically disposed on one or the other side of an imaginary centerline, e.g. B. in a right half R.

However, the present invention is not limited to the above-described arrangements, and other arrangements are also possible. For example, a part of the first and / or second bonding islands 11 . 12 . 14 be arranged in a right half R, while a plurality of the first, second and / or fourth bonding pads 11 . 12 . 14 may be arranged in a left half L or a region near the first side S1a. Also, part of the third Bond Islands 13 in the left half L, while a plurality of the third bonding islands 13 in the right half R can be arranged.

In another embodiment, a plurality of the first bond pads 11 be arranged near the first edge S1a and a plurality of the second bonding pads 12 be arranged near the second edge S2a.

In the 1A For example, an upper side and a lower side may each be designed as a third side (or third edge) and a fourth side (or fourth edge) and vice versa. From another viewpoint, each of the areas A1 and B1 may be any of an upper half T, a lower half B, the left half L, and the right half R of the semiconductor device 1A depending on a direction in which the semiconductor device 1A is arranged, be understood.

In the present description, the term "disposed opposite to each other" may not necessarily refer to opposite directions to face each other or to turn away from each other. The term "oppositely disposed" may not be construed as being in the same direction. If z. For example, when components are close to each other vertically, the "oppositely disposed" components may be located close to each other, or spaced from each other. Accordingly, although top and bottom and left and right sides are usually opposed to each other in the specification, the term "opposite sides" may refer to top and left side, top and right side, bottom and left side or bottom and right side ,

In some embodiments, the fourth bond pads may be 14 be arranged asymmetrically in the area B1 or distributed between the areas A1 and B1.

In terms of the 1A to 1D The present exemplary embodiments described may include the first bond pads 11 Transmit data signals and the second bond pads 12 can transmit address / control signals. The third Bond Islands 13 For example, power supplies (or reference voltages) may be Vdd / Vss for a z. B. in the 20A illustrated address / control circuit 7125 provide. The fourth bond islands 14 For example, power supplies (or reference voltages) may be Vddq / Vssq for a z. B. in the 20A illustrated data circuit 7124 provide.

Since the semiconductor devices 1A to 1D According to some embodiments of the inventive idea, functionally asymmetric bonding pads 11 to 14 The lengths of metal traces of package substrates may be in accordance with the respective semiconductor devices 1A to 1D and decreased according to a deviation between the metal lines as described below when the semiconductor devices 1A to 1D in a housing.

In a symmetrical arrangement, signal bonding pads, e.g. B. Bondinseln for transmitting data signals and bonding pads for transmitting address / control signals of a storage device such. B. a dynamic random access memory (DRAMs) or a non-volatile memory, symmetrically arranged on both sides of a memory device, as shown in the 10 of the present application is shown. In the 10 are Bond Islands 31 for transmitting data signals and bonding islands 33 for transferring address / control signals on both sides of a storage device 21 arranged so that a symmetrical distribution of signal-bonding islands (eg data or address / control), z. B. results in a functionally symmetrical arrangement. In a package-on-package (POP) structure, a memory device may be mounted on a package substrate and electrically coupled to a package substrate. In a functionally symmetrical arrangement, the signal paths in the package substrate coupling the memory device and a logic circuit may be complicated, so that a plurality of package substrate printed circuit board (PCB) layers may be needed. This is especially true when the memory device is stacked on a logic circuit with a control circuit to control the memory device with a POP structure. However, if functionally asymmetric (eg, an asymmetry with respect to the location of the signal pads), arrays of bond pads (as shown, for example, in FIGS 1A to 1D ), the signal pads may be concentrated or disposed on a particular side of the memory device. With this configuration, the lengths of the signal paths required in the package substrates can be significantly reduced and simplified. This is because paths previously divided into plural areas can be accommodated in a single layer, while a layer previously used only for address routing can be omitted and combined with a data signal routing layer or a land design layer. Thus, the number of PCB layers for the package substrate can be reduced. Moreover, when an insulating core layer in a package substrate is replaced with a metal core layer, the metal core layer can be used both as a conductive plane of a package substrate and as a planar ground for a package, thereby reducing the total number of PCB layers of a packaging substrate as will be explained below ,

As described in detail above, the terms "asymmetry," "asymmetric," and "functionally asymmetric" may refer to the location of elements for performing one or more desired functions (such as, for example, transmitting signals or providing reference voltages ), being arranged in a non-symmetrical manner with respect to the device or to the substrate having it.

Accordingly, a signal loss can be reduced, the occurrence of noise can be suppressed, and a signal transmission rate can be increased. In addition, the routing design of the package substrates may be due to the arrangement of the functionally asymmetric bonding pads 11 to 14 be simplified. When the routing design of the package substrates is simplified, the number of metal layers of the package substrate can be reduced. The effects described above will be described in detail later.

Regarding the 1B For example, the semiconductor device 1B According to some embodiments of the inventive idea, first in a region A2a of a surface 3B Of which functionally asymmetrically arranged bonding islands 11 and second in a region A2b of the surface 3B Of which functionally asymmetrically arranged bonding islands 12 exhibit.

Each of the areas A2a and A2b may form a block. In particular, the area A2a may be near a first corner C1 and the area A2b may be near a second corner C2. Third Bond Islands 13 and 14 may be arranged functionally asymmetrically near a third corner C3 or a fourth corner C4 be. The area A2a may be close to a first side S1b and a third side S3b of the semiconductor device 1B be arranged. Assuming that the first side S1b is a left side and the third side S3b is an upper side, the region A2a may be in a left half L and upper half T (eg, an upper left region) of the semiconductor device 1B be arranged. The area A2b may be disposed near the first side S1b and the fourth side S4b while facing a second side S2b and third side S3b of the semiconductor device 1B is arranged. Assuming that the third side S3b is an upper surface and the fourth side S4b is a bottom surface, the region A2b may be in the left half L and a lower half B (eg, at a lower left region) of the semiconductor device 1B be arranged. A region B2 may be close to the second side S2b or right side of the semiconductor device 1B be arranged. That is, the area B2 in a right half R of the semiconductor device 1B can be arranged. The Bond Islands 11 to 14 may be arranged in the form of blocks, rows or columns. In some embodiments, the fourth bond pads may be 14 in a range A2c between the range A2a and the range A2b.

Regarding the 1C For example, the semiconductor device 1C According to one embodiment of the inventive idea, bonding islands 11 to 14 exhibit on a surface 3C thereof are distributed near a first side S1c and a second side S2c opposite to the first side S1c. The Bond Islands 11 to 14 can be arranged in at least one row or column.

The first and second bond islands 11 and 12 may be close to the first side S1c of the semiconductor device 1C be arranged. The first and second bond islands 11 and 12 may be arranged asymmetrically in a left half L. However, some of the first and / or second bonding islands may be 11 and 12 be arranged outside the left half L, while a plurality of the first and / or second bonding islands 11 and 12 are arranged near the first side S1c or the left half L depending on the application. The third Bond Islands 13 may be close to the second side S2c of the semiconductor device 1C be arranged. The third Bond Islands 13 can be arranged asymmetrically in a right half R. However, some of the third Bond Islands can 13 be arranged outside the right half R, while a plurality of the third bonding islands 13 depending on the application near the second side S2c or the right half R is arranged.

Regarding the 1D For example, the semiconductor device 1D According to one embodiment of the inventive idea, bonding islands 1 1 to 14 near a first side S1d of a surface 3D be arranged therefrom. The Bond Islands 11 to 14 can be the first to fourth bond islands 11 to 14 exhibit.

Assuming that the first side S1d is a left side, the plurality (or all) of the bonding pads may be 11 to 14 near the left side S1d (or near the first edge) of the semiconductor device 1D or asymmetrically arranged in the left half L. Alternatively, a plurality (or all) of the bond pads may be 11 to 14 near a right side or the second edge S2d of the semiconductor device 1D or be arranged asymmetrically in the right half R.

Each of the in the 1A to 1D illustrated semiconductor devices 1A to 1D can a storage device such. Dynamic Random Access Memory (DRAM), ReRAM, Magnetoresistive Random Access Memory (MRAM), e.g. A spin-transfer torque (STT) MRAM or a flash memory device.

The 2A to 2D 11 are plan views illustrating a method of redistributing bonding pads of a semiconductor device according to the embodiments of the inventive concept and cross-sectional views along the line II 'of FIG 2A illustrate.

Regarding the 2A may be a semiconductor device 2 according to some embodiments of the inventive idea on a surface thereof distributed bonding islands 15 and Bond Islands 16 exhibit. The Bond Islands 15 and the Bond Islands 16 may each be distributed near a first side S1 and a second side S2. Compared to the 1A to 1D For example, the bond pads distributed near the first side S1 may be 15 first, second and / or fourth bonding islands 11 . 12 . 14 and the bonding pads disposed near the second side S2 16 third bond islands 13 exhibit.

Regarding the 2 B can be a first connection or first chip pad 25 and a second connection or second die pad 26 on a lower structure 20 in a semiconductor production line. Each of the first and second connections 25 and 26 may include a metal that may correspond, for example, to an uppermost metal layer during a wafer processing process. A first insulation layer 30 can be formed around the tops of the first and second joints 25 and 26 expose. First and second connection pads 35 and 36 can each be from the tops of the first and second connections 25 and 26 on a side wall and top of the first insulation layer 30 extend. A cover layer 40 can be the first and second connection pads 35 and 36 partially cover. The cover layer 40 may comprise a polyimide material and / or a dielectric material such as silicon nitride.

Regarding the 2C can be a structuring mask 42 be formed outside the clean room, for example, in a housing production line to the cover layer 40 to cover and the first and second connection pads 35 and 36 uncover, and the redistribution patterns 44 . 45 . 46 and 47 can be formed. The redistribution pattern 44 . 45 . 46 and 47 can redistribute patterns 44 and 47 have, extending laterally from the tips of the connection pads 35 and 36 extend. The structuring mask 42 may comprise photosensitive polyimide. The redistribution pattern 44 . 45 . 46 and 47 may have a metal. Alternatively, the redistribution patterns 44 . 45 . 46 and 47 have a viscous conductive material and are formed using an adhesive or paint process and then cured using a sintering process and / or curing.

Regarding the 2D can be a coating layer 50 be formed to the redistribution pattern 44 and 47 partially uncover, and bond islands 15 and 16 can on the redistribution pattern 44 and 47 be formed. The coating layer 50 and / or the bond islands 15 and 16 can be omitted. That is, some of the redistribution patterns 44 and 47 as the Bond Islands 15 and 16 can serve.

Therefore, the first connection pads or the first die pad 25 electrically with the first bonding islands 15 about the redistribution patterns 44 . 45 . 46 and or 47 be coupled. Likewise, the second connection pads or the second chip support 26 electrically with the second bonding islands 12 about the redistribution patterns 44 . 45 . 46 and or 47 be coupled.

The basis of the 2A to 2D described processes can be performed according to an embodiment of the inventive idea. That is, a method of redistributing bonding pads of a semiconductor device according to the inventive concept may be performed in various ways other than described in the present specification. When performed in the production line as in the present embodiments, the redistribution can be performed in a simpler and less expensive manner than in a wafer production line. For example, the clean room need not be kept as clean as the cleanroom used for the wafer line, and the housing line may require less expensive equipment and cheaper raw and ancillary materials. Likewise, the redistribution patterns 44 and 47 z. B. different shapes than those in the 2D disclosed within the spirit and scope of the present disclosure. For example, the bond islands 15 . 16 with the chip pads 25 . 26 without the first and second connection pads 35 . 36 be coupled.

In some embodiments, the first, second, third and / or fourth bond pads may be 11 . 12 . 13 . 14 using in the 2A - 2D described methods are performed. In other words, those in the 1A - 1D illustrated first, second, third and / or fourth bonding islands 11 . 12 . 13 . 14 Chip pads similar to those in the 2A - 2D illustrated chip pads 25 . 26 ,

The 3A to 3I FIG. 13 is an exploded perspective view of the package stack structures according to various embodiments of the inventive concept. FIG. In the 3A to 3H For example, like components and / or like reference numerals may be construed as components having the same or similar functions. Accordingly, only the main differences between the respective embodiments will be described.

Regarding the 3A and 3B can any of the housing stack structures 100a and 100b According to some embodiments of the inventive idea, an upper housing 105U , a lower case 105L and intermediate housing connections 190A and 190B exhibit. Each of the package stack structures 100a and 100b can also PCB connections 109 on a lower surface of the lower case 105L exhibit.

The upper case 105U may be an upper case substrate 110U and an upper semiconductor device attached thereto 150U exhibit. The upper semiconductor device 150U may comprise a memory device. For example, the upper semiconductor device 150U a DRAM, a static RAM (SRAM), a phase-variable RAM (PRAM), a magnetic RAM (MRAM), a resistance RAM (RRAM), a nonvolatile memory (NVM), a flash memory, an electro-mechanical memory, a carbon nanotube storage and / or various other storage devices have. For the sake of brevity For example, the present embodiment will be described on the assumption that the upper semiconductor device 150U is a DRAM.

Regarding the 3A and 3B For example, the upper semiconductor device 150U Bond Islands 160A with a first property and bond islands 160B having a second property disposed on the surface thereof. The Bond Islands 160A with the first property may be near a left side of the surface of the upper semiconductor device 150U be arranged and the bond islands 160B with the second property may be arranged near a right side thereof. The Bond Islands 160A with the first property can perform a first function. In particular, the bonding islands can 160A with the first characteristic, transmitting or delivering data signals and / or reference voltages (or power supplies) Vddq and Vssq for a data circuit. The Bond Islands 160A with the first property can also serve to fulfill a second function. In particular, the bonding islands can 160A transferred with the first property address / control signals. The Bond Islands 160B with the second property can fulfill a third function. In particular, the bonding islands can 160B with the second characteristic provide reference voltages (or power supplies) Vdd and Vss for an address / control circuit.

As used in the description below, a "first feature" element may refer to an element configured to receive data signals, an address / control signal, a reference voltage (or power supply) for a data circuit, or any other signal or voltage is transmitting or delivering. Likewise, an element having "the second characteristic" may refer to an element configured to transmit or provide a reference voltage (or power supply) for an address / control circuit or any other circuits for desired signals or voltages.

Also, as will be used in the description below, a first function may relate to "transmitting data signals and / or providing reference voltages (or power supplies) for a data circuit". A second function may also refer to "transmitting address / control signals". A third function may relate to "providing reference voltages (or power supplies) for an address / control circuit.

The Bond Islands 160A and 160B The first and second properties may be functionally asymmetric. In particular, the upper semiconductor device 150U or the bonding islands having the first and second characteristics 160A and 160B with respect to the arrangement of the semiconductor devices 1A to 1D and in terms of the 1A to 1D described first to fourth bonding islands 11 to 14 be understood. Accordingly, the bond islands can 160A and 160B having the first and second characteristics, a bottom contact metallization (UBM) for a flip-chip bonding process or wire bonding process. The Bond Islands 160A and 160B with the first and second properties can also by using other technical terms such. "Functional I / O elements" according to their configured function to be performed. The upper semiconductor device 150U can be attached to the upper case substrate 110U be attached by z. B. a die-bond layer 155 is used and covered with an upper impression mass. For reasons of clarity, the upper impression mass is not taken into account.

The upper case substrate 110U can wire solder 170A and 170B having the first and second characteristics on an upper surface thereof and having upper inter-body terminal pads (not shown) on a lower surface thereof. The wire eyes 170A and 170B with the first and second properties can each be with the bond islands 160A and 160B with the first and second characteristics through the wires 175 be electrically coupled. In particular, the Drahtlötaugen 170A with the first property with the bond islands 160A be electrically coupled to the first property while the Drahtlötaugen 170B with the second property with the bond islands 160B can be electrically coupled to the second property. Accordingly, the wire pads can 170A satisfy with the first property the first and / or the second function. In particular, the Drahtlötaugen 170A with the first property, transmitting or delivering data signals and / or reference voltages (or power supplies) for a data circuit. Likewise, the wire eyes 170A transferred with the first property address / control signals. The wire eyes 170B with the second property can fulfill the third function. In particular, the Drahtlötaugen 170B with the second property provide reference voltages (or power supplies) for an address / control circuit.

With reference to the 3A can the wire solder 170A and 170B with the first and second properties functionally asymmetric in accordance with the functionally asymmetric arrangement the Bond Islands 160A and 160B be with the first and second characteristics. For example, the wire lugs 170A and 170B with the first and second properties each near the bonding pads 160A and 160B be arranged with the first and second properties. In other words, the wire pads can 170A with the first property near a left side S1-up (alternatively first side or first edge) of the upper case substrate 110U be arranged while the Drahtlötaugen 170B with the second property near a right side S2-up (alternatively second side or second edge) of the upper case substrate 110U which is located opposite the first page.

Regarding the 3B can the wire solder 170A and 170B with the first and second properties and the bond islands 160A and 160B with the first and second properties at an angle of 90 ° to those in the 3A to be turned around.

Although the 3A and 3B exemplify that the Drahtlötaugen 170A and 170B and the Bond Islands 160A and 160B with the wires 175 coupled, the Drahtlötaugen 170A and 170B and the Bond Islands 160A and 160B in various other forms or species than those in the 3A and 3B be coupled shown. For example, ladder images or through holes such. Silicon via (TSV) can be used around the bond pads 160A and 160B with the wire eyelets 170A and 170B connect to. The upper intermediate case pads (not shown) may be the upper case substrate 110U or the wire eyelets 170A and 170B with the first and second characteristics with inter-body connection pads 190A and 190B electrically couple with the first and second properties, respectively. The upper intermediate housing connection pads will be illustrated in other figures. The upper case substrate 110U may comprise a plurality of successive stacked conductive and non-conductive layers. The conductive and non-conductive layers of the upper package substrate 110U will also be described in more detail with respect to other figures.

The lower case 105L may be a lower case substrate 110L and a lower semiconductor device mounted thereon 150L exhibit.

The lower semiconductor device 150L can a logic device such. B. have a microprocessor (MP). The logic device may be any type of microcontroller (μC), digital signal processor (DSP), or a combination thereof. The logic device may include a processor core (not shown) that includes a floating point processor (FPU), an arithmetic logic unit (ALU), and a digital signal processing core (DSP core), or any combination thereof. The logic module can also have registers (not shown). A memory controller may also be used with the logic device, or the memory controller may be an internal part of the logic device depending on the applications.

The lower semiconductor device 150L can with the lower case substrate 110L using z. B. a flip-chip technology be electrically coupled. The lower semiconductor device 150L can z. B. with the lower housing substrate 105L by a plurality of flip-chip terminals or conductive bumps 120 be electrically coupled. The lower semiconductor device 150L can be attached to the lower case substrate 110L using various methods such. B. the use of a Unterfüllmaterials be appropriate. The underfill material is omitted here for the sake of simplicity, but shown in other figures.

The lower case substrate 110L can lower inter-body connection pads 107 have on a top thereof and on a bottom thereof arranged board connection pads (not shown). The lower intermediate housing connection pads 107 can with the intermediate housing connections 190A and 190B be electrically coupled to the first and second properties. The intermediate housing connections 190A and 190B with the first and second properties may be solder balls, while the lower intermediate-Gehäusungsanschlußlötaugen 107 Ball solder eyes are, which are coupled with the solder balls. The board connection pads of the lower package substrate 110L can via the board connectors 109 be electrically coupled to a module board, a system board or a motherboard of an external device. The lower intermediate housing connection pads 107 and the board connection pads will be illustrated in further detail in further figures. Similarly, the lower housing substrate 110L have a plurality of conductive and non-conductive successive stacked layers. A detailed description of the conductive and non-conductive layers of the lower package substrate 110L will be presented later.

The intermediate housing connections 190A and 190B with the first and second characteristics, the upper case 105U and the lower case 105L couple electrically. The intermediate housing connections 190A and 190B with the first and second properties can z. B. the upper and lower housing 105U and 105L or the upper and lower semiconductor devices 150U and 150L couple electrically. The intermediate housing connections 190A and 190B with the first and second characteristics may be in accordance with the arrangement of the bonding pads 160A and 160B with the first and second properties or the wire pads 170A and 170B be arranged with the first and second properties. For example, the intermediate housing connections 190A and 190B with the first and second properties near one side near the wire pads 170A and 170B be arranged with the first and second properties. In particular, the intermediate housing connections 190A with the first property near a left side (or first side or first edge) near the wire pads 170A be arranged with the first property, while the intermediate housing connections 190B with the second property near a right side (or second side or second edge) near the wire pads 170B may be arranged with the second property. Here, the second side (or the second edge) S2 may be disposed above the first side (or the first edge) S1-above.

In one embodiment, the intermediate housing connections 190A . 190B with the Bond Islands 160A . 160B electrically coupled.

Regarding the 3B can the intermediate housing connections 190A and 190B each with the first and second properties close to the other sides, which are not close to the wire pads 170A and 170B are arranged respectively with the first and second properties. The wire eyes 170A and 170B can z. B. near an upper side and / or lower side of the upper housing substrate 110U be arranged while the intermediate housing connections 190A and 190B with the first and second characteristics near the left and right sides of the upper case substrate 110U can be arranged. In the 3A and 3B For example, the positions of the left, right, top and bottom sides may be interchangeable.

In the present embodiment, the intermediate housing connections 190A perform the first function with the first property. In particular, the intermediate housing connections 190A with the first property, transmitting or delivering data signals and / or reference voltages (or power supplies) for a data circuit. Also, the intermediate housing connections 190A perform the second function with the first property. In particular, the intermediate housing connections 190A transferred with the first property address / control signals.

In some embodiments, the intermediate housing connections 190A first intermediate housing terminals configured to transmit data signals; second inter-chassis terminals configured to transmit address / control signals; fourth inter-package terminals configured to provide power supplies or ground voltages (Vssq / Vddq) for the data circuit. In this embodiment, the first, second and fourth intermediate housing terminals are not numbered one by one.

The intermediate housing connections 190B with the second property can perform the third function. In particular, the intermediate housing connections 190B with the second property provide reference voltages (or power supplies) for an address / control circuit.

In some embodiments, the intermediate housing connections 190B third inter-package terminals configured to provide power supply or ground voltages (Vss / Vdd) to the address / control circuit.

The intermediate housing connections 190A and 190B each with the first and second properties may be arranged asymmetrically close to opposite sides. For example, a plurality (or all) of the intermediate housing connections 190A with the first property, e.g. For example, the first and second intermediate housing terminals discussed above may be disposed near the first side or disposed in a first region near the first side (the first edge) S1-top, while a plurality (or all) of the intermediate housing terminals 190B , z. For example, the third intermediate housing terminals discussed above may be arranged with the second property near the second side, or may be disposed in a second area near the second side (the second edge) S2-up. In some embodiments, the first and second intermediate housing terminals may be disposed exclusively in the first area, and the third intermediate housing terminals may be located exclusively in the second area. The second edge may be opposite the first edge. Alternatively, the intermediate housing connections 190A and 190B with the first and second properties respectively asymmetrical on both Be arranged opposite each other sides. The intermediate housing connections 190A with the first property can z. B. asymmetrically located near the left and / or bottom, while the intermediate housing connections 190B with the second property may be arranged asymmetrically close to the right and / or top.

In some embodiments, a plurality of the fourth intermediate housing terminals are disposed in a region near the first edge S1-above. Alternatively, the fourth inter-housing terminals are arranged exclusively in an area near the first edge S1-above.

In some embodiments, an imaginary boundary line may divide the first and second regions 174 along approximately the center of the upper case substrate 110U extend, as it is in the 3J is shown.

Some of the intermediate housing connections 190B with the second property may be dummies or not formed. Although simplified in the figures for reasons of clarity, the intermediate housing connections 190A and 190B on an underside of the upper case substrate 110U be attached or from the upper housing substrate 110U be separated. Finally, the intermediate housing connections 190A and 190B on the underside of the upper case substrate 110U and on an upper surface of the lower case substrate 110L be upset. The PCB connections 109 can the lower case 105L to electrically couple to a system board or motherboard of an external device. The PCB connections 109 can have solder balls.

The intermediate housing connections illustrated as solder balls in these embodiments 190A and 190B can any other type of electrical connections between the upper and lower housings 105U . 105L be. In one embodiment, the upper housing 105U and the lower case 105L without intermediate housing connections 190A and 190B be coupled.

Regarding the 3C to 3E can any of the housing stack structures 100c to 100e According to some embodiments of the inventive idea, an upper housing 105U , a lower case 105L and intermediate housing connections 190A and 190B exhibit. The upper case 105U For example, an upper semiconductor device mounted on an upper side thereof 150U exhibit. The upper semiconductor device 150U may possibly be any regarding the 1A to 1D described semiconductor devices or their variants or modifications. In the present exemplary embodiments, the upper semiconductor device 150U Bond Islands 160A and 160B having first and second properties which may be arranged asymmetrically in different shapes. The wire eyes 170A and 170B with the first and second properties being the bonding islands 160A and 160B each can be asymmetric on the upper case substrate 110U be arranged. Furthermore, intermediate housing connections 190A and 190B each with the first and second characteristics different in accordance with the arrangement of the wire pads 170A and 170B be arranged with the first and second properties.

Regarding the 3F to 3H can any of the housing stack structures 100f to 100h According to some embodiments of the inventive idea, an upper housing 105U , a lower case 105L and intermediate housing connections 190A and 190B exhibit. The lower case 105L may be a first lower semiconductor device 150L1 and a second lower semiconductor device 150L2 exhibit. The first lower semiconductor device 150L1 can electrically with the second lower semiconductor device 150L2 with inter-chip connections 156 be coupled. The first lower semiconductor device 150L1 may comprise a logic circuit and the second lower semiconductor device 150L2 may have a large I / O memory device. The intermediate chip connections 156 can with the lower case substrate 110L be electrically coupled by lower silicon vias (TSV, not shown). The intermediate chip connections 156 may be asymmetrical in various shapes or positions on the first or second lower semiconductor device 150L1 or 150L2 be arranged. Such as Tie 3F to 3H is shown, the inter-chip connections 156 asymmetric in a left or right half on the first or second lower semiconductor device 150L1 or 150L2 be arranged or evenly arranged.

Regarding the 3I may be a housing stack structure 100i According to one embodiment of the inventive idea, an upper housing 105U , a lower case 105L , upper intermediate housing connections 190AU and 190BU and lower intermediate housing connections 190AL and 190BL exhibit. The in terms of the 3A to 3H described intermediate housing connections 190A and 190B can into the upper intermediate housing connections 190AU and 190BU and the lower intermediate housing connections 190AL and 190BL be classified. The upper intermediate housing connections 190AU and 190BU can be holistically formed and the lower intermediate housing connections 190AL and 190BL may be formed integrally, as illustrated in further attached figures. The inventive idea of 3I Can on each of the in the 3A to 3H illustrated embodiments are applied.

The 4A and 4B 13 are schematic views of upper casings according to the various embodiments of the inventive concept illustrating lateral cross-sectional views of semiconductor memory devices and longitudinal sectional views of package substrates for clarity.

Regarding the 4A can be an upper case 200a according to one embodiment of the inventive idea, one on an upper side of an upper housing substrate 210a applied upper semiconductor device 250 exhibit. The upper semiconductor device 250 can on the upper case substrate 210a with, for example, a die-bonding layer 255 be upset. However, other methods may be used to form the upper semiconductor device 250 on the upper case substrate 210a applied. An upper impression mass 259 may be formed to be the upper semiconductor device 250 surrounds. The upper impression mass 259 may also be an epoxy resin. The upper semiconductor device 250 can be one of those in terms of 1A to 1D described semiconductor devices 1A to 1D or other variations or modifications within the spirit and scope of the present disclosure. The semiconductor device 250 can be one of in conjunction with the 2A - 2D be described semiconductor devices.

As described above, the upper semiconductor device 250 Bond Islands 260A with a first property and bond islands 260B having a second property. Although a single bond pad 260A and a single bond island 260B can be seen in a side view are two bonding islands 260A and two bond islands 260B for better illustration. In addition, the bond islands can 260A with the first property in a region near a first side or the left side of the upper semiconductor device 250 be arranged asymmetrically while the bonding islands 260B are arranged asymmetrically with the second property in a region near a second side or the right side, which may be arranged opposite to the first side thereof. One or more of the Bond Islands 260B with the second property can be a dummy.

The wire eyes 270A with the first property and wire eyelets 270B with the second property can be attached to the upper case substrate 210a be arranged asymmetrically. One or more wire pads 270B with the second property can be a dummy. In particular, the Drahtlötaugen 270A with the first property in a region near a first side S1 (eg, left side) of the upper case substrate 210a be arranged asymmetrically, while the the Drahtlötaugen 270B with the second property may be arranged asymmetrically in a region near a second side S2 (eg, the right side) disposed opposite to the first side S1. The Bond Islands 260A and 260B can each with the wire pads 270A and 270B using z. B. of bonding wires 275 be electrically coupled.

As described above, the bonding pads can 260A with the first property and the wire eyes 270A perform a first function and / or a second function with the first property. The Bond Islands 260A with the first property and the wire eyes 270A with the first property can z. B. data signals, reference voltages (power supplies) for a data circuit and / or address / control signals transmitted or deliver. The Bond Islands 260B with the second feature and the wire pads 270B The second feature may provide reference voltages (or power supplies) for an address / control circuit. In the present embodiment, a dummy can be understood as an element that can not transmit signals.

The upper case substrate 210a may have a plurality of layers. In particular, the upper housing substrate 210a a first insulation layer 231 , a first metal layer 241 , a second insulation layer 232 , an insulation core layer 230 , a third insulation layer 233 , a second metal layer 242 and a fourth insulation layer 234 in a sequential or alternately stacked manner. The first insulation layer 231 , the first metal layer 241 , the second insulation layer 232 , the third insulation layer 233 , the second metal layer 242 and the fourth insulation layer 234 can each be a kind of thin film.

The insulation core layer 230 may be thicker than other layers and may have a stiff material. The insulation core layer 230 can z. As glass, a ceramic material, a plastic or a Have solid material. The insulation core layer 230 can be provided as a type of flat surface and can have holes through which vertical vias 281 and 284 are formed.

Each of the metal layers 241 and 242 can be provided as one of various types of horizontal routes. Instead of a flat plane shape z. B. the metal layers 241 and 242 be divided into small fragments of a flat plane shape or horizontal stretches. Although the 4A a possible form of electrical connection of the metal layers 241 and 242 and the vias 281 to 284 2, the shape of the electrical connection may be of any shape and is not limited to that shown. This concept can be applied to all figures of the present description.

The top intermediate housing connection pads 210A with the first property may be near a first side S1 (left side) of the upper case 200a or the upper case substrate 210a be arranged asymmetrically. In other words, the upper intermediate housing connection pads 210A with the first property in a left half L of the upper case 200a or the upper case substrate 210a be arranged asymmetrically. The top intermediate housing connection pads 210B with the second property may be near a second side S2 (right side) opposite to the first side S1 of the upper housing 200a or the upper case substrate 210a be arranged asymmetrically. In other words, the upper intermediate housing connection pads 210B with the second property asymmetric in a right half R of the upper case 200a or the upper case substrate 210a be arranged. The top intermediate housing connection pads 210A and 210B with the first and second properties, respectively, under the second metal layer 242 be formed and through a bottom of the upper housing substrate 210a be exposed.

The top intermediate housing connection pads 210A with the first property can with the wire solder 270A with the first property through metal layers 241 and 242 and vias 281 and 282 be electrically coupled. Accordingly, the upper intermediate housing connection pads 210A perform the first and second functions with the first property. The top intermediate housing connection pads 210A can z. B. data signals, reference voltages (or power supplies) for a data circuit and / or address / control signals transmitted or deliver.

The top intermediate housing connection pads 210B with the second property can be electrically with wire solder 270B with the second property through the metal layers 241 and 242 and vias 283 and 284 be coupled. Accordingly, the upper intermediate housing connection pads 210B perform a third function with the second property. The top intermediate housing connection pads 210B with the second property can z. B. provide reference voltages (or power supplies) for an address / control circuit. One of the top intermediate chassis connection pads 210B with the second property can be a dummy.

Regarding the 4B can be an upper case 200b according to an embodiment of the inventive idea one on an upper housing substrate 210b applied semiconductor device 250 exhibit. It only differences to the upper case 200a from 4 to be discribed. The upper case substrate 210b can be a first insulation layer 231 , a first metal layer 241 , a second insulation layer 232 , a metal core layer 240 , a third insulation layer 233 , a second metal layer 242 and a fourth insulation layer 234 which are stacked consecutively. The upper case substrate 210b According to an inventive idea, the metal core layer 240 which may be thicker or harder than other layers. The metal core layer 240 can serve as a flat surface for separating element / package reference voltages. In particular, the metal core layer 240 used as a ground voltage with flat surfaces. However, the metal core layer can 240 also z. B. serve essentially conductive components with other functions electrically, such as. B. the first function, the second function or the third function to couple.

To exemplify that the metal core layer 240 for the third function can be used 4B in that the wire pads with the second property 270A 270B , the intermediate housing connection pads 210B with the second property and vias 283a . 283b . 284a and 284b with the second property with the metal core layer 240 are coupled. In contrast, to exemplify that the metal core layer 240 can not be used for the first function and / or the second function, illustrates the 4B that the wire solder 270A with the first feature, the inter-body connection pads 210A with the first property and the vias 281 and 282 with the first property not with the metal core layer 240 are coupled. However, the illustration described above is only an example, and the reverse is also included within the intended scope of the inventive idea.

In the upper cases 200a and 200b According to the embodiments described above, the conductive components 260A . 270A and 210A for the first and second functions in a region near a left half (L) or first side S1 of the upper package substrate 210a and 210b be arranged asymmetrically, so that the track length, which is configured to be the conductive components 260A . 270A and 210A for the first and second functions can be coupled, reduced and a deviation between the routes can be reduced.

Accordingly, the path-like arrangement or design of the metal layers 241 and 242 the upper housing substrates 210a and 210b be simplified, and a caused by a signal path difference deviation of the signal delay can be reduced to improve signal integrity. Also, a ground or voltage transient effect can be enhanced because the metal core layer 240 is used as a plane ground plane or a plane surface configured to provide different reference voltages, and the occurrence of noise can be reduced. Furthermore, the metal layers need 241 and 242 not be used as the planar ground plane or to provide different reference voltages so that the metal layers 241 and 242 can be used more efficiently for forwarding signals. Moreover, as the routing requirements become more complicated, the need for adding another metal layer can be reduced. In other words, since the number of metal layers can be reduced, the overall thickness of the upper package substrates can be reduced 210a and 210b reduced or their increase can be prevented. Of course, the metal core layer 240 partially used to transmit electrical signals. Although the 4B the shape of the metal layers 241 and 242 and the metal core layer 240 to describe a conceptual or virtual shape or electrical connection, the actual shapes are not shown, nor is the inventive idea limited to any particular form. This concept can be applied to all embodiments and figures attached to the present description.

The 5A to 5J 13 are schematic views of the package stack structures according to various embodiments of the inventive concept. The package stack structures may include a storage enclosure and a logic enclosure. The package stack structures will be described in more detail with respect to FIGS 3A to 3I be understood. For the sake of clarity, the 5A to 5J side sectional view, longitudinal section and partial exploded views of the housing stack structures.

Regarding the 5A may be a housing stack structure 300a according to an embodiment of the inventive idea, an upper housing 200a , a lower case 305a and intermediate housing connections 290A and 290B exhibit. The lower case 305a may be a lower case substrate 301 and a lower semiconductor device 350 exhibit. The upper case 200a is in further detail z. B. in relation to the 4A be understood.

The lower case 305a may be the lower semiconductor device 350 on and with the lower housing substrate 301 attached and coupled. In some embodiments, the lower semiconductor device 350 with the lower case substrate 301 , z. B. by a flip-chip method using first and second flip-chip terminals 323 and 324 be coupled. The lower semiconductor device 350 may be a memory controller disposed therein 349 exhibit. The storage control unit 349 may be asymmetric on any side or an area near an edge of the lower semiconductor device 350 be arranged. Like in the 5A can be shown for. B. the memory controller 349 on a left side or an area near a left edge of the lower semiconductor device 350 be arranged. Since the positions of the left and right sides can be exchanged, the memory controller can 349 asymmetric on one side or a portion of the lower semiconductor device 350 be arranged. The first flip-chip connectors 323 can be electrically coupled with and overlaid or near the memory controller 349 while the second flip-chip connectors 324 neither superimposed nor near the memory controller 349 could be. Accordingly, the first flip-chip terminals 323 near a first side S1 (eg, left side) of the lower semiconductor device 350 be arranged while the second flip-chip connectors 324 may be disposed near a second side S2 (eg, right side) located opposite to the first side S1.

The lower case substrate 301 can be a first insulation layer 331 , a first metal layer 341 , a second insulation layer 332 , a second metal layer 342 , a third insulation layer 333 , an insulation core layer 330 , a fourth insulation layer 334 , a third metal layer 343 , a fifth insulation layer 335 , a fourth metal layer 344 and a sixth insulation layer 336 which are stacked consecutively. The insulation core layer 330 may be provided as a kind of flat surface and have holes through which vias are formed vertically. Other components may be provided as a kind of thin film.

In addition, the metal layers can 341 to 344 be provided as one of various types of horizontal routes. Accordingly, instead of a shape of a flat surface, the metal layers may 341 to 344 be divided into small fragments of a flat surface or stretches. Lower 310B with the second property may be on the first metal layer 341 be formed, as in the 5B is shown. The first metal layer 341 Can with the top intermediate housing connection pads 210A and 210B of the upper case 200a through the intermediate housing connections 290A and 290B be electrically coupled.

Lower intermediate housing connection pads 310A and 310B can each come with upper intermediate housing connection pads 210A and 210B (each with the first and second characteristics) through the intermediate housing terminals 290A and 290B be electrically coupled (each with the first and second properties).

The lower intermediate housing connection pads 310A with the first feature can with first flip-chip pads 321 (which suggested this compound, but not explicitly in the 5B is shown) through one of the metal layers 341 - 344 be electrically coupled. The lower intermediate housing connection pads 310A with the first property can z. B. each with the first flip-chip Anschlußlötaugen 321 through the second metal layer 342 be electrically coupled. The first flip-chip connection pads 321 may be arranged such that they the first flip-chip Anschlußlötaugen 323 correspond. That is, the first flip-chip pads 321 may be arranged near an area in which the memory control unit 349 the lower semiconductor device 350 is arranged. Accordingly, the first flip-chip pads can 321 near a left region of the lower semiconductor device 350 be arranged. In other words, the first flip-chip pads can 321 near each of the one side of a region where the lower semiconductor device 350 is arranged on the lower housing substrate 301 be arranged asymmetrically.

In the 5A is illustrated that the first flip-chip pads 321 near the first side S1 of the lower semiconductor device 350 are arranged.

The first flip-chip connection pads 321 can with the lower semiconductor device 350 through the first flip-chip pads 323 be electrically coupled. Therefore, at least one of the bond islands 260A with the first characteristic of the upper semiconductor device 250 , the wire soldering eyes 270A with the first feature, the upper intermediate housing connection pads 210A with the first feature, the intermediate housing connections 290A with the first feature, the lower inter-body connection pads 310A with the first feature, the first flip-chip pads 321 and the first flip-chip connectors 323 be electrically coupled, so that the upper semiconductor device 250 with the memory control unit 349 the lower semiconductor device 350 can be electrically coupled. At least one of the Bond Islands 260B with the second characteristic of the upper semiconductor device 250 , the wire loops 270B with the second feature, the upper intermediate housing connections 210B with the second feature, the intermediate housing connections 290B with the second feature, the lower intermediate housing connections 310B with the second feature and PCB connections 309 can be electrically coupled. The conductive components 260A . 270A . 210A . 290A 310A and with the first property can not directly to the PCB connectors 309 be coupled. However, from the conductive components 260A . 270A . 210A . 290A and 310A with the first feature, components that are configured to provide reference voltages (or power supplies) for a data circuit, directly to the printed circuit board terminals 309 be coupled, if desired. Here can be a direct connection of the components with the PCB connections 309 on a connection of the components with the PCB connections 309 without passing through the lower semiconductor device 350 to get lost. Consequently, the conductive components 260A . 270A . 210A . 290A and 310A with the first property near the first side S1 of the package stack structure 300a be arranged or arranged asymmetrically in a left half L, while the conductive components 260B . 270B . 210B . 290B and 310B with the second property near a second side of the package stack structure 300a may be arranged or arranged asymmetrically in a right half R.

The second flip-chip connection pads 322 may be arranged such that they overlap or the second flip-chip terminals 324 correspond.

The positions of the left and right halves L and R can be exchanged.

A lower underfill material 355 may be between the lower semiconductor device 350 and the lower case substrate 301 be padded to side surfaces of the first and second flip-chip connectors 323 and 324 to surround.

A lower molding compound 359 can on the surface of the lower case substrate 301 be formed to side surfaces of the lower semiconductor device 350 and intermediate housing connections 290A . 290B to surround. The lower molding compound 359 may be a surface of the lower semiconductor device 350 uncover.

Regarding the 5B may be a housing stack structure 300b According to one embodiment of the inventive idea, an upper housing 200a and a lower housing 305b exhibit. The lower case 305b may be a lower case substrate 301b and a lower semiconductor device 350 exhibit. The lower case substrate 301b can be a first insulation layer 331 , a first metal layer 341 , a second insulation layer 332 , a metal core layer 340 , a third insulation layer 333 , a second metal layer 342 , a fourth insulation layer 334 , a third metal layer 343 and a fifth insulation layer 335 which are stacked consecutively. The metal core layer 340 can with at least one of the intermediate housing connections 290A and 290B be electrically coupled to the first and / or second property. The metal core layer 340 can z. B. with one of the intermediate housing connections 290A be electrically coupled to the second property and provide different reference voltages or serve as a flat surface for a reference voltage or ground.

Regarding the 5C may be a housing stack structure 300c According to one embodiment of the inventive idea, an upper housing 200a and a lower housing 305c exhibit. The lower case 305c may be a lower case substrate 301c and a lower semiconductor device 350 exhibit. The lower case substrate 301c can be a first insulation layer 331 , a first metal layer 341 , a second insulation layer 332 , a second metal layer 342 , a third insulation layer 333 , a metal core layer 340 , a fourth insulation layer 334 , a third metal layer 343 and a fifth insulation layer 335 which are stacked consecutively. The metal core layer 340 can with at least one of the intermediate housing connections 290A and 290B be electrically coupled with first and second properties. The metal core layer 340 can z. B. with one of the intermediate housing connections 290 be electrically coupled to the second property and provide different reference voltages or serve as a flat surface for a reference voltage or ground.

Regarding the 5D to 5F can the housing stack structures 300d to 300f According to various embodiments of the inventive idea, the upper housing 200b and the lower case 305a to 305c each have.

Regarding the 5D can the upper case substrate 201b a metal core layer 240 exhibit. Regarding the 5E and 5F can the upper and lower housing substrates 201b and 301b each metal core layers 240 and 340 exhibit. The upper case 200b can in terms of the 4B be understood and the lower case 305a to 305c can in terms of the 5A to 5C be understood. A description of the present embodiments will be described in further detail with respect to FIGS 5A to 5C be understood.

Regarding the 5G to 5J can any of the housing stack structures 300g to 300j According to various embodiments of the inventive idea, an upper housing 200a or 200b and a lower housing 306a . 306b or 306c exhibit. Compared to the lower housings 305a to 305c of the 5A to 5F can any of the lower case 306a to 306c a first lower semiconductor device 350L1 and a second lower semiconductor device 350L2 exhibit. The lower semiconductor device 350L1 can lower silicon vias 367 exhibit. The first and second lower semiconductor devices 350L1 and 350L2 can through inter-chip connections 356 be electrically coupled. The intermediate chip connections 356 can each with the silicon vias (TSV) 357 be electrically coupled. The first lower semiconductor device 350L1 may comprise a logic circuit and the second lower semiconductor device 350L2 may comprise a memory device. The second lower semiconductor device 350L2 can z. B. have a large I / O memory device. That means that each of the lower case 306a to 306c a logic circuit and a memory device, which are electrically coupled together using a flip-chip method.

In reference to the 5G to 5J can the intermediate housing connections 290A and 290B with the first and second characteristics upper intermediate housing connections 290A and 290B and lower intermediate housing connections 290A and 290B each have. As mentioned above, the upper and lower intermediate housing terminals 290A and 290B be holistically trained. According to the inventive idea, the intermediate housing connections 290A and 290B form an intermediate housing connection, z. For example, it can have two or more intermediate housing connections in a holistic manner. Accordingly, the shapes of the intermediate case terminals 290A and 290B in the 5A to 5J matching each other.

Each one based on the 5A to 5J described housing stack structures 300a to 300j may according to the inventive idea conductive components 260A . 270A . 210A . 290A and 310A having the first property, which may be disposed near the first side S1 thereof or may be arranged asymmetrically in the left half L thereof. The conductive components 260A . 270A . 210A . 290A and 310A with the first property may serve to perform a first function and / or a second function. The first function may provide for transmitting or generating data signals and / or reference voltages (or power supplies) for a data circuit. The second function may provide for the transmission of address / control signals.

In reference to the 5A to 5J can any of the housing stack structures 300a to 300j according to the inventive idea conductive components 260B . 270B . 210B . 290B and 310B having the second property, which may be disposed near the second side S2 thereof or may be arranged asymmetrically in the right half R thereof. The conductive components 260B . 270B . 210B . 290B and 310B with the second property can serve to perform a third function. The third function may include transmitting reference voltages for an address / control circuit.

In the inventive idea, the top and bottom semiconductor devices 250 and 350 Data signals and / or address / control signals over some of the conductive components 260A . 270A . 210A . 290A and 310A with the first property, over the first flip-chip pads 321 and via the first flip chip terminals 323 transmit and receive.

In the 5G to 5J can the intermediate housing connections 356 in different ways in relation to the 3E to 3G be arranged. In particular, the intermediate housing connections 356 asymmetric on an area of an upper surface of the lower semiconductor device 350 or arranged substantially on the entire surface. The intermediate chip connections 356 can z. B. according to the arrangement of the other conductive components 260A . 270A . 210A . 290A and 310A be arranged asymmetrically with the first property, or be arranged in an opposite position thereto. The intermediate chip connections 356 may be uniformly disposed on substantially the entire surface of the lower semiconductor device. The arrangement of the inter-chip connections 356 can be determined according to their function. Further, by transmitting different reference voltages Vdd / Vss through the inter-chip terminals 356 gives a shielding effect, the inter-chip connections 356 be arranged generally uniformly or according to the arrangement of the conductive components 260A . 270A . 210A . 290A and 310A be arranged asymmetrically with the first property. If it is intended to transmit data signals, address signals or other oscillatory signals through the inter-chip terminals 356 To transfer, the inter-chip connections 356 be arranged differently according to the type of Signalübetragungs / transport components. According to one embodiment of the inventive idea, the inter-chip connections 356 be arranged asymmetrically in different structures according to their function.

In the case of the package stack structures described above 300a to 300j may be the track-like arrangement or design of the conductive components 260A . 270A . 210A . 290A and 310A with the first feature configured to transmit or deliver data signals, reference voltages (or power supplies) for a data circuit and / or address / control signals, are simplified, and a deviation of the signal delay caused by a difference in the signal path is reduced to improve signal transmission arrival time and thus integrity.

The 6A to 6K FIG. 13 is an exploded perspective view of the package stack structures according to various embodiments of the inventive concept. FIG. In particular, the 6A to 6K a case where an upper case has a plurality of semiconductor devices. In the 6A to 6K For example, like components and / or like reference numerals may be construed as components having the same or similar functions. Accordingly, only the main differences between the respective embodiments will be described.

Regarding the 6A may be a housing stack structure 400a According to one embodiment of the inventive idea, an upper housing 405U , a lower case 405L and intermediate housing connections 490A and 490B exhibit.

The upper case 405U may include a plurality of upper semiconductor devices mounted on an upper side thereof 451 and 452 exhibit. For the sake of brevity, it is assumed that the upper case 405U both upper semiconductor devices 451 and 452 having. However, it may be obvious that the upper housing 405 can have more than two semiconductor devices. Each of the upper semiconductor devices 451 and 452 may be any of the semiconductor devices illustrated in the attached various figures. The semiconductor devices may, for. B. in the 20A shown master semiconductor chips or z. B. in the 20C be shown slave semiconductor chips.

That in other embodiments (e.g. 6B - 6J ) used upper case 405 may also have more than two semiconductor devices mounted thereon. In addition, upper semiconductor devices 451 and 452 of the 6B - 6J also in the 20A illustrated master semiconductor chip or in the 20C be illustrated slave semiconductor chips.

According to one aspect of the present disclosure, both upper semiconductor devices 451 . 452 be the same device. Also, one of the two top semiconductor devices 451 . 452 a DRAM and the other a non-volatile memory such. B. a flash memory.

Regarding the 6A can in a plan view, the upper housing 405U a first upper semiconductor device 451 and a second upper semiconductor device 452 have, which can be rotated by an angle of 90 ° to each other. The upper semiconductor devices 451 and 452 can first bond islands 461A and 462A both having a first property and second bond pads 461b and 462b both having a second property. As described above, the first bonding pads 461A and 462A serve with the first property to perform the first function and / or the second function, and the second bonding islands 461b and 462b with the second property can serve to perform the third function.

The wire eyes 471A and 472A with the first property may be near two sides of the upper case substrate 410U be arranged. In the 6A it is shown that the two sides are left sides and bottom sides. The wire eyes 471B and 472B with the second feature can be near the other sides of the upper case substrate 410U be arranged. The wire eyes 471A and 472A with the first property can be close to each other and with the bond islands 461A and 462A be electrically coupled to the first property. The wire eyes 471B and 472B with the second property can be close to each other and with the bond islands 461b and 462b be electrically coupled to the second property. More specifically, the wire pads 471A and 472A with the first property primary wire solder 471A with the first property and secondary wire eyelets 472A having the first property. The primary wire eyelets 471A with the first property can with the bond islands 461A with the first characteristic of the first upper semiconductor device 451 be electrically coupled. The second wire pads 472A with the first property can with the bond islands 462A with the first characteristic of the second upper semiconductor device 452 be electrically coupled. The wire eyes 471B and 472B with the second property can be in primary wire solder 471B and secondary wire pads 472B be split. The primary wire eyelets 471B with the second property can with the bond islands 461B with the second characteristic of the first upper semiconductor device 451 be electrically coupled. The secondary wire eyes 472B with the second property can with the bond islands 462b with the second characteristic of the second upper semiconductor device 452 be electrically coupled. The wire eyes 471A . 471B . 472A and 472B with the first and second characteristics can each with the intermediate housing connections 490A and 490E with the first and second properties by z. B. internal signal routing structures of the upper housing substrate 410U be electrically coupled.

Regarding the 6B to 6E can the upper case 405U each of the package stack structures 400b to 400e According to the embodiments of the inventive concept, a plurality of upper semiconductor devices arranged in different shapes 451 and 452 exhibit.

Regarding the 6B and 6C can the upper semiconductor devices 451 and 452 relative to a centerline of the package substrate 410U be arranged symmetrically. Regarding the 6B can the bond islands 461A and 462A with the first property and the wire eyes 471A and 472A with the first property closer to an outer portion of the upper case substrate 410U be arranged. The Bond Islands 461B and 462B with the second feature and the wire pads 471B and 472B with the second property may be closer to the center of the upper case substrate 410U be arranged. With reference to the 6C can the bond islands 461A and 462A with the first property and the wire eyes 471A and 472A with the first property closer to the center of the upper case substrate 410U be arranged while the bond islands 461B and 462B with the second feature and the wire pads 471B and 472B with the second property closer to the outer portion of the upper case substrate 410U can be arranged.

Regarding the 6D and 6E can the upper semiconductor devices 451 and 452 be arranged parallel to each other. With reference to the 6D can the upper semiconductor devices 451 and 452 be arranged in a longitudinal direction parallel to each other. With reference to the 6E can the upper semiconductor devices 451 and 452 alternatively be arranged in a width direction parallel to each other.

Regarding the 6F can, if you put them with the case stacking structure 400e from 6E compares, an upper case 405U a housing stack structure 400f According to an embodiment of the inventive idea, a plurality of upper semiconductor devices 451 and 452 on an upper case substrate 410 be arranged parallel to each other in a width direction. The upper semiconductor device 451 of the 6F is at an angle of 180 ° with respect to in the 6E illustrated upper semiconductor device 451 turned.

Regarding the 6G can be an upper case 405U a housing stack structure 400g According to an embodiment of the inventive concept, a plurality of vertically stacked top semiconductor devices 451 and 452 exhibit.

A lower case 405L is under the upper case 405U arranged. The lower case 405L has a lower housing substrate 410L and a lower semiconductor device 450 on. In some embodiments, the lower semiconductor device 450 a memory controller 477 near a first edge S1g (or a first region adjacent to the first edge S1g) of the upper case substrate 410U on. A single signal channel can be between the bonding pads 461A . 462A the first and second upper semiconductor devices 451 . 452 and the memory controller 477 be formed to the first and second upper semiconductor devices 451 . 452 to steer together.

In some embodiments, a longitudinal axis of the second upper semiconductor device 452 substantially parallel to a longitudinal axis of the first upper semiconductor device 451 be aligned.

In some embodiments, each of the bond pads 461A . 462A first bond pads configured to transmit data signals, second bond pads configured to transmit address / control signals, and fourth bond pads configured to provide power supplies for data transfer. A plurality (or all) of the first, second, and / or third bond pads of the bond pads 461A . 462A the first and second upper semiconductor devices 451 . 452 may be near the first region of the upper case substrate 410U be arranged.

Also, the bond islands can 461 . 462B third bonding pads configured to provide power supplies to the address / control circuitry. A plurality (or all) of the third bond pads of the bond pads 461B . 462B the first and second upper semiconductor devices 451 . 452 may be near the second area of the upper case substrate 410U be arranged opposite the first area.

Regarding the 6H can be an upper case 405U a housing stack structure 400h According to an embodiment of the inventive idea, a plurality of upper semiconductor devices 451 and 452 which are stacked in a staggered manner, one above the other, to form a staircase-like configuration.

Regarding the 6I if you can talk to them 6H compares upper semiconductor devices 451 and 452 each bond islands 461 and 462 have, which are arranged near one side thereof. The upper in the 6G to 6I illustrated semiconductor devices 451 and 452 can be rotated by an angle of 90 ° to each other, as it is in the 6A is shown.

Regarding the 6J can be an upper case 405U a housing stack structure 400j According to an embodiment of the inventive idea, a plurality of upper semiconductor devices 451 and 452 have, which are stacked one above the other at right angles. The forms and arrangements of the upper in the 6J illustrated semiconductor devices 451 and 452 can in terms of the 6A and 6G to 6I to be better understood.

In some embodiments, the upper housing substrate 410U a third edge S3j and a fourth edge S4j opposite to the third edge S3j, each of which is disposed between the first edge S1j and the second edge S2j. A plurality (or all) of the first and second bonding pads of the second upper semiconductor device 452 are near the third edge S3j and a plurality (or all) of the third bonding pads of the second upper semiconductor device 452 are arranged near the fourth edge S4j.

In some embodiments, the lower semiconductor device 450 one near the first edge of the upper case substrate 410U arranged first memory control unit 447 and one near the third edge S3g of the upper case substrate 410U arranged second memory control unit 448 exhibit. According to an embodiment, a first signal channel (not shown) may be interposed between the first and second bond pads of the first upper semiconductor device 451 and the first memory controller 447 be formed around the first upper semiconductor device 451 and a second signal channel (not shown) may be interposed between the first and second bond pads of the second upper semiconductor device 452 and the second memory controller 448 be formed around the second upper semiconductor device 452 to control. In this way, a plurality of signal channels are interposed between the first and second upper semiconductor devices 451 . 452 and the lower semiconductor device 450 educated.

In some embodiments, the lower semiconductor device 450 with the lower semiconductor substrate 410L electrically coupled to conductive bumps associated with the first and second memory controllers 447 . 448 can be electrically coupled.

In some embodiments, the first and second top semiconductor devices are 451 . 452 DRAMs and the lower semiconductor device 450 is a logic circuit.

In some embodiments, a longitudinal axis of the second upper semiconductor device 452 at right angles with respect to a longitudinal axis of the first upper semiconductor device 451 arranged.

Regarding the 6K may be a housing stack structure 400k According to an embodiment of the inventive concept, a further on a lower semiconductor device 450 having deposited semiconductor device stack. The semiconductor device stack 453 may have a large I / O memory device. In particular, intermediate chip connections 456 on the surface of the lower semiconductor device 450 be arranged. The intermediate chip connections 456 may not be uniform, not equal, or asymmetric on both sides of the surface of the lower semiconductor device 450 be arranged. However, the inter-chip connections can 456 in one of the 3E to 3G be formed forms shown. The lower semiconductor device 450 and the semiconductor device stack 453 can interconnect through the inter-chip connectors 456 be electrically coupled.

Each of the in the 6A to 6K illustrated housing stack structures 400a to 400k According to various embodiments of the inventive concept, a plurality of upper semiconductor devices 451 and 452 and may further include the intermediate housing terminals 490A and 490B having the first and second properties. The intermediate housing connections 490A and 490B may be asymmetric in a left or right half of the package stack structures 400a to 400k be arranged. The intermediate housing connections 490A and 490B can each upper intermediate housing connections 490AU and 490BU and lower intermediate housing connections 490AL and 490BL exhibit. The inventive idea will be described in more detail with reference to further figures.

The 7A to 7G FIG. 12 are schematic views of the upper cases according to various embodiments of the inventive concept. FIG. For clarity, the show 7A to 7G Side cross-sectional views of semiconductor devices 551 and 552 with bonding wires 575 and schematic longitudinal sectional views of housing substrates 501 to 501h , As in the 6A or 6J one of the semiconductor devices can be represented 551 and 552 be rotated at an angle of 90 ° from the other and horizontally arranged or stacked. However, in the 7A to 7G the semiconductor devices 551 and 552 for simplicity, arranged parallel to one another, similar to the arrangements of the semiconductor devices 451 . 452 as it is in the 6B is shown. A die-bonding layer 555 and a upper molding compound (not shown for simplicity) may be formed. As described above, the term "primary" may refer to conductive structures associated with the first semiconductor device 551 are electrically coupled, and the term "secondary" may refer to conductive structures associated with the second semiconductor device 552 are electrically coupled.

The primary conductive structures having a first property may e.g. B. primary bond islands 561A with the first property, primary wire solder 571A with the first feature and primary upper inter-body connection pads 510A having the first property. The primary conductive structures having a second property may be primary bond pads 561B with the second property, primary wire solder 571E with the second feature and primary upper inter-body connection pads 510B having the second property.

Secondary with the second semiconductor device 552 coupled conductive structures with the first property may be secondary bond pads 562A with the first property, secondary wire eyelets 572A with the first feature and secondary upper intermediate housing connection pads 510A having the first property.

Secondary conductive structures having the second property may also be secondary bonding pads 562B with the second property, secondary wire solder 572B with the second feature and secondary upper intermediate housing connection pads 510E having the second property.

In the present embodiment, the upper intermediate case terminal pads are 510A with the first property not subdivided into primary and secondary top intermediate housing connection pads. In addition, the upper intermediate housing connection pads 510E with the second feature not subdivided into primary and secondary top intermediate housing connection pads.

As described above, conductive structures having the first property may satisfy the first function and / or the second function, and conductive structures having the second characteristic may satisfy the third function. The first function may include transmitting or providing data signals and / or reference voltages for a data circuit. The second function may include transmitting address / control signals. The third function may include transmitting reference voltages for an address / control circuit.

An upper case 500a For example, according to various embodiments of the inventive concept, a plurality of semiconductor devices 551 and 552 horizontally as shown, or vertically on each other (not shown) on a package substrate 501 be stacked. The semiconductor devices 551 and 552 can bond islands 561A . 562A be with a first property. The semiconductor devices 551 and 552 can also bond islands 561B . 562B having a second property. Drahtlötaugen 571A . 572A with the first property can be on the package substrate 501 be arranged. Drahtlötaugen 571B . 572B with the second property may also be on the package substrate 501 be arranged. The wire eyes 571A . 571B . 572A and 572B with the first and second characteristics may be in primary with a first upper semiconductor device 551 electrically coupled wire pads and secondary with a second upper semiconductor device 552 be divided electrically coupled wire solder.

The wire eyes 571A and 572A with the first feature can with the inter-body connection pads 510A be electrically coupled to the first property and the wire pads 571B and 572B with the second feature can with the inter-housing connection pads 510E be electrically coupled to the second property.

According to one aspect of the present disclosure, when the functionally asymmetric bonding pads discussed above may be used 561A . 562A like in the 7A are arranged, the signal path between the bonding pads 561A . 562A and the wire pads 571A . 572A (or other connecting elements and / or the memory control unit) be designed shorter than in conventional arrangements. The housing substrate 501 can be a first insulation layer 531 , a first metal layer 541 , a second insulation layer 532 , a second metal layer 542 , a third insulation layer 533 , an insulation core layer 530 , a fourth insulation layer 534 , a third metal layer 543 , a fifth insulation layer 534 , a fourth metal layer 544 and a sixth insulation layer 536 which are stacked consecutively.

The vias 581a . 581b . 582a . 582b . 582c . 583a . 583b . 586a . 586b . 587a . 587b . 587c and 588 can metal layers 541 to 544 couple vertically and penetrate the second to fifth insulation layers 532 to 535 and the insulating core layer 530 , Although it is shown that the vias 581a . 581b . 582a . 582b . 582c . 583a . 583b . 586a . 586b . 587a . 587b . 587c and 588 are arranged asymmetrically, the vias 581a . 581b . 582a . 582b . 582c . 583a . 583b . 586a . 586B . 587a . 587b . 587c and 588 not be arranged asymmetrically, but they can be arranged at various other locations and take various other forms. In the 7A are the vias 581a . 581b . 582a . 582b . 582c . 583a . 583b . 586a . 586b . 587a . 587b . 587c and 588 for a conceptual description of the electrical connection.

In the present embodiment, the inter-housing terminal pads 510A with the first property near a first side S1 (or a first edge) of the package substrate 501 be arranged. In the 7A For example, the first side S1 may be a left side. Accordingly, the intermediate housing connection pads 510A with the first property in a left half L of the package substrate 501 be arranged. The intermediate housing connection pads 510E with the second property may be near a second side S2 (or a second edge) opposite to the first side S1 of the package substrate 501 be arranged. In the 7A For example, the second side S2 may be a right side. The intermediate housing connection pads 510E with the second property may be in a right half R of the package substrate 501 be arranged.

Regarding the 7B may be a case substrate 501b an upper case 500b According to one embodiment of the inventive idea, a first insulating layer 531 , a first metal layer 541 , a second insulation layer 532 , a second metal layer 542 , a third insulation layer 533 a metal core layer 540 , a fourth insulation layer 534 , a third metal layer 543 and a fifth insulation layer 535 which are stacked in a sequential or alternating manner.

Some of the conductive components 561B . 562B . 572B and 571B and 510E with the second property can not be electrically connected to the metal core layer 540 be coupled. For example, one or more metal core layers, such as the metal core layer 540 , used to provide different reference voltages (or power supplies). In addition, the metal core layer 540 be used as a flat surface for a reference voltage or different reference voltages. In one example, the metal core layer 540 separately or at the same time as the wire pads 571B and 572B with the second property through different vias 583a . 583b . 588a and 588b be coupled.

Regarding the 7C may be a case substrate 501c an upper case 500c According to one embodiment of the inventive idea, a first insulating layer 531 , a first metal layer 541 , a second insulation layer 532 , a metal core layer 540 , a third insulation layer 533 , a second metal layer 542 , a fourth insulation layer 534 , a third metal layer 543 and a fifth insulation layer 535 which are stacked consecutively. A description of the upper case 500c can in terms of the 7B be understood.

Regarding the 7D may be a case substrate 501d an upper case 500d According to one embodiment of the inventive idea, a first insulating layer 531 , a first metal layer 541 , a second insulation layer 532 a metal core layer 540 , a third insulation layer 533 , a second metal layer 542 and a third insulation layer 534 which are stacked consecutively. The first metal layer 541 can z. On the metal core layer 540 be stacked, and the second metal layer 542 can under the metal core layer 540 be stacked. That is, the first and second metal layers 541 and 542 on each side of the metal core layer 540 can be arranged.

In the present embodiment, the primary wire pads 571A with the first property with the inter-body connection pads 510A with the first property using the first metal layer 541 be electrically coupled, and the secondary Drahtlötaugen 572A with the first feature can with the inter-body connection pads 510A with the first property through the second metal layer 542 be electrically coupled.

The metal core layer 540 Can work with some of the primary and secondary wire pads 571B and 572B with the second feature and the intermediate intermediate housing connection pads 510B be electrically coupled to the second property.

Regarding the 7E can be an upper case 500e According to an embodiment of the inventive idea, a plurality of upper semiconductor devices 551 to 554 show through the upper TSVs 561va and 561vb are electrically coupled together. The upper TSVs 561va with the first property, data signals; Reference voltages (or power supplies) for a data circuit; and / or transmit / provide address / control signals. The upper TSVs 561vb The second feature may provide reference voltages (or power supplies) for an address / control circuit and / or element / package reference voltages. The upper case substrate 501e can via connections 271va having the first property associated with the upper TSVs 561va can be electrically coupled to the first property, and via connections 271vb having the second property associated with the upper TSVs 561vb can be electrically coupled to the second property.

The upper TSVs 561va with the first feature and the via connections 571va with the first property, in a left half L, each of the semiconductor devices 551 to 554 or the upper case 500e be arranged asymmetrically or arranged near a first side S1 thereof. The upper TSVs 561vb with the second feature and the via connections 571vb with the second property, in a right half R, each of the semiconductor devices 551 to 554 or the upper case 500e be arranged asymmetrically or arranged near a second side S2 thereof. In the figures, a die-bonding layer and an impression compound are omitted. Any suitable encapsulation or encapsulation material may be used within the spirit and scope of the inventive idea.

The via connections 571va with the first feature can with the inter-body connection pads 510A be electrically coupled to the first property, and the via connections 571vb with the second feature can with the inter-housing connection pads 510B be electrically coupled to the second property. Accordingly, the intermediate housing connection pads 510A with the first property near the first side S1 of the upper housing 500e be arranged or arranged asymmetrically in the left half L. The intermediate housing connection pads 510E with the second property may be near the second side S2 of the upper housing 500e or in the right half R thereof may be arranged asymmetrically.

Regarding the 7F can be an upper case 500f According to an embodiment of the inventive idea, a plurality of upper semiconductor devices 551 and 552 be stacked consecutively. Since the present embodiment can be fully understood with reference to other figures, a detailed description thereof will be omitted. In the 7F are the semiconductor devices 551 and 552 spatially separated from each other without intermediate adhesive layer. In practice, however, the semiconductor device 552 on the semiconductor device 551 with an adhesive layer (not shown) stacked therebetween.

Regarding the 7G can be an upper case 500h According to an embodiment of the inventive idea, a plurality of upper semiconductor devices 551 to 554 which are interconnected by upper TSVs 561va . 561vb . 562va and 562vb are electrically coupled. A detailed description of the present embodiment may be made with reference to FIGS 7F be understood.

Regarding the 7H can be an upper case 500g According to an embodiment of the inventive idea, a plurality of upper semiconductor devices 551 and 552 have, which are stacked in a staircase shape. A stack shape of the upper semiconductor devices 551 and 552 can be understood according to the present embodiment in further detail with respect to other figures of the present description.

With reference to the 7B to 7H can the metal layers 541 to 543 and the metal core layer 540 According to various embodiments of the inventive idea can be used in various ways, as shown in Table 1. The positions of the metal layers 541 to 543 can be exchangeable. In addition, the metal layers 541 to 543 and the metal core layer 540 be used differently than the examples proposed in Table 1 in various ways. [Table 1] First metal layer Second metal layer Third metal layer Metal core layer First example Transmission of data signal and reference voltages for a data signal of the first device / transmission of address / control signals of the first device Transmission of data signal and reference voltages of the second device / transmission of address / control signals of the second device Transmission of other signals Transmission of element / chassis reference voltage / plane area for ground Second example No use Third example Transmitting data signal and reference voltages for a data signal from first and second devices Transmission of address / control signals from first and second devices Transmission of other signals Transmission of element / chassis reference voltage / plane area for ground Fourth example No use Fifth example Transmission of data signal and reference voltages for a data signal of a first device / transmission of address / control signals of a second device Transmission of data signal and reference voltages for a data signal of a second device / transmission of address / control signals of a first device Transmission of other signals Transmission of element / chassis reference voltage / plane area for ground Sixth example No use

The 8A to 8I 12 are cross-sectional views, longitudinal sectional views and partial exploded views of lower housings according to some embodiments of the inventive concept.

Regarding the 8A can a lower case 600a According to one embodiment of the inventive idea, a lower housing substrate 601 and a lower semiconductor device 650 which are on the lower housing substrate 610a is arranged.

The lower case substrate 601 can intermediate housing connection pads 610A having a first property, which are arranged near a first side or a first edge S1. That is, the lower case substrate 601 lower intermediate housing connection pads 610A having the first property, which may be arranged asymmetrically in a left half L thereof. The lower case substrate 601 can first flip-chip connectors 623 which are close to a first side S1 of the lower semiconductor device 650 are arranged, and first flip-chip Anschlußlötaugen 621 comprising the first flip-chip terminals 623 correspond. That is, the lower case substrate 601 the first flip-chip connectors 623 which may be in a left half L of the lower semiconductor device 650 are arranged, and the first intermediate-Gehäusungsanschlusslötaugen 621 comprising the first flip-chip terminals 623 correspond.

The lower case substrate 601 can intermediate housing connection pads 610B having a second property, which are arranged near a second side or a second edge S2 with respect to the first side S1. That is, the lower case substrate 601 the intermediate housing connection pads 610B having the second property, which may be arranged asymmetrically in a right half R thereof. The lower case substrate 601 According to the present embodiment, second flip-chip terminal pads 622 comprise, the second flip-chip terminals 624 correspond, which are arranged near a second side S2 with respect to the first side S1. That is, the lower case substrate 610a the second flip-chip pads 622 may have the second flip-chip connections 624 correspond in a right half R of the lower semiconductor device 650 are arranged asymmetrically.

The lower case substrate 601 can be a first insulation layer 631 , a first metal layer 641 , a second insulation layer 632 , a second metal layer 642 , a third insulation layer 633 , a third metal layer 643 , a fourth insulation layer 634 , an insulation core layer 630 , a fifth insulation layer 635 , a fourth metal layer 644 , a sixth insulation layer 636 , a fifth metal layer 645 , a seventh insulating layer 637 , a sixth metal layer 646 and an eighth insulation layer 638 which are stacked consecutively.

The first metal layer 641 can lower inter-body connection pads 610A and 610B and flip-chip pads 621 and 622 exhibit. The first metal layer 641 can be used to provide different reference voltages or power supplies. In some embodiments, the first metal layer 641 be used as a flat surface for an element / chassis reference voltage, in particular a flat surface for a ground voltage. The second metal layer 642 can be used as lines to send or deliver data signals, reference voltages (or power supplies) for a data circuit, or address / control signals. The third and fourth metal layers 643 and 644 may also be used as powers to send or deliver data signals, reference voltages for the data circuit, or address / control signals. In particular, the third and fourth metal layers 643 and 644 used to transmit the address / control signals. The fifth metal layer 645 may be used to transmit signals other than at least one of the data signal, the reference voltages for the data circuit, and the address / control signals. The lower semiconductor device 650 can z. B. especially used to exchange data signals or other signals with an external device. The sixth metal layer 646 can with board connections 609 be electrically coupled. Accordingly, the sixth metal layer 646 according to the number and arrangement of the board connections 609 be formed. The sixth metal layer 646 can also be used as a flat surface for element / chassis reference voltages.

The lower semiconductor device 650 may comprise a logic circuit. The lower semiconductor device 650 can be a memory control unit 649 near a left half L thereof or a first side S1 of the lower case substrate 601 is arranged. The lower semiconductor device 650 can with the metal layers 641 , around 646 through the first and second flip-chip connectors 623 and 634 be electrically coupled. The first flip-chip connectors 623 may be arranged in a position corresponding to the position of the memory controller 649 the lower semiconductor device 650 equivalent. That is, the first flip-chip connectors 623 and the first flip-chip pads 621 in the position corresponding to the position of the memory controller 649 the lower semiconductor device 650 can be arranged.

The second flip-chip connectors 624 may be near a right half R of the lower semiconductor device 650 or a second side S2 opposite to the first side S1 of the lower case substrate 601 be arranged. The second side S2 may be a right side. Accordingly, the second flip-chip terminals 624 in the right half R of the lower semiconductor device 650 be arranged. The lower semiconductor device 650 can with the first flip-chip connectors 623 and the first flip-chip pads 621 be electrically coupled and signals or data with one above the lower semiconductor device 650 replace a second upper semiconductor device (not shown). As described above, the data signal and the address / control signals between the upper semiconductor device and the lower semiconductor device 650 through the first flip-chip connectors 623 and the first flip-chip pads 621 be transmitted. However, various reference voltages, such as reference voltages for a data circuit, reference voltages for an address / control circuit, and / or element / package reference voltages, may not directly match the first flip-chip terminals 623 and the first flip-chip pads 621 be coupled. That is, the different reference voltages are not provided by the lower semiconductor device 650 can be provided. A lower molding compound 655 can be between the lower semiconductor device 650 and the lower case substrate 610a be padded to side surfaces of the flip-chip connectors 623 and 624 to surround. For the sake of brevity, the lower molding compound will be omitted in the figures.

Regarding the 8B to 8E can any of the lower case 600b bi 600e According to some embodiments of the inventive idea, a lower semiconductor device 650 have on the corresponding one of the lower housing substrates 601b to 601e is arranged. Each of the lower housing substrates 601b to 601e may be a plurality of insulating layers 631 to 637 , a plurality of metal layers 641 to 645 and a metal core layer 640 exhibit. The insulation layers 631 to 637 can on Tops and bottoms of metal layers 641 to 645 and between the metal layers 641 to 645 be formed. The lower case 600b to 600e can be selected and combined in various ways according to the characteristics of a semiconductor device or an electronic system. That is, the position of the metal core layer 640 can be varied to minimize signal loss, noise or time delay caused by interference between adjacent metal layers 641 to 645 transmitted signals are caused.

In reference to the 8A to 8E can the lower housing substrates 601 to 601e with at least five metal layers 641 to 646 be used more efficiently when an upper housing has at least three storage devices. Accordingly, a lower package substrate having at least six metal layers 641 to 646 be used more efficiently when an upper housing has more than two storage devices.

The bottom with respect to the 8A to 8E described housing 600a to 600e may according to the purposes of the lower housing substrates 601 to 601e be selected and trained. In particular, the stacking order of the metal layers 641 to 645 and the metal core layer 640 according to various ways according to purposes of metal layers 641 to 645 be changed. The lower case 600a to 600e can z. B. be constructed so that sensitive to noise susceptible signals can be transmitted to a metal layer, which is close to the metal core layer 640 is arranged.

Regarding the 8F to 8H can any of the lower case 600f to 600h According to various embodiments of the inventive idea, a lower semiconductor device 650 have on the corresponding one of the lower housing substrates 601f around 601H is arranged. Each of the lower housing substrates 601f to 601h may be a plurality of insulating layers 631 to 636 , a plurality of metal layers 641 to 644 and a metal core layer 640 exhibit. The lower case 600f to 600h can be used very effectively if an upper housing has at least two semiconductor devices and requires at least two data signal transmission lines and two address signal transmission lines. Also, the position of the metal core layer 640 be set in different ways. The first to fourth metal layers 641 to 644 and the metal core layer 640 can z. B. be combined in different ways, as z. B. is shown in Table 2. [Table 2] First metal layer Second metal layer Third metal layer Fourth metal layer Metal core layer First example Inter-enclosure bond pads / transfer of primary address / control signals Transmission of primary and secondary data signal and reference voltages for a data signal / transmission of secondary address / control signals Transmission of further signals Platinenanschlusslötaugen Plane area for reference voltage (with area for ground) for element / chassis reference voltages ground Second example Inter-chassis connection pads / transmission of secondary address / control signals Transmission of primary and secondary data signal and reference voltages for a data signal / transmission of primary address / control signals Transmission of further signals Platinenanschlusslötaugen Plane area for reference voltage (with area for ground) for element / chassis reference voltages ground Third example Inter-enclosure bond pads / transmission of secondary data signal and reference voltages for a data signal Transmission of a primary data signal / transmission of primary and secondary address and control signals Transmission of further signals Platinenanschlusslötaugen Plane area for reference voltage (with area for ground) for element / chassis reference voltages ground Fourth example Inter-enclosure pad / transfer of a primary data signal and address for a data signal Transmission of a secondary data signal and reference voltage for a data signal / transmission of primary and secondary address and control signals Transmission of further signals Platinenanschlusslötaugen Layer Area by Element / Box Reference Voltage Ground (with area for ground)

The embodiments proposed in Table 2 are merely exemplary embodiments and other embodiments are within the contemplation of the inventive principles. The stacking order of the metal layers 641 to 644 and the metal core layer 640 and their purpose may be changed according to the use of a product or an intention of a circuit designer.

Regarding the 8I can a lower case 600i According to one embodiment of the inventive idea, a first lower semiconductor device 650L1 and a second lower semiconductor device 650L2 exhibit. The first lower semiconductor device 650L1 may comprise a logic device and the second lower semiconductor device 650L2 may have a large I / O memory device. The first lower semiconductor device 650L1 can lower TSVs 657 exhibit. The intermediate chip connections 656 can on the lower TSVs 657 be arranged. The intermediate housing connections 656 can with flip-chip connectors 623 and 624 each through the lower TSVs 657 be electrically coupled. Accordingly, the first and second lower semiconductor devices 650L1 and 650L2 be electrically coupled together. The various arrangements of the inter-chip connections 656 and the lower TSVs 657 may be understood in further detail with reference to other attached figures. The intermediate chip connections 656 and the lower TSVs 657 can z. B. asymmetric near a side of one of the lower semiconductor devices 650L1 and 650L2 be arranged as will be understood with reference to the accompanying figures.

The 9A to 9H FIG. 12 are cross-sectional views of package stacks according to various embodiments of the inventive concept. FIG.

Regarding the 9A to 9H can any of the housing stack structures 700a to 700i upper housing according to some embodiments of the inventive idea 500a and 500d , lower case 600a and 600g and intermediate housing connections 590A and 590B exhibit. The upper case 500a and 500d may be described in further detail with respect to e.g. B. the 7A to 7H be understood, especially on the 7A or 7D while the lower case 600a and 600g in further detail with respect to z. B. the 8A to 8I , especially on the 8A and 8G can be understood.

Regarding the 9A can upper and lower housing substrates 501 and 601 each insulation core layers 330 and 630 exhibit. An upper case 500a can in more detail in relation to the 7A and a description of it while a lower case 600a in more detail in relation to the 8A and a description of it can be understood.

Regarding the 9B can the upper case substrate 501 an insulation core layer 330 and the lower housing substrate 610g can be a metal core layer 640 exhibit. The upper case 500a can in more detail in relation to the 7A and a description thereof, and the lower case 600g can in more detail in relation to the 8G and a description of it will be understood.

Regarding the 9C may be an upper case substrate 501d a metal core layer 340 and a lower housing 601 can be an insulation core layer 630 exhibit. An upper case 500d can in more detail in relation to the 7A and a description thereof, and a lower case 600a can in more detail in relation to the 8A and a description of it will be understood.

Regarding the 9D may be an upper case substrate 501d and a lower case substrate 601g each metal core layers 340 and 640 exhibit. An upper case 500d can in more detail in relation to the 7D and a description thereof, and a lower case 600g can in more detail in relation to the 8G and a description of it will be understood.

In reference to the 9A to 9D can be any of the upper case 500a and 500d at least two upper semiconductor devices 551 and 552 exhibit. In a plan view, the upper semiconductor devices 551 and 552 may be rotated at an angle of 90 ° to each other and arranged in a horizontal or vertical direction, as described in further detail with respect to FIGS 6A to 6K is described. In each of the upper semiconductor devices 551 and 552 can each of the housing stack structures 700a to 700d Intermediate housing connections 590A having a first property near a first side S1 thereof (or around an area near the first side or first edge S1) and intermediate housing terminals 590B with a second property near a second side S2 opposite to the first side S1 thereof (or near a region near the second side or the second edge S2). Alternatively, each of the housing stack structures 700a to 700d Intermediate housing connections 590A having a first characteristic asymmetrically arranged in a left half L thereof and inter-housing terminals 590B having a second property, which are arranged asymmetrically in a right half R.

As described above, the intermediate housing connections 590A perform with the first property a first function and / or a second function and the intermediate housing connections 590B with the second property can perform a third function. The first function may be to transmit or provide data signals and / or reference voltages (or power supplies) for a data circuit of the upper semiconductor devices 551 and 552 exhibit. The second function may be the transmission of address / control signals of the upper semiconductor devices 551 and 552 exhibit. The third function may be to provide reference voltages (or power supplies) to an address / control circuit of the upper semiconductor devices 551 and 552 exhibit.

A description of the other components may be understood with reference to some of the other appended figures.

In reference to the 9E to 9H can any of the housing stack structures 700e 700h According to various embodiments of the inventive idea upper housing 500a and 500d , lower housing 610a and 610g and intermediate housing connections 591 to 593 and 596 to 598 and each of the lower housings 610a and 610g may be a first lower semiconductor device 650L1 and a second lower semiconductor device 650L2 exhibit. A detailed description of the package stack structures 700e to 700h can be based on the 8I be understood.

The 10 FIG. 12 is a conceptual plan view of the arrangement of bond pads of a semiconductor device according to some embodiments of the inventive concept. FIG.

Regarding the 10 may be a semiconductor device 21 first bond islands 31 and fourth bond islands 34 which are arranged in a left region Ls of a left half L, and third bonding islands 33 and second bond islands 32 which are arranged in a right region Rs of a right half R. The fourth bond islands 34 may be arranged in a left region Ls of a left half L. The first bond islands 31 can transmit data signals, the fourth bond islands 34 may provide reference voltages (or power supplies) for a data circuit, the third bond pads 33 can transmit address / control signals and the second bond pads 32 can reference voltages (or Power supplies) for the address / control circuitry and / or the element / chassis reference voltages. More specifically, the first and fourth bond islands 31 and 34 corresponding to the data signal in the left area Ls, and the third bonding pads 33 corresponding to the address / control signals and the second bonding pads 32 corresponding to the element / case reference voltages in the right-hand area RS. Accordingly, embodiments of the present disclosure may also be used when semiconductor devices include a balanced signal pad arrangement as discussed above. In other words, even if the bond islands 31 for the data signal and the bonding islands 33 for the address / control signal is not asymmetric on the memory device (as in FIG 10 12), the conductive elements or intermediate housing terminals for data signals and the conductive elements or intermediate housing terminals for the address / control signal may be arranged asymmetrically in a memory package substrate of a POP structure. As a result, the number of package substrate PCB layers can be reduced and efficient signal path guidance can be achieved.

The 11A and 11B 12 are side cross-sectional views, longitudinal sectional views, and partial exploded views of semiconductor packages according to other embodiments of the inventive concept.

Regarding the 11A can be a semiconductor case 800a According to one embodiment of the inventive idea, a semiconductor device 850 having on a housing substrate 801 is arranged.

The semiconductor device 850 can first bond islands 861 and second bond islands 862 which are arranged in a left region Ls of a left half L thereof, and third bonding islands 863 and fourth bond islands 864 which are arranged in a right region Rs of a right region R. The fourth bond islands 864 may be in the left region Ls of the left half L of the semiconductor device 850 be arranged. The second to fourth bond islands 862 to 864 can in more detail in relation to the 10 be understood.

The housing substrate 801 can be a first insulation layer 831 , a first metal layer 841 , a second insulation layer 832 , an insulation core layer 830 , a third insulation layer 833 , a second metal layer 842 and a fourth insulation layer 834 which are stacked consecutively.

The housing substrate 801 may be a first wire loop 871 , a second wire loop 872 , a third wire eyelet 873 and a fourth wire loop 874 have, which are arranged on the first metal layer.

The first, second, third and fourth bond islands 861 . 862 . 863 and 864 can each with the first, second, third and fourth Drahtlötaugen 871 . 872 . 873 and 874 each by bonding wires 875 be electrically coupled.

The housing substrate 801 can intermediate housing connection pads 810A having a first property lying on a lower surface of the second metal layer 842 are arranged, and intermediate-Gehäusungsanschlußlötaugen 810B having a second property lying on a lower surface of the second metal layer 842 are arranged. The intermediate housing connection pads 810A with the first property can with the first to third wire solder 871 to 873 be electrically coupled, and the intermediate-Gehäusungsanschlußlötaugen 810B with the second property can with the fourth wire bonding 874 be electrically coupled.

The intermediate housing connection pads 810A with the first property, near a first side (or a first edge) S1 of the package substrate 801 be arranged, and the intermediate-Gehäusungsanschlusslötaugen 810B with the second property, close to a second side (or a second edge) S2 may be disposed opposite to the first side thereof.

In the 11A For example, the first side S1 may correspond to a left side, and the second side S2 may correspond to a right side. Accordingly, the intermediate housing connection pads 810A with the first property in a left half L of the package substrate 801 be arranged asymmetrically, while the intermediate-Gehäusungsanschlußlötaugen 810B with the second property in a right half R thereof are arranged asymmetrically.

Regarding the 11B as with the semiconductor package 800a of the 11A compared, a semiconductor package 800b According to one embodiment of the inventive idea, a first insulating layer 831 , a first metal layer 841 , a second insulation layer 832 , a metal core layer 840 , a third insulation layer 833 , a second metal layer 842 and a fourth insulation layer 834 that have consecutively or alternately stacked. Some of the fourth wire pads 874 can with the metal core layer 840 be electrically coupled. In particular, the metal core layer 840 is used as a flat surface (especially a flat surface for a ground) for an element / package reference voltage. The other components are related to the 11A be understood.

The 12A to 12J 13 are side sectional and longitudinal sectional views of package stack structures according to various embodiments of the inventive concept.

Regarding the 12A to 12J can any of the housing stack structures 805a to 805j upper housing according to some embodiments of the inventive idea 800a and 800b , lower case 305a to 305c and intermediate housing connections 890A and 890B exhibit. The upper case 800a and 800b can be described in further detail with reference to z. B. the 11A and 11B be understood while the lower case 305a to 305c in more detail with respect to 5A to 5C can be understood.

The intermediate housing connection pads 890A and 890B can intermediate housing connections 890A with the first feature and intermediate housing connections 890B having the second property. The intermediate housing connections 890A with the first feature can with upper intermediate housing connection pads 810A with the first feature and lower inter-body connections 310A be electrically coupled to the first property. The intermediate housing connections 890B with the second feature can be with upper intermediate housing connection pads 810B with the second feature and lower inter-body connection pads 310B be electrically coupled to the second property. The intermediate housing connections 890A with the first property, near a first side (or first edge) S1 of each of the package stack structures 805a to 805j be arranged or arranged asymmetrically in a left half L thereof. The intermediate housing connections 890B with the second characteristic, each of the package stack structures may be near a second side S2 805a to 805j be arranged or arranged asymmetrically in a right half R thereof. In addition, a description of the upper and lower intermediate case connection pads 810A . 810B . 310A . 310B and the flip-chip pads 321 and 322 and the flip-chip connectors 323 and 324 in more detail with respect to 11A and 11B and 5A to 5C be understood.

Regarding the 12A . 12B . 12C . 12G and 12H may be an upper case substrate 801 an insulation core layer 830 exhibit. Regarding the 12D . 12E . 12F . 12I . 12J may be an upper case substrate 801b a metal core layer 840 exhibit. Regarding the 12A . 12D . 12G and 12I may be a lower case substrate 301 an insulation core layer 33 exhibit. Regarding the 12B . 12C . 12E . 12F . 12H and 12J can any of the lower housing substrates 301b and 301c a metal core layer 340 exhibit. The metal core layer 340 Can with some of the intermediate housing connections 890B be electrically coupled to the second property.

A detailed description of the metal core layer 340 and other components may be understood in further detail with respect to other appended figures.

Regarding the 12G by 12J can any of the housing stack structures 805g to 805j According to some embodiments of the inventive idea, a lower housing 306a or 306c further comprising a first lower semiconductor device 350L1 , a second lower semiconductor device 350L2 , Inter-chip connectors 356 . 357 and lower TSVs. The housing stack structures 805g to 805j can be constructed using various embodiments as described in the 12A to 12F are constructed. In accordance with additional aspects of the present disclosure, portions of the previously described embodiments, e.g. B. Embodiments of 12A to 12F combined to form package stack structures within the spirit and scope of the present disclosure. The first and second lower semiconductor devices 350L1 and 350L2 , the inter-chip connectors 356 and the lower TSVs 357 can be combined, applied and understood in various ways with reference to other figures and descriptions thereof. The 13A to 13D 10 are schematic views of the upper housings according to some embodiments of the inventive concept illustrating lateral cross-sectional views of semiconductor devices and longitudinal cross-sectional views of package substrates for clarity. Hereinafter, the term "primary" may refer to conductive structures electrically coupled to a first semiconductor device, and the term "secondary" may refer to conductive structures electrically coupled to a second semiconductor device. However, the terms "primary" and "secondary" are not classified in the figures because one Distinction between primary and secondary structures does not affect the understanding of the inventive idea.

Regarding the 13A to 13D can be any of the upper case 900a to 900d According to embodiments of the inventive idea, a plurality of upper semiconductor devices 951 and 952 have on the corresponding one of the upper housing substrates 901 to 901D are arranged. The upper semiconductor devices 951 and 952 can bond islands 961 to 964 and wire loops 971 to 974 have, which are distributed on both sides thereof. The semiconductor devices 951 and 952 can in the in the 6A to 6H be arranged illustrated various forms. Accordingly, it is to be understood that although illustrated for the sake of clarity, the two semiconductor devices 951 and 952 are arranged horizontally in a mirror-image manner, the semiconductor devices 951 and 952 can be rotated by any angle of 90 ° or 180 ° of each or can be vertically stacked.

With reference to the 13A can the upper case substrate 901 an insulation core layer 330 exhibit. With reference to the 13B to 13D can be any of the upper case 900b to 900d a metal core layer 340 exhibit.

Each of the upper housing substrates 901 to 901d can top intermediate housing connection pads 910A having a first property, which may be disposed near a first side S1 (or first edge) or left side thereof, or may be arranged asymmetrically in a left half L thereof and upper inter-body connection pads 910B having a second property, which may be disposed near a second side S2 (or second edge) or right side opposite to the first side S1, or may be arranged asymmetrically in a right half R. The upper semiconductor substrates 910a to 910d may be described in further detail with respect to e.g. B. the 7A to 7D be understood.

The 14A to 14U Figure 4 is a side cross-sectional and longitudinal sectional view of package stack structures of the various embodiments of the inventive concept. The 14A to 14U illustrate various forms of intermediate housing connections. In the present application are in the 14A to 14U Shown forms of the intermediate housing connections not in the in the 14A to 14U can be applied to the other embodiments described in the present disclosure and other modifications thereof.

Regarding the 14A to 14U can any of the housing stack structures 1000a to 1000u according to various embodiments of the inventive idea of one of the upper housing 900a to 900f , one of the lower case 605a to 605c and intermediate housing connections 990A and 990b exhibit.

The respective components of the upper and lower housings 900a to 900f and 605a to 605c may be understood in more detail with respect to other attached figures. The intermediate housing connections 990A and 990B can intermediate housing connections 990A having a first property described above and inter-housing connections 990B having a second property described above. In some embodiments, the intermediate housing connections 990A with the property Data Signals; Reference voltages (or power supplies) for a data circuit; and address / control signals of the upper semiconductor devices 951 and 952 transfer or provide. The intermediate housing connections 990A with the first property may be near a first side (or a first edge) S1 or the left side of each of the package stack structures 1000a to 1000u be arranged or arranged asymmetrically in a left half L. The intermediate housing connections 990B The second feature may provide reference voltages (or power supplies) for an address / control circuit. The intermediate housing connections 990B with the second property may be near a second side S2 or right side (or second edge) of each of the package stacks 1000a to 1000u be arranged or arranged asymmetrically in a right half R. The intermediate housing connections 990A and 990B can be formed in various forms. The different forms of intermediate housing connections 990A and 990B will be discussed in more detail later on 15A to 15D to be discribed.

Regarding the 14A to 14C and 14M to 14O can the upper case substrate 901 an insulation core layer 330 exhibit. Regarding the 14D to 14I and 14P to 14U each of the upper housing substrates can 901b . 901c . 501f . 501g and 501h a metal core layer 340 exhibit.

Regarding the 14A . 14D . 14G . 14M . 14P and 14S may be a lower case substrate 606a an insulation core layer 630 exhibit. Regarding the 14B and 14C . 14E and 14F . 14H and 14I . 14N and 14O . 14Q and 14R , and 14T and 14U can any of the lower housing substrates 606b and 606c a metal core layer 640 exhibit.

The 15A to 15D 13 are schematic views of intermediate housing terminals according to various embodiments of the inventive concept.

Regarding the 15A can be an intermediate housing connection 61 according to an embodiment of the inventive idea between an upper housing substrate 51U and a lower case substrate 51L be educated. In particular, the intermediate housing connection 61 with an upper metal layer 54U and an upper pad 55U of the upper case substrate 51U be electrically coupled and with a lower metal layer 54L and a lower pad 55L of the lower case substrate 51L be electrically coupled. The intermediate housing connections 61 may have an upper part with a volume larger than the volume of the lower part. The entire intermediate housing connection 61 can form a single body.

Regarding the 15B can be an intermediate housing connection 62 According to one embodiment of the inventive idea, an upper intermediate housing connection 62U with a relatively large volume and a lower intermediate housing connection 62L having a relatively small volume. If the lower intermediate housing connection 62L has the relatively small volume, may be a horizontal distance from the lower Zwischen-Gehäusungsanschlußlötauge 55L be reduced. Accordingly, the intermediate housing connection 62 be formed with a smaller horizontal distance.

Regarding the 15C can be an intermediate housing connection 63 According to one embodiment of the inventive idea, an upper intermediate housing connection 63U with a relatively small volume and a lower intermediate housing connection 63L having a relatively large volume.

Regarding the 15D can be an intermediate housing connection 64 According to one embodiment of the inventive idea, an upper intermediate housing connection 64U , an intermediate housing connection 64M and a lower intermediate case connector 64L exhibit. If the intermediate housing connection 64 According to the present embodiment has a very small horizontal distance, the intermediate housing connection 64 (composed of the combination of upper, middle and lower intermediate housing connections 64U . 64M and 64L ) have a relatively large length and a small width.

Regarding the 16A and 16B can be a module 2000 according to an embodiment of the inventive idea also housing stack structures 2030 have on a module substrate 2010 according to various embodiments of the inventive idea are applied. The module substrate 2000 can continue on the module substrate 2010 applied MP 2020 exhibit. The I / O ports 2040 can on at least one side of the module substrate 2010 be arranged. The housing stack structures 2030 can on the module substrate 2010 be applied using a flip-chip technique. The housing stack structures 2030 and the module substrate 2010 can z. B. by board connections 2035 be electrically coupled together. The housing stack structure 2030 may be an upper semiconductor device 2032U and a lower semiconductor device 2032L exhibit. The upper semiconductor device 2032U may comprise a semiconductor memory device while the lower semiconductor device 2032L may comprise a semiconductor logic device.

The housing stack structure 2030 can be conductive connections 2031a with a first characteristic and conductive connections 2031b having a second property disposed therein. The conductive connections 2031a with the first property, electrical signals can be transmitted to the communication between the upper and lower semiconductor devices 2032U and 2032L to enable. The conductive connections 2031a with the first property can z. B. data signals, reference voltages for a data circuit, and / or address / control signals transmitted or deliver. Accordingly, some of the conductive connections 2031a with the first feature not directly with the board connectors 2035 be coupled. The conductive connections 2031a with the first property, the z. B. are configured so that they transmit the data signal and address / control signals can not directly to the board connections 2035 be coupled. However, the conductive connections can 2031a with the first feature configured to provide the reference voltages for a data circuit, directly to the board terminals 2035 be coupled. Also, the conductive connections 2031E with the second characteristic with the upper semiconductor device 2032U be electrically coupled, but they can not directly with the lower semiconductor device 2032L be coupled. The conductive connections 2031E with the second property can z. B. directly to the board connections 2035 be coupled. However, the conductive connections can 2031 B with the second feature configured to provide reference voltages (or power supplies) for an address / control circuit with the lower semiconductor device 2032L be electrically coupled. The embodiments described above may be modified in various ways as needed within the scope of the present disclosure.

Regarding the 17 For example, various semiconductor devices, package substrates, semiconductor packages, and / or package stacks may be included in an electronic system in accordance with some embodiments of the inventive concept 2100 be used. The electronic system 2100 can a body 2110 , an MP unit 2120 , a power supply 2130 , a functional unit 2140 and / or a graphics card 2150 exhibit. The body 2110 may be a system board or motherboard with a printed circuit board (PCB). The MP 2120 , the power supply 2130 , the functional unit 2140 and the graphics card 2150 can on the body 2110 be upset. The display device 2160 can on a top of the body 2110 or outside the body 2110 to be appropriate. The display device 2160 can z. B. on the surface of the body 2110 be attached and one of the graphics card 2150 show processed image.

The power supply 2130 may receive a predetermined voltage from an external voltage source, divide the voltage into voltages having different voltage levels, and divide the sub-voltages into the MP 2120 , the functional unit 2140 and the graphics card 2150 provide. The MP 2120 can be a voltage of the power supply 2130 received and the functional unit 2140 and the display device 2160 Taxes. The functional unit 2140 can for different functions of the electronic system 2100 be used. If the electronic system 2100 a mobile electronic device, such as a mobile phone, may be the functional unit 2140 z. B. have multiple components to wireless communication functions such. B. the image output on the display device 216 or the voice output to a speaker, by dialing or transmitting to an external device 2170 perform. Even if the electronic system 2100 Having a camera, the electronic system 2100 serve as an image processor.

In some embodiments, when the electronic system 2100 coupled to a memory card to increase its capacity, the functional unit 2140 be a memory card control unit. The functional unit 2140 can send signals to and from the external device 2170 via a wired or wireless communication unit 2180 send and receive. In addition, if the electronic system 2100 requires a Universal Serial Bus (USB) to extend functionality, the functional unit 2140 serve as an interface control unit.

The semiconductor devices, package substrates, semiconductor packages, and / or package stack structures described in various embodiments of the inventive concept may include at least one of the MP units 2120 and the functional unit 2140 exhibit.

The 18 is a schematic view of an electronic system 2200 , in which the semiconductor device according to an embodiment of the inventive concept is used. Regarding the 18 can the electronic system 2200 a semiconductor device or a semiconductor stack package according to exemplary embodiments. The electronic system 2200 can be used to make a mobile device or a computer. The electronic system 2200 can z. B. a storage system 2212 a microprocessor 2214, RAM 2216 and a user interface 2218 comprising the data communication over a bus 2220 can perform. The microprocessor 2214 can run the program and can the electronic system 2200 Taxes. The RAM 2216 can be used as a function memory of the processor 2214 be used. The processor 2214 or the RAM 2216 can z. For example, a semiconductor device or a semiconductor stack package according to exemplary embodiments. The processor 2214 , the ram 2216 and / or other components may be constructed in a single housing. The user interface 2218 can when entering / outputting data to the electronic / by the electronic system 2200 be used. The storage system 2212 can use codes to operate the processor 2214 , from the processor 2214 processed data, or external input data store. The storage system 2212 may include a controller and a memory.

The 19 is a schematic view of a wireless mobile phone 2300 in which the electronic system ( 2200 in 18 ) can be used according to an embodiment of the inventive idea. In addition, the electronic system ( 2200 from 18 ) for a portable notebook computer, a MPEG-1 audio layer 3- (MP3) player, an MP4 player, a navigation device, a solid state drive (SSD), desktop PC, cars or household appliances can be used.

The 20A FIG. 10 is a block diagram of an exemplary master semiconductor chip. FIG 7100 according to one embodiment. Regarding the 20A has the semiconductor chip 7100 a memory cell area 7110 and a border area 7120 on. In one embodiment, the memory cell area 7110 a memory bank containing a memory cell array 7111 , a sense amplifier matrix 7112 , a row address decoder 7114 and a column address decoder 7115 having.

In one embodiment, the border area 7120 an address / control circuit discussed above 7125 exhibit. Also, some of the inter-chassis terminals discussed above may be configured to provide a voltage supply (or reference voltage) for the address / control circuitry 7125 provide. Furthermore, the border area 7120 additionally a data circuit 7124 have, with a clock circuit 7113 is electrically coupled. Also, some of the inter-chassis terminals discussed above may be configured to provide a power supply for the data circuitry 7124 as discussed above.

In another embodiment discussed above, some of the bonding pads discussed above may be configured to provide a voltage supply (or reference voltage) for the address / control circuit 7125 provide. Also, some of the bonding pads discussed above may be configured to supply the power to the data circuit 7124 provide.

In detail, the border area 7120 the address / control circuit 7125 with a command decoder 7121 which decodes an external command signal, an address register 7122 and a bank control unit 7116 exhibit. The border area 7120 can also use the data circuit 7124 and an input / output (I / O) driver, an I / O sense amplifier, and the clock circuit 7113 exhibit.

In an embodiment, the semiconductor chip 7100 a plurality of memory banks, wherein the bank control unit 7116 can be used to select one of the banks.

In one embodiment, different areas of the master semiconductor chip 7100 be powered independently of each other. The data circuit 7124 can z. B. receive a voltage of Vddq and Vssq from a first voltage source, while the remaining edge area 7120 receives a voltage of Vdd and Vss from a second voltage source. In addition, the memory cell area 7110 a master semiconductor chip 7100 receive a voltage equal to the voltage Vdd and Vss from the same voltage source as the rest of the edge region 7120 is received or received from another power source. In one embodiment, Vddq and Vssq may be for the circuit for data switching 7124 be determined, and are thus electrically isolated from other areas of the chip within the chip. That is, Vddq and Vssq have no circuit other than the affected input / output circuit in the peripheral area of the master semiconductor chip 7100 are electrically coupled. In one embodiment, Vddq has a lower voltage value than Vdd to reduce power consumption in the data input / output circuit.

The 20B FIG. 10 is a block diagram of an exemplary slave semiconductor chip. FIG 7200 according to one embodiment. Regarding the 20B For example, the slave semiconductor chip is a second chip that has only one memory cell area 7210 and a pad area, but no border area 7120 has, as well as the master semiconductor chip 7100 , In one embodiment, the memory cell area 7210 a memory bank containing a memory cell array 7211 , a sense amplifier matrix 7212 , a row address decoder 7214 and a column address decoder 7215 having. In one embodiment, these elements have the same construction as the corresponding elements of FIG 20A illustrated master semiconductor chips 7100 on.

In one embodiment, the slave semiconductor chip receives 7200 from a voltage source the same voltage Vdd and Vss as the Vdd and Vss applied to the memory cell area 7110 of the master semiconductor chip 7100 is applied. Alternatively, different voltages can be applied to the slave semiconductor chip 7200 in comparison to the master semiconductor chip 7100 be applied. The 20C FIG. 10 is a block diagram of an exemplary semiconductor device. FIG 7000 according to some embodiments. In one embodiment, the semiconductor device 7000 a series of circuits with a master semiconductor chip 7100 with a memory cell area 7110 and with a border area 7120 (with a document area), such as. B. above in connection with the 20A discussed and a number of additional slave Semiconductor chips 7200 with memory cell areas 7210 . 7310 . 7410 , etc., and document areas, as above in connection with the 20B is described. Although only three additional semiconductor chips 7210 . 7310 . 7410 can be a semiconductor device 7000 have additional additional semiconductor chips.

Like in the 20C each additional semiconductor chip may comprise a memory cell region ( 7210 . 7310 . 7410 ) with a memory cell matrix ( 7211 . 7311 . 7411 ), a sense amplifier matrix ( 7212 . 7312 . 7412 ), a column address decoder ( 7215 . 7315 . 7415 ) and a row address decoder ( 7214 . 7314 . 7414 ) exhibit. Each further semiconductor chip can be controlled by the edge circuit of the master semiconductor chip. For example, instructions on each additional semiconductor chip are issued by the instruction decoder 7121 receive, an address is at every other semiconductor chip from the address register 7122 a chip (or memory bank, as the chips are labeled) can be received using the bank control unit 7116 and input and output of data may be selected by the data transmission unit 7124 and the input / output (I / O) driver, an I / O sense amplifier and the clock circuit 7113 to be controlled.

In an embodiment, the slave semiconductor chips may include a plurality of memory banks, wherein the bank control unit 7116 can be used to select one of the banks. The voltage supply Vdd and / or the ground voltage Vss that may be applied to the master semiconductor chip and the additional slave semiconductor chips may be used to operate the memory cell regions or edge regions. However, if the power supply Vdd and / or the ground voltage Vss are used to drive the memory cell areas, noise generated in the power supply Vdd and / or the ground voltage Vss may decrease memory performance. Consequently, as described in the above previous embodiments, a path in which the power supply Vdd and / or the ground voltage Vss is applied to the master semiconductor chip may be a certain electrical isolation path, as compared with a path in which the Voltage supply Vdd and / or the ground voltage Vss is applied to the slave semiconductor chips.

Furthermore, the voltage supply Vdd and / or the ground voltage Vss can be applied to different blocks of the memory cell areas from the outside. In some cases, the deterioration degree of the memory power when a noise-containing power supply Vdd and / or a ground voltage Vss is applied to some blocks of the memory cell areas may be different if the noise-containing power supply Vdd and / or the ground voltage Vss are applied to the other blocks be applied. Thus, in one embodiment, the power supply Vdd and / or the ground voltage Vss may be applied to some blocks of the memory cell areas of the master semiconductor chip and the slave semiconductor chip in the same path and on the other blocks of the memory cell areas of the master semiconductor chip and the slave semiconductor chips applied on different paths. Even if z. B. the noise-containing power supply Vdd and / or ground voltage Vss on the row address decoder 7114 . 7214 . 7314 and 7414 and the column address decoder 7115 . 7215 . 7315 and 7415 be applied, the degree of degradation of the storage capacity is relatively small. Thus, the power supply Vdd and / or the ground voltage Vss may be applied to the row address decoder 7114 of the master semiconductor chip and the row address decoder 7214 . 7314 and 7414 of the slave semiconductor chip via the same electrical path (eg, by TSVs in an aligned stack electrically coupled to each of the four semiconductor chips). Also, the voltage supply Vdd and / or the ground voltage Vss may be on the column address decoder 7115 of the master semiconductor chip and on the column address decoder 7215 . 7315 and 7415 the slave semiconductor chips are applied on the same path. For this purpose, the power supply Vdd or the ground voltage Vss is applied to the row address decoder 7114 or the column address decoder 7115 of the master semiconductor chip with a second via (not shown) applied to the master semiconductor chips. Similarly, the voltage supply Vdd or the ground voltage Vss may be applied to the row address decoder 7214 . 7314 and 7414 or the column address decoder 7215 . 7315 and 7415 the slave semiconductor chips are applied through the third via (not shown) formed on the slave semiconductor chips and electrically coupled to the second vias. However, when a noise applied to a memory bank or to a sense amplifier occurs in the power supply Vdd and / or the ground voltage Vss, the memory performance is significantly degraded. Thus, the power supply Vdd and / or the ground voltage Vss can be applied to the memory bank 7111 and on the sense amplifier 7112 of the master semiconductor chip may be applied to another path which is electrically isolated from the path on which the power supply Vdd and / or the ground voltage Vss of the slave semiconductor chips are applied. The power supply Vdd or the ground voltage Vss is z. B. on the memory bank 7111 or 7112 of the sense amplifier of the master semiconductor chip is applied to the master semiconductor chip through a first via (not shown) but to the memory banks 7211 . 7311 and 7411 or on the sense amplifier 7212 . 7312 and 7412 the slave semiconductor chips applied by the second via, that of the first Through hole is isolated and formed on the master semiconductor chip and through the third vias on the slave semiconductor chips.

In some embodiments, a housing stack structure includes: an upper housing, a lower housing, and a plurality of intermediate housing terminals; the upper case has an upper case substrate and an upper semiconductor device mounted on the upper case substrate, the upper semiconductor device having a plurality of functional conductive members configured to communicate with the upper case substrate through a plurality of terminals functional conductive elements are configured to provide a first set of functions and a second set of functions different from the first set of functions; the first set of functions having one or more functions selected from the group comprises: transmitting data signals, providing a reference voltage for a data circuit, and transmitting an address / control signal; the second set of functions having one or more functions selected from the group comprises: providing a voltage supply or reference voltage (Vss / Vdd) for an address / control circuit, and providing element / chassis reference voltages; the upper housing further includes first and second upper inter-housing terminal pads disposed on a lower surface of the upper housing substrate, the first upper inter-housing terminal pads are disposed exclusively on a first area of the underside of the upper housing substrate, and the second set of upper intermediate The housing pad is exclusively on a second area of the underside of the upper package substrate, the second area is generally second to the first area, the upper package substrate having a plurality of conductive routing patterns configured to terminate the terminals with the package upper semiconductor device route that the functional conductive elements corresponding to the first set of functions are in communication with the first upper inter-housing pads, and that the functional elements corresponding to the second set of functions communicate with the first second intermediate housing connection pads in communication.

In some embodiments, a housing stack structure comprises: an upper housing having a first corner connecting a first edge and a third edge; a second corner connecting the first edge and a fourth edge; a third corner connecting the third edge and a second edge connects, and a fourth corner connecting a second edge and the fourth edge; the upper housing may further include a first area adjacent the first corner, a second area near the second corner, a third area near the third corner, and a fourth area adjacent to the fourth corner and a fifth area near the second edge exhibit;
a lower housing coupled to the upper housing by a plurality of intermediate housing terminals, the intermediate housing terminals including: first inter-housing terminals configured to transmit data signals, second inter-housing terminals configured such in that they transmit address / control signals, third inter-chassis terminals configured to provide a voltage supply or reference voltage (Vss / Vdd) for an address / control circuit, and fourth inter-chassis terminals configured to provide a power supply or reference voltage Providing voltage supply or reference voltage (Vssq / Vddq) for a data circuit to be provided, wherein the first inter-enclosure terminals are arranged exclusively in the first area, the second inter-enclosure terminals being disposed exclusively in the first area, the third inter-enclosure slots are arranged exclusively in the first region, the fourth intermediate housing connections are arranged in the second region.

In some embodiments, a housing stack structure includes an upper housing having a housing substrate having a first corner connecting a first edge and a third edge, a second corner connecting the first edge and a fourth edge, a third corner connecting the third Edge and a second edge connects, and a fourth corner connecting the second edge and the fourth edge, wherein a hypothetical diagonal line (eg a dotted in 3J illustrated line 176 between the first corner and the fourth corner, the diagonal line dividing areas of the upper housing into a first area near the first edge and a second area near the second edge; a lower housing coupled to the upper housing by a plurality of intermediate housing terminals, the intermediate housing terminals comprising: first inter-housing terminals configured to transmit data signals, second inter-housing terminals configured such in that they transmit address / control signals, third inter-chassis terminals configured to provide a voltage supply or reference voltage (Vss / Vdd) for an address / control circuit, and fourth inter-chassis terminals configured to provide a power supply or reference voltage Provide voltage supply or reference voltage (Vssq / Vddq) for a data circuit, wherein a plurality of the first and second second intermediate case terminals are disposed in the first area, and wherein a plurality of the third intermediate case terminals are arranged in the second area.

In some embodiments, a semiconductor package substrate includes a substrate for mounting a semiconductor device. The substrate has a first edge and a second edge opposite the first edge. The substrate has a first region near the first edge and a second region disposed near the second edge. The substrate also has a plurality of intermediate housing terminals mounted thereon. The plurality of intermediate case terminals include first intermediate case terminals configured to transmit data signals; second inter-housing terminals configured to transmit address / control signals; third inter-chassis terminals configured to provide a power supply for an address / control circuit; fourth inter-package terminals configured to provide a power supply for a data circuit. A plurality of the first and second intermediate housing terminals may be disposed in the first area. Also, a plurality of the third intermediate case terminals may be disposed in the second area.

In some embodiments, a method of operating a functionally asymmetric semiconductor device overlying a package substrate having a first edge and a second edge opposite the first edge comprises: transmitting data signals substantially from first bond pads proximate the first edge of the package substrate Transmit address / control signals substantially from second bond pads disposed near the first edge of the package substrate; and providing a voltage supply or reference voltage (Vss / Vdd) for an address / control circuit through third bond pads disposed near the second edge of the package substrate.

In some embodiments, a system includes a housing stack structure having an upper housing of an upper housing substrate having a first edge and a second edge opposite the first edge, the upper housing substrate having a first region disposed near the first edge and a second proximate the second edge Area, wherein an upper housing has a first upper semiconductor device overlying the upper housing substrate; a lower housing having a lower housing substrate and a lower semiconductor device, the lower housing having the upper housing through a plurality of intermediate housing terminals, wherein the intermediate housing terminals include: first intermediate housing terminals configured to transmit data signals; second inter-housing terminals configured to transmit address / control signals; third inter-chassis terminals configured to provide a power supply for an address / control circuit; fourth inter-package terminals configured to provide a power supply for a data circuit, wherein a plurality of the first and second inter-package terminals are arranged in the first area, and wherein a plurality of the third inter-package terminals are arranged in the second area is; a display device electrically coupled to the package stack structure; and an input / output device coupled to the display device.

In addition, the terms and functions of the components heretofore described or described may be readily understood with reference to other figures of the present specification and the descriptions thereof. In addition, one skilled in the art will recognize that a particular scope of each of the exemplary embodiments may be coupled with other embodiments within the scope of the present disclosure.

A semiconductor device, a package substrate, a semiconductor package, a package stack structure, and an electronic system according to some embodiments of the inventive concept include asymmetric conductive components or a metal core layer so that the signal paths of metal layers on a package substrate plane can be simplified. The signal paths of the metal layers can, for. B. be arranged so that they do not overlap each other. Accordingly, the signal paths can be routed on a reduced number of metal layers as compared to the conventional case in which the signal paths are arranged in a relatively large number of metal layers.

Therefore, electronic components according to the inventive concept can reduce signal loss, suppress occurrence of noise, and increase a signal transmission rate. Further, with the embodiments of the present disclosure, thinner and smaller electronic devices can be manufactured compared to prior art devices, since electronic components using the concept of the present invention require only a small space and are much thinner than conventional components.

Exemplary embodiments of the present application may also be applied to ASICs, PLDs / gate arrays, DSPs, graphics and PC chipsets. In addition, embodiments of the present application may be used to utilize a storage device for notebooks and subnotebooks for business, ultra-mobile PCs (UMPC), and tablet PCs.

Throughout this description, references to "a single embodiment" or "an embodiment" mean that at least one embodiment of the present invention has a particular feature, structure, or characteristic described in connection with the embodiment. Thus, the occurrence of the term "in one embodiment" at various points in this description does not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or properties may be combined in any suitable manner in one or more embodiments.

The foregoing is illustrative of embodiments and is not intended to be limiting. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications of the embodiments are conceivable without materially departing from the novel teachings and advantages. Accordingly, it is intended that all such modifications be included within the scope of this inventive idea as defined in the claims. In the claims, means-plus-function clauses are provided to cover the structures described herein that perform the specified function, and to cover not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims (20)

A package stack structure comprising: an upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c . 900d ), which is an upper housing substrate ( 110U ; 201 . 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ) having a first edge (S1) and a second edge (S2) opposite to the first edge (S1), wherein the upper housing substrate (S1) 110U ; 201 ; 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ) has a first area near the first edge (S1) and a second area near the second edge (S2), the upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) one the upper housing substrate ( 110U ; 201 ; 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ) overlapping first upper semiconductor device ( 150U ; 250 ; 451 ; 551 ; 951 ; 2032U ) having; a lower housing ( 105L ; 305a ; 305b ; 305c ; 306a ; 306b ; 306c ; 405L ; 600a ; 600b ; 600c ; 600d ; 600e ; 600f ; 600g ; 600h ; 600i ; 605a ; 605b ; 605c ) with a lower housing substrate ( 110L ; 301 ; 301b ; 301c ; 410L ; 601 ; 601b ; 601c ; 601d ; 601e ; 601f ; 601g ; 601h ; 606a ; 606b ; 606c ) and a lower semiconductor device ( 150L ; 350 ; 450 ; 650 ; 2032L ), the lower housing ( 105L ; 305a ; 305b ; 305c ; 306a ; 306b ; 306c ; 405L ; 600a ; 600b ; 600c ; 600d ; 600e ; 600f ; 600g ; 600h ; 600i ; 605a ; 605b ; 605c ) with the upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) by a plurality of intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ), wherein the intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ): first inter-housing terminals configured to transmit data signals; second inter-housing terminals configured to transmit address / control signals; third intermediate housing terminals configured to supply a supply voltage for an address / control circuit ( 7125 ) provide; fourth intermediate housing terminals configured to supply a supply voltage for a data circuit ( 7124 ), wherein a plurality of the first and second intermediate case terminals are disposed in the first region, and wherein a plurality of the third intermediate case terminals are disposed in the second region. The package stack structure of claim 1, wherein a plurality of the fourth set of inter-package terminals are disposed in the first region. A structure according to claim 1, wherein said first upper semiconductor device ( 150U ; 250 ; 451 ; 452 ; 551 ; 552 ; 553 ; 554 ; 951 ; 952 ; 2032U ) comprise: first bonding pads configured to transmit data signals and electrically connected to the inter-chassis terminals (10); 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ) are coupled; second bond pads configured to carry the address / control signals and electrically connected to the inter-chassis terminals (FIG. 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ) are coupled; third bond pads configured to provide the supply voltage for the address / control circuit; and fourth bond pads configured to supply power to the data circuitry (FIG. 7124 ) provide. The structure of claim 3, wherein a plurality of the first bonding pads are disposed near the first edge (S1) and a plurality of the second bonding pads are located near the second edge (S2). The structure of claim 3, wherein a plurality of the first and second bonding pads are disposed near the first edge (S1). Structure according to claim 5, wherein a plurality of the third bonding pads is disposed near the second edge (S2) and wherein a plurality of the fourth bonding pads are disposed near the first edge (S1). A structure according to claim 3, wherein the upper housing ( 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 900a ; 900b ; 900c ; 900d ) further comprises a second upper semiconductor device ( 452 ; 552 ; 952 ) adjacent to the first upper semiconductor device ( 451 ; 551 ; 951 ), wherein the second upper semiconductor device ( 452 ; 552 ; 952 ): first bonding pads configured to transmit the data signals and electrically coupled to the first inter-chassis terminals; second bond pads configured to transmit the address / control signals and electrically coupled to the second inter-package terminals, third bond pads configured to provide the supply voltage for the address / control circuitry, and fourth bond pads which are configured to supply the supply voltage for the data circuit ( 7124 ) provide. The structure of claim 7, wherein a plurality of said first and second bonding pads of said first and second upper semiconductor devices ( 452 ; 552 ; 952 ) is arranged near the first region and a plurality of the third bonding pads of the first and second upper semiconductor devices ( 451 . 452 ; 551 . 552 ; 951 . 952 ) is disposed near the second region. A structure according to claim 8, wherein said lower semiconductor device ( 450 ) a memory control circuit ( 477 ), which is close to the first region of the upper housing substrate (FIG. 410U ), wherein a single signal channel between the first and second bonding pads of the first and second upper semiconductor devices (FIG. 451 . 452 ) and the memory control circuit ( 477 ) for jointly controlling the first and second upper semiconductor devices ( 451 ; 452 ) is trained. A structure according to claim 7, wherein said upper package substrate ( 410U ) has a third edge and a fourth edge opposite to the third edge disposed between the first edge (S1) and the second edge (S2), wherein a plurality of the first and second bonding pads of the second upper semiconductor device ( 452 ) is arranged near the third edge and wherein a plurality of the third bonding pads of the second upper semiconductor device ( 452 ) is disposed near the fourth edge opposite to the third edge. A structure according to claim 10, wherein said lower semiconductor device ( 450 ) one near the first edge (S1) of the upper case substrate (FIG. 410U ) first memory control circuit ( 447 ) and a near the third edge of the upper housing substrate ( 410U ) arranged second memory control circuit ( 448 ), wherein a first channel between the first and second bonding pads of the first upper semiconductor device ( 451 ) and the first memory control circuit ( 447 ) is formed around the first upper semiconductor device ( 451 ), and wherein a second channel between the first and second bonding pads of the second upper semiconductor device ( 452 ) and the second memory control circuit ( 448 ) is formed around the second upper semiconductor device ( 452 ) such that a plurality of channels are interposed between the first and second upper semiconductor devices ( 451 . 452 ) and the lower semiconductor device ( 450 ) are formed. The structure of claim 1, wherein said upper package substrate ( 210b ) a first upper metal layer ( 241 ), an upper metal core layer ( 240 ) and a second upper metal layer ( 242 ) which are stacked consecutively, and wherein the upper metal core layer ( 240 ) thicker than each of the first and second upper metal layers ( 241 ). A structure according to claim 12, wherein the upper metal core layer ( 240 ) of the upper case substrate ( 210b ) is electrically coupled to the second intermediate case terminals. The structure of claim 1, wherein the lower case substrate ( 301 ) a first lower metal layer ( 341 ), a second lower metal layer ( 342 ), a lower metal core layer ( 340 ), a third lower metal layer ( 343 ), and a fourth lower metal layer ( 344 ), which are stacked successively, and wherein the lower metal core layer ( 340 ) thicker than each of the first lower metal layers ( 341 ), the second lower metal layer ( 342 ), the third lower metal layer ( 343 ) and the fourth lower metal layer ( 344 ). The structure of claim 14, wherein the lower metal core layer ( 340 ) of the lower case substrate ( 301 ) is electrically coupled to the second intermediate case terminals. The structure of claim 14, wherein the first inter-package terminals are connected to the first upper semiconductor device (14). 250 ) through the first metal layer ( 341 ) is electrically coupled. Upper housing configured to attach to a lower housing (FIG. 105L ; 305a ; 305b ; 305c ; 306a ; 306b ; 306c ; 405L ; 600a ; 600b ; 600c ; 600d ; 600e ; 600f ; 600g ; 600h ; 600i ; 605a ; 605b ; 605c ) is mounted in a housing stack structure, wherein the upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) comprises: an upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ), which is an upper housing substrate ( 110U ; 201 ; 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ) having a first edge (S1) and a second edge (S2) opposite to the first edge (S1), wherein the upper housing substrate (S1) 110U ; 201 ; 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ) one near the first edge ( 51 ) arranged first region and a second edge (S2) arranged near the second region, wherein the upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) further comprises an upper semiconductor device ( 150U ; 250 ; 451 ; 551 ; 951 ; 2032U ) having the upper housing substrate ( 110U ; 201 ; 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U superimposed, wherein the upper housing with the lower housing ( 105L ; 305a ; 305b ; 305c ; 306a ; 306b ; 306c ; 405L ; 600a ; 600b ; 600c ; 600d ; 600e ; 600f ; 600g ; 600h ; 600i ; 605a ; 605b ; 605c ) by a plurality of intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ), wherein the plurality of intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ): first inter-housing terminals configured to transmit data signals; second inter-housing terminals configured to transmit address / control signals; third inter-housing terminals configured to provide a supply voltage for the address / control circuit; fourth intermediate housing terminals configured to supply a supply voltage for the data circuit ( 7124 ), wherein a plurality of the first and second intermediate case terminals are arranged in the first region, and wherein a plurality of the third intermediate housing terminals are arranged in the second area. Semiconductor package comprising: a package substrate ( 110U ; 201 . 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ) having a first edge (S1) and a second edge (S2) opposite the first edge (S1), wherein the housing substrate (S1) 110U ; 201 . 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ) has a first region disposed near the first edge (S1) and a second region disposed near the second edge (S2); a semiconductor device ( 150U ; 250 ; 451 ; 551 ; 951 ; 2032U ), the housing substrate ( 110U ; 201 . 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U superimposed; a plurality of intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ) located on a lower side of the housing substrate ( 110U ; 201 . 201b ; 210a ; 210b ; 410U ; 501 ; 501b ; 501c ; 501d ; 501e ; 501f ; 501g ; 501h ; 801 ; 801b ; 901 ; 901b ; 901c ; 901d ; 901e ; 901f ; 901g ; 901h ; 51U ), wherein the plurality of intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ): first inter-housing terminals configured to transmit data signals; second inter-housing terminals configured to transmit address / control signals; third intermediate housing terminals configured to supply a supply voltage to an address / control circuit ( 7125 ) provide; fourth inter-package terminals configured to supply a supply voltage for a data circuit ( 7124 ), wherein a plurality of the first and second intermediate case terminals are disposed in the first region, and wherein a plurality of the third intermediate case terminals are disposed in the second region. A package stack structure comprising: an upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) having a first edge (S1) and a second edge (S2) opposite or near the first edge (S1), the upper housing (S1) 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) further comprises a surface having a first region located near the first edge (S1) and a second region disposed near the second edge (S2); one with the upper case ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) by a plurality of intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ) coupled lower housing ( 105L ; 305a ; 305b ; 305c ; 306a ; 306b ; 306c ; 405L ; 600a ; 600b ; 600c ; 600d ; 600e ; 600f ; 600g ; 600h ; 600i ; 605a ; 605b ; 605c ), wherein the intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ): first inter-package terminals configured to transmit data signals, second inter-package terminals configured to transmit address / control signals, and third inter-package terminals configured to provide a power supply voltage provide for an address / control circuit, wherein the first and second intermediate housing terminals are arranged exclusively in the first region, and wherein the third intermediate housing terminals are arranged exclusively in the second region. A package stack structure comprising: an upper housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) with a housing substrate ( 501 ; 501b ; 501c ; 501d ; 501e ; 501f; 501g ; 501h ) having a first corner (C1) coupling a first edge (S1) and a third edge, a second corner coupling the first edge (S1) and a fourth edge, a third corner including the third edge and a second edge Edge (S2), and a fourth corner coupling the second edge (S2) and the fourth edge, wherein a hypothetical diagonal line extends between the first corner (S1) and the fourth corner, the diagonal line being regions of the upper corner Housing ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) separates into a first region near the first edge (S1) and a second region near the second edge (S2); one with the upper case ( 105U ; 200a ; 200b ; 405U ; 500a ; 500b ; 500c ; 500d ; 500e ; 500f ; 500g ; 500h ; 800a ; 800b ; 900a ; 900b ; 900c ; 900d ) by a plurality of intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ) coupled lower housing ( 105L ; 305a ; 305b ; 305c ; 306a ; 306b ; 306c ; 405L ; 600a ; 600b ; 600c ; 600d ; 600e ; 600f ; 600g ; 600h ; 600i ; 605a ; 605b ; 605c ), wherein the intermediate housing connections ( 190A . 190B ; 290A . 290B ; 490A . 490B ; 590A . 590B ; 890A . 890B ; 990A . 990B ): a first set of intermediate case terminals configured to transmit data signals, a second set of intermediate case terminals configured to transmit address / control signals, a third set of intermediate case terminals are configured to supply a supply voltage for an address / control circuit ( 7125 ) and a fourth set of inter-chassis terminals configured to supply a supply voltage for a data circuit ( 7124 ), wherein a plurality of the first and second sets of intermediate case terminals are disposed in the first region, and wherein a plurality of the third set of intermediate case terminals are disposed in the second region.

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