DE102012104160A1 - Switching power supply and working method for a switching power supply - Google Patents

Abstract

The invention relates to a switched-mode power supply (1) comprising a first switching stage (6) for generating a rectified intermediate voltage (Vc) from a primary alternating voltage (Vp), a memory element (7) for temporarily storing the intermediate voltage (Vc) generated by the first switching stage (6) ) and a second switching stage (8) for generating a secondary output voltage (Vs) from the latched intermediate voltage (Vc). The switching power supply (1) has a control circuit (9) for activating and deactivating the first switching stage (6), wherein the control circuit (9) is adapted to the first switching stage (6) for a determined by the control circuit (9) portion of a to activate the first half-wave (11) of the primary AC voltage (Vp) and for at least a subsequent half-wave (12, 13) of the primary AC voltage (Vp) to disable. The invention further relates to a working method for operating such a switching power supply (1).

Description

The invention relates to a switching power supply having a first switching stage for generating a rectified intermediate voltage from a primary alternating voltage, a memory element for buffering the intermediate voltage generated by the first switching stage and a second switching stage for generating a secondary output voltage from the buffered intermediate voltage. The invention further relates to a working method for operating such a switching power supply.

Various types of switched-mode power supplies for supplying portable computers and other electronic devices with a secondary DC voltage generated from a primary AC mains voltage are known in the art. Basically, such switching power supplies have a relatively high efficiency and allow the design of lightweight and cost-effective power supplies for a variety of applications.

However, a disadvantage of known switching power supplies lies in the fact that they have a relatively poor efficiency in the so-called low-load range, ie in a work area in which the secondary-output power represents only a small fraction of a possible output power.

This problem is caused, inter alia, by the relatively high losses of the switching stages used in a switching power supply in the almost powerless area. In order to switch an electronic semiconductor switch, in particular a MOSFET transistor, one needs energy which is independent of the power to be switched. At higher switched powers, this energy hardly matters, whereas in the low load range, this energy accounts for a very high proportion of the power loss.

In particular, in devices of electronic data processing (EDP) and consumer electronics devices are often used that have a relatively high recording power in the range between 50 and 250 watts in a so-called standby or standby mode, however, only a recording power of less than 5 watts and often less than 1 watt.

An object of the present invention is to describe a switching power supply and a method of its operation, which improves the power loss of the switching power supply in the so-called low load range. In particular, solutions are to be shown that reduce the switching losses during operation of a switching power supply with 10 percent or less of its maximum output power.

Different embodiments of particularly energy-efficient switching power supplies and working methods for their operation are disclosed in the appended claims.

According to a first aspect of the present invention, a switching power supply is disclosed comprising a first switching circuit for generating a rectified intermediate voltage from a primary AC voltage, a storage element for latching the intermediate voltage generated by the first switching stage and a second switching stage for generating a secondary output voltage from the buffered intermediate voltage. The switching power supply has a control circuit for activating and deactivating the first switching stage, wherein the control circuit is adapted to monitor a dependent on the primary AC voltage first size and the first switching stage in at least one mode of the switching power supply in dependence of the first size for one of the Control circuit to activate certain portion of a first half-wave of the primary AC voltage and disable for at least a subsequent half cycle of the primary AC voltage.

The invention is based inter alia on the finding that by tuning the activation of a first switching stage for charging a memory element with an intermediate voltage with the half-waves of a primary AC voltage used to power the switching power supply and the deactivation of the first switching stage for one or more subsequent half-waves Improvement of the energy efficiency of the switching power supply can be achieved in total.

According to an advantageous embodiment, the control circuit is adapted to activate the first switching stage at the beginning of the first half-wave and to deactivate it at the end of the first half-wave. Such a procedure allows the use of the entire energy of a half wave and thus the reduction of the required switching cycles. At the same time, such an utilization of an entire half-wave leads to a significant improvement with respect to the harmonic distortion caused by the switched-mode power supply.

According to an advantageous embodiment, the control circuit is further configured to monitor a dependent of the state of charge of the memory element second size, in particular a level of the intermediate voltage, and in the at least one mode, the first portion of the first half-wave of the primary AC voltage for activating the first switching stage and determining the number of half-waves of the primary alternating voltage for deactivating the first switching stage as a function of the second variable. By taking into account the state of charge of the memory element, a reliable operation of the switching power supply can be ensured taking into account the highest possible energy efficiency.

According to an advantageous embodiment, the first switching stage at least one controllable by the control circuit semiconductor switching element for disconnecting an electrical connection between an input of the first switching stage for connecting the primary AC voltage and the memory element. By using a first semiconductor switching element to disconnect the first switching stage, the power consumption of the switching power supply can be controlled from a primary AC power supply network.

According to one embodiment, the first switching stage comprises at least one rectifier circuit for converting a primary alternating voltage into a primary direct voltage and at least one first switching converter for generating the intermediate voltage from the primary direct voltage. In this case, the at least one semiconductor switching element is arranged between the rectifier circuit and the switching converter.

In an advantageous embodiment, the control circuit is set up to monitor the level of the primary DC voltage. Such an arrangement allows a particularly simple monitoring of a state of the externally applied primary AC voltage.

According to a further advantageous embodiment, the control circuit comprises a microcontroller, wherein the microcontroller is adapted to specify a switching threshold for recharging the memory element as a function of a mode and / or output power of the second switching stage of the switching power supply. By adapting at least one switching threshold to an actual output power of the switching power supply, the use of predetermined parts or complete half-waves of a primary AC voltage can be ensured.

According to an advantageous embodiment, the microcontroller is used inter alia for driving a circuit for pulse width modulation, which is adapted to generate a pulse width modulated signal for driving at least one semiconductor switching element of the switching power supply, wherein the microcontroller is adapted to at least one operating parameter of the circuit for pulse width modulation in dependence from the operating mode and / or the output power of the second switching stage of the switching power supply to specify.

• – Überwachen wenigstens einer von der primären Wechselspannung abhängigen ersten Größe,
• – Aktivieren wenigstens einer ersten Schaltstufe des Schaltnetzteils zur Erzeugung einer gleichgerichteten Zwischenspannung aus der primären Wechselspannung für einen vorbestimmten Teilbereich einer ersten Halbwelle der primären Wechselspannung in Abhängigkeit der ersten Größe,
• – Zwischenspeichern der gleichgerichteten Zwischenspannung in einem Speicherelement,
• – Deaktivieren der wenigstens einen ersten Schaltstufe des Schaltnetzteils für wenigstens eine nachfolgende Halbwelle der primären Wechselspannung und
• – Erzeugen der sekundären Gleichspannung aus der zwischengespeicherten Zwischenspannung des Schaltnetzteils.

In another aspect, a method of operating a switched-mode power supply to generate a secondary DC voltage from a primary AC voltage is described. The method comprises the following steps:

• Monitoring at least one of the primary alternating voltage-dependent first variable,
• Activating at least one first switching stage of the switched-mode power supply to generate a rectified intermediate voltage from the primary alternating voltage for a predetermined partial area of a first half-wave of the primary alternating voltage as a function of the first variable,
• Buffering the rectified intermediate voltage in a memory element,
• - Disabling the at least one first switching stage of the switching power supply for at least one subsequent half-wave of the primary AC voltage and
• - Generating the secondary DC voltage from the cached intermediate voltage of the switching power supply.

The above-mentioned method steps synchronize the activation and deactivation of the first switching stage with the half-waves of a primary AC voltage used to supply the switching power supply. By using a predetermined part of the first half-wave, in particular the entire first half-wave, and the deactivation of the first switching stage for at least one subsequent half-wave, the switching losses of the switching power supply are reduced and simultaneously causes a reduction of harmonic distortion.

According to an advantageous embodiment, the method comprises the step of determining an activation frequency for activating the at least one first switching stage as a function of an operating mode and / or an output power of the at least one second switching stage such that the double frequency of the primary alternating voltage corresponds to an integer multiple of the determined activation frequency ,

By determining an activation frequency which is in a harmonic ratio of the frequency of the alternating voltage used for the supply, the harmonic distortion generated by the switching power supply or the circuitry required for their compensation can be reduced.

Further advantageous embodiments are described in the dependent claims and the disclosed in the following detailed description of exemplary embodiments.

The invention will be explained in more detail with reference to different embodiments with reference to the attached figures. In the different embodiments, the same reference types are used for the same or similar components.

In the figures show:

1 a schematic representation of a switching power supply according to different embodiments of the invention,

2A an exemplary current consumption of a switched-mode power supply together with a level of an alternating voltage,

2 B the time course of charge states of a memory element,

3 a circuit diagram of a first circuit according to a first embodiment of the invention,

4 a circuit diagram of a second circuit according to a second embodiment of the invention and

5 a circuit diagram of a third circuit according to a third embodiment of the invention.

6 a circuit diagram of a fourth circuit according to a fourth embodiment of the invention.

1 shows a schematic representation of a switching power supply 1 to power an electronic device 2 from an AC voltage of an AC power supply network 3 , According to the embodiment of the 1 it is an external switching power supply 1 , Of course, the solution according to the invention can also be used in integrated in a device switching power supplies.

A primary power input 4 of the switching power supply 1 is connected to a primary phase line L and a neutral conductor N of the AC power supply network 3 connected. The switching power supply 1 includes a rectifier 5 for converting the primary AC voltage into a primary DC voltage, a first switching stage 6 for converting the pulsating, primary DC voltage into an intermediate voltage and for power factor correction, a memory element 7 for latching the primary DC voltage and a second switching stage 8th for generating a stabilized secondary DC voltage V _s from the latched DC voltage of the memory element 7 , In some versions is the rectifier 5 in the first switching stage 6 integrated or not required at all.

The switching power supply 1 further comprises a control circuit 9 the operation of the switching power supply 1 controls. Preferably, the control circuit monitors 9 this at the primary power input 4 applied primary AC voltage or through the rectifier 5 generated pulsating primary DC voltage and the state of charge of the memory element 7 , The control circuit 9 in particular regulates the first switching stage used for power factor correction 6 and, optionally, the second switching stage used to generate the stabilized DC voltage V _s 8th ,

At the control circuit 9 It can either be a discrete control circuit or a by a microcontroller of the switching power supply 1 or the electronic device 2 act executed control program. In one embodiment, it is a combination comprising a microcontroller and a circuit for pulse width control, the microcontroller specifying parameter values such as a switch-on time, a switching frequency and / or a duty cycle for the pulse width control and the pulse width control the first switching stage 6 controls.

When the control circuit 9 also the second switching stage 8th it receives information from an associated control circuit, such as a switching frequency of the second switching stage 8th , which gives an indication of the current output power of the switching power supply 1 allow. Alternatively, the current output power or mode of operation may also be explicit from the electronic device 2 predetermined or via a measuring circuit in the switching power supply 1 be determined.

It should be noted that the switching power supply 1 in the 1 is shown only schematically and may contain other components, such as a manual on / off switch, connections for other secondary output voltages and active and passive line filter, which in the 1 are not shown for reasons of clarity.

To the power consumption of the power supply according to 1 compared to known switching power supplies to improve, a new sequence for power transmission through the first switching stage 6 of the switching power supply 1 proposed, at the same time to an improvement by the switching power supply 1 caused harmonic distortion.

The new sequence for power transmission is in the 2A exemplified. The in the 2A solid line represents a sinusoidal waveform of the primary AC voltage V _{p of} the AC power supply network 3 In addition to the course of the primary supply voltage V _p is in the 2 Furthermore, the course of the of the switching power supply 1 recorded primary operating current I _p shown. As is clear from the 2A results, are the recorded operating current I _p and the supply voltage V _p because of the phase-correcting input stage in the form of the first switching stage 6 in a fixed phase relationship. In particular, the absorbed current is for a first half-wave 11 proportional to the input voltage V _p . For two consecutive half-waves 12 and 13 takes the switching power supply 1 in each case no current I _p from the primary AC power supply network 3 on. From the fourth half-wave 14 the cycle of the first three half-waves is repeated 11 to 13 ,

From the 2A It can be seen that the activation frequency of the first switching stage 6 and the frequency of the primary supply voltage are in harmonic relationship. More specifically, duration T _S corresponds to a complete switching cycle of the first switching stage 6 an integer multiple of the duration T _{P of} a half-wave of the supply voltage V _p , namely 3 times, or generally T _S = n · T _P for any natural number n. At this point it should be noted that the activation frequency of the first switching stage 6 is typically independent of the switching frequency of a switching transistor contained therein, in particular a MOSFETs of a switching converter for generating the intermediate voltage.

Furthermore, it can be seen that a duty cycle for activating the first switching stage 6 in a fixed relationship to the mains frequency of the supply voltage V _p and the activation frequency of the first switching stage 6 stands. In the example, the duty cycle corresponds to 1/3, or generally 1 / n. As a result, a switch-on period is synchronized with the phase curve of the supply voltage V _p . The result is an offset, complete half-wave utilization.

In the 2 B is the time course of a state of charge of a memory element 7 , exemplified as the voltage V _{c of} a storage capacitor.

In conventional control of a first switching stage 6 an intermediate voltage remains largely constant (not shown). Alternatively, it is also possible to operate the first switching stage in a so-called burst mode in which the intermediate voltage is slightly between a fixed first switch-on threshold 21 and a fixed predetermined first turn-off threshold 22 fluctuates. In the illustrated course, in each case an indefinite fraction of one or two adjacent half-waves 12 to 14 for loading the memory element 7 used.

According to one embodiment of the invention, other switching thresholds are used, at least in a low load range, for example at a utilization of less than 10 percent of the maximum output power. For this purpose, the control circuit changes 9 a variable lower switch-on threshold 23 and / or a variable upper turn-off threshold 24 such that a switching cycle duration with an integer multiple of a half-wave of the primary supply voltage V _s results. The second switch-on threshold is preferred 23 opposite the first switching threshold 21 lowered in a normal mode and / or the second switch-off 24 opposite the first switch-off threshold 22 raised. In the illustrated course, the charging phase corresponds exactly to the first half-wave 11 and a subsequent discharge phase the three half-waves 12 to 14 , The turn-on times are preferably synchronized with zero crossings of the primary supply voltage V _s .

In the illustrated embodiment, in each case a complete half-wave 11 for power transmission from the primary AC power supply network 3 to the storage element 7 used. By the appropriate control of switching elements of the first switching stage 6 Thus, in particular, a phase contact and phase section can be dispensed with at any time in the phase characteristic of the primary supply voltage V _p, as in the burst mode described above. In addition to saving energy by effectively reducing the switching frequency, this also results in the switching power supply 1 produces only a very small harmonic distortion and thus has a very good so-called total Harmonic Distortion (THD) value.

Instead of in the 2A and 2 B shown staggered use of complete sine half-waves can also be used portions of staggered half-waves. Alternatively or additionally, the control 9 also be set up with the first half-wave 11 transmitted power in the memory element 7 to regulate the power loss of the switching power supply 1 to minimize. For example, a charging current for the memory element 7 be reduced in a low load range to the utilization of a full half wave 11 to enable. For example, it is possible, the duty cycle of a switching converter of the first switching stage 6 to select such, related the best possible efficiency is achieved on the complete charging cycle within a half-wave.

In one embodiment, the adaptation of the sequence of power transmission to the current output power of the switching power supply 1 essentially by determining the number of half-waves in which no power from the AC supply network 3 is received by the control circuit 9 certainly. For example, assume that the power consumption of the electronic device 2 in another mode versus the power consumption according to the situation 2A halved again, would be omitted in the fourth half wave 14 provided power consumption completely, so that effectively further halving the activation frequency for the first switching stage 6 would result.

To further improve the efficiency at very small secondary output powers, it is also possible to use the second switching stage 8th disable for predetermined periods. For example, a pulse width modulated control signal of the control circuit 9 for controlling the second switching stage 8th in the period of unused half-waves 12 and 13 be prevented, provided that the secondary side has a corresponding buffer capacity or tolerance with respect to the input voltage.

3 shows an exemplary circuit 30 that the function of the rectifier 5 and the first switching stage 6 Combined and the realization of a switching power supply 1 is suitable according to an embodiment of the invention.

The circuit 30 according to 3 includes a rectifier circuit 35 comprising the diodes D1 to D4, which essentially form a so-called Graetz bridge. At a first node 31 behind the rectifier circuit 35 the magnitude of the rectified, pulsating voltage V _{1 is determined} with respect to a reference electrical potential GND. The magnitude of the voltage V ₁ becomes a logic circuit 32 for controlling the first switching stage 6 fed.

The logic circuit 32 controls both a first switching transistor Q1 for activating the first switching stage 6 as well as a second switching transistor Q2, which is the actual switching element of the switching converter 33 forms. The switch Q1 is from the logic circuit 32 during a first half-wave 11 closed to the first switching stage 6 to activate. During subsequent half waves 12 and 13 opens the logic circuit 32 the switch Q1 to the switching converter 33 from the rectifier circuit 35 to separate.

In the switching converter 33 In the illustrated embodiment, in particular, a circuit for power factor correction according to the principle of an inverse converter (English: Buck Boost Converter). When switch Q2 is closed, a current flows from the primary power input 4 through the switch Q1, a coil L1 and the switch Q2. In this way, the core of coil L1 is magnetized to draw energy from the primary AC power supply network 3 temporarily. When the switch Q2 is interrupted, the inductance of the coil L1 causes the current flow through the coil L1 to be maintained. The current flows in this case via the diode D5 to a storage element 7 used storage capacitor C1 and back via the diode D6 to the coil L1. The capacitor C1 is thus charged in this circuit architecture in the periods in which no energy transfer from the primary network input 4 to the switching converter 33 takes place. The switching frequency of the second switch Q2 is significantly greater than the activation frequency of the first switch Q1 in the exemplary embodiment and is typically in the range of several kHz.

Because of the separation of the switching converter 33 from the primary power input 4 By the switch Q1, the intermediate voltage of the capacitor C1 can be lowered to a voltage below the maximum voltage of the primary AC voltage, without resulting in an unwanted recharging of the capacitor C1. For example, a nominal AC voltage of 240 volts has a maximum peak voltage of about 340 volts, which would result in the charging of an intermediate voltage of 300 volts across capacitor C1.

In an advantageous embodiment, the logic circuit monitors 32 according to the embodiment, in addition to the height of the voltage V ₁ at the first node 31 also the state of charge of the capacitor C1 via its charging voltage V _c at a second node 34 , In rejection of known control circuits, the activation of the switch is not made Q1 and Q2 in this embodiment, only by the height of the capacitor voltage on capacitor C1 depends but additionally selected in dependence on the primary supply voltage V _p.

In the exemplary embodiment, the logic circuit switches 32 the transistor Q1 only when a predetermined lower state of charge of the capacitor C1 has been reached and the primary-side supply voltage passes through a zero point. The logic circuit 32 turns off transistor Q1 when a subsequent zero crossing has been detected. As a result, the logic circuit switches 32 the transistor Q1 at a time in a fixed relationship to the half-waves and the frequency of the AC power supply network 3 stands. there is ensured by monitoring the capacitor voltage V _C that the storage capacitor C1 is always sufficiently charged to one in the 3 not shown secondary switching stage 8th to supply with a sufficient input voltage V _c .

4 shows a second embodiment of a circuit 40 according to a second embodiment of the invention. The functioning of one in the circuit 40 contained switching converter 41 for power factor correction largely corresponds to that of the switching converter 31 according to the embodiment according to 3 ,

Deviating from the 3 were a circuit 41 for power factor correction and a circuit 43 for rectifying the primary supply voltage V _p in the circuit 40 combined together. In particular, the diodes D3 and D4 and the first switching element Q1 of the circuit 30 according to 3 in the semiconductor switching elements Q3 to Q6 of the circuit 40 according to 4 united. By the use of two each antiparallel MOSFET transistors Q3 and Q4 or Q5 and Q6, a logic circuit 42 the over the network entrance 4 provided primary AC voltage from the coil L1 of the switching converter 41 separate. By phase-controlled driving of the transistors Q3 to Q6 by the logic circuit 42 These take over in conjunction with the diodes D1 and D2 simultaneously the function of a rectifier circuit 43 ,

For correct driving of the transistors Q3 to Q6 and for monitoring the phase characteristic of the primary AC voltage is the logic circuit 42 im in the 4 illustrated embodiment directly to the primary power input 4 connected. Incidentally, the function of the circuit corresponds 40 that of the circuit 30 according to 3 ,

Instead of in the 4 Two transistors Q3 to Q6 can also be used, two thyristors can be used. For reasons of energy efficiency, however, the use of two MOSFET transistors per branch of the rectifier circuit is currently 40 preferred, since they have a lower power loss than known thyristors.

5 shows a circuit 50 for the realization of a first switching stage 6 without separate rectifier 5 according to a third embodiment of the invention. This is a so-called nested switching converter with two parallel switching stages 51 and 52 for power factor correction. Therein processes the first switching stage 51 a positive half-wave of a sinusoidal primary supply voltage V _s and the second switching stage by means of a first switching transistor Q1 52 by means of a second switching transistor Q2, a negative half-wave of the sinusoidal supply voltage V _s . The driving of the transistors Q1 and Q2 is carried out as previously with reference to the 3 and 4 described by a logic circuit 53 ,

Furthermore, the circuit includes 50 a third transistor Q3 and a fourth transistor Q4 for disconnecting the first switching stage 51 or second switching stage 52 from a primary mains voltage V _P. To correctly drive the transistors Q3 and Q4 monitors the logic circuit 53 Both the state of charge of the capacitor C1 and the height of the primary supply voltage V _p and their phase passages as already with respect to the capacitor Q1 of the circuit 30 according to 3 has been described.

Each of the circuits 30 . 40 and 50 according to the 3 to 5 allows electrical isolation between the primary supply input and a memory element 7 , in particular a capacitor C1 of a DC link. This allows, as described above, a lowering of a voltage V _{C of} the intermediate circuit and thus serves to improve the energy balance.

However, to simplify the circuit, it is also possible to dispense with a complete network separation and instead the voltage V _{C of} the memory element 7 to raise to a value above the maximum peak voltage of the primary supply voltage V _P. The increase takes place for example by appropriate design or control of the first switching stage 6 ,

In the figure is a circuit 60 illustrated according to a fourth embodiment of the invention. The circuit 60 largely corresponds to the circuit 50 according to 50 , Deviating from that was in the circuit 50 Transistors Q3 and Q4 used for grid separation are dispensed with. In addition, a logic circuit 61 for controlling the first switching converter 51 and the second switching converter 52 provided, which already takes into account the phase position of the primary supply voltage V _P in the control of the switching transistors Q1 and Q2. For example, the logic circuit is 61 based on the example 2A only in the period of the first half-wave 11 Control pulses to the first transistor and only in the period of the fourth half-wave 14 Drive pulses to the second transistor Q2 from. In this case, the activation sequence and the duty cycle for driving the transistors Q1 and Q2 is selected so that the charging voltage V _{C of} the capacitor C1 is always above a threshold which corresponds to a maximum peak voltage of the primary supply voltage V _P , so that when transistors Q1 and Q2 no electrical power is taken from the primary supply network.

The features described with respect to the individual embodiments can be combined with each other in a variety of ways. Although the circuits 30 . 40 . 50 and 60 according to the 3 to 6 have been shown in detail by means of different types of switching converter, the related circuit design of the first switching stage 6 for the achievement of the advantages of the invention largely irrelevant.

Beneficial for reducing the harmonic distortion of the switching power supply 1 It is an activation period for connecting a primary network input 4 with the sharing of the first switching stage 6 , in particular with a storage coil and / or a storage capacitor, used to select switching element so that the activation period corresponds to an integer multiple of a duration of a half-wave of the primary supply voltage V _s . In addition, it is advantageous to synchronize the activation time of such a switching element with the zero crossings of the primary supply voltage V _p . Finally, it is advantageous for reducing the energy consumption and thus for increasing the efficiency of the switching power supply 1 in total, an adaptation of the first switching stage 6 to the one from the power supply 1 Regulated absorbed or delivered power by extending the offset between each active half-waves of a primary supply voltage. Alternatively or additionally, the threshold values for activating or deactivating the first switching stage can also be used 6 be adjusted in response to a charge of a capacitor of the intermediate circuit to allow a vote of the activation periods with the half-waves of a primary supply voltage.

LIST OF REFERENCE NUMBERS

1

 Switching Power Supply

2

 electronic device

3

 AC power supply network

4

 primary power input

5

 rectifier

6

 first switching stage

7

 storage element

8th

 second switching stage

9

 control circuit

11

 first half wave

12

 second half-wave

13

 third half wave

14

 fourth half-wave

21

 first switch-on threshold

22

 first switch-off threshold

23

 second switch-on threshold

24

 second switch-off threshold

30

 first circuit

31

 first node

32

 logic circuit

33

 switching converters

34

 second node

35

 Rectifier circuit

40

 second circuit

41

 switching converters

42

 logic circuit

43

 Rectifier circuit

50

 third circuit

51

 first switching stage

52

 second switching stage

53

 logic circuit

60

 fourth circuit

61

 logic circuit

Claims (16)

Switching power supply ( 1 ), comprising: - a first switching stage ( 6 ) for generating a rectified intermediate voltage (V _C ) from a primary AC voltage (V _p ); A memory element ( 7 ) for the intermediate storage of the first switching stage ( 6 ) generated intermediate voltage (V _c ); A second switching stage ( 8th ) for generating a secondary output voltage (V _s ) from the latched intermediate voltage (V _c ); and - a control circuit ( 9 ) for activating and deactivating the first switching stage ( 6 ); wherein - the control circuit ( 9 ) is adapted to monitor one of the primary AC voltage (V _p ) dependent first size and the first switching stage ( 6 ) in at least one operating mode of the switched-mode power supply ( 1 ) in dependence on the first size for one by the control circuit ( 9 ) certain subarea of a first half-wave ( 11 ) of the primary alternating voltage and for at least one subsequent half wave ( 12 . 13 ) of the primary AC voltage (V _p ). Switching power supply ( 1 ) according to claim 1, wherein the control circuit ( 9 ) is adapted to the first switching stage ( 6 ) at the beginning of the first half-wave ( 11 ) and at the end of the first half-wave ( 11 ). Switching power supply ( 1 ) according to claim 1 or 2, comprising means for determining an output power of the switched-mode power supply ( 1 ), wherein the control circuit ( 9 ) is arranged, depending on the particular output power, a number of half-waves ( 12 . 13 ) of the primary alternating voltage for which the first switching stage ( 6 ) is deactivated. Switching power supply ( 1 ) according to one of claims 1 to 3, comprising means for regulating the input power of the first switching stage ( 6 ), wherein the control circuit ( 9 ) is adapted to the input power depending on the output power and / or the determined number of half waves ( 12 . 13 ). Switching power supply ( 1 ) according to one of claims 1 to 4, characterized in that the control circuit ( 9 ) is further adapted to the second switching stage ( 6 ) for the at least one subsequent half wave ( 12 . 13 ) of the primary AC voltage (V _p ). Switching power supply ( 1 ) according to one of claims 1 to 5, in which the control circuit ( 9 ) is further adapted to one of a state of charge of the memory element ( 7 ) dependent second size, in particular a height of the intermediate voltage (V _c ) to monitor and in the at least one mode, the portion of the first half-wave ( 11 ) of the primary alternating voltage (V _p ) for activating the first switching stage ( 6 ) and the number of halfwaves ( 12 . 13 ) of the primary alternating voltage (V _p ) for deactivating the first switching stage ( 6 ) depending on the second size. Switching power supply ( 1 ) according to one of claims 1 to 6, in which the control circuit ( 9 ) and / or the first switching stage ( 6 ) are further adapted to effect a power factor correction of the switched-mode power supply ( 1 ). Switching power supply ( 1 ) according to one of claims 1 to 7, in which the first switching stage ( 6 ) at least one controllable by the control circuit switching element, in particular a semiconductor switching element, for disconnecting an electrical connection between an input ( 4 ) of the first switching stage ( 6 ) for connecting the primary alternating voltage (V _p ) and the memory element ( 7 ) having. Switching power supply ( 1 ) according to claim 8, wherein the first switching stage ( 6 ) at least one rectifier circuit ( 35 ) for converting the primary alternating voltage (V _p ) into a primary direct voltage (V ₁ ) and at least one first switching converter ( 33 ) for generating the intermediate voltage (V _c ) from the primary DC voltage, wherein the at least one switching element between the rectifier circuit ( 35 ) and the switching converter ( 33 ) is arranged. Switching power supply ( 1 ) according to claim 9, in which the control circuit ( 9 ) is adapted to monitor the magnitude of the primary DC voltage (V ₁ ). Switching power supply ( 1 ) according to one of claims 1 to 10, wherein the control circuit comprises a microcontroller, wherein the microcontroller is adapted to a switching threshold for a recharging of the memory element ( 7 ) as a function of an operating mode and / or output power of the second switching stage ( 8th ) pretend. Switching power supply ( 1 ) according to claim 11, wherein the control circuit ( 9 ) further comprising a with at least one semiconductor switching element of the switching power supply ( 1 ) connected pulse width modulation circuit, which is adapted to generate a pulse width modulated signal for driving the at least one semiconductor switching element, and wherein the microcontroller is adapted to at least one operating parameter of the pulse width modulation circuit depending on the operating mode and / or the output power of the second Switching stage ( 8th ) of the switching power supply ( 1 ) pretend. Working method for a switching power supply ( 1 ) for generating a secondary DC voltage (V _s ) from a primary AC voltage (V _p ) comprising the steps of: - monitoring at least one of the primary AC voltage (V _p ) dependent first size; Activating at least one first switching stage ( 6 ) of the switching power supply ( 1 ) for generating a rectified intermediate voltage (V _c ) from the primary alternating voltage (V _p ) for a predetermined partial range of a first half-wave ( 11 ) of the primary alternating voltage (V _p ) as a function of the first variable; - Caching the rectified intermediate voltage (V _c ) in a memory element ( 7 ); Deactivating the at least one first switching stage ( 6 ) of the switching power supply ( 1 ) for at least one subsequent half wave ( 12 . 13 ) of the primary AC voltage (V _p ); and - generating the secondary DC voltage (V _s ) from the intermediately stored intermediate voltage (V _c ) of the switched-mode power supply ( 1 ). Working method according to Claim 13, in which the first switching stage ( 6 ) at the beginning of the first half-wave ( 11 ) is activated and in which the first switching stage ( 6 ) at the end of the first half-wave ( 11 ) is deactivated. A method of operation according to claim 13 or 14, comprising the additional step of: - determining an activation frequency for activating the at least one first switching stage ( 6 ) in dependence on an operating mode and / or output power of the at least one second switching stage ( 8th ) such that the double frequency of the primary AC voltage corresponds to an integer multiple of the determined activation frequency. Working method according to one of claims 13 to 15, with the additional steps of: - determining a lower and an upper switching threshold ( 23 . 24 ) for reloading the memory element ( 7 ) depending on a mode and / or output of the switching power supply ( 1 ); Continuous monitoring of a state of charge of the memory element ( 7 ); - activate the first switching stage ( 6 ) when the monitored state of charge reaches or falls below the lower threshold ( 23 ); and deactivating the first switching stage ( 6 ), if the monitored state of charge exceeds the upper threshold ( 24 ) reaches or exceeds.

Images