DE102011115656B4 - Semiconductor detector with a buffer for signal charge carriers and corresponding operating method - Google Patents

Abstract

Semiconductor detector for the detection of radiation with a) a semiconductor substrate (HS), whereby the radiation to be detected falls into the semiconductor substrate (HS) and generates signal charge carriers in the semiconductor substrate (HS), b) a DEP-FET integrated into the semiconductor substrate (HS) Structure (S, G, D, IG) which detects the radiation-generated signal charge carriers and generates an electrical output signal as a function of the radiation-generated signal charge carriers, c) where the DEPFET structure (S, G, D, IG) has a controllable conduit (K) and an internal gate (IG) which is buried in the semiconductor substrate (HS) under the conduction channel and receives the signal charge carriers, so that the signal charge carriers accumulated in the internal gate (IG) control the conduction channel (K), characterized by d) at least an intermediate store (PM) for the signal charge carriers, the intermediate store (PM) from the internal gate (IG) of the DEPFET structure (S, G, D, IG) g is separated and temporarily stores the radiation-generated signal charge carriers before the radiation-generated signal charge carriers are transferred to the internal gate of the DEPFET structure for reading.

Description

The invention relates to a semiconductor detector for the detection of radiation and a corresponding operating method according to the independent claims.

Semiconductor drift detectors for radiation detection have been known for some time and are described, for example, in LUTZ, Gerhard: "Semiconductor radiation detectors", Springer-Verlag 1999. In this case, the radiation to be detected generates signal electrons in a lightly doped, depleted semiconductor substrate, wherein a plurality of annular and concentrically arranged electrodes are arranged on one surface of the semiconductor substrate, which generate a drift field in the semiconductor substrate through which the signal electrons generated by the radiation are centered Readout element drift, which detects the signal electrons and thus the received radiation.

The readout element can consist of a DEPFET transistor (DEPFET: Depleted Field Effect Transistor), which was invented in 1984 by J. Kemmer and G. Lutz and, for example, in US Pat DE 10 2004 004 283 A1 is described. Such a DEPFET transistor may comprise a weakly n-doped, depleted semiconductor substrate, wherein on a surface of the semiconductor substrate, a heavily p-doped back electrode is arranged, which forms a reversely poled diode with the weakly n-doped semiconductor substrate and depletion of the semiconductor substrate is used, wherein in the semiconductor substrate caused by exposure to radiation holes are sucked through the back electrode from the semiconductor substrate.

On the opposite surface of the semiconductor substrate is located in a DEPFET transistor as a readout element, a heavily p-doped source region and also a heavily p-doped drain region, wherein between the source region and the drain region can form a conduction channel , whose conductivity can be adjusted by an externally controllable gate electrode.

In this case, a weakly n-doped inner gate region, in which the signal electrons formed in the semiconductor substrate by the action of radiation collect, is located below the conduction channel in the semiconductor substrate. The electrical charge accumulated in the inner gate region controls the conductivity of the conduction channel between the source region and the drain region in a manner similar to the external gate electrode, so that the drain-source current of the DEPFET transistor is a measure of the detected radiation is.

In such a pixel detector with a multiplicity of image cells (pixels) arranged in rows and columns in the form of a matrix, the individual image cells are as a rule read out sequentially. This has the disadvantage that during the read-out process, incident photons in the already read-out image cells no longer contribute to the output signal, whereas the image cells, which have not yet been read, still detect the incident photons. A disadvantage of the conventional semiconductor detectors is therefore the fact that the different image cells have a different signal integration interval. In many applications, however, one would like to take a whole picture at a fixed time, whereby the individual picture cells should reproduce the same time of the picture to be recorded.

A solution to this problem is out EP 1 873 834 B1 known. Thus, this patent discloses a semiconductor detector which can be switched insensitive during the read-out process and then no longer detects any further radiation. This offers the advantage that all image cells detect the radiation that has fallen into place until the insensitive state is set, so that all image cells have the same signal integration interval. However, in this case, radiation-generated signal charge carriers, which are generated outside the sensitive state, are dissipated directly to an erase contact and are therefore lost.

Furthermore, it should be noted on the prior art WO 2006/018477 A1 and US 5 712 498 A ,

The invention is therefore based on the object to provide a better solution to the above-mentioned problem, according to which the output signal of the individual picture cells is to reproduce the same recording time.

This object is achieved by a semiconductor detector according to the invention and a corresponding operating method according to claims 1 and 19. The features of the respective preamble are from the EP 1 873 834 B1 known.

The invention starts from the conventional semiconductor detector described above with a semiconductor substrate, wherein the radiation to be detected is incident on the semiconductor substrate and generates signal charge carriers in the semiconductor substrate, the signal charge carriers generally being signal electrons.

Furthermore, the semiconductor detector according to the invention comprises, in a manner known per se, an integrated DEPFET structure as readout element, wherein the DEPFET structure detects the radiation-generated signal charge carriers and as a function of generates an electrical output signal to the radiation-generated signal charge carriers. The DEPFET structure has for this purpose a controllable conduction channel and an internal gate, which is buried in the semiconductor substrate under the conduction channel and receives the signal charge carriers, so that the accumulated in the internal gate signal charge carriers control the conduction channel. This mode of operation of the semiconductor substrate and the DEPFET structure serving as a readout element is known per se from the prior art and therefore does not need to be described in detail.

The invention is characterized in that the radiation-generated signal charge carriers do not immediately enter the internal gate of the DEPFET structure, but are first stored separately in at least one intermediate memory from the internal gate of the DEPFET structure, before the radiation-generated signal charge carriers are then read out the internal gate of the DEPFET structure are transferred.

During the actual measuring process, the incident radiation thus generates signal charge carriers in the semiconductor substrate, which then collect in the buffer separately from the internal gate of the DEPFET structure. The isolation of the latch from the internal gate of the DEPFET structure is important so that the signal charge carriers accumulated in the latch do not affect the conduction channel of the DEPFET structure.

After this measuring process, a read-out process then takes place in order to measure the incident radiation. At first, the signal charge carriers accumulated in the buffer are transferred from the buffer into the internal gate of the DEPFET structure. The signal charge carriers located in the internal gate then control the conduction channel of the DEPFET structure, which leads to a corresponding electrical output signal of the DEPFET structure, the electrical output signal being a measure of the signal charge carriers generated during the measurement process by the incident radiation.

The invention has the advantage that the actual measurement process can be separated from the read-out process, so that the individual DEPFET structures in the individual image cells can be read out sequentially, while the incident radiation already generates signal charge carriers in the individual image cells, which then enter into the image cells respective caching of the individual image cells are stored.

In a preferred embodiment of the invention, the semiconductor detector has a transfer mechanism for transferring the signal charge carriers stored in the buffer into the internal gate of the DEPFET structure so that the radiation-generated signal charge can then be read out from the DEPFET structure. In this case, the transfer mechanism can preferably be actuated by at least one external control signal, the transfer mechanism selectively transferring the signal charge carriers stored in the buffer into the internal gate of the DEPFET structure or leaving them in the buffer in response to the external control signal. The transfer of the radiation-generated signal charge carriers accumulated in the buffer into the internal gate of the DEPFET structure can therefore be triggered by the external control signal.

In addition, the semiconductor detector according to the invention preferably has an erase contact arrangement in order to be able to erase the signal charge carriers stored in the intermediate memory by removing the signal charge carriers via the erase contact arrangement. The transfer mechanism preferably serves not only to transfer the radiation-generated signal charge carriers from the buffer into the internal gate of the DEPFET structure, but preferably also allows the signal charge carriers accumulated in the buffer to be transferred to the clear contact arrangement. Again, the transfer mechanism is preferably triggered by the external control signal or by the external control signals, wherein the transfer mechanism leaves the stored in the latch signal charge carrier in response to the external control signal either in the buffer or transferred to the internal gate of the DEPFET structure or to transferred to the erase contact arrangement.

• – Überführen der strahlungsgenerierten Signalladungsträger aus dem Zwischenspeicher in das interne Gate der DEPFET-Struktur,
• – Überführen der in dem internen Gate der DEPFET-Struktur gesammelten Signalladungsträger zu der ersten Lösch-Kontaktanordnung, um das interne Gate der DEPFET-Struktur zu löschen.
• – Überführen der in dem Zwischenspeicher gespeicherten Signalladungsträger zu der zweiten Lösch-Kontaktanordnung, um die in dem Zwischenspeicher gespeicherten Signalladungsträger zu löschen.
• – Inaktiver Zustand des Überführungsmechanismus, wobei die in dem Zwischenspeicher befindlichen Signalladungsträger in dem Zwischenspeicher verbleiben und neue Ladungsträger zusätzlich gesammelt werden, während die in dem internen Gate der DEPFET-Struktur befindlichen Signalladungsträger in dem internen Gate verbleiben.

In the preferred embodiment of the invention, the semiconductor detector comprises two erase contact arrangements, namely a first erase contact arrangement for erasing the signal charge carriers from the internal gate of the DEPFET structure and a second erase contact arrangement for erasing the signal carriers from the cache. The transfer mechanism thus enables the following transfer processes in dependence on the external control signal or the external control signals:

• Transferring the radiation-generated signal charge carriers from the buffer into the internal gate of the DEPFET structure,
• Transferring the signal charge carriers collected in the internal gate of the DEPFET structure to the first erase contact arrangement to erase the internal gate of the DEPFET structure.
• Transferring the signal charge carriers stored in the buffer to the second one Erase contact arrangement for erasing the signal charge carriers stored in the temporary memory.
• Inactive state of the transfer mechanism, wherein the signal charge carriers located in the buffer remain in the buffer and additional charge carriers are collected while the signal charge carriers located in the internal gate of the DEPFET structure remain in the internal gate.

The two above-mentioned erase contact arrangements for erasing the latch of the DEPFET structure are preferably arranged on opposite sides of the DEPFET structure and the buffer so that the DEPFET structure is located between the two erase contact arrangements.

It should also be mentioned that the DEPFET structure with its line channel is preferably arranged transversely to a connecting line between the two erase contact arrangements. This means that the signal charge carriers accumulated in the internal gate of the DEPFET structure are removed in an erase operation across the conduction channel of the DEPFET structure.

By contrast, the buffer is preferably located between the DEPFET structure and the erase contact arrangement for the buffer. This means that the signal charge carriers accumulated in the buffer are transferred in one direction upon erasure, whereas the transfer of the signal electrons from the buffer into the internal gate of the DEPFET structure occurs in the opposite direction.

It should also be mentioned that the transfer mechanism preferably has a controllable transfer gate in order to control the transfer of the signal charge carriers from the buffer into the internal gate of the DEPFET structure, wherein the transfer gate preferably surrounds the DEPFET structure in an annular manner.

In addition, the transfer gate may also annularly surround the erase contact arrangement for the internal gate of the DEPFET structure. This means that the DEPFET structure, together with its associated erase contact arrangement, is located within the annular transfer gate.

It should also be mentioned that the generation of radiation-generated signal charge carriers directly underneath the erase contact arrangements involves the risk that the radiation-generated signal charge carriers will be captured directly by the respective erase contact arrangement. To solve this problem, in the preferred embodiment of the invention, a shield is provided in the semiconductor substrate, the shield preferably consisting of a buried p-type dopant disposed under the respective erase contact arrangement and shielding it from radiation-generated signal charge carriers.

Particularly advantageous is the realization of the invention in a semiconductor detector with a plurality of image cells, which may be arranged for example in a matrix in rows and columns. In this case, each image cell is preferably assigned a DEPFET structure as readout element and an intermediate memory. The transfer mechanism then transfers the signal charge carriers stored in the latches of the individual image cells to the internal gates of the associated DEPFET structures, collectively and substantially simultaneously with all the image cells of a group. For example, in this way, all image cells of a row or a column can be read jointly and substantially simultaneously by transferring the signal charge carriers from the latches of the group (row or column) into the internal gates of the associated DEPFET structures. After this transfer of the buffered signal charge carriers in the DEPFET structures, the image cells can then detect radiation again, while the DEPFET structures are read out sequentially.

The semiconductor detector according to the invention is therefore preferably connected to an external read-out electronics, which reads the individual DEPFET structures of the individual image cells in a conventional manner. The read-out of the individual DEPFET structures preferably takes place sequentially, while radiation-generated signal charge carriers are already collected again in the latches of the individual image cells.

• – Halbleitersubstrat: schwach n-dotiert.
• – Rückkontakt des Halbleitersubstrats: p-dotiert (dient als Strahlungs-Eintrittsfenster und wird dafür optimiert)
• – Drain, Source und Oberflächendotierung des Halbleitersubstrats: stark p-dotiert.
• – Lösch-Kontakte: stark n-dotiert.
• – Zwischenspeicher, internes Gate und tiefe Dotierung: n-dotiert.
• – Abschirmungen: p-dotiert.

In the preferred embodiment, the following doping ratios are present within the various regions of the semiconductor detector according to the invention:

• Semiconductor substrate: weakly n-doped.
• - back contact of the semiconductor substrate: p-doped (serves as a radiation entrance window and is optimized for this)
• - Drain, source and surface doping of the semiconductor substrate: heavily p-doped.
• - Erase contacts: heavily n-doped.
• - Latch, internal gate and deep doping: n-doped.
• - Shielding: p-doped.

However, it is also possible in principle to invert the doping ratios correspondingly or to modify the doping thereof, in order, for. B. to obtain an optimized beam entrance window.

It should also be mentioned that the invention not only comprises the semiconductor detector described above, but also relates to a corresponding operating method, which already results from the above description, so that a separate description of the operating method can be dispensed with.

Other advantageous developments of the invention are characterized in the subclaims or are explained in more detail below together with the description of the preferred embodiments of the invention with reference to FIGS. Show it:

1 a plan view of a semiconductor detector according to the invention,

2 a cross-sectional view through the semiconductor detector according to 1 along the section line AA,

3 a cross-sectional view through the semiconductor detector according to 1 along the section line BB,

4 a cross-sectional view through the semiconductor detector according to 1 along the section line CC,

5 a modification of 1 with a double DEPFET structure in which the two DEPFETs have a common source,

6 a plan view of a semiconductor detector according to the invention, in which the buffer is designed as a MOS structure,

7 a cross-sectional view through the semiconductor detector according to 6 along the section line BB,

8A and 8B the operating method according to the invention in the form of a flowchart,

9 a variant of the operating method according to the invention in the form of a flow chart, and

10 a schematic representation of a two-dimensional, matrix-shaped detector structure with numerous image cells.

The 1 to 4 show various views of a semiconductor detector according to the invention, the drawings are shown only schematically and show no scale reproduction.

As a basic element, the semiconductor detector has a weakly n-doped semiconductor substrate HS, wherein a p-doped back contact R is arranged in a planar manner on the rear side of the semiconductor substrate HS.

In this case, the radiation to be detected enters the semiconductor substrate HS through the back contact R and generates signal charge carriers which are initially collected in a buffer PM in the form of an (electron) potential minimum before the signal charge carriers collected in the buffer PM are then read out in an internal gate IG of a DEPFET structure are transferred, as will be described in detail.

The DEPFET structure used for reading out the radiation-generated signal charge carriers conventionally consists of an external gate G, a source S, a drain D, a conduction channel K between the source S and the drain D, and an internal gate IG, which is present in the semiconductor substrate HS is buried under the duct K. In this case, the internal gate IG of the DEPFET structure forms a potential maximum in which the signal charge carriers transferred from the intermediate memory PM can collect. The signal charge collected in the internal gate IG of the DEPFET structure then conventionally controls the conductivity of the conduction channel K, so that the DEPFET structure outputs an electrical output signal which forms a measure of the signal charge accumulated in the internal gate IG.

On the surface of the semiconductor substrate HS, laterally adjacent to the DEPFET structure, there is an erase contact arrangement with a clear contact CL1 for dissipating the signal charge carriers collected in the internal gate IG during an erase operation. In addition, the erase contact arrangement also includes a clear gate CG1 which controls the erase operation. The erase contact arrangement consisting of the erase contact CL1 and the clear gate CG1 thus serves to erase the signal charge accumulated in the internal gate IG of the DEPFET structure.

On the opposite side is another erase contact arrangement which has the task of erasing the signal charge accumulated in the buffer PM. This erase contact arrangement also has an erase contact CL2 and a clear gate CG2 to control the erase contact.

During operation of the semiconductor detector, there is the danger that signal charge carriers, which are generated directly below the two clear contacts CL1, CL2 by the incident radiation, are captured by the clear contacts CL1 and CL2, respectively, and therefore not in the buffer PM or get into the internal gate IG. Therefore, in each case a shield SHLD1 or SHLD2 is arranged under the two clear contacts CL1 and CL2, the two shields SHLD1, SHLD2 consisting of a buried p-doping. The two shields SHLD1, SHLD2 thus prevent signal charge carriers generated below the clear contacts CL1, CL2 from being captured directly by the clear contacts CL1, CL2.

In addition, located at the top of the semiconductor detector, a transfer gate TG, which surrounds the DEPFET structure and the erase contact arrangement CL1, CG1 annular and is part of a transfer mechanism, the transfer of the signal charge carriers from the buffer PM in the internal gate IG The DEPFET structure controls, as will be described in detail.

Furthermore, a heavily p-doped surface doping SB, which is also known per se from the prior art, is located on the upper side of the semiconductor detector.

Furthermore, a buried n-doping dn is located in the semiconductor substrate HS, along which radiation-generated signal charge carriers can reach the intermediate memory PM and then to the internal gate IG.

The 5 shows a modification of 1 where the simple DEPFET is a double DEPFET arrangement with common source S but otherwise separate gates G1, G2, drains D1, D2 and internal gates. Furthermore, at least one shift gate SG is provided for shifting the signal charge between the internal gates of the two DEPFETs. With this arrangement, the same charge can be measured repeatedly and thus the measurement accuracy can be increased drastically.

The 6 and 7 show a further modification of 1 , wherein the buffer PM is generated not by a doping, but by a MOS structure (MOS: Metal Oxide Semiconductor) with a suitably selected gate voltage. With more complicated arrangements of MOS structures and dopings, it is also possible to generate a plurality of separately controllable latches in which a signal collection takes place. Likewise, the transfer of the collected signal charge from a selected latch into the internal gate IG can be controlled.

The following is now with reference to the flowchart in the 8A and 8B the operation method of the semiconductor detector described above is explained.

In a first step S1, first the source S of the DEPFET structure is driven with a zero potential. Furthermore, the back contact R is driven with a negative potential, while the surface doping SB is at a moderately positive potential. In this case, it is assumed as the initial state that all the electrons have already been removed from the semiconductor substrate HS (English "bulk") of the semiconductor detector, so that the volume of the semiconductor substrate HS is depleted. Thus, between the two main surfaces of the semiconductor substrate HS, approximately at the depth of the buried n-doping dn, a potential back is formed, which, given a correspondingly negative potential on the transfer gate TG, is separated from one another at the positions of the intermediate memory PM and the internal gate IG Has potential maxima, in which signal charge carriers can collect.

In a second step S2, the radiation to be detected is then introduced into the sensitive region of the semiconductor substrate HS, wherein the incident radiation generates signal charge carriers.

The radiation-generated signal charge carriers are then initially collected in the potential well of the temporary storage PM in a step S3.

In a step S4 it is then checked whether a readout of the semiconductor detector is desired, which is triggered by an external control signal, as will be described in detail.

Furthermore, it is checked in a step S5 whether it is desired to cancel the signal charge carrier accumulated in the buffer PM, which is also triggered by an external control signal.

The accumulation of the radiation-generated signal charge carriers in the buffer PM is then continued until a read-out or a clear is triggered by the external control signal.

The deletion of the signal charge carriers accumulated in the buffer PM then takes place, if appropriate, in a step S6 by discharging via the clear contact CL2, by applying positive voltage pulses to the clear contact CL2 and to the clear gate CG2, whereupon those in the buffer PM accumulated signal charge carriers via the clear contact CL2 can flow.

To read out the accumulated signal charge carriers, these are first transferred from the intermediate memory PM into the internal gate IG of the DEPFET structure in a step S7. This transfer of the signal charge carriers from the intermediate memory PM into the internal gate IG can be effected, for example, with an unchanged potential of the transfer gate TG by short-term and sufficiently strong lowering of the potential of the intermediate memory PM. This in turn is achieved by applying enough negative voltage pulses to the surface doping SB.

Subsequently, the drain current of the DEPFET structure is then read in a step S8 as a measure for the radiation-generated signal charge carriers, which is known per se from the prior art.

In a step S9, the signal charge carriers collected in the internal gate IG of the DEPFET structure are then erased by discharging the signal charge carriers via the clear contact CL1.

It should be mentioned again here that the signal charge can be determined from the difference of the transistor current when the internal gate is filled and emptied, whereby the sequence of these two measurements can also be inverted. In the RNDR DEPFET structures (RNDR: Repeated Non-Destructive Readout), which can be used in a manner analogous to the simple DEPFET presented here, the signal charge between two adjacent DEPFETs (or a DEPFET and a buffer) is shifted several times. Thus, measurement accuracies of 0.25 element charges were achieved. In the case of the RNDR DEPFET, the advantage of the invention is particularly great, since without the arrangement according to the invention the time-consuming multiple reading would result in particularly long dead times.

9 shows a variant of the operating method according to the invention for a semiconductor detector with a plurality of matrix-like arranged in rows and columns image cells, such as those in 7 are shown.

Each of these image cells has its own buffer PM for the radiation-generated signal charge carriers and a DEPFET structure for reading out.

In a first step S1, the radiation to be detected is in this case introduced into the semiconductor substrate HS, wherein the incident radiation generates signal charge carriers in the semiconductor substrate HS.

The radiation-generated signal charge carriers are then temporarily stored in a step S2 in the individual latches PM of the individual image cells.

In a step S3, the signal charge carriers accumulated in the latches PM are then transferred to the internal gates IG of the associated DEPFET structures, at the same time for all image cells or for a group of image cells, for example for the image cells of one or more lines. In each group of image cells of the matrix-shaped detector structure, therefore, the signal charge carriers from the intermediate buffers PM are transferred to the internal gates IG in all image cells of the respective group.

In a further step S4, the individual DEPFET structures of the group are then sequentially read out image cell by cell. Parallel readout of cells in several columns is also possible.

During this sequential readout of the individual image cells, the individual image cells are already radiation-sensitive again, the radiation-generated signal charge carriers being collected in the respective intermediate memories PM.

The separation of the latches PM from the internal gates IG thus makes it possible that the readout of the DEPFET structures can take place simultaneously with the radiation measurement.

10 additionally shows that the matrix-shaped detector structure can have different image areas which are read out with different readout modes and / or repetition rates R1, R2 or R3.

Thus, the read-out rate R1 in the outer image area is relatively small, since relatively little radiation is incident there, so that a read-out process is correspondingly rarely required.

On the other hand, in a central image area, the read-out rate R3 is maximum, because there substantially more radiation is incident, so that readings must also take place correspondingly more often.

In the annular intermediate region between the outer region and the central region, however, the read-out processes take place with a mean read-out rate R2.

• – Die Werwendung verschiedenster DEPFET Strukturen, wie z. B. Enhancement- und Depletion-MOS-Typ-DEPFETs, JFET-DEPFETs, lineare und geschlossene Geometrien, RNDR-DEPFETs.
• – Strukturen mit mehreren Zwischenspeichern, bei denen durch externe Steuersignale gewählt werden kann, in welchem der Zwischenspeicher die Ladung gesammelt werden soll. Dies würde es beispielsweise erlauben, mehrere Bilder in rascher Reihenfolge aufzunehmen und sie dann zeitlich verzögert sequentiell auszulesen.
• – Zwischenspeicher in Abweichung von dem in den 1–3 vorgeschlagenen Zwischenspeicher. Dieser besteht aus einer voll verarmten p-n-p-Struktur, in der sich ein Potentialmaximum ausbildet. Dieses Potentialmaximum kann durch eine zusätzliche vergrabene n-Dotierung lokal (lateral) begrenzt werden. Es ist aber beispielsweise auch möglich, eine Abgrenzung dieses Zwischenspeichers von der Umgebung mithilfe von MOS-Gates vorzunehmen.

In particular:

• - The use of various DEPFET structures, such. Enhancement and depletion MOS type DEPFETs, JFET DEPFETs, linear and closed geometries, RNDR DEPFETs.
• - Structures with a plurality of latches, which can be selected by external control signals, in which the cache the charge is to be collected. This would, for example, allow multiple images to be captured in rapid succession and then sequentially read out in time.
• - Buffer in deviation from that in the 1 - 3 proposed cache. This consists of a fully depleted pnp structure in which a potential maximum is formed. This potential maximum can be limited locally by an additional buried n-doping. But it is also possible, for example, to delineate this buffer from the environment using MOS gates.

LIST OF REFERENCE NUMBERS

• CG1

  Clear gate for the internal gate

  CG2

  Clear gate for the cache

  CL1

  Erase contact for the internal gate

  CL2

  Delete contact for the cache

  D

  Drain of the DEPFET structure

  dn

  buried n-doping

  G

  External gate of the DEPFET structure

  HS

  Semiconductor substrate

  IG

  Internal gate of the DEPFET structure

  K

  Conduit of the DEPFET structure

  PM

  cache

  R

  back contact

  S

  Source of the DEPFET structure

  SB

  surface doping

  SHLD1

  shielding

  SHLD2

  shielding

  TG

  Transfer gate

Claims (23)

Semiconductor detector for the detection of radiation with a) a semiconductor substrate (HS), wherein the radiation to be detected is incident on the semiconductor substrate (HS) and generates signal charge carriers in the semiconductor substrate (HS), b) a DEP-FET structure (S, G, D, IG) integrated into the semiconductor substrate (HS) which detects the radiation-generated signal charge carriers and generates an electrical output signal as a function of the radiation-generated signal charge carriers, c) wherein the DEPFET structure (S, G, D, IG) has a controllable conduction channel (K) and an internal gate (IG) buried in the semiconductor substrate (HS) under the conduction channel and accommodating signal charge carriers such that the signal charge carriers accumulated in the internal gate (IG) control the line channel (K), marked by d) at least one latch (PM) for the signal charge carriers, the latch (PM) being separate from the internal gate (IG) of the DEPFET structure (S, G, D, IG) and latching the radiation-generated signal charge carriers before the radiation-generated signal charge carriers for reading into the internal gate of the DEPFET structure are transferred. Semiconductor detector according to claim 1, characterized in that a) that the DEPFET structure is a MOS structure or a JFET structure, and / or b) that the DEPFET structure has open geometry or a closed geometry, and / or c) that the DEPFET structure is an RNDR structure. Semiconductor detector structure according to one of the preceding claims, characterized in that the buffer (PM) is a vertical pnp structure. Semiconductor detector according to claim 3, characterized in that the lateral extent of the buffer (PM) is limited by a buried doping. Semiconductor detector according to claim 2, characterized in that the lateral extent of the intermediate memory (PM) is limited by a gate structure. Semiconductor detector structure according to one of the preceding claims, characterized in that the buffer (PM) is a MOS structure. Semiconductor detector according to one of the preceding claims, characterized in that a) the semiconductor detector has at least one transfer mechanism (TG, SB, CG1) for transferring the signal charge carriers stored in the buffer memory (PM) into the internal gate (IG) of the DEPFET structure (S , G, D, IG), and b) that the transfer mechanism (TG, SB, CG1) is controllable by at least one external control signal, and c) that the transfer mechanism (TG, SB, CG1) stores those stored in the buffer (PM) signal charge carriers. as a function of the external control signal or the external control signals optionally in the internal gate (IG) of the DEPFET structure (S, G, D, IG) transferred or in the temporary memory (PM) leaves. Semiconductor detector according to one of the preceding claims, characterized in that a) that the semiconductor detector comprises an erase contact arrangement (CG2, CL2) for erasing the in the signal charge carriers stored in the temporary store (PM) by removing the signal charge carriers via the deletion contact arrangement (CG2, CL2), and b) that the transfer mechanism (TG, SB, CG2) stores the signal charge carriers stored in the temporary store (PM) in dependence on the (the) external control signal (s) - in the latch (PM) leaves or - transferred to the internal gate (IG) or - transferred to the clear contact arrangement (CG2, CL2). Semiconductor detector according to one of the preceding claims, characterized in that a) that the semiconductor detector comprises at least one group of several image cells, b) that the individual image cells of the group each have a DEPFET structure (S, G, D, IG) and in each case one buffer memory ( PM), c) that the transfer mechanism (TG, SB, CG1) transfers the signal charge carriers stored in the latches (PM) of the individual image cells into the internal gates (IG) of the associated DEPFET structures (S, G, D, IG) in common and essentially at the same time with all image cells of the group. Semiconductor detector according to claim 9, characterized in that the groups of image cells are each one or more rows or columns of a two-dimensional detector structure. Semiconductor detector according to claim 9 or 10, characterized in that a) that the semiconductor detector has an external read-out electronics for reading the individual DEPFET structures (S, G, D, IG) of the individual image cells of the group, b) that the external readout electronics, the DEPFET Structures (S, G, D, IG) of the individual image cells read sequentially, and / or c) that the external read-out electronics, the individual DEP-FET structures (S, G, D, IG) of the group reads, while in the buffer ( PM) radiation-generated signal charge carriers are collected. Semiconductor detector according to one of the preceding claims, characterized in that a) that the transfer mechanism (TG, SB, CG1, CG2) has a controllable transfer gate (TG) for transferring the signal charge carriers from the buffer memory (PM) into the internal gate (TG). IG) of the DEPFET structure (S, G, D, IG), and / or b) that the transfer gate annularly surrounds the DEPFET structure (S, G, D, IG). Semiconductor detector according to one of the preceding claims, characterized by a) a first erase contact arrangement (CL1, CG1) for erasing the signal charge carriers from the internal gate (IG) of the DEPFET structure, and b) a second erase contact arrangement (CL2, CG2) for erasing the signal charge carriers from the intermediate memory (PM). Semiconductor detector according to claim 13, characterized in that a) that the first erase contact arrangement (CG1, CL1) and the second erase contact arrangement (CG2, CL2) arranged on opposite sides of the DEPFET structure (S, G, D, IG) are, and / or b) that the DEPFET structure (S, G, D, IG) with its conduction channel (K) transversely to a connecting line between the first erase contact arrangement (CG1, CL1) and the second erase contact arrangement (CG2 , CL2), and / or c) that the latch (PM) is located between the second erase contact arrangement (CG2, CL2) and the DEPFET structure, and / or d) that the transfer gate (TG) also the first erase contact arrangement (CG1, CL1) surrounds annularly, and / or e) that in the semiconductor substrate (HS) under the first erase contact arrangement (CG1, CL1) and / or under the second erase contact arrangement (CG2, CL2 ) is a shield (SHLD1, SHLD2) in the form of a buried doping, the respective erase K ontaktanordnung (CG1, CL1, CG2, CL2) shields and thereby prevents radiation-generated signal charge carriers are directly captured by the first erase contact arrangement (CG1, CL1) or the second erase contact arrangement (CG2, CL2). Semiconductor detector according to one of the preceding claims, characterized in that a) the semiconductor substrate (HS) is lightly doped according to a first doping type, b) the semiconductor substrate has surface doping heavily doped according to the second doping type, c) that the semiconductor substrate (HS ) has a back contact (R) which is doped according to the second doping type, d) that the source (S) and the drain (D) of the DEPFET structure (S, G, D, IG) is heavily doped according to the second doping type , e) that the first erase contact arrangement (CL1) and / or the second erase contact arrangement is doped in accordance with the first doping type, f) that the shield is doped in accordance with the second doping type. Semiconductor detector according to Claim 15, characterized a) that the first doping type is an n-doping, while the second doping type is a p-type doping, or b) that the first doping type is a p-type doping, while the second doping type is an n-type doping. Semiconductor detector according to one of the preceding claims, characterized in that a) the semiconductor detector has a two-dimensional detector structure with a multiplicity of image cells, b) the two-dimensional detector structure has a plurality of image regions which are spatially separated and each contain a plurality of image cells, c) the image cells in the different image regions are read out differently often, the signal charge carriers stored in the buffer or buffers in each case being respectively transferred to the internal gate (IG) of the associated image cell and the respective DEPFET structure (S, G, D, IG) generates an electrical output signal. A semiconductor detector according to claim 17, characterized a) that the two-dimensional detector structure has a central image area and an outer image area, b) that the image cells in the centrally located image area are read out more often than the image cells in the image area located outside. Operating method for a semiconductor detector for detecting radiation, in particular for a semiconductor detector according to one of the preceding claims, comprising the following steps: a) introducing the radiation to be detected into a semiconductor substrate (HS) of the semiconductor detector so that the radiation in the semiconductor substrate (HS) generates signal charge carriers, b) reading out the radiation-generated signal charge carriers by means of a DEPFET structure (S, G, D, IG) integrated in the semiconductor substrate (HS), the DEPFET structure (S, G, D, IG) comprising a controllable conduction channel (K ) and an internal gate (IG) buried in the semiconductor substrate (HS) under the conduction channel (K) and receiving the signal charge carriers so that the signal charge carriers accumulated in the internal gate (IG) control the conduction channel (K), characterized by the following steps: c) buffering the radiation-generated signal charge carriers in a buffer memory (PM) in the semiconductor substrate (HS), the buffer memory (PM) being separated from the internal gate (IG) of the DEPFET structure (S, G, D, IG), d) Transferring the signal charge carriers stored in the buffer memory (PM) by means of a transfer mechanism from the buffer memory (PM) for reading into the internal gate (IG) of the DEPFET structure (S, G, D, IG) Operating method according to claim 19, characterized by the following steps: a) transferring the signal charge carriers stored in the temporary store (PM) from the temporary store (PM) to an erase contact arrangement (CG2, CL2) in order to erase the signal charge carriers stored in the temporary store (PM), and b) driving the transfer mechanism with at least one external control signal, the transfer mechanism storing the signal charge carriers stored in the latch (PM) in response to the external control signal - leaves in the buffer (PM) or - transferred to the internal gate (IG) of the DEPFET structure (S, G, D, IG) or - transferred to the clear contact arrangement (CG2, CL2). Operating method according to one of Claims 19 to 20, characterized in that a) the semiconductor detector has at least one group with a plurality of picture cells, in particular in the form of at least one row or at least one column of a two-dimensional detector structure, b) that the individual picture cells of the group each have a DEPFET C) that the signal charge carriers stored in the buffer or buffers (PM) of the individual image cells are transferred to the internal gates (IG) of the associated DEPFET structures (S, G, D, IG) be transferred together and essentially at the same time in all image cells of the group. Operating method according to one of claims 19 to 21, characterized in that a) that the DEPFET structures (S, G, D, IG) of the individual picture cells of the group are read out sequentially, and / or b) that in the latches of the individual picture cells of Group already radiation-generated signal charge carriers are collected while the DEPFET structures (S, G, D, IG) of the individual image cells of the group are read out. Operating method according to one of Claims 19 to 22, characterized in that the semiconductor substrate (HS) is driven in a surface doping (SB) with a positive electrical potential relative to the source of the DEPFET structure (S, G, D, IG) that signal charge carriers, which are generated in the area of the DEPFET structure (S, G, D, IG) by the incident radiation, also accumulate in the buffer memory (PM) and not in the internal gate (IG) of the DEPFET structure (S, G, D, IG).

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