DE102011083962A1 - Method for fabricating semiconductor substrate for micro-electromechanical system (MEMS) sensor device, involves singulating structure at the chip singulation trench - Google Patents

Abstract

The method involves etching an opening and a chip singulation trench into a substrate (102) are performed concurrently. A lamella (151) is defined between the opening and the chip singulation trench. A sense element is fabricated for sensing a deflection of the lamella. The structure is singulated at the chip singulation trench. An independent claim is included for semiconductor substrate.

Description

Cross reference to related applications

This application is a continuation-in-part application Serial No. 12 / 208,897 filed on Sep. 11, 2008. The content of the preceding application is incorporated herein by reference.

A number of applications in the field of microelectronics require not only electrical interaction with the environment, but also some sort of mechanical, thermodynamic, fluid dynamic, chemical, radiative or other environmental interaction. Examples of such applications are, for example, in the field of sensory devices, in the field of micro-electro-mechanical systems (MEMS), etc. A mechanical force, pressure, temperature, chemical substance, physical quantity, etc., interacts with a specific part of a semiconductor structure to form a to achieve desired effect, for. A certain voltage or capacitance that is a function of the applied physical quantity.

The example of a pressure sensor is intended to represent the technical context in an illustrative manner for application types that require similar interaction with the environment. Pressure sensors are typically used to control the pressure of a liquid or gas, such as gas. As air to measure. Pressure sensors typically provide an output signal that varies based on the pressure sensed by the pressure sensor. A type of pressure sensor includes a stand-alone pressure sensor that interfaces with a sensor surface, such as a pressure sensor. B. an application specific integrated circuit (ASIC) coupled or connected. Another type of pressure sensor is a pressure capsule (eg, a polysilicon plate) connected to a sensor circuit, such as a polysilicon plate. As an ASIC, during a BEOL process (BEOL = back-end-of-line = output side of the production line) is integrated. The pressure typically interacts with a fin of the semiconductor structure that extends in a direction parallel to the major surfaces of a substrate of the semiconductor structure. The fin is typically located near one of the major surfaces of the substrate. Thus, the main surface including the fin must be positioned to face the volume whose pressure is to be measured.

In alternative designs, the blade was moved to the interior of the substrate. The pressure is typically directed through a pressure channel to the fin, which may have a more or less complicated shape, depending on where the inlet of the pressure channel is positioned relative to the fin.

It is the object of the present invention to provide methods for manufacturing a semiconductor structure and semiconductor structures with improved characteristics.

The object is solved by the features of the independent claims. Further developments can be found in the dependent claims.

An embodiment of the invention addresses a method of fabricating a semiconductor structure, the method comprising the steps of: etching a first opening into a substrate; Etching a chip-input trench into the substrate to define a fin between the first opening and the chip-input trench; Producing a detection element for detecting a deflection of the blade; and singulating the semiconductor structure at the chip-input trench.

The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of the embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale. Like reference numerals designate corresponding like parts.

Preferred embodiments of the present invention will be explained in more detail below with reference to accompanying drawings. Show it:

1 a schematic vertical cross-section through a semiconductor structure according to teachings herein disclosed;

2 a schematic horizontal cross section through a semiconductor structure according to teachings herein disclosed;

3 a partial view of a schematic cross section of a semiconductor structure;

4A and 4B horizontal cross sections through cavities and two variants of internal structures in the cavities;

5 a perspective view of a variant of an internal structure;

6A to 6D various stages of an application process and a subsequent etching of a semiconductor substrate;

7A to 7F a process sequence for electrically isolating pressure sensitive structures;

8th a sensor structure implemented using a semiconductor structure;

9 a cross-section through a substrate with cavities with tapered cross sections;

10 a cross-section through a semiconductor structure with cavities and tapered fins between the cavities;

11A to 11D various stages of an embodiment of a manufacturing process of a semiconductor structure;

12A to 12D various stages of another embodiment of a manufacturing process of a semiconductor structure;

13A a first scanning electron microscope image of a portion of a semiconductor structure, which in an intermediate step of the manufacturing process of 11A - 11D or 12A - 12D is obtained;

13B a second scanning electron microscope image of a portion of a semiconductor structure, which in an intermediate step of the manufacturing process of 11A - 11D or 12A - 12D is obtained;

14 a cross-section through a semiconductor structure in which another combination of some of the disclosed features is implemented; and

15 a portion of a semiconductor wafer having a plurality of semiconductor structures prior to a singulation process for obtaining individual semiconductor structures.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such. As "top" and "bottom", "front" and "rear", "front", "rear", etc. used with reference to the orientation of the figure (s) described. Because components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only and is by no means limiting. It will be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be considered in a limiting sense and the scope of the present invention is defined by the appended claims.

It should be understood that the features of the various exemplary embodiments described herein may be combined with each other unless specifically noted otherwise.

In an earlier stage of the engineering process leading to the teachings disclosed herein, pressure sensors with a vertical design have been developed, ie, the blade extends into a direction substantially orthogonal to the main surfaces of the substrate. Unlike a compact design, this concept also offers an option to provide different pressure sensors with one or more highly configurable pressure channels. For applications in environments that are severely contaminated by liquids and the like, there may be a risk that pressure channels and other structures of the pressure sensor will be permanently clogged or overloaded, depending on the use of the pressure sensor. As a result of the overload, a change in the dielectric conditions between the pressure-sensitive plates to be read out and thus a change in the capacitance signal may occur. It is conceivable that applications in less polluted environments with lower demands for chemical inertia and less demanding specifications can be provided with the vertical design pressure sensors. However, in the field of automotive technology in particular, the requirements are typically severe (among other things, the pressure sensor is tested for different chemical substances in terms of their robustness). Perhaps these high standards can be met with a skilled use of auxiliary layers that act liquid repellent. However, it is of great interest to provide alternative robust solutions for these very demanding applications.

Some of the teachings disclosed herein suggest that the sensor element be created parallel to the chip edge so that a pressure channel can be completely eliminated. 1 to 3 represent corresponding sensor elements.

1 shows a schematic vertical cross section through a semiconductor structure. A substrate 102 has a first main surface 103 and a second main surface 104 , Further, the substrate has 102 a cavity formed therein 152 , The cavity 152 is on its left side by a wall of the substrate 102 bounded and on the right by a slat 151 that is actually part of the substrate 102 is and usually an integral part of it. The slat 151 is thin enough to respond to a stress with a pressure P (or some other type of physical quantity, such as a force) coming from the outside of the lamella 151 is designed to be distracting. Above is the cavity 152 closed by a cover material 155 and thus provides a reference pressure volume. The slat 151 and the opposite wall of the substrate 102 form a capacitor, which in an illustrative way through the two capacitor plates or plate regions 170 is shown as dashed lines. Due to the deflection of the lamella 151 the distance between the capacitor plates varies 170 as a function of the pressure P. A variation of the distance between the capacitor plates 170 results in a variation of the capacitance of the capacitor. The slat 151 is disposed close to a boundary of a chip on which the semiconductor structure is realized and is actually part of a chip edge 159 the semiconductor structure.

At the in 1 The implementation shown has the substrate 102 multiple layers 182 and 183 on. These layers 182 . 183 act as electrically insulating layers. The layers 182 and 183 For example, layers with opposite doping types, e.g. B. that the layer 182 is a p + -type doped layer and the layer 183 is an n + -type doped layer. The structure passing through the layers 182 and 183 is formed creates a pn junction in the substrate. In the alternative, other types, at least one of the layers, may be used 182 . 183 electrically insulating to be used, such as. B. implanting oxygen atoms in (one of) the layers 182 . 183 and a subsequent annealing to produce a silicon oxide. It should be noted that one of the layers 182 . 183 can be sufficient. The cavity 152 cuts at least one of the layers 182 . 183 , Thus, the slat 151 electrically isolated with respect to the remainder of the substrate 102 at the position where the lamella merges with the rest of the substrate 102 mixed. The cavity 152 is typically also enclosed with walls which are arranged on the narrow sides, ie above and below the plane of the drawing (in 1 not shown). These walls typically also need to be electrically insulating to allow the sipe 151 completely electrically isolated from the rest of the substrate 102 , The cover material 155 is also typically electrically insulating.

Above the first main surface 103 of the substrate 102 are tie layers 180 provided via which the electrodes of the capacitor, passing through the lamella 151 and the opposite wall can be formed, connected to an evaluation circuit arrangement. The elements represented by the reference number 181 are displayed belong to one or more metal layers.

The semiconductor structure further includes circuit layers 190 . 191 as used to implement CMOS circuits. The circuit layers 190 . 191 are at a distance I _distance from the chip edge 159 arranged. As an example, the distance I _{distance is} in the range of about 1 μm to 5 μm, e.g. B. 2 microns, 3 microns or 4 microns. The distance I _distance could also be greater than 5 μm, for example 7 μm, 10 μm or 12 μm. This gap _distance provides a margin to avoid damaging the potentially sensitive circuit layers resulting from handling the chip at the chip edge, in particular when performing a chip-injection on the chip edge. The Elements 181 used for electrically connecting the capacitor plates 170 with the circuit layers 190 . 191 be used (in particular that for connecting the blade 151 ) can be designed to be sufficiently robust to withstand typical stresses observed when handling the semiconductor structure.

The concept without a pressure channel is well adapted to be used in a harsh environment since no cavity is directly exposed to the environment. In addition, the location where external pressure is applied is provided on the chip edge, resulting in a more compact package compared to pressure sensors in which the blade is in a direction parallel to the main surfaces of the substrate 102 extends. Moreover, a pressure sensor comprising an upright louver (ie, perpendicular to the major surfaces) that coincides with the edge of a semiconductor chip can typically be produced at a lower cost than the above-mentioned horizontal louver or pressure sensing element devices.

A simple estimate of the total available capacity and the sensitivity associated with it shows that the implementation shown is within the range of current sizing. Depending on the width of the closed cavity 152 For example, capacitance values on the order of ten femtofarads (fF) per micron slat length can be achieved, ie the length of the respective chip edge 159 , where the chip edge 159 for example, belongs to an ASIC chip. An overall length of the chip edge 159 , which is for example 2 mm, can reach a total capacity of 2 picofarads. The overall change in capacity depends greatly on the dimensions of the slat 151 from. With a lamella height of 10 μm and a lamella thickness between 200 nm and 300 nm, capacity changes of up to 10% per 1 bar pressure change can be achieved, ie a few Femtofarads. The total capacitance and sensitivities can be adjusted by selecting an etch depth and the fin thickness. The dimensions of the blade (thickness, length, height, etc.) and the cavity (width, length, etc.) can also be adjusted, for example, depending on the desired measuring range and the sensitivity.

Another topic is chip-coding. It is possible to etch a much deeper trench at the same time as a trench is etched for the cavity. The much deeper trench circumferentially adjoins the entire active chip area and specifies a rupture edge or chip edge. Several contiguous contiguous chips may be replaced by technologies such as For example, "stealth dicing" or other suitable technologies may be singulated. Depending on the design of the circumferential etch trench, it may be possible to do without chip processing during the process of adding chips.

In accordance with the teachings disclosed herein, a pressure-sensitive (or force-sensitive, acceleration-sensitive, etc.) structure is at the chip edge 159 arranged. The pressure sensitive lamella 151 limits the chip. The break-edge or chip-inducing edge can be defined over a circumferential deeper trench.

2 FIG. 10 is a partial schematic plan view of a horizontal cross section of a semiconductor substrate according to some of the teachings disclosed herein. FIG. Several first cavities 252 are in the substrate 102 educated. The cavities 252 are configured as circumferential trenches, the inner structures 253 surround. The internal structures 253 are at the in 2 shown embodiment as a flat tubes with inner reinforcing walls and lumens 254 educated. In other embodiments, the internal structures may have other configurations. The first cavities 252 are on one side through slats 251 limited. The slats 251 separate the first cavities 252 from a chip-initiating trench 270 , The chip-formation trench 270 typically has a greater width and a greater depth than the first cavities 252 ,

The internal structures 253 and the substrate 102 , in particular the slats 251 , form capacitors. The fins act as the first electrodes of the capacitors and the internal structures 253 act as second electrodes. In one embodiment, the internal structures 253 not centered with respect to their corresponding first cavity 252 , A portion of the circumferential first cavity 252 , arranged between the inner structure 253 and the lamella 251 , defines a capacitor gap and has a smaller width than the three other portions of the first cavity in one embodiment. The capacitance C of a plate capacitor can be fed by the relationship C = εA / d, where ε is the permittivity of the material between the plates, A is the area of the plates, and d is the distance of the two plates from each other. Since the capacitance is inversely related to the distance d of the two plates, the narrow gap portion of the capacitor, ie the portion passing through the fin, carries 251 is limited most of the capacity. As mentioned above, the lamella steers 251 off, then external pressure or a force on the same occurs. This causes the gap between the lamella 251 and the inner structure 253 its width changes, which in turn leads to a change in the capacitance of the capacitor. The inner structure 253 remains relatively firm during pressure changes, in part due to its shape and reinforcement walls. The same basically applies to the part of the substrate 102 under the first cavities 252 ("Under" refers to the direction relative to the drawing). Thus, only the lamella experiences 251 a significant distraction or deformation during pressure changes.

2 indicates a number of dimensions that can be adjusted to obtain a desired operating range and sensitivity. The following table shows the symbol of a certain dimension as shown in 2 their meaning, exemplary ranges and exemplary values. Symbol in FIG. 2 importance Exemplary ranges Example value W _s Width of the chip-formation trench 270 100 to 500 nm 250 to 350 nm 300 nm W _I Thickness of the slat 251 100 to 500 nm 250 to 350 nm 300 nm W _G Width of the gap between the lamella 251 and inner structure 253 50 to 250 nm 100 to 180 nm 150 nm W _C Width of the circumferential trench on opposite side of the gap 100 to 500 nm 250 to 350 nm 300 nm W _IS Thickness of the walls of the internal structure 253 200 to 600 nm 350 to 450 nm 400 nm W _I Width of the lumen in the inner structure 253 100 to 300 nm 180 to 230 nm 200 nm I _S Length of the lumen in the inner structure 253 1 to 30 μm 5 to 15 μm 10 μm I _C Length of the cavity 252 10 to 100 μm 45 to μm 50 μm

3 shows a detail of 2 , Electrical contacting elements or devices 360 . 361 are provided to the lamella 251 and the inner structure 253 to connect with an evaluation circuit, such. B. a capacitance measuring circuit (not shown). The electrical connection elements or devices 360 . 361 For example, they can become the connection layers 180 and the metallic layers 181 from 1 extend.

The electrical contacting elements or devices 360 . 361 are at sections of the inner structure 253 and the substrate 102 arranged at a certain distance from the chip-input trench 270 lie. In particular, the lamella 251 not directly through the electrical contacting element or device 361 contacted, but over an inner wall of the substrate 102 wherein the inner wall has two first cavities 252 separates, the contacting element or the contacting device 360 for the inner structure is in one embodiment at a portion of the inner structure 253 opposite the slat 251 arranged.

• – Das Ätzen der ersten Öffnung (des Hohlraums) und das Ätzen des Chipsingulierungsgrabens können gleichzeitig durchgeführt werden. Typischerweise wird der gleiche Lithographieschritt verwendet, um die erste Öffnung und den Chipsingulierungsgraben zu definieren. Der Chipsingulierungsgraben hat typischerweise eine größere Breite als die erste Öffnung. Abhängig von der verwendeten Ätztechnologie beeinträchtigt die Breite eines zu ätzenden Grabens auch die Tiefe (große Breite führt zu größerer Tiefe und umgekehrt).
• – Die erste Öffnung kann in der Form eines Umfangsgrabens sein, der eine innere Struktur umgibt. Um die innere Struktur elektrisch zu isolieren, ist es ausreichend, die Unterseite oder den „Fuß” der inneren Struktur zu isolieren. Dies kann erreicht werden durch eine isolierende Schicht, die an der gewünschten Tiefe in dem Substrat vorliegt. Das Bereitstellen von isolierenden Schichten und/oder Materialien zwischen den Seitenwänden der inneren Struktur bezüglich des Substrats ist bei einem Ausführungsbeispiel nicht notwendig, da der Umfangsgraben als ein Isolator wirkt.
• – Das Verfahren kann ferner das Bereitstellen eines elektrischen Kontakts zu der inneren Struktur aufweisen zum elektrischen Verbinden der inneren Struktur mit dem Erfassungselement.
• – Der elektrische Kontakt kann an einem Abschnitt der inneren Struktur angeordnet sein, der dem Chipsingulierungsgraben gegenüber liegt. Dies bedeutet, dass der elektrische Kontakt relativ weit entfernt von dem Singulierungsgraben angeordnet ist, wodurch derselbe aus einer Region bewegt ist, die mechanischer Belastung ausgesetzt sein kann, insbesondere während des Singulierungsprozesses, aber auch während eines Betriebs der Halbleiterstruktur, wenn z. B. ein Druck auf eine Seite eines Halbleiterchips auftrifft bei einer Region nahe der Lamelle und wo der Singulierungsgraben vorher war.
• – Vor dem Ätzen der ersten Öffnung in das Substrat kann das Verfahren ferner folgende Schritte aufweisen: Erzeugen einer elektrisch isolierenden Schicht auf einer Hauptoberfläche des Substrats; und Aufbringen einer äußeren Schicht von Substratmaterial auf die elektrisch isolierende Schicht. Das Aufbringen der äußeren Schicht führt typischerweise dazu, dass das Substrat dicker wird. Das Ätzen der ersten Öffnung und des Chipsingulierungsgrabens können dann von einer Oberfläche der äußeren Schicht durchgeführt werden und sich nach unten erstrecken, zumindest zu der elektrisch isolierenden Schicht. Diese Verfahrensschritte können einen synergetischen Effekt haben mit anderen hierin offenbarten Merkmalen, z. B. der inneren Struktur, die durch den Umgebungsgraben umgeben ist.
• – Das Verfahren kann ferner folgende Schritte aufweisen: Aufbringen eines Deckschichtmaterials an Wände der ersten Öffnung; Füllen der ersten Öffnung mit Polysilizium; und Ätzen zumindest eines Teils des Deckschichtmaterials und dadurch Zurücklassen eines Zwischenraums zwischen dem Polysilizium und zumindest Teilen der Wände der ersten Öffnung. Diese Schritte definieren eine alternative Option zum Isolieren einer der Elektroden des Kondensators bezüglich des Substrats. Das Deckschichtmaterial ist typischerweise ein isolierendes Material, wie z. B. eine Oxiddeckschicht. Es kann auch in Betracht gezogen werden, unterschiedliche Schichten mehrere Schichten unterschiedlicher Deckschichtmaterialien auf die Wände der ersten Öffnung aufzubringen, wobei jede Schicht einen bestimmten gewünschten Effekt hat. Wenn das Polysilizium beispielsweise als eine im Wesentlichen längliche oder flache Struktur gebildet ist, wie z. B. eine Lamelle oder schichtartige Struktur, kann das Deckschichtmaterial (zumindest teilweise) an beiden Hauptoberflächen der flachen Struktur (die sich typischerweise von den Hauptoberflächen des Substrats unterscheiden) entfernt werden. Stattdessen wird das Deckschichtmaterial an den schmalen Seiten oder den Rändern beibehalten. Somit ist die im Wesentlichen flache Struktur nur an den Enden mit dem Substrat verbunden, möglicherweise auch an einigen ausgewählten Abschnitten an den Hauptoberflächen und typischerweise an der Unterseite. Dies reduziert eine parasitäre Kapazität zwischen dem Polysilizium und der umgebenen Wand des Substrats bei einem Ausführungsbeispiel.
• – Zumindest entweder die erste Öffnung oder die Lamelle können einen sich verjüngenden Querschnitt aufweisen. Im Gegensatz zu einem rechteckigen oder einheitlichen Querschnitt ermöglicht ein sich verjüngender Querschnitt einen großen Messbereich z. B. eines Drucksensors, während in einem Abschnitt des Messbereichs eine hohe Empfindlichkeit beibehalten wird, typischerweise dem Bereich niedriger Werte. Somit liefert der sich verjüngende Querschnitt gemäß einem Ausführungsbeispiel ein progressives Verhalten für eine Sensorstruktur.

The method for manufacturing a semiconductor structure as well as the semiconductor structure itself may be improved by some of the following aspects.

• The etching of the first opening (of the cavity) and the etching of the chip-formation trench can be carried out simultaneously. Typically, the same lithography step is used to define the first opening and the chip-formation trench. The chip-well trench typically has a larger width than the first opening. Depending on the etching technology used, the width of a trench to be etched also affects the depth (large width leads to greater depth and vice versa).
• The first opening may be in the form of a circumferential trench surrounding an internal structure. In order to electrically insulate the internal structure, it is sufficient to cover the bottom or the "foot" of the inside Isolate structure. This can be achieved by an insulating layer which is present at the desired depth in the substrate. Providing insulating layers and / or materials between the sidewalls of the internal structure with respect to the substrate is not necessary in one embodiment because the circumferential trench acts as an insulator.
• The method may further comprise providing an electrical contact to the internal structure for electrically connecting the internal structure to the sensing element.
• The electrical contact may be located at a portion of the internal structure facing the chip-input trench. This means that the electrical contact is located relatively far from the singulation trench, whereby it is moved out of a region which may be exposed to mechanical stress, in particular during the singulation process, but also during operation of the semiconductor structure, e.g. B. a pressure on one side of a semiconductor chip impinges on a region near the lamella and where the singulation trench was before.
• Before etching the first opening into the substrate, the method may further comprise the steps of: forming an electrically insulating layer on a major surface of the substrate; and applying an outer layer of substrate material to the electrically insulating layer. The application of the outer layer typically results in the substrate becoming thicker. The etching of the first opening and the chip-forming trench may then be performed from a surface of the outer layer and extend downwardly, at least to the electrically insulating layer. These process steps may have a synergistic effect with other features disclosed herein, e.g. B. the internal structure, which is surrounded by the surrounding trench.
• The method may further comprise the steps of: applying a capping material to walls of the first opening; Filling the first opening with polysilicon; and etching at least a portion of the capping material and thereby leaving a gap between the polysilicon and at least portions of the walls of the first opening. These steps define an alternative option for isolating one of the electrodes of the capacitor with respect to the substrate. The cover layer material is typically an insulating material, such as. B. an oxide topcoat. It may also be considered to apply different layers to a plurality of layers of different coverlay materials on the walls of the first opening, each layer having a certain desired effect. For example, when the polysilicon is formed as a substantially elongated or flat structure, such as a polycarbonate. As a lamella or layered structure, the cover layer material (at least partially) on both major surfaces of the flat structure (which typically differ from the main surfaces of the substrate) can be removed. Instead, the topsheet material is retained on the narrow sides or edges. Thus, the substantially flat structure is connected to the substrate only at the ends, possibly also at some selected portions on the major surfaces and typically at the bottom. This reduces a parasitic capacitance between the polysilicon and the surrounding wall of the substrate in one embodiment.
• - At least either the first opening or the lamella may have a tapered cross-section. In contrast to a rectangular or uniform cross section allows a tapered cross section a large measuring range z. A pressure sensor, while maintaining high sensitivity in a portion of the measurement range, typically the range of low values. Thus, in one embodiment, the tapered cross-section provides progressive behavior for a sensor structure.

• – Der erste Hohlraum kann einen Umfangsgraben aufweisen, der eine innere Struktur umgibt, die in dem ersten Hohlraum angeordnet ist.
• – Die Halbleiterstruktur kann ferner einen elektrischen Kontakt zu der inneren Struktur aufweisen zum elektrischen Verbinden der inneren Struktur mit dem Erfassungselement.
• – Der elektrische Kontakt kann an einem Abschnitt der inneren Struktur gegenüber dem Singulierungsgraben angeordnet sein.
• – Die innere Struktur kann eine elektrisch isolierende Schicht aufweisen zum Isolieren der inneren Struktur bezüglich eines Rests des Substrats.
• – Die Halbleiterstruktur kann ferner folgende Merkmale aufweisen: eine Polysiliziumstruktur, die in dem ersten Hohlraum angeordnet ist; eine Deckschichtmaterialschicht zwischen der Polysiliziumstruktur und einer Wand des ersten Hohlraums; und einen Zwischenraum zwischen der Polysiliziumstruktur und der Wand des ersten Hohlraums, wo das Deckschichtmaterial nicht zwischen der Polysiliziumstruktur und der Wand des ersten Hohlraums liegt.
• – Zumindest entweder der erste Hohlraum oder die Lamelle können einen sich verjüngenden Querschnitt aufweisen.

According to some teachings disclosed herein, a semiconductor structure includes: a first cavity in a semiconductor substrate; a chip-in edge coincident with a portion of a periphery of the semiconductor substrate, the chip-input edge and the first cavity defining a fin therebetween; and a sensing element configured to detect a deflection of the blade.

• The first cavity may include a circumferential trench surrounding an internal structure disposed in the first cavity.
• The semiconductor structure may further comprise an electrical contact to the internal structure for electrically connecting the internal structure to the sensing element.
• The electrical contact can be arranged on a section of the inner structure opposite the singulation trench.
• The inner structure may comprise an electrically insulating layer for insulating the inner structure with respect to a remainder of the substrate.
• The semiconductor structure may further comprise: a polysilicon structure disposed in the first cavity; a cap layer material layer between the polysilicon structure and a wall of the first cavity; and a gap between the polysilicon structure and the Wall of the first cavity, where the cover layer material is not between the polysilicon structure and the wall of the first cavity.
• - At least either the first cavity or the blade may have a tapered cross-section.

When concentrating on the semiconductor structure having a circumferential trench, a method of providing such a semiconductor structure includes forming a circumferential trench surrounding an internal structure in a substrate. At least one wall defined by the circumferential trench has a louver. The method also includes isolating the internal structure relative to the substrate at a portion of the internal structure that carries the internal structure to the substrate. The provision of a circumferential trench around the internal structure reduces the regions where electrical isolation must be provided between the internal structure and the substrate. The internal structure may then be used, for example, as an electrode of a capacitor. The method typically results in a semiconductor structure having a semiconductor substrate and a first cavity in the semiconductor substrate, the first cavity having a circumferential trench having an internal structure in the first cavity, the internal structure being electrical relative to a sidewall of the first cavity is isolated. The method may further include manufacturing a sensing element to detect deflection on the blade and providing a connection between the inner structure and the sensing element. For example, the sensing element may evaluate a current capacitance value between the internal structure and the substrate. Another type of sensing element may be based on evaluating a piezo effect.

According to some teachings disclosed herein, a method of fabricating a semiconductor structure comprises the steps of: etching a first opening into a substrate; Etching a second opening into the substrate to define a fin between the first opening and the second opening; Producing a detection element for detecting a deflection on the lamella; and closing at least one of the first opening and the second opening. At least either the first cavity or the fin has a tapered cross-section. As a result, a resulting semiconductor has a first cavity in a semiconductor substrate; a second cavity in the semiconductor substrate, the second cavity being open to atmosphere and defining a first fin between the first cavity and the second cavity; and a detection element configured to detect a deflection on the first fin. Again, at least either the first cavity or the fin has a tapered cross-section.

• – Das Verfahren kann ferner folgende Schritte aufweisen: Ätzen einer zweiten Öffnung in das Substrat; Abdichten der ersten Öffnung und der zweiten Öffnung mit einem Abdichtungsmaterial nach dem Aufbringen des Deckschichtmaterials; und Entfernen zumindest eines Teils des Abdichtungsmaterials der ersten Öffnung, um das Ätzen von zumindest dem Teil des Deckschichtmaterials zu erleichtern oder zu ermöglichen.
• – Das Verfahren kann ferner das Entfernen von zumindest einem Teil des Abdichtungsmaterials der zweiten Öffnung aufweisen nach dem Ätzen des Deckschichtmaterials.
• – Das Verfahren kann ferner das Durchführen einer Polysiliziumausnehmung aufweisen nach dem Füllen der ersten Öffnung mit Polysilizium.

According to some teachings disclosed herein, a method of fabricating a semiconductor structure comprises the steps of: etching a first opening into a substrate; Applying a cover layer material to walls of the first opening; Filling the first opening with polysilicon; Etching at least a portion of the capping material leaving a gap between the polysilicon and at least a portion of the walls of the first opening. Optional aspects of this method include:

• The method may further comprise the steps of: etching a second opening in the substrate; Sealing the first opening and the second opening with a sealing material after the application of the cover layer material; and removing at least a portion of the sealing material of the first opening to facilitate or facilitate the etching of at least the portion of the cover sheet material.
• The method may further include removing at least a portion of the sealing material of the second opening after etching the cover sheet material.
• The method may further comprise performing a polysilicon recess after filling the first opening with polysilicon.

The method based on filling one or more trenches with polysilicon enables the resulting semiconductor structure to be in-line tested by e.g. B. a C (V) measurement (capacitance over voltage). Further, the polysilicon structure forms one of two or more capacitor electrodes and is insulated by the cover layer material from the structure, provided the cover layer material is an insulating material.

• – einen zweiten Hohlraum; eine ablenkbare Lamelle zwischen dem ersten Hohlraum und dem zweiten Hohlraum; und ein Erfassungselement zum Erfassen einer Ablenkung der Lamelle.
• – ein Abdichtungsmaterial zum Abdichten des ersten Hohlraums.
• – Das Deckschichtmaterial kann zwischen einem Teil der Wand des ersten Hohlraums und dem Polysilizium vorliegen zum Tragen und elektrischen Isolieren des Polysiliziums von dem Substrat.
• – Der Abschnitt der Wand, wo das Deckschichtmaterial vorliegt, kann dem Zwischenraum gegenüber liegen.

The resulting semiconductor structure has the following features: a first cavity in a semiconductor substrate; a polysilicon structure disposed in the first cavity; a cap layer material layer between the polysilicon structure and at least a portion of a wall of the first cavity; and a gap between the polysilicon structure and the wall of the first cavity where the capping material is not between the polysilicon structure and the wall of the first cavity. Optional aspects include:

• A second cavity; a deflectable blade between the first cavity and the second cavity; and a detection element for detecting a deflection of the sipe.
• A sealing material for sealing the first cavity.
• The cover layer material may be present between a portion of the wall of the first cavity and the polysilicon for supporting and electrically insulating the polysilicon from the substrate.
• The portion of the wall where the cover sheet material is present may be opposite the gap.

The present disclosure also teaches a method of fabricating a semiconductor structure, the method comprising the steps of: forming an electrically insulating layer on a first major surface of a semiconductor substrate; Providing semiconductor material on the electrically insulating layer; Etching a first opening into the provided semiconductor material and the semiconductor substrate; and etching a second opening into the provided semiconductor material and the semiconductor substrate to define a fin between the first opening and the second opening. The method may further comprise the steps of: producing a detection element for detecting a deflection on the fin. The two etching steps may be performed during a single step of the process. The semiconductor substrate may be doped with a first doping type. The formation of the electrically insulating layer may then include doping the first main surface of the semiconductor substrate with a second doping type. Another option is to implant or otherwise inject z. B. oxygen atoms on the first main surface of the semiconductor substrate and performing an annealing step to produce an oxide layer on the first main surface of the semiconductor substrate. The provision of the additional semiconductor material can be achieved by an epitaxial process or a Venezia process.

A corresponding semiconductor structure has the following feature: a semiconductor substrate having a base substrate, an applied or additional (upper) layer, and an electrically insulating layer between the base substrate and the deposited (or additional) layer. A first cavity is disposed in the deposited (or additional) layer, the electrically insulating layer, and the base substrate; and a second cavity is disposed in the deposited (or additional) layer, the second cavity being open to atmosphere and defining a first fin between the first cavity and the second cavity, wherein the first fin intersects the electrically insulating layer. The semiconductor may also include a sensing element configured to detect a deflection of the first blade. The base substrate and the deposited (additional) layer may be of a first doping type and the electrically insulating layer may be of a second doping type, the second doping type being opposite in polarity to the first doping type. As in the context of the method, the electrically insulating layer may have been obtained by an annealing process.

4A and 4B Figure 4 illustrates a plan view of cross-sections through cavities where the cutting plane is substantially parallel to the major surfaces 103 . 104 . 203 . 204 of the substrate 102 . 202 , With reference to 4A has the substrate 202 three similar cavities or trenches 412 on. The cavities 412 are in the form of circumferential cavities that have an internal structure 413 surround. The inner structure 413 can with the substrate 202 be connected at a position above and / or below the plane of the drawing. Sidewalls of the inner structure 413 , in the 4A and 4B represented by their cross-sections are typically not in contact with the sidewalls of the cavity 412 as it is in 4A and 4B is apparent. Therefore, the inner structure 413 as being substantially freestanding in the cavity 412 be considered. For the purposes of this disclosure, the term "freestanding" may refer to an internal structure 413 have, at two of their outermost ends with the substrate 202 is connected, typically the upper and the lower extremity. The term "freestanding" also includes internal structures 413 which is at a single extremity with the substrate 202 regardless of a spatial relationship of the connection between the internal structure 413 and the substrate 202 (top, bottom or side).

4B similar 4A but the cavity 442 is larger than the cavity 412 , Besides, the inner structure is 443 bigger than the inner structure 413 and has a different configuration.

In both 4A and 4B are the internal structures 413 . 443 configured as tubes with reinforcing members, to ensure the stability of internal structures 413 . 443 to improve. Especially if the internal structures 413 . 443 with a single of its outermost ends to the substrate 202 are connected, is sufficient stability of the internal structure 413 . 443 advantageous. The configuration as a tube with reinforcing members or reinforcing walls is capable of providing the required level of stability.

The internal structures 413 . 443 may be used as one of the electrodes, for example a capacitor. With reference to 4A can the lower cavity 412 the three cavities shown adjacent to a side wall or a lamella 411 be. The slat 411 can distract as a function of a pressure difference between the cavity 412 and a volume on the other side of the lamella 411 , As a result, the gap between the lamella changes 411 and the inner structure 413 its width, which leads to a variation in the capacitance of a capacitor passing through the lamella 411 and the inner structure 413 is formed. Because the inner structure 413 is relatively stable and / or rigid, causing neither the pressure difference nor the deflection of the blade 411 that is the inner structure 413 moved significantly. If the inner structure 413 . 443 As an electrode of a capacitor or the like, it is typically necessary to use an electrical connector or device 460 to be provided (shown schematically as the position where the electrical connection is arranged) between the internal structures 413 . 443 and a kind of evaluation circuitry. The slat 411 . 441 is typically close to a large cavity 220 , or even an edge of a semiconductor chip. The substrate 202 is relatively sensitive in the vicinity of the large cavity or the chip edge; ie the substrate can have reduced rigidity in this region. Therefore, it may be advantageous to use the electrical connection element or device 460 at a certain distance from the lamella 411 . 441 to position. In particular with the in 4B shown inner structure 443 may be the electrical connection element or device 460 sufficiently far away from the lamella 441 be provided because the internal structure 443 is relatively large. The electrical connection device can be provided, for example, at the position which is defined by the circle in FIG 4B is displayed.

5 shows a perspective view of an embodiment of an internal structure 543 similar to the one in 4B shown inner structure 443 , As an alternative to the above-mentioned use as a relatively rigid structure, the in 5 shown inner structure 543 Also configured to be the deflecting section (s) on the sidewalls of the internal structure 543 provided. To illustrate this, shows 5 how much different sections of the internal structure distract attention to the occupancy with a pressure (or pressure difference) of 1 bar. 5 shows the result of a simulation of a finite element model (FEM). The minimum deflection caused by the FEM simulation is 0.1 nm (indicated by a wide hatching in the drawing), the maximum deflection is 4.6 nm (indicated by cross-hatching). Interleaving levels are displayed, usually in alternating fashion, through non-hatched areas or different narrow hatched areas. In these ranges, deflection values may be observed, depending on their distance from the minimum deflection range (s) and the maximum deflection range (s). In the 4A . 4B and 5 The inner structures shown are configured to provide sufficient process capability over sufficient rigidity. During operation at a later time, a sufficiently large deflection occurs at the long portions of the fins, as can be seen at the portion shown in crosshatch, where a deflection of 4.6 nm was given by the FEM simulation. A sufficiently large deflection ensures a desired level of sensitivity. It should be noted that the internal structure 543 at its upper end is not necessarily open as it is in 5 is shown. It is equally possible that the internal structure 543 is closed at its upper end, so that four closed cavities (or any other number of closed cavities) are formed. The closed cavity may take on the role of a pressure reference volume while the pressure to be measured is applied by the circumferential trench, which is the internal structure 543 surrounds. It is also possible that the circumferential trench constitutes the reference volume and is therefore closed by a cover material. The pressure to be measured is then applied to the four or more cavities acting as pressure channels.

6A to 6D show four stages of a process by which an electrically insulating layer in a semiconductor substrate 602 can be provided. The substrate 602 is typically a semiconductor material having a fundamental doping of a first polarity, e.g. B. n ^- or p ^- . In a first step, the substrate becomes 602 doped on one surface with an opposite polarity to an oppositely doped layer 632 to create. Subsequently, an epitaxial or Venezia process is performed to form a layer 634 on the oppositely doped layer 632 to build. 6D shows how a plurality of trenches 612 . 670 in the layer 634 , the oppositely doped layer 632 and the (original) substrate 602 was etched. At the opposite doped layer 632 For example, two pn junctions are formed, one of which is typically in reverse mode when there is a voltage between, for example, the top and bottom major surfaces of the substrate 602 is created. Since one of the two pn junctions is in reverse mode, the opposite doped layer acts 632 as an insulator. On the other hand, there is the substrate 602 from a homogeneous material. The opposite doped layer 632 can have different electrical properties compared to the rest of the substrate 602 but their chemical properties are essentially identical. Therefore, the majority of trenches 612 in essentially the same way through all three layers 634 . 632 and 602 etched, for example by a DT etching process.

The in 6A to 6D presented process can be before the in 1 . 2A and 2 B be performed procedures shown. The in 6A to 6D The process shown can also be combined with the arrangement of circumferential cavities and internal structures that are in 4A . 4B and 5 are shown. With reference to 6D It can be seen that the thin walls have portions that extend from the lower part of the substrate 602 through the oppositely doped layers 632 are electrically isolated. In particular, when the trenches are formed as circumferential trenches, as in 4A is shown, the inner structure of the lower part of the substrate 602 completely electrically isolated, exclusively by the oppositely doped layer 632 , Thus, no additional measures must be taken to provide electrical insulation of the internal structure 413 to reach ( 4A ).

Pressure sensors having a vertical configuration formed in a semiconductor substrate (as shown in FIG 8th and illustrated below) have been developed by the inventors in the past. With some of these pressure sensors, it is a challenge to apply doping to trenches that have extreme aspect ratios, with the doping providing electrical isolation of the pressure sensitive fins. Furthermore, a lateral doping of opposite polarity must be provided at the ends of the trenches. If possible, the process step sequence used for this purpose should be mask-free and robust.

• – Aufbringen des Hartmaskehaufens für Grabenätzen (7A)
• – Grabenätzen und Hartmaskenhaufenentfernung (Nitridschicht bleibt an der Oberfläche und blockiert die zukünftige Arsenglasbeschichtung und Borimplantation an den betreffenden Stellen) (7B)
• – Arsenglasbeschichtung und Eindringen des Arsens (7C)
• – Borimplantation und Aktivierung des Bors (7D)
• – Aufbringen von Oxynitrid (dünne Anschlussfläche Oxid darunter), Ausnehmung des Oxynitrids (das oberflächliche Nitrid wird gleichzeitig entfernt) (7E)
• – Metallisierung (7F)

One proposal has lamella doping by arsenic glass coating and subsequently providing the electrical isolation of the lamellae at the bottom and sides by two angled boron implantations. A process sequence for electrically isolating the pressure sensitive structures is disclosed in U.S. Patent Nos. 4,378,355 7A to 7F and includes the following steps:

• - application of the hard mast run for trench etching ( 7A )
• - Trench etching and hard mask stack removal (nitride layer remains on the surface and blocks the future arsenic glass coating and boron implantation at the sites concerned) ( 7B )
• Arsenic glass coating and arsenic penetration ( 7C )
• Boron implantation and activation of the boron ( 7D )
• - Application of oxynitride (thin pad oxide underneath), recess of oxynitride (the surface nitride is simultaneously removed) ( 7E )
• - metallization ( 7F )

In 7D For example, boron implantation is provided at an angle of 45 degrees with respect to the plane of the drawing and a second boron implant rotated 180 degrees to simultaneously ensure the opposite polarity doping for the bottom (layer at height indicated by "p +") and at the trench end. Typical setting accuracies in the implantation equipment are about 1 degree. Depending on the aspect ratio of the trench, higher accuracies are required so that, for example, implantation has been done several times to get a hit. This can lead to a relatively large variance of the implanted dose. Even though several implantations have been performed, it is challenging to achieve a sufficiently high doping of opposite polarity to isolate the lamellae.

In accordance with teachings disclosed herein, a combination of structural modifications and a modified integration scheme or doping sequence for electrically isolating the structure is proposed. First, the pressure-sensitive structures are adjusted in a manner that insulation at the fin end can be omitted, the result being, for example, in FIG 4A . 4B and 5 to see. An angled implantation for doping the fin ends is no longer necessary. To completely isolate the pressure fins from the substrate, it is sufficient to dope the inner structure (s) at the bottom of the trench. This introduces new integration options. A simple variation is an epitaxy of the substrate in a way that the doping of opposite polarity can be made on the wafer even before the trenches are etched. This sequence is for example in 6A to 6D outlined.

The implanted dose can be controlled relatively accurately and sufficiently high doping can be achieved with a few implants or even a single implant.

The teachings disclosed herein may be combined or implemented with a silicon-on-insulator (SOI) technology. This technology refers to the use of a layered silicon insulator silicon substrate instead of conventional silicon substrates in semiconductor manufacturing, particularly microelectronics, to reduce parasitic device capacitance and thereby improve performance. The insulator is typically silicon dioxide or sometimes sapphire. Instead of doping, for example, before 6B has been performed, the insulator layer of an SOI structure may be deposited or formed by processes known in the art of SOI technology.

A non-angled implantation in the bottom of the trench is also conceivable in one embodiment. This typically results in a simpler process compared to the angled implant. Depending on the depth of the structures, ultra high energy implantation is also possible - with a high temperature annealing step that sufficiently disperses and activates the dopants (eg, 3 MeV phosphorus and 240 minutes at 1200 degrees Celsius). The latter combination would be somewhat more favorable than a sequence with an epitaxy step, as suggested above.

8th FIG. 12 illustrates a cross section through a semiconductor structure used as a pressure sensor. The cavity 706 is a pressure channel and the cavity 707 is a pressure chamber that serves as a reference for pressure measurement. A slat 711 is between the pressure channel 706 and the pressure chamber 707 intended. The two slats 711 that the pressure chamber 707 enclose, are able to under the influence of a pressure difference between the pressure channel 706 and the pressure chamber 707 distract. The left lamella forms a first electrode of a capacitor, the right lamella 711 forms a second electrode of the capacitor and the pressure chamber 707 forms the gap of the capacitor. To be electrically conductive, each of the two fins 711 acting as a capacitor electrode, n ⁺ doped, at least on the surface of the fin. The two electrodes are electrically connected to an evaluation circuitry arranged in one or more layers 730 is provided. In the 8th The structure shown also has a second major surface 704 to which the pressure channels 706 are open. The width of the gap of the capacitor is indicated by the letter s, while the width of the louver 711 in 8th is indicated with the letter w. Around the slats 711 with respect to each other at their lower ends to electrically isolate, the p ⁺ -doped portion is provided, which acts as an insulating layer, in a similar manner as that with reference to FIG 6A to 6D is described.

The design of the pressure sensors (either standalone or integrated into an ASIC) is typically very similar to currently available models: a cavity is bounded on one or more sides by a louver. The blade is exposed to external media so that it deflects upon a change in external pressure. This mechanical information is then converted into an electrical signal by piezoresistive capacitors or other suitable methods and processes.

In the case of capacitive information conversion, the fin forms a capacitor with a sidewall of the cavity facing the fin. In order to achieve high sensitivity of this arrangement, the lamella must be thinned and the cavity must be narrow. In this way, a large change in the electrode gap relative to a starting distance is achieved. At the same time, the measuring range of the device is limited because a further increase in pressure will not cause any further change in the capacitance signal once the two electrodes are in contact.

This problem can be circumvented by a manufacturer of capacitance-based pressure sensors offering a number of different sized sensors (in terms of fin thickness and / or cavity width). A user may then select a suitable sensor for the intended application. It is possible that pressure fluctuations over a very large area must be detected by using multiple sensors, each optimized for a subarea. Alternatively, a single sensor may cover the entire area, but at the expense of lower sensitivity due to the use of a thicker fin and / or a wider cavity.

The problem of a limited range of measurement can be solved by placing the fin in a tapered relationship with respect to the opposite cavity sidewall rather than a parallel relationship. Alternatively, the blade itself may be formed in a tapered shape. As a further alternative, a combination of these variants can be used. The provision of a tapered cavity, a tapered blade, or both, results in an arrangement in which a highly sensitive conversion of the pressure signal in the first portion can be observed, while in other portions a sufficient distance remains between the blade and an opposing wall. in order to be able to capture a much larger pressure range. In other words, the tapered cavity, the tapered space and / or the tapered Slats can give the sensor progressive sensitivity (measured value small → sensitivity high and vice versa).

With a deep trench etch process, the dimensions and shape of the cavities (or etch trenches) and lamellae (silicon mesa) can be defined by lithography and process parameters. For example, an etching trench for a lamella having a wedge-shaped lateral cross-section can be obtained by lithography. By controlling the etching process, a wedge-shaped cross section in the vertical direction can be generated. Furthermore, the etch depth varies with the width of the trench opening and the process parameters. Varying the process parameters during the etching allows a more or less pronounced effect, so that a further degree of freedom in forming the cavities and / or the lamellae is available.

According to the teachings disclosed herein, the cavity and / or louver of a pressure sensor are arranged so that surfaces defining the plates of a capacitor are not parallel to one another but exhibit a tapered or wedge-like geometry. The term "tapering" means that the cavity or louver has varying thickness or width. The variation in thickness or width is not limited to linear variation, but may take other forms of variations, such as variations in thickness and width. B. curved or stepped.

9 shows a first variation where the lithography mask (not shown) defines a trapezoidal cross section of the cavities. 9 is a horizontal cross-section through the substrate at about the position indicated by VIII-VIII in FIG 8th is displayed.

10 shows another variant in which the lithography mask defines a trapezoidal cross section for the lamella. The arrows in 9 and 10 indicate which of the cavities to the back of the second major surface 704 are open (see 8th ).

Many other implementations are possible. Not shown in the drawings, for example, is an etching depth that varies across the cavity, which can be obtained by combining a lithography of 9 with an etching process that is strongly influenced by the trench width (shallow regions for narrow trench width, deep etches for wider trench widths). Furthermore, it is not necessary to increase the widths linearly.

11A to 11D show four stages of a method of providing a semiconductor structure in which some of the cavities are filled with a polysilicon fill according to teachings disclosed herein. As stated above with reference to 8th has been mentioned, pressure sensors having a vertical configuration have been developed by some of the inventors. In addition to the in 8th As shown, alternative embodiments may also use a capacitive signal variation for pressure measurement. However, in these alternative embodiments, one of the plates of the capacitor is a polysilicon plate and electrically separated from the substrate by an oxide. This has the advantage that a functionality of the micromechanical structures can be verified by a voltage-dependent capacitance measurement already during the manufacturing process. The test scheme used utilizes the fact that the polysilicon plate bends due to the applied electrical voltage. Thus, production control can be ensured by a C (V) measurement (ie, capacitance as a function of voltage).

The test scheme mentioned above can not readily be used, for example, with the in 8th shown pressure sensor can be used. On the one hand, a maximum permissible blocking voltage depends on the doping concentration at the lower edge of the lamella (diode breakdown) and is also influenced by the geometry of the trench (defines the channel length, punching). Further, the space charge region (SCR) capacitance varies with the applied voltage. With typical structural dimensions, capacitance variations of the order of a few picofarads result as a consequence of a voltage fluctuation of ten volts. The variation caused by the deflection of the lamella is about an order of magnitude smaller. Thus, the above-mentioned test scheme is based on similar embodiments of the structure disclosed in U.S.P. 8th shown is limited or not applicable at all. However, a running (inline) test by a C (V) measurement would be desirable.

According to teachings disclosed herein, polysilicon filling is performed in defined trenches after trench etching and the application of an auxiliary layer (cap layer oxide). The polysilicon material is then used as one of the capacitor electrodes, typically the counter electrode, ie, the other electrode adjacent to the electrode formed (or carried) by the blade. After a Polysiliziumausnehmung, the oxide can be etched out of the trench in a one-sided manner by a lithography step to form a cavity between the polysilicon electrode and the lamella. Thus, the test scheme presented above can be maintained and is suitable for in-line C (V) measurement.

According to teachings disclosed herein, a poly (silicon) electrode structure in a deep trench is proposed. A cavity is disposed between the polysilicon electrode and the adjacent fins, the cavity defining the spacing of the capacitor plates.

The integration of the proposed concept is conceivable in different forms. 11A to 11D show, according to an embodiment, a first sequence of the embodiment for producing a capacitive pressure sensor with an insulated counter electrode. In 11A were trenches 1112 in the substrate 1102 etched using a deep trench etch process. Then an oxide cover layer 1116 on the inside of the trenches 1112 applied as it is in 11B you can see. The oxide topcoat 1116 forms a relatively uniform layer on the inner walls of the trenches 1112 and is used as a sealing material to seal the trenches. 11B also shows that the trenches 1112 through a sealing material 1115 were closed. One of the steps after the in 11B is performed selectively, is a selective reopening of some of the trenches 1112 , 11C shows that the first and third trenches have been opened, for example by a lithography-based etching process. Once the defined trenches have been reopened, a polysilicon deposition is performed which results in the formation of a polysilicon structure 1119 in the defined trenches of the majority of trenches 1112 leads. Then, a polysilicon recess is made to remove the polysilicon that is on the sealing material 1115 is applied, and also around an upper portion of the polysilicon in the trenches 1112 to remove. Further, the oxide cover layer becomes 1116 from the trenches 1112 etched away down to a certain depth. This leaves the polysilicon structure 1119 essentially freestanding, as it is supported only on its underside (including a small lower portion of the sidewalls of the polysilicon structure 1119 ), where the oxide topcoat 1116 was not etched away. Thus, the polysilicon structure is 1119 surrounded by a circumferential trench and electrically isolated from the substrate 1102 because the oxide topcoat 1116 is typically an electrically insulating material. By using a circumferential trench around the polysilicon structure, a relatively small parasitic capacitance between the polysilicon structure and the walls of the substrate can be achieved. In the alternative to a full circumferential trench, it is possible to maintain the overcoat material on the narrower sides of the polysilicon structure to provide some structural stability. 11C shows the semiconductor structure in an intermediate state, in which the oxide topcoat 1116 already been etched away. In 11D is shown as the defined trenches 1112 be closed again using the same material as the sealing material 1115 or any other suitable material. The sealing material 1115 is typically chosen to be electrically insulating to provide electrical connection between the polysilicon structure 1119 , which forms the counter electrode, and the substrate 1102 to avoid. After re-closing the defined trench 1112 a step of chemical mechanical polishing (CMP) is carried out ( 11D ). After the in 11D As shown, the second and fourth trenches can be reopened to define pressure channels through which the external pressure to the fins 1121 is directed. Thus, the trench (s) not filled with the polysilicon mold (s) form the pressure inlet (s). A measurement signal is taken as a varying capacitance value between the polysilicon plate (s) and the substrate silicon plates. The basic capacity can be precisely adjusted by the thickness of the oxide topcoat 1116 ,

The structure may alternatively be created so that the compressive forces are detected only on one side of the polysilicon structure. 12A to 12D show a possible embodiment of a corresponding process sequence for producing a one-sided capacitive pressure sensor with insulated counter electrode. 12A essentially corresponds 11B ie the trenches 1112 were etched, the oxide topcoat 1116 was applied to the inner walls of the trenches and the sealing material 1115 was applied to close the trenches. 12B shows a state in which the sealing material 1115 was partially removed to expose some of the interstices that were covered with oxide topcoat 1116 between the polysilicon structure 1119 and the substrate 1102 are filled. The polysilicon recess was also in front of the in 12B shown state performed. In 12C became the oxide topcoat 1116 etched away in the cleared spaces. In contrast, the oxide topcoat became 1116 maintained in the interstices, which are still due to the sealing material 1115 are covered, as the etchant that is used to remove the oxide topcoat 1116 was prevented from entering these spaces. The etchant is chosen to cover only the oxide capping layer 1116 dissolve and the sealing material and the polysilicon structure 1119 essentially unimpaired. A Hydrofluoric acid may be used for this purpose, for example, a buffered hydrofluoric acid, a dilute hydrofluoric acid or a concentrated hydrofluoric acid. By using a hydrofluoric acid, a good selectivity between silicon and silicon nitride is achieved. Silicon nitride may be used as an etch stop to protect surrounding structures.

12D corresponds broadly 11D , In particular, the spaces in which the oxide topcoat 1116 was etched, closed again, and a chemical mechanical polishing step was performed. Thus, a gap was formed between the polysilicon structures 1119 and the slats 1121 , As related to 11D has been mentioned, those trenches that are not filled with polysilicon, between the in 12A and 12B shown stages are opened again to act as pressure channels.

This in 12A to 12D The illustrated embodiment may be used in conjunction with, for example, a pressure sensor by placing the fin (s) near an edge of the chip, as shown in FIG 1 to 3 is shown. The slat 1121 is then configured as a boundary lamella or edge lamella. The rightmost of the trenches 1112 may in this case be measured as a singulation trench, ie with a relatively large width and depth.

With the in 12A to 12D The process illustrated is the stability of the polysilicon structure 1119 ensured by the one-sided oxide topcoat 1116 which is not removed and thus the polysilicon structure 1119 supports. Consequently, sufficient stability can be obtained even when the polysilicon structure 1119 is very thin. Apart from the mentioned cover layer materials, other auxiliary layers are conceivable (nitride cover layer in the cavity between polysilicon structure and lamella, etc.).

To explain that the in 11A to 11D and 12A to 12D shown process sequence has been tested show 13A and 13B at least in part for some of the process steps structural results in the form of scanning electron microscope (SEM) images. 13A shows a trench filled with polysilicon 1119 , 13A shows a state of the process, which is approximately the same as in 12B shown state corresponds. An exact recess to the top of the silicon 1102 was carried out. The oxide topcoat 1116 has a thickness t _{covering layer} of about 66 nm, ranging from about 64 nm to 68 nm. The value of 68 nm applies to the layer on the substrate 1102 is applied. 13B shows the semiconductor structure after the trenches 1312 with a trench close 1340 were closed. Thus corresponds 13B on the whole 11B and 12A , The slats 1321 are also in 13B to see. The bright borders of the trenches 1312 in 13B correspond to the oxide topcoat 1316 ,

In the 11A to 11D and 12A to 12D Proposed process sequences are useful if a follow-up (inline) functionality test is to be performed via a C (V) measurement or if a dependence of the capacitance response of different voltages should be prevented. The resulting structure is similarly space-saving and only slightly more complex than the previous methods that were used to make the in 8th To obtain the structure shown.

14 shows a combination of a tapered cavity 1312 with an internal structure 1343 , The tapered cavity 1312 is separated from a large cavity 1320 through a lamella 1311 , As mentioned above, the measuring range of, for example, a pressure sensor may be extended by using a tapered cavity. The inner structure 1343 is relatively rigid and electrical insulation between the internal structure 1343 and the rest of the substrate can be achieved relatively easily, for. B. by the in 6A to 6D presented process. An electrical connection between the internal structure 1343 and an evaluation circuit (not shown) may be provided, for example, at the position indicated by the circle 1360 is displayed. In this way, the electrical connection is sufficiently far away from the lamella 1311 which is arranged to respond to pressure fluctuations within the large cavity 1320 distract. The deflection of the lamella 1311 and the proximity of a potentially high pressure in the cavity 1320 can place mechanical stress on the substrate near the lamella 1311 and the cavity 1320 induce. The end of the inner structure 1343 , that of the lamella 1311 is located farther from the location or position where the mechanical stress is induced. Therefore, the electrical connection 1360 potentially more resistant.

15 represents how a semiconductor structure 1400 on a wafer 1401 can be arranged. In a schematic way, the semiconductor structure 1400 a cavity 1412 which may be a closed cavity or an open cavity. The cavity 1412 is near a chip ditch 1420 positioned so that only the slat 1411 the cavity 1412 from the chip-input trench 1420 separates. At the end of a manufacturing process, the semiconductor structure becomes 1400 at the chip-input trench 1420 singulated as indicated by the dashed rectangle. As a result, the cavity 1412 near an edge of the semiconductor structure 1400 , z. B. near a chip edge. Thus, the space around the semiconductor structure takes 1400 around the role of, for example, the pressure channel. In the case of a pressure sensor, no additional cavity is required to fulfill the role of the pressure channel. The semiconductor structure 1400 Can be fixed so that the chip edge near the cavity 1412 exposed to the medium whose pressure is to be measured. The cavity 1412 serves as a reference volume. The cavity 1412 may go to another side of the surface of the semiconductor structure 1400 be open so that a differential pressure can be measured.

Embodiments provide sensors that are inexpensive and integrated on a single chip with logic devices. Embodiments of the sensors are combined using CMOS manufacturing processes. The sensor cavities and sensing elements can be defined for the desired sensitivity and working range.

While specific embodiments are illustrated and described herein, it will be understood by those of ordinary skill in the art that a variety of corresponding and / or equivalent implementations will be employed for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of these specific embodiments discussed herein.

Claims (30)

A method of manufacturing a semiconductor structure, the method comprising the steps of: Etching a first opening into a substrate; Etching a chip-input trench into the substrate to define a fin between the first opening and the chip-input trench; Producing a detection element for detecting a deflection of the blade; and Singulate the semiconductor structure at the chip-input trench. The method of claim 1, wherein the etching of the first opening and the etching of the chip-formation trench are performed simultaneously. The method of claim 1 or 2, wherein the first opening has a circumferential trench surrounding an internal structure. The method of claim 3, further comprising the step of: Providing an electrical contact to the internal structure for electrically connecting the internal structure to the sensing element. The method of claim 4, wherein the electrical contact is located at a portion of the internal structure opposite the chip-input trench. Method according to one of claims 1 to 5, further comprising the steps of prior to etching the first opening in the substrate: Forming an electrically insulating layer on a major surface of the substrate; Applying an outer layer of substrate material on the electrically insulating layer; wherein the etching of the first opening and the chip-forming trench is performed from a surface of the outer layer and extends at least to the electrically insulating layer. Method according to one of claims 1 to 6, further comprising the following steps: Applying a cover layer material to walls of the first opening; Filling the first opening with polysilicon; Etching at least a portion of the capping material leaving a gap between the polysilicon and at least a portion of the walls of the first opening. Method according to one of claims 1 to 7, wherein at least one of the first opening or the lamella has a tapered horizontal cross-section. A semiconductor structure comprising: a first cavity in a semiconductor substrate; a chip-in edge coincident with a portion of a periphery of the semiconductor substrate, the chip-input edge and the first cavity defining a fin therebetween; and a sensing element configured to detect a deflection of the blade. The semiconductor structure of claim 9, wherein the first cavity has a circumferential trench surrounding an internal structure disposed in the first cavity. A semiconductor structure according to claim 10, further comprising an electrical contact to the internal structure for electrically connecting the internal structure to the sensing element. The semiconductor structure of claim 11, wherein the electrical contact is disposed at a portion of the inner structure opposite the singulation edge. A semiconductor structure according to any one of claims 10 to 12, wherein the internal structure comprises an electrically insulating layer for insulating the internal structure with respect to a remainder of the substrate. A semiconductor structure according to any one of claims 9 to 13, further comprising: a polysilicon structure disposed in the first cavity; a cap layer material layer disposed between the polysilicon structure and a wall in a portion of the first cavity; and a gap between the polysilicon structure and the wall of the first cavity in a portion where the capping material is not between the polysilicon structure and the wall of the first cavity. A semiconductor structure according to any one of claims 9 to 14, wherein at least one of the first cavity and the fin has a tapered horizontal cross-section. A method of manufacturing a semiconductor structure, the method comprising the steps of: Forming a circumferential trench surrounding an inner structure in and near a peripheral edge of a substrate, wherein at least one wall of the circumferential trench faces the peripheral edge defining a sipe; and Isolating the internal structure with respect to the substrate at a portion of the internal structure that supports the internal structure on the substrate. The method of claim 16, further comprising the steps of: Producing a detection element for detecting a deflection on the lamella; and Providing a connection between the inner structure and the detection element. A method of manufacturing a semiconductor substrate, the method comprising the steps of: Etching a first opening into a substrate; Etching a second opening into the substrate to define a fin between the first opening and the second opening; Producing a detection element for detecting a deflection on the lamella; Closing at least one of the first opening and the second opening; wherein at least one of the first opening and the fin has a tapered horizontal cross-section. Semiconductor structure having the following features: a first cavity in a semiconductor substrate; a second cavity in the semiconductor substrate, the second cavity being open to atmosphere and defining a first fin between the first cavity and the second cavity; a detection element configured to detect a deflection on the first fin; wherein at least one of the first cavity and the fin has a tapered horizontal cross-section. A method of fabricating a semiconductor structure, comprising the steps of: etching a first opening into a substrate; Applying a cover layer material to walls of the first opening; after application of the cover layer material: Filling the first opening with polysilicon; Etching at least a portion of the capping material and thereby leaving a gap between the polysilicon and at least a portion of the walls of the first opening. The method of claim 20, further comprising the steps of: Etching a second opening into the substrate; Sealing the first opening and the second opening with a sealing material after the application of the cover layer material; and Removing at least a portion of the sealant material from above the first opening to facilitate etching of at least a portion of the coverstock material. The method of claim 21, further comprising the step of: Removing at least a portion of the sealing material from above the second opening after etching the cover sheet material. A method according to any one of claims 20 to 22, further comprising the step of: Performing a polysilicon recess operation after filling the first opening with polysilicon. Semiconductor structure having the following features: a first cavity in a semiconductor structure; a polysilicon structure disposed in the first cavity; a cap layer material layer between the polysilicon structure and at least a portion of a wall of the first cavity; and a gap between the polysilicon structure and the wall of the first cavity where the capping material is not between the polysilicon structure and the wall of the first cavity. A semiconductor structure according to claim 24, further comprising: a second cavity; a deflectable fin defined by the substrate between the first cavity and the second cavity; and a sensing element configured to detect a deflection of the blade. A semiconductor structure according to claim 24 or 25, further comprising a sealing material for sealing the first cavity. A semiconductor structure according to any one of claims 24 to 26, wherein the capping material between a portion of the wall of the first cavity and the polysilicon carries the polysilicon from the substrate and electrically insulated. A semiconductor structure according to claim 27, wherein the portion of the wall where the capping material is present opposes the gap. A method of manufacturing a semiconductor structure, the method comprising the steps of: Forming an electrically insulating layer on a first main surface of a semiconductor substrate; Providing semiconductor material on the electrically insulating layer; Etching a first opening into the provided semiconductor material and the electrically insulating layer; and Etching a second opening into the provided semiconductor material and the electrically insulating layer to define a fin in the semiconductor material between the first opening and the second opening. Semiconductor structure having the following features: a semiconductor substrate having a base substrate, an applied layer, and an electrically insulating layer between the base substrate and the deposited layer; a first cavity in the deposited layer, the electrically insulating layer, and the base substrate; and a second cavity in the deposited layer, wherein the second cavity is open to atmosphere and in the deposited layer between the first cavity and the second cavity defines a first fin, wherein the first fin intersects the electrically insulating layer.

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