DE102011083491A1 - Connection assembly for use in scintillation detector of computed tomography system to connect e.g. memory chip with substrate, has two micro-components connected with each other as pair and arranged on functional side opposite to rear face - Google Patents
Connection assembly for use in scintillation detector of computed tomography system to connect e.g. memory chip with substrate, has two micro-components connected with each other as pair and arranged on functional side opposite to rear face Download PDFInfo
- Publication number
- DE102011083491A1 DE102011083491A1 DE102011083491A DE102011083491A DE102011083491A1 DE 102011083491 A1 DE102011083491 A1 DE 102011083491A1 DE 102011083491 A DE102011083491 A DE 102011083491A DE 102011083491 A DE102011083491 A DE 102011083491A DE 102011083491 A1 DE102011083491 A1 DE 102011083491A1
- Authority
- DE
- Germany
- Prior art keywords
- substrate
- microcomponents
- connection
- detector
- connection arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 238000002591 computed tomography Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 8
- 230000006870 function Effects 0.000 claims description 9
- 235000012431 wafers Nutrition 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 2
- 238000005476 soldering Methods 0.000 abstract description 4
- 238000003491 array Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/115—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Measurement Of Radiation (AREA)
Abstract
Description
Die Erfindung betrifft eine Verbindungsanordnung zum Kontaktieren von Mikrobauteilen mit einem Substrat und ein Verfahren zum Herstellen einer Verbindungsanordnung, sowie einen Detektor und ein CT-System. The invention relates to a connection arrangement for contacting microcomponents with a substrate and to a method for producing a connection arrangement, as well as to a detector and a CT system.
In vielen Anwendungen der Mikrosystemtechnik stellt sich die Herausforderung, mehrere Mikrobauteile gleicher oder unterschiedlicher Bauart auf einer geringen Fläche eines Substrats unterzubringen und untereinander bzw. mit dem Substrat zu verbinden. Dies ist beispielsweise bei der Kontaktierung von mehreren, gestapelten Mikrobauteilen in Form von Speicherchips oder Prozessoren in einem gemeinsamen Gehäuse oder bei Sensorarrays, beispielsweise in Kameras oder bei der Röntgenbildgebung, und Auslesechips der Fall. In many applications of microsystems technology, the challenge arises of accommodating a plurality of microcomponents of the same or different types of construction on a small area of a substrate and connecting them to one another or to the substrate. This is the case for example when contacting a plurality of stacked microcomponents in the form of memory chips or processors in a common housing or in sensor arrays, for example in cameras or in X-ray imaging, and readout chips.
Bei gestapelten Mikrobauteilen werden diese stufenweise jeweils mit der funktionsfähigen Vorderseite, der Funktionsseite, nach oben auf dem Substrat angeordnet und jede Stufe beziehungsweise Funktionsseite wird durch Drahtbonden mit dem gemeinsamen Substrat kontaktiert, auch Drahtkontaktierung genannt. Dabei benötigen die Drähte der Drahtkontaktierung zusätzlichen Platz auf dem Substrat. Alternativ hierzu werden die einzelnen Mikrobauteile mittels einer so genannten Durchkontaktierung mit dem gemeinsamen Substrat verbunden. Dabei werden die Verbindungen zwischen den Mikrobauteilen durch Bohrungen durch das Material der Mikrobauteile hergestellt. Die Bohrungen verlaufen von der Funktionsseite des obersten Mikrobauteils zu der Funktionsseite des unteren Mikrobauteils bis hindurch zum Substrat. In the case of stacked microcomponents, these are arranged stepwise in each case with the functional front side, the functional side, upwards on the substrate, and each step or functional side is contacted by wire bonding to the common substrate, also called wire contacting. The wires of the wire bonding need additional space on the substrate. Alternatively, the individual microcomponents are connected to the common substrate by means of a so-called through-connection. In this case, the connections between the microcomponents are produced by drilling through the material of the microcomponents. The bores extend from the functional side of the uppermost microcomponent to the functional side of the lower microcomponent up to the substrate.
Beide Kontaktierungsmöglichkeiten sind aufwendig in der Herstellung und haben einen erhöhten Platzbedarf, zum einen durch die separaten Drähte und zum anderen, da die Mikrobauteile aufgrund der Bohrungen nicht beliebig klein gestaltet werden können. Aus diesem Grund sind die mittels Drahtkontaktierung oder Durchkontaktierung hergestellten Verbindungsanordnungen nicht für alle Verwendungsmöglichkeiten der Mikrobauteile geeignet. Both contacting options are complicated to manufacture and have an increased space requirement, on the one hand by the separate wires and on the other hand, since the microcomponents can not be made arbitrarily small due to the holes. For this reason, the connection arrangements produced by means of wire bonding or plated-through are not suitable for all possible uses of the microcomponents.
Es ist daher Aufgabe der Erfindung, eine Verbindung zum Kontaktieren von Mikrobauteilen mit einem Substrat zu schaffen, welche einfach in der Herstellung ist und auf einer sehr geringen Substratfläche ausgeführt werden kann. Weiter ist es eine Aufgabe der Erfindung, ein Verfahren zum Herstellen einer derartigen Verbindungsanordnung sowie einen Detektor und ein CT-System hierfür zu schaffen. It is therefore an object of the invention to provide a connection for contacting microcomponents with a substrate, which is simple to manufacture and can be carried out on a very small substrate surface. It is a further object of the invention to provide a method of making such a connector assembly and a detector and CT system therefor.
Diese Aufgabe wird durch die Merkmale der unabhängigen Patentansprüche gelöst. Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand untergeordneter Ansprüche. This object is solved by the features of the independent claims. Advantageous developments of the invention are the subject of the subordinate claims.
Die Erfinder haben erkannt, dass eine platzsparende Verbindungsanordnung von Mikrobauteilen auf einem Substrat möglich ist. Unter einer Verbindungsanordnung werden im Rahmen dieser Patentanmeldung die auf einem Substrat angeordneten Mikrobauteile, das Substrat selbst und die Verbindungen der Mikrobauteile zu dem Substrat verstanden. Hierzu werden Mikrobauteile jeweils paarweise mit ihrer der Funktionsseite gegenüberliegenden Rückseite miteinander verbunden, also in Form einer Back-to-Back-Anordnung. Dies kann entweder bereits mit den Wafern der Mikrobauteile durchgeführt werden, als so genanntes Wafer-Bonding, oder erst mit den aus den Wafern hergestellten Speicherchips. Diese Mikrobauteil-Paare werden dann mit der Funktionsseite eines der beiden Mikrobauteile auf dem Substrat angeordnet. Anschließend wird die Funktionsseite des unteren der beiden Mikrobauteile direkt mit dem Substrat verbunden, beispielsweise mittels der so genannten Flip-Chip-Methode, durch Löten und/oder leitfähiges Kleben. Die Funktionsseite des anderen, oberen Mikrobauteils wird mittels Drahtkontaktierung mit dem Substrat verbunden. Hierdurch werden aufwendige Durchkontaktierungen vermieden und die Anzahl an Drahtkontaktierungen bleibt gering, sodass der benötigte Platz verringert wird. The inventors have recognized that a space-saving connection arrangement of microcomponents on a substrate is possible. In the context of this patent application, a connection arrangement is understood to be the microcomponents arranged on a substrate, the substrate itself and the connections of the microcomponents to the substrate. For this purpose, microcomponents are each connected in pairs with their opposite side of the function side, ie in the form of a back-to-back arrangement. This can be carried out either with the wafers of the microcomponents, as so-called wafer bonding, or only with the memory chips produced from the wafers. These microcomponent pairs are then arranged with the functional side of one of the two microcomponents on the substrate. Subsequently, the functional side of the lower of the two microcomponents is directly connected to the substrate, for example by means of the so-called flip-chip method, by soldering and / or conductive bonding. The functional side of the other, upper microcomponent is connected to the substrate by means of wire bonding. As a result, complex plated-through holes are avoided and the number of wire contacts remains low, so that the required space is reduced.
Demgemäß schlagen die Erfinder vor, eine Verbindungsanordnung zum Kontaktieren von Mikrobauteilen mit einem Substrat, aufweisend mindestens ein Substrat und mindestens zwei auf dem Substrat angeordnete Mikrobauteile, die an einer Funktionsseite eine leitfähige Verbindung zu dem Substrat aufweisen, dahingehend zu verbessern, dass die mindestens zwei Mikrobauteile mit einer der Funktionsseite gegenüberliegenden Rückseite paarweise aneinander angeordnet sind. Eine derartige Verbindungsanordnung ist platzsparend auf einem Substrat auszuführen. Entsprechend sind Mikrobauteile mit derartigen Verbindungsanordnungen vielseitig einsetzbar. Accordingly, the inventors propose to improve a connection arrangement for contacting microcomponents with a substrate comprising at least one substrate and at least two microcomponents arranged on the substrate, which on a functional side have a conductive connection to the substrate, in that the at least two microcomponents are arranged in pairs with one another on the opposite side of the function side. Such a connection arrangement is space-saving to perform on a substrate. Accordingly, microcomponents with such connection arrangements are versatile.
Als Mikrobauteile werden beispielsweise Wafer, die aus den Wafern hergestellten Speicherchips und/oder Photodioden verwendet. Als Material der Mikrobauteile eignet sich bevorzugt Silizium oder GaAs. Für das Substrat wird allgemein übliches Leiterplattenmaterial verwendet. Vorteilhafterweise werden jeweils zwei Mikrobauteile paarweise auf dem Substrat angeordnet. Entsprechend ist eine gerade Anzahl an Mikrobauteilen vorteilhaft. In einer Ausführung der erfindungsgemäßen Verbindungsanordnung sind genau zwei Mikrobauteile vorgesehen, in anderen Ausführungen sind mehr als zwei Mikrobauteile, beispielsweise vier, sechs oder acht Mikrobauteile, vorgesehen. As micro components, for example, wafers, the memory chips produced from the wafers and / or photodiodes are used. The material of the microcomponents is preferably silicon or GaAs. For the substrate, common circuit board material is generally used. Advantageously, in each case two microcomponents are arranged in pairs on the substrate. Accordingly, an even number of microcomponents is advantageous. In one embodiment of the connection arrangement according to the invention, exactly two microcomponents are provided, in other embodiments more than two microcomponents, for example four, six or eight microcomponents, are provided.
Die Mikrobauteile weisen jeweils eine leitfähige Funktionsseite und eine nicht-leitfähige Rückseite auf, welche der Funktionsseite gegenüberliegend ausgeführt ist. Erfindungsgemäß sind die Mikrobauteile mit ihren Rückseiten paarweise aneinander angeordnet und verbunden. Diese Anordnung wird auch Back-to-Back-Anordnung genannt. Zum Beispiel können die Rückseiten der Mikrobauteile hierzu miteinander verklebt oder gelötet werden. Entsprechend ist ein unteres Mikrobauteil mit der Funktionsseite auf dem Substrat angeordnet und das andere, obere Mikrobauteil ist auf das unteren Mikrobauteil gestapelt, wobei die Funktionsseite des oberen Mikrobauteils von dem Substrat weg orientiert ist. Zum Kontaktieren der Mikrobauteile mit dem Substrat ist jeweils eine leitfähige Verbindung zwischen den Funktionsseiten der Mikrobauteile und dem Substrat ausgebildet. Die Ausführung dieser Verbindung ist vorzugsweise bei dem unteren und dem oberen Mikrobauteil unterschiedlich ausgeführt. The microcomponents each have a conductive functional side and a non-conductive backside, which is designed opposite the functional side. According to the invention, the microcomponents are arranged with their backs in pairs against each other and connected. This arrangement is also called back-to-back arrangement. For example, the backs of the microcomponents can be glued or soldered together for this purpose. Correspondingly, a lower microcomponent with the functional side is arranged on the substrate and the other, upper microcomponent is stacked on the lower microcomponent, wherein the functional side of the upper microcomponent is oriented away from the substrate. For contacting the microcomponents with the substrate, in each case a conductive connection is formed between the functional sides of the microcomponents and the substrate. The execution of this connection is preferably carried out differently in the lower and the upper microcomponent.
In einer Ausführung der erfindungsgemäßen Verbindungsanordnung ist diese Verbindung zwischen der Funktionsseite eines Mikrobauteils und dem Substrat als eine direkte Verbindung ausgebildet. Die Verbindung ist hierbei unmittelbar, ohne etwaige Verbindungsmittel, ausgeführt. Vorzugsweise ist die Verbindung des unteren Mikrobauteils, welches direkt auf dem Substrat angeordnet ist, als direkte Verbindung ausgeführt. Die direkte Verbindung ist bevorzugt als Bondkontaktierung ausgebildet, beispielsweise nach dem so genannten Flip-Chip-Verfahren, auch Wende-Montageverfahren genannt, mittels Löten, leitfähigem Kleben und/oder Pressschweißen. Eine Ausführung sieht vor, dass die Bondkontaktierung mittels anisotropischem leitfähigem Kleber realisiert ist (englisch: anisotropic conductive film = ACF). In one embodiment of the connection arrangement according to the invention, this connection is formed between the functional side of a microcomponent and the substrate as a direct connection. The connection is in this case directly, without any connection means executed. Preferably, the connection of the lower microcomponent, which is arranged directly on the substrate, designed as a direct connection. The direct connection is preferably formed as a bonding contact, for example, by the so-called flip-chip method, also called turning assembly method, by means of soldering, conductive bonding and / or pressure welding. An embodiment provides that the bonding contact is realized by means of anisotropic conductive adhesive (English: anisotropic conductive film = ACF).
Entsprechend ist in einer anderen Ausführung der erfindungsgemäßen Verbindungsanordnung diese Verbindung zwischen der Funktionsseite des anderen Mikrobauteils und dem Substrat als eine indirekte Verbindung ausgebildet. Die Verbindung ist hierbei mit zusätzlichen Verbindungsmitteln, das heißt mittelbar, ausgeführt. Vorzugsweise ist die Verbindung des oberen Mikrobauteils zu dem Substrat, welches auf das untere Mikrobauteil gestapelt ist und somit keinen direkten Kontakt zu dem Substrat aufweist, als indirekte Verbindung ausgeführt. Die indirekte Verbindung ist bevorzugt als Drahtkontaktierung ausgebildet. Als Verbindungsmittel dient hier ein leitfähiger Draht, beispielsweise aus Gold oder auch legiertem oder dotiertem Gold, aber auch aus Aluminium, gegebenenfalls auch mit einem geringen Siliziumanteil. Accordingly, in another embodiment of the connection arrangement according to the invention, this connection between the functional side of the other microcomponent and the substrate is formed as an indirect connection. The connection is in this case with additional connection means, that is, indirectly executed. Preferably, the connection of the upper microcomponent to the substrate, which is stacked on the lower microcomponent and thus has no direct contact with the substrate, is designed as an indirect connection. The indirect connection is preferably formed as a wire contact. The connecting means used here is a conductive wire, for example of gold or alloyed or doped gold, but also of aluminum, optionally also with a low silicon content.
Weiterhin kann als Mikrobauteil mindestens ein Element oder mehrere unterschiedliche Elemente aus der nachstehenden Liste an Mikrobauteilen kontaktiert werden: Prozessoren, ASICs, Sensoren, insbesondere optische Sensoren, Speicherchips. Es wird explizit darauf hingewiesen, dass eine Kombination verschiedener Typen von Mikrobauteilen möglich ist. Furthermore, as a microcomponent at least one element or several different elements can be contacted from the following list of microcomponents: processors, ASICs, sensors, in particular optical sensors, memory chips. It is explicitly pointed out that a combination of different types of microcomponents is possible.
Die erfindungsgemäße Verbindungsanordnung ist aufgrund der Back-to-Back-Anordnung der Mikrobauteile wesentlich platzsparender als die herkömmliche Anordnung der Mikrobauteile auf dem Substrat. Dabei lassen sich die verschiedenen Verbindungsmöglichkeiten, also das Flip-Chip-Verfahren und die Drahtkontaktierung, vorteilhaft kombinieren. Gegenüber den herkömmlichen Verbindungsanordnungen von Mikrobauteilen ergibt sich der Vorteil, dass keine Stufe zwischen den Mikrobauteilen mehr ausgebildet ist und die Mikrobauteile somit auch mit nahezu identischer Abmessung auf dem Substrat platzsparend angeordnet werden können. Des Weiteren werden aufwändige Durchkontaktierungs-Prozesse vermieden. Mikrobauteile mit der erfindungsgemäßen Verbindungsanordnung sind entsprechend vielseitig einsetzbar. Due to the back-to-back arrangement of the microcomponents, the connection arrangement according to the invention is significantly more space-saving than the conventional arrangement of the microcomponents on the substrate. In this case, the various connection options, ie the flip-chip method and the wire contacting, can be advantageously combined. Compared with the conventional connection arrangements of microcomponents, there is the advantage that no step between the microcomponents is formed more and the microcomponents can thus be arranged to save space even with almost identical dimensions on the substrate. Furthermore, complex plated-through processes are avoided. Microcomponents with the connection arrangement according to the invention are correspondingly versatile.
Weiter betrifft die Erfindung einen Detektor, insbesondere einen Szintillationsdetektor, zur Verwendung in einem CT-System, mit einer Vielzahl von Detektorpixeln, wobei zwischen zwei Detektorpixeln jeweils eine vorstehend beschriebene, erfindungsgemäße Verbindungsanordnung vorgesehen ist, und ein CT-System mit einem derartigen Detektor. Furthermore, the invention relates to a detector, in particular a scintillation detector, for use in a CT system, with a plurality of detector pixels, wherein between each detector pixel is provided in each case a connection arrangement according to the invention described above, and a CT system with such a detector.
Eine spezielle Anwendung der erfindungsgemäßen Verbindungsanordnung von Mikrobauteilen ergibt sich für die Auslese von Szintillationsdetektoren mit Back-to-Back angeordneten Mikrobauteilen, in Form von Photodiodenstreifen oder -arrays. Back-to-Back angeordnete Photodiodenstreifen erlauben die Auslese von mehrlagigen Szintillationsdetektoren über ein gemeinsames Substrat, zum Beispiel bei einem Dual-Layer-Detektor für Röntgenanwendungen. Hierbei werden die mit den Rückseiten verbundenen Photodiodenstreifen vorzugsweise spaltenweise in den planaren Szintillatorarrays jeweils in die Zwischenräume zwischen den Pixeln eingebracht und ermöglichen somit die Auslese der einzelnen Pixel von zwei Seiten. Dies hat eine vorteilhafte Steigerung der Lichtausbeute und eine Reduktion der Dosis bei Röntgendetektoren zur Folge. A special application of the micro-component connection arrangement according to the invention results for the read-out of scintillation detectors with back-to-back arranged microcomponents, in the form of photodiode strips or arrays. Back-to-back arranged photodiode strips allow the readout of multilayer scintillation detectors across a common substrate, for example a dual-layer detector for X-ray applications. In this case, the photodiode strips connected to the rear sides are preferably introduced in columns in the planar scintillator arrays in each case into the interspaces between the pixels and thus permit the readout of the individual pixels from two sides. This results in a favorable increase in the luminous efficacy and a reduction in the dose in the case of X-ray detectors.
Schließlich betrifft die Erfindung noch ein Verfahren zum Herstellen einer Verbindungsanordnung zum Kontaktieren von Mikrobauteilen mit einem Substrat, insbesondere zum Kontaktieren von Wafern und/oder Speicherchips mit einem Substrat, wobei zwei Mikrobauteile jeweils mit ihrer Rückseite miteinander verbunden werden und die den Rückseiten jeweils gegenüberliegenden Funktionsseiten mit dem Substrat kontaktiert werden. Die Verbindung der Rückseiten der Mikrobauteile ist platzsparend herstellbar und kann auch bei Mikrobauteilen mit nahezu gleichen Abmessungen durchgeführt werden. Bei dem Kontaktieren der Funktionsseiten werden erfindungsgemäß direkte und indirekte Verbindungen kombiniert. Die Funktionsseite des unteren Mikrobauteils, welches direkt auf dem Substrat angeordnet ist, wird bevorzugt mittels des Flip-Chip-Verfahrens mit dem Substrat kontaktiert und die Funktionsseite des oberen Mikrobauteils, welche von dem Substrat weg zeigt, wird bevorzugt mittels einer Drahtkontaktierung mit dem Substrat kontaktiert. Finally, the invention also relates to a method for producing a connection arrangement for contacting microcomponents with a substrate, in particular for contacting wafers and / or memory chips with a substrate, wherein two microcomponents are connected to each other with their rear side and the back sides respectively opposite sides of the function contacted the substrate. The connection of the backs of the microcomponents can be produced in a space-saving manner and can also be carried out with microcomponents having almost the same dimensions. When contacting the function pages direct and indirect connections are combined according to the invention. The functional side of the lower microcomponent, which is arranged directly on the substrate, is preferably contacted to the substrate by means of the flip chip method, and the functional side of the upper microcomponent, which points away from the substrate, is preferably contacted to the substrate by means of a wire contact ,
Im Folgenden wird die Erfindung anhand der bevorzugten Ausführungsbeispiele mit Hilfe der Figuren näher beschrieben, wobei nur die zum Verständnis der Erfindung notwendigen Merkmale dargestellt sind. Es werden folgende Bezugszeichen verwendet:
Es zeigen im Einzelnen: They show in detail:
Die
Die Mikrobauteile
Die
Insgesamt wird mit der Erfindung also eine Verbindungsanordnung zum Kontaktieren von Mikrobauteilen mit einem Substrat, aufweisend mindestens ein Substrat und mindestens zwei auf dem Substrat angeordnete Mikrobauteile, die an einer Funktionsseite eine leitfähige Verbindung zu dem Substrat aufweisen, wobei die mindestens zwei Mikrobauteile mit einer der Funktionsseite gegenüberliegenden Rückseite paarweise aneinander angeordnet sind, vorgeschlagen. Weiter werden ein Detektor, wobei zwischen zwei Detektorpixeln jeweils eine erfindungsgemäße Verbindungsanordnung vorgesehen ist, und ein CT-System mit einem derartigen Detektor vorgeschlagen. Schließlich wird noch ein Verfahren zum Herstellen einer erfindungsgemäßen Verbindungsanordnung zum Kontaktieren von Mikrobauteilen mit einem Substrat, wobei zwei Mikrobauteile jeweils mit einer Rückseite miteinander verbunden werden und die den Rückseiten jeweils gegenüberliegenden Funktionsseiten mit dem Substrat verbunden werden, vorgeschlagen. Overall, the invention therefore provides a connection arrangement for contacting microcomponents with a substrate, comprising at least one substrate and at least two microcomponents arranged on the substrate, which have a conductive connection to the substrate on one functional side, the at least two microcomponents having one of the functional side opposite back are arranged in pairs, proposed. Furthermore, a detector, wherein a connection arrangement according to the invention is provided between each two detector pixels, and a CT system with such a detector are proposed. Finally, a method for producing a connection arrangement according to the invention for contacting microcomponents with a substrate, two microcomponents each being connected to one another with a rear side and the back sides respectively opposite functional sides being connected to the substrate, is proposed.
Obwohl die Erfindung im Detail durch das bevorzugte Ausführungsbeispiel näher illustriert und beschrieben wurde, so ist die Erfindung nicht durch die offenbarten Beispiele eingeschränkt und andere Variationen können vom Fachmann hieraus abgeleitet werden, ohne den Schutzumfang der Erfindung zu verlassen. Although the invention has been further illustrated and described in detail by the preferred embodiment, the invention is not limited by the disclosed examples, and other variations can be derived therefrom by those skilled in the art without departing from the scope of the invention.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102011083491A DE102011083491A1 (en) | 2011-09-27 | 2011-09-27 | Connection assembly for use in scintillation detector of computed tomography system to connect e.g. memory chip with substrate, has two micro-components connected with each other as pair and arranged on functional side opposite to rear face |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102011083491A DE102011083491A1 (en) | 2011-09-27 | 2011-09-27 | Connection assembly for use in scintillation detector of computed tomography system to connect e.g. memory chip with substrate, has two micro-components connected with each other as pair and arranged on functional side opposite to rear face |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102011083491A1 true DE102011083491A1 (en) | 2013-03-28 |
Family
ID=47827724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102011083491A Withdrawn DE102011083491A1 (en) | 2011-09-27 | 2011-09-27 | Connection assembly for use in scintillation detector of computed tomography system to connect e.g. memory chip with substrate, has two micro-components connected with each other as pair and arranged on functional side opposite to rear face |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102011083491A1 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040212088A1 (en) * | 2003-04-28 | 2004-10-28 | Advanced Semiconductor Engineering Inc. | Multi-chip package substrate for flip-chip and wire bonding |
US20110168904A1 (en) * | 2008-09-08 | 2011-07-14 | Konninklijk Philips Electronics N.V. | Radiation detector with a stack of converter plates and interconnect layers |
-
2011
- 2011-09-27 DE DE102011083491A patent/DE102011083491A1/en not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040212088A1 (en) * | 2003-04-28 | 2004-10-28 | Advanced Semiconductor Engineering Inc. | Multi-chip package substrate for flip-chip and wire bonding |
US20110168904A1 (en) * | 2008-09-08 | 2011-07-14 | Konninklijk Philips Electronics N.V. | Radiation detector with a stack of converter plates and interconnect layers |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102014117209B4 (en) | A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE | |
DE10257707B4 (en) | Method for producing a stacked chip package | |
DE102010016696B4 (en) | Semiconductor device | |
DE69938431T2 (en) | METHOD OF MANUFACTURING A MULTILAYER PIEZOELECTRIC COMPONENT AND A TWIN-DIMENSIONALLY ARRANGED COMPONENT PACKING STRUCTURE | |
DE112008002372T5 (en) | Piezoelectric film sensor | |
DE10392637B4 (en) | Backlit photodiode array and method of making the same | |
DE102008053489A1 (en) | Carrier body for a semiconductor device, semiconductor device and method for producing a carrier body | |
DE10122720A1 (en) | Stack arrangement for an image sensor chip for electrically connecting to a circuit board | |
DE102004031954B4 (en) | Semiconductor package with stacked chips | |
EP2207344B1 (en) | Image sensor | |
DE102014118228A1 (en) | CHIP, CHIP ASSEMBLY AND THE | |
DE102019201492B4 (en) | SENSOR FOR A PHYSICAL QUANTITY AND SEMICONDUCTOR DEVICE | |
DE10251527B4 (en) | Method for producing a stack arrangement of a memory module | |
DE3234744C2 (en) | Device for holding a plurality of semiconductor wafers, each provided with integrated circuits, when making contact with strip conductors formed on a film-shaped substrate | |
DE102013103351B4 (en) | ELECTRONIC MODULE | |
DE112015000931T5 (en) | Image recording device and method for producing the image recording device | |
DE102013111540A1 (en) | Bump housing and method for its production | |
DE19900969C2 (en) | slot microphone | |
DE102008063323A1 (en) | Radiation detector, light detector assembly, manufacturing method and imaging system | |
DE102011083491A1 (en) | Connection assembly for use in scintillation detector of computed tomography system to connect e.g. memory chip with substrate, has two micro-components connected with each other as pair and arranged on functional side opposite to rear face | |
WO2004008522A2 (en) | Method for producing a component having submerged connecting areas | |
DE102014116030A1 (en) | Method for producing a connection and arrangement for a direct connection chip assembly | |
DE112014001285T5 (en) | Semiconductor chip and semiconductor device, which is provided with the semiconductor chip | |
DE112012002860T5 (en) | Solar cell module on molded lead frame and manufacturing process | |
DE112020001626T5 (en) | IMAGE CAPTURE DEVICE |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R012 | Request for examination validly filed | ||
R016 | Response to examination communication | ||
R081 | Change of applicant/patentee |
Owner name: SIEMENS HEALTHCARE GMBH, DE Free format text: FORMER OWNER: SIEMENS AKTIENGESELLSCHAFT, 80333 MUENCHEN, DE |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |