DE102011080659B4 - DEVICE AND METHOD FOR TESTING A CIRCUIT TO BE TESTED - Google Patents

Abstract

Apparatus (100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100) for testing a circuit under test (102, 13, 24, 44, 54, 641, 642, 742, 86), comprising: a syndrome determiner (110, 11, 21, 41, 51, 61, 81) adapted to determine an error syndrome bit sequence (s (v ')) based on a coded binary word (v'), the Error syndrome bit sequence (s (v ')) indicates whether the coded binary word (v') is a codeword of an error correction code (C) used to encode the coded binary word (v '); a test sequence provider (120), which is adapted, at least once, to select a different test bit sequence (Ti) of the circuit under test (102, 13, 24, 44, 54, 641, 642, 742 , 86) if the error syndrome bits sequence (s (v ')) indicates that the coded binary word (v') is a codeword of the error correction code (C); and an evaluation circuit (130, 14, 25, 58, 89) arranged to generate, based on a test output signal (R (Ti) ') caused by the test bit sequence (Ti), of the circuit under test (102, 13, 24, 44 , 54, 641, 642, 742, 86) detect erroneous processing of the test bit sequence (Ti) by the circuit under test (102, 13, 24, 44, 54, 641, 642, 742, 86).

Description

Embodiments according to the invention relate to the field of error correction and error detection in binary signals, and more particularly to an apparatus and method for testing a circuit under test.

Due to the further miniaturization of the components of integrated circuits and the associated smaller voltage values and current values, errors in integrated circuits and also in circuits for error correction or for error detection are becoming increasingly common.

Such errors can lead to a false correction, even though there is no faulty code word at the input of the correction circuit at all, which is disadvantageous. If a fault is erroneously displayed due to a faulty fault detection circuit, then system-level measures can be triggered unnecessarily, which is also detrimental.

By adding redundancy, a static or temporary error in the circuits can be detected in electronic circuits. However, the additional hardware effort should be kept as low as possible with a high detection probability.

From the US 5515383 A is a built-in integrated circuit test system having multiple fault detection / correction circuits. A matrix of test signals may be applied to the error detection / correction circuits while the circuits are not used in normal mode.

It is the object of the present invention to provide an improved concept for testing electrical circuits, which makes it possible to increase the error detection characteristics with little additional hardware expenditure and / or little additional computing time.

This object is achieved by a device according to claim 1, a method according to claim 20 or a computer program according to claim 21.

One embodiment provides an apparatus for testing a circuit under test with a syndrome tester, a test sequence provider, and an evaluation circuit. The syndrome determiner is designed to determine an error syndrome bit sequence based on a coded binary word. The error syndrome bit sequence indicates whether the coded binary word is a codeword of an error correction code used to encode the coded binary word. Further, the test sequence provider is arranged to provide, at least once, a different test bit sequence of the circuit under test from the particular error syndrome bit sequence when the error syndrome bit sequence indicates that the coded binary word is a code word of the error correction code. Furthermore, the evaluation circuit is designed to detect erroneous processing of the test bit sequence by the circuit under test on the basis of a test output signal of the circuit to be tested caused by the test bit sequence.

By providing a test bit sequence at times when the coded binary word has no error and thus is codeword of the error correction code, the time when no correction of the coded binary word is necessary can be used to test the circuit under test. As a result, the freedom from errors of the circuit to be tested can be checked with only a small additional or without additional computing time. In addition, the hardware required for this can be kept low because the test sequence provider and the evaluation can be realized with little effort.

Embodiments will be explained below with reference to the accompanying figures. Show it:

1 a block diagram of an apparatus for testing a circuit under test;

2 a block diagram of an apparatus for correcting a bit error in a coded binary word;

3 a block diagram of an apparatus for testing a circuit under test;

4 a block diagram of another device for testing a circuit under test;

5 a block diagram of an apparatus for testing a circuit under test;

6 a block diagram of a portion of a test sequence provider;

7 a block diagram of a device for correcting a bit error in a coded binary word with a device for testing a circuit under test;

8th a block diagram of a device for correcting a bit error in a coded binary word with a device for testing a circuit under test;

9 a block diagram of a device for correcting a bit error in a coded binary word with a device for testing a circuit under test;

10 a block diagram of a device for correcting a bit error in a coded binary word with a device for testing a circuit under test;

11 a block diagram of a device for correcting a bit error in a coded binary word with a device for testing a circuit under test; and

12 a flowchart of a method for testing a circuit under test.

The concept described below relates generally to the processing of encoded data encoded using a code C. In particular, the following introduction serves to explain how the usual terms of coding theory are used herein.

Is C z. A linear (n, k) code, d. H. a linear code of length n with k information bits and n - k = m check bits, then the code C can be described by a (m, n) parity check matrix H and a (k, n) generator matrix G.

If the data bits or information bits to be coded are described by u = u ₁ ,... U _k , the codeword v = v ₁ , v _n becomes the information bits u according to the relationship v = u · G educated. An n-digit word v '= v' ₁ , ..., v ' _n , which is either a codeword of the code C or a non-codeword of the code C, is denoted by s (v ') ^T = H * v' ^T a syndrome s (v ') = s ₁ (v'), ..., s _m (v '). Here, v ' ^T denotes the transposed column vector of the row vector v' and s (v ') ^T the transposed column vector of the row vector S (v').

A word v 'is a codeword if and only if its syndrome is 0, ie Hv ' ^T = 0 applies.

If a codeword v is disturbed in a non-codeword v 'and applies v = v ' ₁ , ..., v' _n = v ₁ ⊕ e ₁ , ..., v _n ⊕ e _n = v ⊕ e then e = e ₁ , ..., e _{n is the} error vector. The components of e equal to 1 indicate the bits that are disturbed.

For the syndrome s (v ') then applies s (v ') = H · v' ^T = H · [v ⊕ e] ^T = H · e ^T and the error syndrome is determined from the error vector.

In the usually performed correction of errors of a word v '= v ⊕ e by an error-correcting code C, first the error syndrome s (v') is determined in a syndrome generator. If the error syndrome equals 0, then there is no detectable error. If the error syndrome is not 0, then an error can be detected. On the basis of the error syndrome can thus be determined in a simple manner by checking the syndrome to 0, whether or not there is a detectable by the considered code C error.

A decoder then assigns to the error syndrome s (v ') the bits to be corrected in v'. These are just the bits of the error vector that are equal to 1. This procedure is successful if the errors that have occurred can be corrected by the selected code. In addition, error correction circuits also include error type determination circuits which indicate which type of error has occurred. For example, an error type indicator may indicate that a 1-bit error, a 2-bit error, a 3-bit error, or another multi-bit error has occurred. The determination of the error type is based on the error syndrome.

In cases where errors rarely occur at the inputs of the syndrome generator, the output of the syndrome generator is practically always 0. If, for example, a permanent stuck-to-0 (stuck-at-0) fault is present on output lines of the syndrome generator, then such an error will not be effective as long as no non-codeword is present at the input of the syndrome generator. However, this permanent error can falsify a faulty syndrome determined by an applied non-codeword so that an error on the input values of the syndrome generator can then not be detected and no correction of the wrong bits by the decoder occurs. Furthermore, at the other sub-circuits, such as the decoder, the error type determiner, the values 0 are always present in their input, as long as no error has occurred on the input lines of the syndrome generator. If such an error occurs very rarely, then practically the same value, here 0, is entered into the decoder and into the error type determiner, so that errors present in these circuit parts during operation can not and do not affect the outputs of these subcircuits can be recognized, which is disadvantageous.

während ein Codewort vⁱ¹, dessen i-te Komponente gleich 1 ist zu einem Syndrom

führt.In order to avoid such a situation that practically always the value 0 occurs at the outputs of the syndrome generator, the H matrix of the code C can be modified into a matrix Hmod, for example by component-inverted a column of the H matrix of the code C. , If the i-th column of the H-matrix has been inverted, then a codeword v ⁱ⁰ whose i-th component is equal to 0 results in an error syndrome

while a codeword v ⁱ¹ whose i-th component is 1 to a syndrome

leads.

oder den Wert

aus. Stuck-at 0/1-Fehler an den Ausgängen des Syndromgenerators können auf diese Weise erkannt werden, auch sogar wenn nur korrekte Codewörter in den Syndromgenerator eingegeben werden. Allgemein kann man eine Teilmenge der Spalten der H-Matrix komponentenweise invertieren. Sind die i₁-te, die i₂-te, ..., die i_r-te Spalte der H-Matrix komponentenweise invertiert, dann gibt der modifizierte Syndromgenerator den Wert

aus, wenn für ein Codewort v = v₁, ..., v_n f(v₁, ..., v_n) = v_i1 ⊕ v_i2 ⊕ ... ⊕ v_ir = 0 ist und den Wert

aus, wenn f(v₁, ..., v_n) = v_i1 ⊕ v_i2 ⊕ ... ⊕ v_ir = 1 ist. Nun ist es möglich, die modifizierte H-Matrix Hmod zur Bestimmung des Fehlersyndroms und zur Fehlererkennung zu benutzen und dadurch zu vermeiden, dass am Ausgang im fehlerfreien Fall stets der gleiche Wert ausgegeben wird, solange am Eingang des Syndromgenerators ein fehlerfreies Codewort anliegt.So as long as there is a code word of the code C at the input of the syndrome generator and the syndrome generator works correctly, it either gives the value

or the value

out. Stuck-at 0/1 errors at the outputs of the syndrome generator can be detected in this way, even if only correct codewords are input to the syndrome generator. In general, you can invert a subset of the columns of the H matrix component by component. If the i ₁ -te, the i ₂ -te, ..., the i _r -th column of the H matrix are component-inverted, then the modified syndrome generator returns the value

for a codeword v = v ₁ , ..., v _n f (v ₁ , ..., v _n ) = v _i1 ⊕ v _i2 ⊕ ... ⊕ v _ir = 0 is and the value

out, though f (v ₁ , ..., v _n ) = v _i1 ⊕ v _i2 ⊕ ... ⊕ v _ir = 1 is. Now it is possible to use the modified H-matrix Hmod to determine the error syndrome and for error detection and thereby avoid that at the output in error-free case always the same value is output, as long as the input of the Syndromgenerators an error-free code word is applied.

For a better understanding, the determination of a modified H-matrix will be described here by a simple example.

und mit der (5,9)-G-Matrix G

betrachtet. Den Informationsbits u = u₁, ..., u₅ ist das Codewort v = v₁, ..., v₉ mit v = u·G = u, c mit den Prüfbits c = c₁, ..., c₄ zugeordnet, wobei c₁ = u₁ ⊕ u₂ ⊕ u₄ ⊕ u₅ c₂ = u₁ ⊕ u₃ ⊕ u₄ c₃ = u₂ ⊕ u₃ ⊕ u₄ c₄ = u₅ gilt. Die beiden Wörter v = 110110001 und v' = 1011001000 sind gültige Codewörter, da H·v^T = 0 und H·v' = 0 gilt.To explain the procedure in detail, an abbreviated Hamming code with the (4,9) -H matrix H as an example of an error-correcting code is now described

and with the (5,9) -G-matrix G

considered. The information bits u = u ₁ ,..., U ₅ are the codeword v = v ₁ ,..., V ₉ with v = u. G = u, c with the check bits c = c ₁ , ₄ assigned, where c ₁ = u ₁ ⊕ u ₂ ⊕ u ₄ ⊕ u ₅ c ₂ = u ₁ ⊕ u ₃ ⊕ u ₄ c ₃ = u ₂ ⊕ u ₃ ⊕ u ₄ c ₄ = u ₅ applies. The two words v = 110110001 and v '= 1011001000 are valid codewords since H · v ^T = 0 and H · v' = 0.

As a subset of the columns, which are inverted component by component to form the modified H-matrix H _mod , we choose here the second column of H. For H _mod we have then

ausgibt und gleich einer modifizierten Paritätsprüfmatrix H_mod ist, die aus der Paritätsprüfmatrix H abgeleitet wird, indem die Komponenten einer Teilmenge der Spalten von H komponentenweise invertiert sind, wenn der Syndromgenerator bei Eingabe verschiedener Codewörter entweder

ausgibt. Sind die i₁-te, die i₂-te, ..., die i_q-te Spalte der H-Matrix komponentenweise invertiert, dann gibt der modifizierte Syndromgenerator in Abhängigkeit des Funktionswertes der Funktion f(v₁, ..., v_n) = v_i1 ⊕ v_i2 ⊕ ... ⊕ v_iq

In summary, the syndrome s (v ') of a word v' for a linear code C is by the relationship s (v ') = K * v' ^T determined, wherein the (m, n) matrix K is equal to the parity check matrix H of the code C, if the syndrome generator always the value when entering a codeword

and equal to a modified parity check matrix H _mod derived from the parity check matrix H by component-inverse-inverting the components of a subset of the columns of H when the syndrome generator inputs either different codewords

outputs. Are the i th _1, th, the i _2, ..., the _q th column of the H matrix is inverted i component-wise, then the modified syndrome generator is a function of the function value of the function f (v ₁ , ..., v _n ) = v _i1 ⊕ v _i2 ⊕ ... ⊕ v _iq

Hereinafter, the same reference numerals are used in part for objects and functional units having the same or similar functional properties. Furthermore, optional features of the various embodiments may be combined with each other or interchangeable.

1 shows a block diagram of a device 100 for testing a circuit under test 102 according to an embodiment. The device 100 includes a syndrome tester 110 , a test sequence provider 120 and an evaluation circuit 130 , The syndrome tester 110 determined based on a coded binary word v 'an error syndrome bit sequence s (v'). Here, the error syndrome bit sequence s (v ') indicates whether the coded binary word v' is a codeword of an error correction code C used to encode the coded binary word v '. Furthermore, the test sequence provider provides 120 at least once a test bit sequence T _i of the circuit under test that differs from the specific error syndrome bit sequence s (v ') 102 when the error syndrome bit sequence s (v ') indicates that the coded binary word v' is a codeword of the error correction code C. Furthermore, the evaluation circuit detects 130 based on a test output signal R (T _i ) 'of the circuit to be tested caused by the test bit sequence T _i 102 an incorrect processing of the test bit sequence T _i by the circuit under test 102 ,

By providing a test bit sequence T _i to the circuit under test 102 while the coded binary word is a correct codeword of the error correction code C, those times when no error correction of the coded binary word is necessary can be used to test the circuit under test.

In this case, the circuit to be tested 102 for example, be a part of an error detection and / or error correction circuit. As a result, static and temporary errors in the circuit under test can be detected without or with little additional time. In addition, the added hardware overhead can be especially for the test sequence provider 120 and the evaluation circuit 130 be kept low.

In other words, by the described concept, an improvement of the error detection, in particular in circuit parts of circuits for error detection and error correction can be enabled by circuit parts can be tested during operation with any predetermined test bit sequences (test inputs) without interrupting the normal operation of the overall circuit have to.

The circuit to be tested 102 can be part of the device 100 for testing the circuit under test, but this is not necessary since the proposed concept is independent of the circuit under test 102 is applicable. As part of an error detection and / or error correction circuit, the testing circuit 102 for example, a decoder (decoder unit) for generating a correction signal for correcting a defective coded binary word v 'or an error type determiner for determining an error type of a defective coded binary word v'.

The error syndrome bit sequence s (v ') indicates or indicates whether the coded binary word v' is a codeword of the error correction code C. In this case, the error syndrome bit sequence s (v ') assumes the value of a predefined error syndrome bit sequence if the encoded binary word v' is a code word of the error correction code C. This may always be exactly the same predefined error syndrome bit sequence (eg, 0000 or 1111) or a predefined error syndrome bit sequence from a plurality of error syndrome bit sequences. For example, two different predefined error syndrome bit sequences can be provided for two different groups of code words of the error correction code C (eg the bit sequence 0000 for a first part of the code words and the bit sequence 1111 for a second part of the code words). In other words, the syndrome tester 110 may determine the error syndrome bit sequence s (v ') such that the error syndrome bit sequence s (v') for a first plurality of code words of the error correction code C is equal to a first predefined error syndrome bit sequence and the error syndrome bit sequence s (v ') for a second plurality of code words of the error correction code C is equal to a second predefined error syndrome bit sequence. The first predefined error syndrome bit sequence and the second error syndrome bit sequence differ. Furthermore, the first plurality of codewords and the second plurality of codewords do not have common codewords. Alternatively, the Syndrombestimmer 110 For example, determine the error syndrome bit sequence s (v ') such that the error syndrome bit sequence s (v') is always equal to a predefined error syndrome bit sequence if the coded binary word v 'is a codeword of the error correction code C.

The error syndrome bit sequence s (v ') can be generated, for example, by means of the parity check matrix H of the error correction code C. In other words, the syndrome tester 110 For example, the error syndrome bit sequence s (v ') may be based on a multiplication of a parity check matrix H of the error correction code C with the coded binary word v' or a multiplication of a parity check matrix K of the error correction code C component-inverted in at least one column (or in one row in a transposed parity check matrix) determine the coded binary word v '.

The error correction code C can in principle be any error correction code. For example, error correction code C may be a linear error correction code (eg Hamming code).

The test bit sequence T _i can in principle be any bit sequence of which wholly or at least in part (eg when considering only a subset of the bits of the test output signal) is known which test output signal is the circuit under test 102 in response to the test sequence T _i outputs when the circuit under test 102 works without errors. For example, the test sequence T _i may be equal to an error syndrome bit sequence s (v ') for a coded binary word v' that is not a codeword of the error correction code C. This can be used, for example, to test whether the circuit under test 102 would work correctly if the syndrome tester 110 would output this error syndrome bit sequence s (v '). For example, if the circuit under test is an error detection and / or correction circuit or part of it, it can be determined whether that circuit would work properly for an error in the coded binary word simulated by the test bit sequence.

Is the circuit under test 102 an error detection and / or error correction circuit or a part thereof, then the test sequence provider 120 the error syndrome bit sequence of the circuit under test 102 when the error syndrome bit sequence detects an error in the binary word. This error can then be corrected by the error correction circuit, for example. The test sequence provider 120 Thus, the test bit sequence T _{i can} provide if the coded binary word has no error and provide the error syndrome bit sequence s (v ') if the coded binary word v' has an error, ie does not correspond to a codeword of the error correction code. In other words, the test sequence provider 120 may be the error syndrome bit sequence s (v ') of the circuit under test 102 when the error syndrome bit sequence s (v ') indicates that the coded binary word v' is not a codeword of the error correction code C. Alternatively, for example, the Syndrombestimmer 110 the error syndrome bit sequence s (v ') directly to the circuit under test 102 provide. The circuit to be tested 102 processes the error syndrome bit sequence s (v ') if the coded binary word is not a codeword, and processes the test bit sequence T _i if the coded binary word v' is a codeword.

The test sequence provider 120 When the coded binary word v 'is a codeword of the error correction code, it is not always necessary to have a test bit sequence T _i to the circuit under test 102 provide. In principle the proposed concept is already realized by a one-time provision, but the test coverage and the probability of detecting an incorrect processing of a test bit sequence T _i can be increased if a test bit sequence T _i is often provided. For example, the test sequence provider 120 at least 10%, 20%, 50%, or 80% of a test bit sequence T _i of the circuit under test that is different from the particular error syndrome bit sequence s (v ') 102 when the error syndrome bit sequence s (v ') indicates that the coded binary word v' is a codeword of the error correction code C. Alternatively, the test sequence provider 120 also provide a test bit sequence T _i when the coded binary word v 'is a codeword.

In this case, the test sequence provider 120 For example, each of a different test bit sequence T _i (which differs from the previous test bit sequence) from a plurality of test bit sequences provide when the coded binary word is a codeword. In other words, the test sequence provider 120 may each comprise a test bit sequence T _i of a plurality of test bit sequences for each coded binary word v 'that matches the syndrome 110 which is a codeword of the error correction code C, of the circuit under test 102 provide. The plurality of test bit sequences may for example be stored in a memory or generated by a linear feedback shift register. In other words, the test sequence provider 120 may comprise a memory storing and providing the plurality of test bit sequences, or having a linear feedback shift register enabling generation of a test bit sequence T _{i of} the plurality of test bit sequences.

The evaluation circuit 130 can from the test output signal R (T _i ) 'an error in the circuit under test 102 detect. This can be done with the evaluation circuit 130 For example, the test output signal R (T _i ) 'or a signal derived from the test output signal R (T _i )' signal with an expected reference test signal R (T _i ) compare. If the test output signal R (T _i ) 'or the signal derived therefrom does not coincide with the expected reference test signal R (T _i ), an erroneous processing of the test bit sequence T _{i will result} from the circuit under test 103 recognized. The evaluation circuit can output a corresponding error signal. In other words, the evaluation circuit 130 may compare the test output signal R (T _i ) 'or a processed or reduced test output signal based on the test output signal R (T _i )' with an expected reference test signal R (T _i ) and detect an erroneous processing of the test bit sequence T _i if the test output signal R ( T _i ) 'or the processed or reduced test output signal does not match the expected reference test signal R (T _i ). In this case, the processed or reduced test output signal may be a bit sequence which can be obtained by a logical function of the bits of the test output signal R (T _i ) 'or which contains only a subset of the bits of the test output signal R (T _i )'. In this case, the subset of bits of the test output signal R (T _i ) 'refers to the bit width of the test output signal R (T _i )'.

In some embodiments, the error correction code C is based on an inversion of one or more columns of the parity check matrix H, as previously described. In such cases, the test sequence provider may be 120 For example, a bit sequence inverter that compensates for the partial inversion of the columns (or rows in a transposed parity check matrix) of the parity check matrix for further processing. In other words, the test sequence provider 120 may comprise a bit sequence inverter that inverts the test bit sequence T _i or the error syndrome bit sequence s (v ') based on a function f (v') of a subset of bits of the coded binary word v '. The function f (v ') of the subset of bits may be chosen, for example, so that the bit sequence inverter does not invert the test bit sequence T _i if the error syndrome bit sequence s (v') is equal to the first predefined error syndrome bit sequence, and the test bit sequence T _{i is} inverted, if the error syndrome bit sequence s (v ') is equal to the second predefined error syndrome bit sequence. This is an example of a possible function f (v ') if the error syndrome bit sequence for different codewords of the error correction code can take on two different error syndrome bit sequences s (v').

2 shows a block diagram of a device 200 for correcting a bit error in a coded binary word v 'according to an embodiment. The device 200 comprises a device for testing a circuit under test according to the concept described above and a decoder 250 as a circuit to be tested and a correction unit 240 , The syndrome tester 110 is with the test sequence provider 120 connected, the test sequence provider 120 is with the decoder 250 connected and the decoder 250 is with the correction unit 240 and the evaluation circuit 130 connected. The decoder 250 generates an output signal based on the error syndrome bit sequence s (v '), so that the output signal of the decoder 250 represents a coded binary word v 'correction signal e when the error syndrome bit sequence s (v') indicates that the coded binary word v 'is not a codeword of the error correction code C. The decoder 250 corresponds to the circuit under test and the output signal of the decoder 250 corresponds to the test output signal R (T _i ) 'when the error syndrome bit sequence s (v') indicates that the coded binary word v 'is a codeword of the Error correction codes C is. Furthermore, the correction unit corrects 240 based on the coded binary word v 'and the correction signal e, a bit error in the coded binary word v' and outputs a corrected coded binary word v _corr .

In other words, there is an erroneous coded binary word v ', so gives the decoder 250 a correction signal e to the correction unit 240 off and the correction unit 240 corrects the error in the coded binary word and outputs a corrected coded binary word v _corr (if the error is an error correctable by the error correction code, eg a 1-bit error using a 1-bit error correcting code). However, if an error-free coded binary word is present, then the test sequence provider provides 120 a test bit sequence T _i to the decoder 250 ready, which then outputs the test output signal R (T _i ) ', that of the evaluation circuit 130 is used to incorrectly process the test bit sequence T _i by the decoder 250 to recognize.

The syndrome determiner 110 , the test sequence provider 120 , the evaluation circuit 130 , the correction unit 240 and / or the decoder 250 For example, they may be embodied as independent hardware units or as part of a computer, microcontroller or digital signal process, as well as a computer program or software product for execution on a computer, microcontroller or digital signal processor. The syndrome determiner 110 , the test sequence provider 120 , the evaluation circuit 130 , the correction unit 240 and / or the decoder 250 For example, they can also be partially realized together.

In the following, the proposed concept will be explained in more detail with reference to several detailed exemplary embodiments. However, the described details are also independently applicable to both a device for testing a circuit under test and a device for correcting a bit error in a coded binary word. Likewise, the various aspects of the various embodiments may be combined.

3 shows a first detailed circuit arrangement 300 in the case that the matrix K is equal to the parity check matrix H of the code C. It consists of sub-circuits S1 11 (Syndrome tester), S2 12 (Error syndrome connoisseur), S3 13 (circuit under test), 14 (Evaluation circuit) and S5 15 , At the n binary inputs of the first subcircuit S1 11 to form a syndrome s, the n-bit-wide coded data v 'are applied, which are processed in the circuit S1 to an m-bit-wide syndrome s (v'). In this case, the circuit S1 is designed such that s (v) ≠ s (v ') holds when v is a code word of the code C and v is not a code word of the code C. Since K is equal to the parity check matrix H of the code C, the syndrome of a codeword is always 0 here, and the syndrome of a non-codeword is not 0. The test sequence provider 120 is through the sub-circuit S2 12 and the sub-circuit S5 15 educated.

The m-bit-wide output of the first subcircuit S1 is in the m-bit-wide input of the circuit for error detection S2 12 (Error syndrome recognizer) and at the same time in the m-bit-wide first input of the sub-circuit S5 15 guided. The circuit for error detection S2 12 outputs different error signals at its r bit wide output if a syndrome s (v) of a codeword of the code C or a syndrome s (v ') of a non codeword of the code C is present at its m-bit wide input. The r-bit wide output of the fault detection circuit is routed to the third r-bit wide input of the subcircuit S5. If an error signal which corresponds to a code word of the code C from the error detection circuit S2 12 outputted, then a test bit sequence T _i (test vector) is input to the third m-bit input of the sub-circuit S5.

The subcircuit S5 15 is configured to output, at its m-bit wide output, the value applied to its first input when the error signal from the second sub-circuit S2 12 is output, corresponds to a syndrome of a non-codeword of the code C and outputs the value of the test bit sequence T _i when the error signal output from this sub-circuit corresponds to a syndrome of a codeword of the code C.

Generally speaking, the test sequence provider 120 may have an error syndrome recognizer. The error syndrome recognizer may provide a test trigger signal indicating the provision of a test bit sequence T _i by the test sequence provider 120 triggers when the error syndrome bit sequence s (v ') equals a predefined error syndrome bit sequence. Here, the predefined error syndrome bit sequence indicates that the coded binary word v 'is a codeword of the error correction code C.

The m-bit wide output of the subcircuit S5 15 is in the m-bit wide input of the subcircuit S3 to be tested 13 which outputs a test response signal R (T _i ) at its M bit wide output if the signal T _i is present at its input and outputs the signal R (s (v)) if the syndrome s (v) is present at its input where v is a codeword of the code C. The M-bit wide output of the circuit under test S3 13 is in an evaluation circuit 14 performed, which checks whether actually output from the sub-circuit S3 test output signal (test response signals) with expected test output signal (expected test response signals) match. If a mismatch is detected, then an error has been detected in the sub-circuit S3 to be tested.

If a syndrome of a codeword from the sub-circuit to form a syndrome S1 11 generated and as such from the sub-circuit for error detection S2 12 is detected, a test of the sub-circuit S3 13 respectively.

If, however, a syndrome of a non-codeword of the sub-circuit to form a syndrome S1 11 generated and as such from the sub-circuit for error detection S2 12 detected, then no test of the sub-circuit S3 13 and the syndrome applied to their inputs is processed by the sub-circuit S3.

4 shows a circuit arrangement 400 for the case that the matrix K was derived from the parity check matrix H by q columns of the matrix H have been component-inverted and K = H _mod . Let the component-inverted columns be the columns h _i1 , ..., h _iq . The circuit parts that have the same function as in 3 have the same symbols and numbers, and they are not to be described again here. In addition to 3 here is a circuit 16 with a q-bit input and a 1-bit output for realizing a linear function. f (v ' ₁ , ..., v' _n ) = v _i1 ⊕ ... ⊕ v _iq and a circuit S7 17 with a m-bit first input and a 1-bit second input and a m-bit output for controlled inversion of its inputs at its first input. Sub-circuits S2, S5, S6 and S7 form the test sequence provider, and sub-circuits S6 and S7 form a bit-sequence inverter that is part of the test-sequence provider.

The q-bit wide input of the circuit S6 16 to realize a function f 16 is connected to the q input lines of the circuit S1 11 connected, carrying the values v _i1 , ..., v _iq , and the 1-bit wide output of this circuit is in the second, 1-bit wide input of the circuit S7 17 guided. The first m bit wide input of the circuit S7 17 is connected to the output of the circuit S5 15 connected during the m-bit output of the circuit S7 17 in the m bit wide input of the circuit under test S3 13 is guided. Is the value of the circuit S6 16 is output to determine the function f is equal to 0, then the circuit S7 17 pass the value entered at its first input directly to its output. Is the value of the circuit S6 16 for the determination of the function f, equal to 1, then the circuit S7 17 the component-by-inverted value of the value applied to its first input.

oder

vorliegt.The Schaltun S2 12 determines if one of the values

or

is present.

In 5 is a concrete design 500 the in 3 shown circuit shown.

As code C here is assumed a linear code of length n with m components of the error syndrome. The first subcircuit S1 21 Here is a common syndrome generator to form an m-component syndrome of the linear code C. At the n-bit input of the syndrome generator S1 21 is an n-component coded word v '. The syndrome generator S1 21 outputs at its m bit wide output the associated error syndrome s (v ') = w. If v 'is a codeword of the code C, then s (v') = 0. If v 'is not a codeword of the code C, then s (v ') ≠ 0. The output of the syndrome generator (syndrome tester) is simultaneous with the m input lines of a NOR gate 22 (Error syndrome recognizer) and connected to the m first input lines of m XOR gates each having a first and a second input indicated by the XOR symbol 27 are illustrated. The circuit S2 12 in 3 is here through the NOR gate 22 (Non-OR gate) realized with m inputs and one output, so here r = 1 applies. The 1-bit wide output (to provide the test trigger signal) of the NOR gate 22 is in the first 1 bit wide input of the AND circuit 26 (And circuit) led. As shown in the example, it may be sufficient that the test trigger signal is only exactly one bit wide. The AND circuit, here as an AND symbol 26 is illustrated, consists of m AND gates, each having a first and a second input and one output, at their respective first input of the 1-bit wide output of the NOR gate 22 is connected and at their respective second input the correct m components of a test bit sequence T _i (test inputs) for the circuit S4 24 are entered when s (v ') = 0 and through the fault detection circuit 22 no error is displayed. The m output lines of the AND circuit 26 are with the m each second inputs of the XOR gate 27 their m outputs connected to the m inputs of the sub-circuit S4 to be tested 24 are guided. The circuit S5 15 from 3 is here through the m XOR gates 27 (Exclusive-OR gate) and the m AND gate 26 (And gate) realized. Located at the m second inputs of the AND circuit 26 the test vector T _i and is s (v ') = 0, then lies at the input of the sub-circuit S4 to be tested 24 the test vector T _i , which is processed by this circuit to a test output signal R (T _i ) ', and the M bit wide output of the circuit S4 24 which is in the input of an evaluation circuit 25 is performed, is spent. The evaluation circuit 25 serves to determine if the test output R (T _i ) 'corresponds to the expected test output or if the actual test output R (T _i )' due to an error in the circuit under test S4 24 deviates from the expected test output. If v 'is not a codeword, then the NOR gate 22 (Non-OR gate) has the value 0, so that the m outputs of the m AND gates 26 will result in the value 0 being added in the XOR gates with s (v ') to s (v') ⊕ 0 = s (v ') modulo 2 such that s (v') at the m inputs of the subcircuit S4 is applied.

6 shows another possible embodiment 600 the subcircuit S5 15 (Part of the test sequence provider) of 3 that's here as a multiplexer 33 with m-bit-wide first data inputs, which carry an m-digit binary value w, with m-bit wide second data inputs at which the m-bit-wide test vector T _i is present, with m-bit outputs and a r = 1-bit wide control input is realized , Depending on the fault signal present on the r = 1 bit wide control line, which is supplied by the fault detection circuit S2 (FIG. 12 . 22 ), the signal w is the leading input line or the input line of the multiplexer carrying the test vector Ti 33 directly connected to the output line.

7 shows a concrete design 700 of the proposed concept where the circuit under test is an error type determiner 44 a circuit arrangement for error correction and error detection is. The subcircuit S1 11 from 3 to form an error syndrome is referred to here as Syndromgenerator (Syndrombestimmer).

At the n bit wide input of the syndrome generator S1 41 For example, the coded values v '= v' ₁ ,..., v ' _{n of} a linear error-correcting code C of length n with an m-dimensional error syndrome are applied. The H-matrix of the code C is denoted by H. At the m-bit output of the syndrome generator the syndrome s (v ') is output, that here after the relation s (v ') = Hv' ^T is formed. The output of the syndrome generator S1 41 is in the m bit wide input of a decoder 47 which output at its n-bit wide output the correction bits e1, ..., en, which are combined to the correction vector e ₁ , ..., e _n (correction signal) outputs. The n bit wide output of the decoder 47 is in each of the first inputs of the n XOR gate 48 (Correction unit) with two inputs and one output, at whose second inputs the coded values are applied and at whose outputs the values corrected by the code C are v _corr = v _{1, corr} ,..., V _{n, corr} = v Ausgegeben e be spent.

The output of the syndrome generator S1 41 is beyond that with the input of a NOR gate 42 and with the respective first input of m XOR gates 431 connected. The circuit S2 12 in 3 is here through the NOR gate 42 realized with m inputs and one output, so that here r = 1 applies. The 1-bit wide output of the NOR gate 42 is in the first 1 bit wide input of the AND circuit 432 guided. The AND circuit, here as an AND symbol 432 is illustrated, consists of m AND gates, each having a first and a second input and one output, at their respective first input of the 1-bit wide output of the NOR gate 42 is connected and at their second input correct the m components of a test input T _i for the error type determiner 44 when s (v ') = 0 and through the NOR gate 42 the value 1 is output and no error is displayed. The m output lines of the AND circuit 432 are with the m second inputs of the XOR gate 431 whose m outputs are in the m inputs of the error type determiner to be tested 44 S4 are guided. The circuit S5 15 from 3 is here through the m XOR gates 431 and the m AND gates 432 realized. Located at the m second inputs of the AND circuit 26 If the test vector T _{i is} on and s (v ') = 0, then there is an error type determiner at the input of the subcircuit under test 44 the test vector T _i , which is processed by this circuit to a test output signal R (T _i ). In 7 1 illustrates that the test bit sequence T _{i is represented} by a test input generator TIG 46 (Test input generator) is generated with an r = 1 bit wide input, which is connected to the output of the NOR gate 42 is connected and with an m-bit wide output, the test signal T _i for the circuit under test Fehlertypbestimmer 44 leads. The test input generator TIG may, for example, be composed of a counter and a ROM (read only memory), wherein whenever the NOR gate 42 the value 1, ie the indication that no error was detectable, is output, the counter is incremented and a new test vector T _{i is} output from the test input generator.

The test input generator may also be implemented as a linear feedback shift register that transitions to a new state each time through the NOR gate 42 the value 1 is output, the state of this linear feedback shift register being able to serve as the test input for the error type determiner.

In this example, the test sequence provider becomes 120 through the NOR gate 42 , the XOR gate 431 the AND gate 432 and the test input generator 46 educated.

Is from the NOR gate 42 If the value 1 is output and that no error has been detected on the basis of the syndrome, then it is up to the error type determiner 44 a test input T _i at its input, that of the error type determiner 44 to a response value R (T _i ) 'is processed. The M-bit wide output of the error type determiner 44 is in the first, M-bit wide input of an evaluation circuit, which in this embodiment as a multiple input signature analyzer MISA 45 (Multi-input signature analyzer) is implemented. At the second, r = 1 bit wide input of the MISA 45 this is due to the NOR gate 42 generated error signal. In the MISA 45 are those at the times in which by the NOR gate 42 generated error signal is equal to 1, applied test output signal values R (T _i ) 'accumulated into a signature. If the signature actually determined matches a signature expected in the error-free case, then no error is detected in the error type determiner. Is true the specific signature of the MISA 45 does not match the expected signature, then an error is detected.

At the times when the NOR gate 42 outputs the value 0 and indicates that a syndrome s (v ') ≠ 0 from the syndrome former S1 41 output is at the input of the error type determiner 44 the value s (v ') of the syndrome and the error type determiner outputs at its M-bit wide output a binary value characterizing the error type.

For example, if the code C is a 2-bit error correcting 3-bit error detecting code, then it is possible that the error type determiner on three different output lines will indicate by a binary signal whether a 1-bit error, a 2-bit error Bit error or a 3-bit error has occurred. Then M = 3.

8th shows a further concrete embodiment 800 where the circuit under test is a decoder S4 57 a circuit arrangement for error correction. The subcircuit S1 11 from 3 to form an error syndrome is referred to here again as a syndrome generator.

At the n bit wide input of a syndrome generator S1 51 For example, the coded values v '= v' ₁ ,..., v ' _{n of} a linear error-correcting code C of length n with an m-dimensional error syndrome are applied. The H matrix of the code C is again denoted by H. At the m-bit output of the syndrome generator the syndrome s (v ') is output, that here after the relation s (v ') = Hv' ^T is formed.

The output of the syndrome generator S1 51 is with the m-digit input of an OR gate with an output 52 and with the respective first input of m XOR gates 531 each with a first and connected to a second input. The circuit S2 12 for error detection in 3 is here by the OR gate 52 realized with m inputs and one output, so that here r = 1 applies. The 1-bit wide output of the OR gate 52 (OR gate) is negated in the first 1 bit wide input of the AND circuit 532 guided. The AND circuit 532 , here as an AND symbol 532 is illustrated, consists of m AND gates each having a first and a second input and one output, at their respective first input of the 1-bit wide, negated output of the OR gate 52 is connected and at their respective second input the correct m components of a test input T _i for the decoder 57 when s (v ') = 0 and through the OR gate 52 the value 0 is output and no error is displayed.

The m output lines of the AND circuit 532 are with the m second inputs of the XOR gate 531 their m outputs are connected to the m inputs of the decoder under test 57 are guided. The circuit S5 15 from 3 is here through the m XOR gates 531 and the m AND gates 532 realized. Located at the m second inputs of the AND circuit 532 the test vector T _i and is s (v ') = 0 then lies at the input of the decoder under test 57 the test vector T _i , which is processed by the decoder to a test output signal R (T _i ) '. In 8th is also illustrated that the test input T _i by a test input generator TIG 56 is generated with an r = 1 bit wide input, which is connected to the output of the OR gate 52 is connected and with an m bit wide output, the test signal T _i for the circuit under test decoder 57 leads. The test input generator TIG may be constructed, for example, of a counter and a ROM, and whenever provided by the OR gate 52 the value 0, ie the indication that no error was detectable, is output, the counter is incremented and a new test vector T _{i is} output from the test input generator.

For example, the test input generator may also be implemented as a linear feedback shift register that transitions to a new state each time it passes through the OR gate 52 the value 0 is output and the state of this linear feedback shift register may serve as the test input (test input) to the error type determiner.

The M = n bit wide output of the decoder 57 is in the first, n-bit wide input of an evaluation circuit 58 led, in this embodiment as Kompaktor 59 with downstream multiple input signature analyzer MISA 510 is realized. At the second r = 1 bit wide input of the MISA 510 this is due to the OR gate 52 generates error signal. In the MISA 510 at the times in which that through the OR gate 52 generated error signal is equal to 0, adjacent, ie by the Kompaktor 59 compacted test response values Komp [R (T _i ) '] accumulated into a signature. If the actually specified signature matches a signature expected in the error-free case, then no error is detected in the decoder. Is true the specific signature of the MISA 45 does not match the expected signature, then an error is detected.

At the times when the OR gate 52 outputs the value 1 and indicates that a syndrome s (v ') ≠ 0 from the syndrome generator S1 51 output is at the input of the decoder 57 the value s (v ') of the syndrome and the decoder outputs at its n-bit wide output an n-ary binary correction value which is in bits 1 which are corrected by the code C.

For example, if the code C is a 2-bit error-correcting code, then it is possible to correct a single bit or two bits. The n-digit coded value v 'is also present at the respective n first inputs of the n XOR gates 512 with two inputs and one output. The n-digit correction value provided by the decoder 57 is also present at the respective first input of the n AND gate 511 each with two inputs and one output, whose second input to the output of the OR gate 52 connected is. The n outputs of the n AND gates are connected to the respective n second inputs of the n XOR gates 511 connected, whose n bits wide outputs the corrected value v _{corr is} output.

If s = 0 and no error is detected on the error syndrome, then the OR gate returns 52 0 and at the second inputs of the n XOR gates 512 in each case the value 0 is applied so that v 'is output unchanged as v _corr = v'. On the other hand, if s ≠ 0, then there is the OR gate 52 the value 1 off. At the m inputs of the decoder 57 Then there is the m-bit syndrome s (v '), since the AND gates 532 the m-digit value 0 is output so that the m XOR gates 531 output at their outputs the error syndrome s (v ') at the inputs of the decoder 57 is applied. The decoder 57 Outputs at its n outputs the corresponding correction values that are passed through the n AND gates 511 in the n XOR gates 512 be linked to the corrected value v _corr . If the errors in v 'can be corrected by the chosen code C, then v _{corr is} error-free.

The evaluation circuit 58 consists in the special embodiment of a Kompaktor 59 and a downstream multi-input signature analyzer MISA 510 , The compactor 59 maps an n-bit input to a n-bit wide output, where n '<n. The compactor 59 In the simplest case, it can be a parity tree with n inputs and one output. In this case, n '= 1. Similarly, n', with n '> 1, parity trees can be realized. Also it is possible that the compactor 59 Has memory elements. Is the output value of the OR gate 52 equals 0, then in the MISA those of the decoder 57 output response values R (T _i ) and from the Kompaktor 59 compacted values in the MISA accumulated. If the syndrome is s (v ') ≠ 0 and an error is detected, the MISA does not accumulate any value at its inputs.

The test sequence provider 120 is through the OR gate 52 , the XOR gate 531 , the AND gate 532 and the test input generator 56 , the evaluation circuit 58 through the compactor 59 and the multiple input signature analyzer 510 and the correction unit through the AND gate 511 and the XOR gate 512 educated.

9 represents a further circuit arrangement 900 according to the proposed concept.

bedeutet.At the n bit wide input of a syndrome generator S1 61 For example, the coded values v '= v' ₁ ,..., v ' _{n of} a linear error-correcting code C of length n with an m-dimensional error syndrome are applied. The H matrix of the code C is again denoted by H. At the m bit wide output of the syndrome generator 61 the syndrome s (v ') is spent here after the relationship s (v ') = Hv' ^T is formed. If v 'is a codeword, then the syndrome is 0, but if v' is not a codeword then the syndrome is not 0, where 0

means.

The output of the syndrome generator S1 61 is in the m bit wide input of the error detection circuit S2 62 and at the same time in the m-bit-wide first input of the subcircuit S5 63 guided. The circuit for error detection S2 62 outputs different error signals at its r = 1-bit wide output if a code word codeword syndrome or a code C non-codeword syndrome is present at its m-bit input. The r = 1 bit wide output of the error detection circuit is in the third r bit wide input of the subcircuit S5 and in the input of a test input generating circuit TIG 612 guided. The test input generating circuit always generates a test input Ti when the error detection circuit outputs a value corresponding to a code word code word syndrome. The output of the circuit TIG carrying the value T _i 612 is the second m bit wide input of the subcircuit S5 63 connected. If an error signal which corresponds to a code word of the code C from the error detection circuit S2 12 is output, then at the third m bit wide input of the subcircuit S5 63 entered a test vector Ti.

The subcircuit S5 63 is configured to output at its m-bit wide output the value applied to its first input when the error signal from the second sub-circuit S2 62 outputting a syndrome of a code C non-codeword and outputting the value T _i when the error signal output from this subcircuit corresponds to a syndrome of a codeword of the code C.

The test sequence provider is controlled by the sub-circuit S2, the sub-circuit S5 and the test input generator TIG 612 educated.

The output of the subcircuit S5 63 is simultaneously in the input of a decoder 642 and to the input of an error type determiner 641 guided. The n bit wide output of the decoder 642 is in each of the first inputs of n XOR gates 66 each having two inputs and one output, at whose respective second inputs the coded values v ' ₁ ,..., v' _{n are} present, which are also present at the input of the syndrome generator S1 61 issue. If v '= v' ₁ , ..., v ' _{m is} a codeword then that of syndrome generator S1 61 generated syndrome s (v ') = 0 and the output of the subcircuit S5 63 is connected to its second input carrying the test input T _i , so that at the entrance of the decoder 642 the test input T _i is present. From the decoder 642 the corresponding test output signal R '(T _i ) is output and in the XOR gates 66 is added to v '⊕ R (T _i )' modulo 2 and output at the n outputs of these n XOR gates.

These outputs are in the respective n first inputs of further n XOR gates 67 each having two inputs and one output, at their respective second inputs the outputs of n AND gates 68 each with two inputs and one output are connected. At the respective first input of these AND gates 68 is that of the error detection circuit S2 62 outputted error signal E ₁ that, since there is a code word, is equal to 1. The respective second inputs of these AND gates are connected to the input of a test response generator TRG 610 whose input is also connected to the error signal E ₁ supporting the output of the error detection circuit S2 62 connected is. If E ₁ = 1, then the input of the test input T _i of decoder 642 outputted error-free test output R (T _i ) from the test response generator TIG 610 spent in the XOR gates 67 with v '⊕ R (T _i )' v _corr = v '⊕ R (T _i )' ⊕ R (T _i )

XOR and on the n output lines of these n XOR gates 66 provided.

The n-digit output of these n XOR gates is in the input of a code checker 69 and directly connected to the v _corr bearing circuit output. The code checker 69 checks if v _{corr is} a codeword of the code C. If R (T _i ) = R (T _i ) ', then v _corr = v'. The code checker can be realized, for example, as a syndrome generator of the code C with n inputs and m outputs, which outputs the error syndrome s ( _vcorr ) at its m outputs and which has an OR connection of its output lines. However, only a few components of the error syndrome can be realized by the code checker. Since the person skilled in the design of code reviewers is known and the special form of the Code Tester is not the subject of the claims, this should not be further elaborated here.

If v _{corr is} not a valid codeword, then R (T _i ) ≠ R (T _i ) 'and upon input of the test input T _i an error in the decoder is detected.

The evaluation circuit 14 from 3 is here as a circuit 652 realized from the circuit components 66 . 67 . 68 and 69 consists. Here is the correction unit 240 through the circuit components 66 . 67 formed and part of the evaluation circuit.

Generally speaking, the correction unit can generate a processed test output signal based on a logical XOR combination of the correction signal with the coded binary word v 'and provide the evaluation unit. In general, a logical XOR operation can be realized by an XOR logic gate.

In general terms, the evaluation unit can have a code checker. In addition, the correction unit may generate the processed test output based on a logical XOR of an expected reference test signal R (T _i ) resulting in XORing the correction signal e with the coded binary word v 'when the error syndrome bit sequence indicates s (v') in that the coded binary word v 'is a codeword of the error correction code C. The code checker then generates an error signal indicating whether the processed test output is a codeword of the error correction code C.

The output of the subcircuit S5 is also in the input of an error type determiner 641 which indicates at its r bit wide output using the values of the error syndrome s (v ') which type of error is present. The r bit wide output of this error type determiner 641 is in a first, r bit wide input of a first evaluation circuit 651 led to the second, here 1-bit wide input the error signal E1 is input, that of the sub-circuit for error detection S2 62 is issued. In addition, it is possible that additional outputs of the error type determiner 641 , which is about improving the testability of the error type determiner 641 serve, are used, which are also performed in additional inputs of the evaluation circuit. The evaluation circuit 652 For example, a multi-input signature analyzer MISA may be used which accumulates the test output signal values (test response values) generated by the error type determiner whenever the subcircuit S2 for error detection indicates that the syndrome of a codeword is present at its input.

In 9 is just a test input generator TIG 612 located. It is also possible to use two or more test input generators, with the first test input generator providing test inputs for the error type determiner 641 generated and the second test input generator test inputs for the decoder 642 generated.

10 shows another possible realization 1000 the evaluation circuit 14 from 3 for example, the evaluation circuit 652 from 9 can replace. The output of the decoder 742 is in each of the first inputs of n XOR gates 76 each having two inputs and one output, whose respective second inputs are connected to the n lines which carry the coded values n and which are simultaneously connected to the n first inputs of a multiplexer MUX 71 are connected. The n bit wide output of the n XOR gates 76 is simultaneously in the n bit wide input of a code checker 72 and in the second n inputs of the multiplexer MUX 71 guided, which outputs at its input the value V _corr and at whose control input the error signal E1, which at the output of the circuit for error detection S2 62 in 9 is issued.

The evaluation circuit 130 includes in the example the code checker 72 and the MISA 73 and the correction unit 240 includes the XOR gate 76 and the multiplexer 71 ,

If v 'is a codeword of the considered code C, then the error signal E _{1 is} in 9 equal to 0 and in the decoder 742 the test input signal T _{i is} input. The decoder 742 outputs the test response signal R (T _i ) '. At the output of the XOR gate 76 is the value v '⊕ R (T _i )' in the code checker 72 is entered. The multiplexer MUX 71 connects its first input to its output, to which the value v _corr = v 'is applied. The code checker is executed, for example, as a syndrome generator of the linear code C. It then gives the value at its m bit wide output C _odepr (v '⊕ R (T _i )') = C _odepr (v ') ⊕ C _odepr (R (T _i )') = C _odepr (R (T _i ) ') which depends only on R (T _i ) 'and which in the cycles where E ₁ equals 0 in the MISA 73 accumulated to a signature.

If v 'is not a codeword of the considered code C, then the error signal E _{1 is} equal to 1. At the input of the decoder 742 then the value v 'is applied. The decoder then outputs correction values e ₁ ,..., E _n , which are combined to form an n-digit correction vector e = e ₁ ,..., E _n . The correction vector e is in the XOR gates 76 linked to v 'to v' ⊕ e = v _corr . Since the error signal E1 is equal to 1, the second input of the multiplexer becomes MUX 71 linked to its output, on which now v _corr = v '⊕ e is output. The one by the code checker 72 output value C _odepr (v '⊕ e) is ignored in the MISA and not accumulated since E ₁ = 1.

11 shows a further embodiment of a circuit arrangement in which the matrix K = H _mod from the parity check matrix H = (h1, ..., h _n ) is derived by q columns h _i1 , ..., h _iq ) are component-inverted. The subcircuit f 810 realizes the function f (v ' ₁ , ..., v' _n ) = v ' _i1 ⊕ ... ⊕ v _ig whose q inputs are connected to the q inputs of the syndrome former S1 81 are connected, which carry the components v _i1 , ..., v _iq . The m-component output of the syndrome former S1 81 is simultaneous with the m inputs of an OR gate 821 with m inputs and one output, an AND gate 822 with m inputs and one output and the m each first inputs of m XOR gates 831 connected to two inputs and one output. The outputs of the OR gate carrying the binary values E ₁ and E ₂ 821 and the AND gate 822 are both in the first and second input of an XOR gate 823 and in the first and second input of a test input generator TIG 85 as well as in the first two inputs of an evaluation circuit 89 guided.

The output of the test input generator TIG 85 is with the respective first inputs of m AND gates 832 connected to two inputs and one output, with their respective second inputs of the negated output of the XOR gate 823 which is at the same time unnegated to the respective first input of n AND gates 88 is connected with two inputs and one output. The second inputs of the XOR gates 831 are with the outputs of the AND gates 832 connected. The m outputs of the m XOR gates 831 are in the m first inputs of the m XOR gates 84 each having two inputs and one output each having its second inputs connected to the output of the circuit for forming the function f 810 are connected. The m outputs of the m XOR gates 84 are with the m inputs of a decoder 86 connected, which provides at its n outputs the n-component correction value, wherein the n outputs of the decoder 86 simultaneously with the n third inputs of the evaluation circuit 89 are connected. The n outputs of the n AND gates 88 are in each of the n first inputs of the n XOR gates 87 at whose n first inputs the values v '= v' ₁ , ..., v ' _n are connected to leading input lines and whose output lines output the corrected value v _corr .

The correction unit 240 in this example includes the AND gate 88 and the XOR gate 87 and the test sequence provider 120 includes the circuit for forming the function f 810 , the XOR gate 84 , the OR gate 821 , the AND gate 822 , the XOR gate 831 , the XOR gate 823 , the AND gate 832 and the test input generator 85 wherein the circuit for forming the function f 810 and the XOR gate 84 a bit sequence inverter of the test sequence provider 120 form.

For a better understanding, the operation of the circuit arrangement of 11 to be discribed.

aus, wenn f(v') = 0 ist und den Wert

aus, wenn f(v') = 1 ist. Wir betrachten zunächst den Fall f(v') = 0. Es gilt E₁ = E₂ = 0, E = 0 und der Testinput-Generator TIG gibt einen Wert T_i aus, der, geleitet über die AND-Gatter 832, die XOR-Gatter 831 und 84 am Eingang des Decoders 86 anliegt. Da der das Fehlersignal E tragende Ausgang des XOR-Gatters 823 gleich 0 ist, gilt v_corr = v'. Der Decoder gibt den Wert R(T_i)' aus, der in der Auswerteschaltung 89 akkumuliert wird.If v 'is a codeword then the syndrome generator gives S1 81 the value

off if f (v ') = 0 and the value

off if f (v ') = 1. We first consider the case f (v ') = 0. E ₁ = E ₂ = 0, E = 0, and the test input generator TIG outputs a value T _i , which is passed through the AND gates 832 , the XOR gate 831 and 84 at the entrance of the decoder 86 is applied. Since the output of the XOR gate carrying the error signal E 823 is 0, v _corr = v '. The decoder outputs the value R (T _i ) 'in the evaluation circuit 89 is accumulated.

aus, der an den m Eingängen des OR-Gatters 821 und an den m Eingängen des AND-Gatters 822 anliegt, so dass diese beiden Gatter die Werte E₁ = E₂ = 1 ausgeben, die in dem XOR-Gatter 823 zu 0 verknüpft werden, so dass an den m Ausgängen der m AND-Gatter 832 jeweils der Wert T_i anliegt und in den m XOR-Gattern 831 zu (1, ..., 1) ⊕ T_i und in den XOR-Gattern 84 zu (1, ..., 1) ⊕ T_i ⊕ (1, ..., 1) = T_i verknüpft wird, so dass der Testinput T_i in den Eingang des Decoders 86 eingegeben wird, der an seinem Ausgang den Testresponsewert R(T_i)' ausgibt, der in die Auswerteschaltung 89 zur Auswertung eingegeben wird. Da der von dem XOR-Gatter ausgegebene Wert E = 0 ist, wird von den Ausgängen der AND-Gatter 88 der Wert

ausgegeben, und es gilt v' = v_corr.Now let f (v ') = 1. The syndrome generator S1 81 now gives the value

off, at the m entrances of the OR gate 821 and at the m entrances of the AND gate 822 is applied so that these two gates output the values E ₁ = E ₂ = 1, which in the XOR gate 823 are linked to 0 so that at the m outputs of the m AND gate 832 in each case the value T _i is present and in the m XOR gates 831 to (1, ..., 1) ⊕ T _i and in the XOR gates 84 to (1, ..., 1) ⊕ T _i ⊕ (1, ..., 1) = T _{i is} linked, so that the test input T _i in the input of the decoder 86 is input, which outputs at its output the Testresponsewert R (T _i ) ', which in the evaluation circuit 89 is entered for evaluation. Since the value E = 0 output from the XOR gate becomes the outputs of the AND gates 88 the value

and v '= v _corr .

und ebenfalls ungleich

If v 'is now no code word, then this is from the syndrome generator S1 81 generated syndrome s (v ') unequal

and also unequal

Thus, E ₁ ≠ E ₂ and thus E = 1. The syndrome s (v ') is unchanged from the XOR gates 831 output and in the XOR gates 84 then inverted when f (v ') = 1, so that the syndrome is now applied to the decoder as if it were from the parity check matrix H of the code C after the relationship s (v ') ^T = H * v' would have been determined. In the decoder 86 the bits to be corrected are determined which can be combined to form the correction vector e, which, because of E = 1, is passed through the AND gates 88 and in the XOR gates 87 to v '⊕ e = v _corr modulo 2. In the evaluation circuit 89 be the ones from the decoder 86 output values are not evaluated, since E ₁ ≠ E ₂ applies.

In principle, it is possible to change the order of the XOR gates 831 and 84 to swap. In the 11 specified order has the advantage that the values in the inputs of the XOR gates 831 and 84 are not constant even if only codewords v 'are input to the circuit inputs. Likewise, the values of the error syndromes generated by the syndrome generator S1 are not constant when only codewords are input, which is advantageous because stuck-at errors of the corresponding inputs and outputs of the respective gates can be detected during operation.

Some embodiments relate to an apparatus for testing a circuit under test, having means for determining an error syndrome bit sequence, means for providing a test sequence, and means for detecting erroneous processing. The means for determining an error syndrome bit sequence determines an error syndrome bit sequence s (v ') based on a coded binary word v'. Here, the error syndrome bit sequence s (v ') indicates whether the coded binary word v' is a codeword of an error correction code C used to encode the coded binary word v '. Furthermore, the means for providing a test bit sequence at least once provides a test bit sequence T _i of the circuit under test different from the error syndrome bit sequence s (v ') if the error syndrome bit sequence s (v') indicates that the coded binary word is a code word of the error correction code C. Furthermore, the means for detecting erroneous processing based on a caused by the test bit sequence T _i test output signal R (T _i ) 'of the circuit under test detects an erroneous processing of the test bit sequence T _i by the circuit under test.

In addition, the device may include other optional units that implement one or more of the previously described aspects of the proposed concept.

12 shows a flowchart of a method 1200 for testing a circuit under test according to an embodiment. The procedure 1200 includes a determination 1210 an error syndrome bit sequence s (v ') based on a coded binary word v'. Here, the error syndrome bit sequence s (v ') indicates whether the coded binary word v' is a codeword of an error correction code C used to encode the coded binary word v '. Further, the method has 1200 at least once a provision 1220 one of the error syndrome bit sequence v 'different test bit sequence T _i to the circuit under test when the error syndrome bit sequence v' indicates that the encoded binary word v 'is a code word of the error correction code C. Furthermore, the method includes 1200 a recognition 1230 faulty processing of the test bit sequence T _i by the circuit under test, based on a test output signal R (T _i ) 'of the circuit to be tested caused by the test bit sequence T _i .

In addition, the process can 1200 include further optional steps that implement one or more of the previously described aspects of the proposed concept.

Some embodiments relate to a circuit arrangement that allows the test during operation (online test).

For example, a circuit arrangement for processing data coded using a code C comprises a first sub-circuit S1 11 with n binary inputs and m binary outputs with m <n for forming an m-bit-wide syndrome, to whose n binary inputs the encoded n-bit wide data to be processed v '= v' ₁ , ..., v ' _{n are} present and At its m binary outputs m components s ₁ (v '), ..., s _m (v') = s (v ') of a syndrome s (v') are output. The syndrome s (v ') becomes from the coded data v' on the relation s (v ') ^T = K. and K is a binary (m, n) matrix corresponding to code C.

Furthermore, a second sub-circuit S2 12 for error detection with m binary inputs and r, 1 ≤ r, outputs present, wherein the m syndrome components s ₁ , ..., s _m carrying outputs of the first subcircuit are connected to the m inputs of the second subcircuit. The second subcircuit outputs different values upon input of s (v ') when no codeword of the code C is and when v' is a codeword of the code C.

Furthermore, a third sub-circuit S3 to be tested is provided 13 with m ', m' ≥ 1 binary inputs and M, M ≥ 1, binary outputs at whose m 'binary inputs at times t _i to which the second subcircuit outputs values indicating that a syndrome s (v' ) of a code word v 'of the code C has been input at its inputs, a test input T _i is present. This third sub-circuit outputs on its M outputs a test response value R (T _i ) 'dependent on the applied test input T _i and on any error present on its M outputs.

In one aspect, there is an evaluation circuit 14 for the evaluation of test responses, the test output signals R (T _i ) from the third sub-circuit S3 13 are output at times t _i , to which the second sub-circuit S2 = F 12 for error detection, outputs values indicating that a syndrome s (v ') of a codeword v' of the code C is present at the inputs of the second subcircuit, and related to expected correct test responses.

Further, the matrix K may be equal to the parity check matrix H = (h ₁ ,..., H _n ) of the code C.

Alternatively, the matrix K may be a binary (m, n) matrix determined by component-by-component inversion of q columns of the parity check matrix H = (h ₁ ,..., H _n ) of the code C and 1 ≤ q ≤ n ,

It can be z. B. q = 1.

In another aspect, a fifth sub-circuit is S5 15 with m first binary inputs, m second binary inputs, r third binary inputs and m binary outputs, the m binary outputs of the first subcircuit S1 11 having the syndrome s (v ') with the first m binary inputs of the fifth subcircuit S5 15 are connected. An m-digit test vector T _i is applied to the second m binary inputs of the fifth subcircuit at a time t _i and the r binary outputs of the second subcircuit S 2 12 are connected to the third r binary inputs. The fifth subcircuit S5 15 is designed such that at its m binary outputs, the syndrome s (v ') is output when the second sub-circuit S2 12 outputs a value which does not correspond to a codeword and so that the value T _{i is} output when the second sub-circuit outputs a value corresponding to a codeword of the code C.

Further, the m binary inputs are the third sub-circuit S3 to be tested 13 with the m binary outputs of the subcircuit S5 15 connected and the M binary outputs of the subcircuit S3 13 are in M binary inputs of the subcircuit 14 guided, the test response values R (T _i ) ', of the third sub-circuit S3 to be tested 13 at times t _i when the second subcircuit outputs a value corresponding to a codeword associated with expected non-defective test output signals.

Furthermore, a further sub-circuit S6 16 with q binary inputs and a binary output to realize a function f (v ' ₁ , ..., v' _n ) = v ' _i1 ⊕ ... ⊕ v' _iq

Be present whose q inputs are connected to the input lines of the subcircuit S1 carrying the values v ' _i1 , ..., v' _iq and their 1-bit wide output to the first, 1-bit wide input of a seventh subcircuit S7 17 is guided, whose second m bit wide input is connected to the output of the fifth sub-circuit S5 and the sub-circuit S7 is configured so that at the m-bit-wide output of the seventh sub-circuit S7 17 the values applied to their second input are output unchanged if f (v ₁ ,..., v _n ) = 0 and the component-negated values of the values present at their inputs are output, if f (v ₁ , ... , v _n ) = 1.

Furthermore, the m binary inputs are the subcircuit S3 to be tested 13 with the m outputs of the seventh subcircuit S7 17 connected, so that at the inputs of the sub-circuit S3, the value T _i is present when the second sub-circuit outputs a value corresponding to a code word and the third sub-circuit S3 13 outputs a test output signal value R (T _i ) 'on its M outputs which depends on the test input T _i and on any errors which may be present in it, the M inputs of an evaluation circuit 14 to Evaluation of test response values, in which the current test response values are compared with expected error-free test response values at appropriate times.

In addition, q = 1, f (v, ..., v ' _n ) = v' _i with 1 ≤ i ≤ n, and the function f (v ' ₁ , ..., v' _n ) can be replaced by a 1 Bit wide line is realized, which carries the value v ' _i .

The subcircuit under test may be an error type determiner 44 to be a code.

Alternatively, the sub-circuit under test may be a decoder of an error correcting circuit using a code C.

In addition, there may be another circuit under test which is an error type determiner 641 of the error correcting code.

In one aspect, a test input generator 46 be present, which at times t _i , in which the circuit for error detection indicates no error, outputs a test signal T _i .

The test input generator may include a ROM and a counter.

Alternatively, the test input generator may include a linear feedback shift register.

Further, the evaluation circuit of the test output signal values may include a multiple input signature analyzer (Multi-Input Signature Analyzer).

Furthermore, the evaluation circuit 14 the test output values a code checker 69 . 76 of the code C included.

Furthermore, m '= m.

Optionally, additional outputs of the circuit to be tested, which serve to improve the testability of the circuit to be tested, can be evaluated in the evaluation circuit.

Although some aspects have been described in the context of a device, it will be understood that these aspects also constitute a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Similarly, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device.

Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software. The implementation may be performed using a digital storage medium, such as a floppy disk, a DVD, a Blu-ray Disc, a CD, a ROM, a PROM, an EPROM, an EEPROM or FLASH memory, a hard disk, or other magnetic disk or optical memory are stored on the electronically readable control signals that can cooperate with a programmable computer system or cooperate such that the respective method is performed. Therefore, the digital storage medium can be computer readable. Thus, some embodiments according to the invention include a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the methods described herein is performed.

In general, embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is operable to perform one of the methods when the computer program product runs on a computer. The program code can also be stored, for example, on a machine-readable carrier.

Other embodiments include the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine-readable medium.

In other words, an embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer. A further embodiment of the inventive method is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program is recorded for carrying out one of the methods described herein.

A further embodiment of the method according to the invention is thus a data stream or a sequence of signals, which represent the computer program for performing one of the methods described herein.

The data stream or the sequence of signals may be configured, for example, to be transferred via a data communication connection, for example via the Internet.

Another embodiment includes a processing device, such as a computer or a programmable logic device, that is configured or adapted to perform one of the methods described herein.

Another embodiment includes a computer on which the computer program is installed to perform one of the methods described herein.

In some embodiments, a programmable logic device (eg, a field programmable gate array, an FPGA) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform one of the methods described herein. In general, in some embodiments, the methods are performed by any hardware device. This may be a universal hardware such as a computer processor (CPU) or hardware specific to the process, such as an ASIC.

The embodiments described above are merely illustrative of the principles of the present invention. It will be understood that modifications and variations of the arrangements and details described herein will be apparent to others of ordinary skill in the art. Therefore, it is intended that the invention be limited only by the scope of the appended claims and not by the specific details presented in the description and explanation of the embodiments herein.

Claims (21)

Contraption ( 100 . 200 . 300 . 400 . 500 . 600 . 700 . 800 . 900 . 1000 . 1100 ) for testing a circuit under test ( 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ), having the following features: a syndrome tester ( 110 . 11 . 21 . 41 . 51 . 61 . 81 ) adapted to determine an error syndrome bit sequence (s (v ')) based on a coded binary word (v'), the error syndrome bits sequence (s (v ')) indicating whether the coded binary word (v') is a codeword is an error correction code (C) used to encode the coded binary word (v '); a test sequence provider ( 120 ), which is designed, at least once, to have a test bit sequence (T _i ) of the circuit under test (T _i ) which differs from the specific error syndrome bit sequence (s (v ')) ( 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ) when the error syndrome bits sequence (s (v ')) indicates that the coded binary word (v') is a codeword of the error correction code (C); and an evaluation circuit ( 130 . 14 . 25 . 58 . 89 ) which is designed to be based on a test output signal (R (T _i ) ') of the circuit under test (T _i ) caused by the test bit sequence (T _i ). 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ) an erroneous processing of the test bit sequence (T _i ) by the circuit under test ( 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ) to recognize. The device of claim 1, wherein the test sequence provider ( 120 ) is designed to match the error syndrome bit sequence (s (v ')) of the circuit under test ( 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ) when the error syndrome bits sequence (s (v ')) indicates that the coded binary word (v') is not a codeword of the error correcting code (C). Device according to claim 1 or 2, wherein the evaluation circuit ( 130 . 14 . 25 . 89 ) is adapted to compare the test output signal (R (T _i ) ') or a processed or reduced test output signal based on the test output signal (R (T _i )') with an expected reference test signal (R (T _i )) and erroneous processing the test bit sequence (T _i ) if the test output signal (R (T _i ) ') or the processed or reduced test output signal does not match the expected reference test signal (R (T _i )). Apparatus according to any one of the preceding claims, wherein the test sequence (T _i ) is equal to an error syndrome bits sequence (s (v ')) for a coded binary word (v') which is not a codeword of the error correction code (C). Device according to one of the preceding claims, further comprising the circuit under test ( 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ), wherein the circuit under test ( 102 . 13 . 24 . 44 . 547 . 641 . 642 . 742 . 86 ) a decoder ( 54 . 642 . 742 . 86 ) for generating a correction signal for correcting a faulty coded binary word (v ') or an error type determiner ( 44 . 641 ) for determining an error type of a defective coded binary word (v '). Device according to one of the preceding claims, wherein the syndrome tester ( 110 . 11 . 21 . 41 . 51 . 61 . 81 ) is adapted to determine the error syndrome bit sequence (s (v ')) such that the error syndrome bit sequence (s (v')) is always equal to a predefined error syndrome bit sequence if the coded binary word (v ') is a code word of the error correction code (C ). Apparatus according to any one of claims 1 to 5, wherein the error syndrome bits sequence (s (v ')) for a first plurality of codewords of the error correction code (C) is equal to a first predefined error syndrome bits sequence and the error syndrome bits sequence (s (v')) for a second plurality of codewords of the error correction code (C) is equal to a second predefined error syndrome bit sequence, wherein the first predefined error syndrome bit sequence and the second predefined error syndrome bit sequence differ and the first plurality of codewords and the second plurality of codewords do not have common codewords. Apparatus according to claim 7, wherein the test sequence provider ( 120 ) a bit sequence inverter ( 16 . 17 . 810 . 84 ) configured to invert the test bit sequence (T _i ) or the error syndrome bit sequence (s (v ')) based on a function (f (v')) of a subset of bits of the coded binary word (v '). Apparatus according to claim 8, wherein the function (f (v ')) of the subset of bits is selected, such that the bit sequence inverter ( 16 . 17 . 810 . 84 ) the test bit sequence (T _i ) is not inverted if the error syndrome bit sequence (s (v ')) equals the first predefined error syndrome bit sequence, and the test bit sequence (T _i ) inverts if the error syndrome bit sequence (s (v')) equals the second predefined one Error syndrome bit sequence is. Device according to one of the preceding claims, wherein the test sequence provider ( 120 ) an error syndrome recognizer ( 12 . 22 . 42 . 52 . 62 . 821 . 822 ) adapted to provide a test trigger signal comprising the provisioning of a test bit sequence (T _i ) by the test sequence provider ( 120 ) when the error syndrome bit sequence (s (v ')) equals a predefined error syndrome bit sequence, the predefined error syndrome bit sequence indicating that the encoded binary word (v') is a code word of the error correction code (C). The device of claim 10, wherein the test trigger signal is a 1 bit wide signal. Device according to one of the preceding claims, wherein the syndrome tester ( 110 . 11 . 21 . 41 . 51 . 61 . 81 . 110 ) is adapted to calculate the error syndrome bit sequence (s (v ')) based on a multiplication of a parity check matrix (H) of the error correction code (C) with the coded binary word (v') or a multiplication of a parity check matrix (K) component-inverted in at least one column. of the error correction code (C) with the coded binary word (v '). Device according to one of the preceding claims, wherein the test sequence provider ( 120 ) is adapted to generate in each case one test bit sequence (T _i ) from a plurality of test bit sequences for each coded binary word (v '), that of the syndrome tester ( 110 . 11 . 21 . 41 . 51 . 61 . 81 ) and a code word of the error correction code (C) is the circuit under test ( 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ). The device of claim 13, wherein the test sequence provider ( 120 ) has a memory which stores the plurality of test bit sequences or has a linear feedback shift register enabling generation of a test bit sequence (T _i ) of the plurality of test bit sequences. Apparatus according to any one of the preceding claims, wherein the error correction code (C) is a linear error correction code. Device according to one of the preceding claims, wherein the test sequence provider ( 120 ) is adapted to at least 10%, at least 50%, or always a different test bit sequence (T _i ) of the circuit under test (S (v ')) from the determined error syndrome bit sequence ( 102 . 13 . 24 . 44 . 54 . 641 . 642 . 742 . 86 ) when the error syndrome bit sequence (s (v ')) indicates that the coded binary word (v') is a codeword of the error correction code (C). Contraption ( 200 . 700 . 800 . 900 . 1000 . 1100 ) for correcting a bit error in a coded binary word (v ') comprising: an apparatus for testing a circuit under test according to any one of claims 1 to 16; a decoder ( 250 . 54 . 642 . 86 ) which is adapted to generate an output signal based on the error syndrome bit sequence (s (v ')), such that the output signal of the decoder ( 250 . 54 . 642 . 86 ) represents a coded binary word (v ') correction signal (e) if the error syndrome bits sequence (s (v')) indicates that the coded binary word (v ') is not a codeword of the error correction code (C), the decoder ( 250 . 54 . 642 . 86 ) is the circuit under test and the output signal of the decoder ( 250 . 54 . 642 . 86 ) corresponds to the test output (R (T _i ) ') when the error syndrome bits sequence (s (v')) indicates that the coded binary word (v ') is a codeword of the error correction code (C); and a correction unit ( 240 ) adapted to correct, based on the coded binary word (v ') and the correction signal (e), a bit error in the coded binary word (v') and output a corrected coded binary word (V _corr ). Apparatus according to claim 17, wherein the correction unit ( 240 ) is designed to generate a processed test output signal based on a logical XOR combination of the correction signal with the coded binary word (v ') and the evaluation circuit ( 130 . 14 . 25 . 89 ). Apparatus according to claim 18, wherein the evaluation circuit ( 130 . 14 . 25 . 89 ) a code checker ( 69 . 72 ), wherein the correction unit ( 240 ) is adapted to generate the processed test output signal based on an XOR logical combination of an expected reference test signal (R (T _i )) resulting in the XOR logic operation of the correction signal (e) with the coded binary word (v ') the error syndrome bit sequence (s (v ')) indicates that the coded binary word (v') is a codeword of the error correction code (C), the coder ( 69 . 72 ) is adapted to generate an error signal indicating whether the processed test output signal is a code word of the error correction code (C). Procedure ( 1200 ) for testing a circuit under test, comprising the steps of: determining ( 1210 ) of an error syndrome bits sequence (s (v ')) based on a coded binary word (v'), the error syndrome bits sequence (s (v ')) indicating whether the coded binary word (v') is a codeword of a coding coded coded binary word (v ') is error correction code (C); Provide ( 1220 ) at least once one of the error syndrome bit sequence (s (v ')) different test bit sequence (T _i ) to the circuit under test, if the error syndrome bit sequence (s (v')) indicates that the coded binary word (v ') is a code word of the error correction code (C) is; and recognizing ( 1230 ) faulty processing of the test bit sequence (T _i ) by the circuit under test, based on a test output signal (R (T _i ) ') of the circuit under test caused by the test bit sequence (T _i ). Computer program with a program code for carrying out the method according to claim 20, when the computer program runs on a computer or microcontroller.

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