DE102011079835B4 - Method for reducing the mechanical strain in complex semiconductor devices during chip-substrate bonding by means of a multi-stage cooling scheme - Google Patents

Abstract

A method of assembling at least one of a semiconductor chip and a package substrate, comprising: heating a composite device above a melting temperature of a solder material formed between a contact structure of the package substrate and a contact structure of the at least one semiconductor chip, the composite device comprising at least one semiconductor chip and the package substrate; Applying a first cooling phase having at least one time-averaged first cooling rate for cooling to a grain stabilization temperature of the composite component and causing solidification of the solder material, wherein the spatially averaged temperature of the at least one semiconductor chip is in the range of 80 ° C to 150 ° C at the end of the first cooling phase such that an average grain size of the contact structure is in a range of 1 μm to 39 μm; and applying a second cooling phase near the first cooling phase at a second time-averaged cooling rate that is less than the first cooling rate, wherein the first cooling rate is at least twice the second cooling rate, and wherein the second cooling phase reduces mechanical stress in the contact structure of the at least one semiconductor chip ,

Description

Field of the present invention

In general, the present invention relates to integrated circuits, and more particularly, to complex semiconductor devices comprising a complex metallization system that includes sensitive dielectrics and / or a three-dimensional chip configuration, resulting in significant sensitivity to mechanical stress during the bonding process of the chip package device.

Description of the Related Art

Semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific integrated circuits), single-chip systems or systems-on-a-chip (SoC), and the like, are typically mounted on suitable substrate materials, such as silicon dioxide. Silicon, and the like, with the individual integrated circuits arranged on a wafer in an array such that most manufacturing steps involve complex integrated circuits except for photolithography processes, measurement processes, and the packaging of the individual elements after dicing the substrate for all chip areas be executed simultaneously. As a result, economic constraints are driving semiconductor manufacturers to steadily increase substrate dimensions, thereby also increasing the area available for the production of current semiconductor devices and, consequently, increasing the production yield.

In addition to increasing the area of the substrate, it is also important to optimize the utilization of the substrate area for a given size such that as much substrate area as possible is used for semiconductor devices and / or test structures that can be used in process control. In an attempt to maximize the usable surface area for a given size, the feature sizes of circuit elements are constantly being reduced. Copper in conjunction with low ε dielectrics, so-called low-k dielectrics, has become a commonly used alternative in the fabrication of complex interconnect structures due to this constant demand for reducing feature sizes. These interconnect structures include metal line layers and via layers having metal lines as interconnects within a layer and vias between the layers, which generally interconnect individual circuit elements to provide the required function of the integrated circuit. Typically, a plurality of stacked metal line layers and via layers are necessary to implement the interconnections between all of the internal circuit elements and I / O (input / output), supply, and ground connections of the related circuitry.

The delay of signal propagation is no longer limited by the circuit elements in extremely scaled integrated circuits such. But limited by the immediate proximity of the metal lines, due to the increased density of circuit elements requiring even an increased number of electronic connections, as the line-to-line capacitance increases, whereas, reduced line performance is due to the reduced cross-sectional area of the metal regions. For this reason, conventional dielectrics, such as. As silicon dioxide (ε> 4) and silicon nitride (ε> 7) replaced by dielectrics, which have a low permittivity, which are therefore also referred to as dielectrics with low ε, or low-k dielectrics, which has a relative permittivity less than or equal to 3 exhibit. However, the density and mechanical strength or strength of low ε, or low-k dielectrics may be significantly less compared to the prior art dielectrics, such as silicon dioxide and silicon nitride. Consequently, during the fabrication of the metallization system and subsequent integrated circuit fabrication processes, the production yield will depend on the mechanical properties of these sensitive dielectrics and their adhesion to other materials.

In addition to the low mechanical strength issues encountered with modern dielectrics with dielectric constants or permeabilities of 3.0 or significantly lower, the reliability of the components during final assembly of complex semiconductor devices by these materials may be due to interaction between the chip and the package be influenced to a significant extent, caused by the thermal mismatch of the corresponding thermal expansion coefficients of the different materials. In the manufacture of complex integrated circuits, for example, a contact technology for connecting the package carrier to the chip, which is known as a flip-chip mounting technique, is increasingly being used. In contrast to established wire bonding techniques in which suitable pads are disposed on the periphery of the very last metal layer of the chip and the pads are connected to respective terminals of the package by means of a wire, in the flip-chip technique a corresponding bump structure is formed on the last metal layer , which can be brought into contact with corresponding contact surfaces of the housing, which are formed on it from a solder material. As a result, a reliable electrical and mechanical connection can be formed between the terminal metal formed on the last metallization layer and the contact surfaces of the package carrier after the solder materials are fused. In this way, a large number of electrical connections can be made along the entire chip area of the last metallization layer with a low contact resistance and parasitic capacitance, thereby providing the I / O (input / output) resources required for complex integrated circuits such as z. As CPU's and the like, are required. During the corresponding process sequence for connecting the mound structure to a housing support, pressure and heat are to some extent applied to the assembled component such that a reliable connection is formed between each of the on-chip mounds and mounds or lands provided on the housing substrate. However, the thermally or mechanically induced stress can also act on the underlying metallization layers, which typically include low-k dielectrics or even very low-k dielectrics, so-called ultra low-k dielectrics (ULK), thereby increasing the likelihood of defect formation in the form of cracks, material separation and the like due to the reduced mechanical stability and adhesion to other materials significantly increased.

In particular, the phase in which the package substrate is actually regarded with the semiconductor chip by melting the solder material and then solidifying the solder material to form an intermetallic bond between the bump structure formed on the semiconductor chip and the bump structure formed on the package substrate is considered to be a pronounced failure mechanism. In this process, the semiconductor chip and the package substrate are mechanically coupled to each other and heated above the melting temperature of the solder material, whereby the solder material melts and forms an intermetallic compound. Then the composite component, i. H. the semiconductor chip and the package substrate, cooled, but a pronounced yield loss may arise.

Pronounced yield losses will also be observed in complex semiconductor devices in which two or more semiconductor chips in a stacked-die configuration are designed to increase the overall bulk density of the package in a thinned semiconductor device. Due to the general trend towards increasing the functionality of complex semiconductor devices and the significant difficulties that have been encountered in constantly reducing the feature sizes of complex semiconductor-based circuit elements and metal structures in complex metallization systems, as previously discussed, three-dimensional chip configurations are being developed to an increasing extent "Dimension in a semiconductor package to use. For this, two or more semiconductor substrates may be processed to receive suitable circuit elements and corresponding metallization systems, thereby distributing the various functions of the entire integrated circuit over two or more individual semiconductor chips. In each of these three-dimensional housing strategies, the connections between the individual semiconductor chips can typically be realized by using suitable dielectrics, such as, for example, silicon dioxide. As silicon dioxide, polyimides and the like, are provided, which then act as passivating buffer materials between the individual semiconductor chips. On the other hand, these layers of material provide the mechanical strength of the three-dimensional chip configuration. However, after the three-dimensional chip configuration has finally been housed, significant mechanical stress is introduced into these inter-chip layers, which may result in delamination, the formation of gaps, or the like.

With reference to the 1a - 1c A conventional process sequence will now be described in which a die-body connection may be formed based on a soldering process resulting in significant mechanical stress forces in sensitive device surfaces, such as complex metallization systems and / or dielectric buffer materials, between individual semiconductor chips of the three-dimensional chip configuration are intended to lead.

1a schematically shows a cross-sectional view of a semiconductor device 150 in a state of the formation of a semiconductor chip 100 and a package substrate 160 precedes. In the illustrated manufacturing state, the semiconductor chip 100 a suitable substrate 101 , such as a silicon material or other suitable semiconductor material, in which and over which semiconductor-based circuit elements (not shown) are provided according to the overall device requirements. Critical dimensions of the semiconductor-based circuit elements can be as much as 50 nm or significantly less in complex applications as discussed above, thereby typically also having a pronounced complexity in one on the substrate 101 trained metallization system 115 is required. The metallization system 115 typically includes a variety of Metallization layers, such as. B. the metallization layers 110 . 120 and 130 which in turn consist of a suitable dielectric material or material system and corresponding metal regions. The metallization layer 110 includes z. B. a dielectric 111 , in the metal lines 112 are embedded. Likewise, the metallization layer comprises 120 a dielectric material or a material system 121 in connection with suitable metal pipes and areas 122 , Also the metallization layer 130 includes a dielectric 131 in connection with metal areas 132 which in turn is for connecting to a contact structure for connection to the housing substrate 160 representing hill structure or contact structure 140 may be designed suitable. In complex metallization systems, at least some of the metallization layers typically include the dielectric in the form of a low-k dielectric or an ultra-low-k dielectric (ULK) to eliminate all parasitic capacitance in the metallization system 115 to reduce. The above-average electrical performance of the sensitive dielectric, however, is accompanied by a significantly reduced mechanical robustness, which consequently a multiple increased sensitivity to mechanical stress compared to conventional dielectrics, such as. As silicon dioxide, silicon nitride and the like may result. Furthermore, since the entire complexity of the electrical circuit at the semiconductor level of the semiconductor chip 100 The number and, consequently, the complexity of the electrical connections within the metallization system must also increase 115 in their complexity, which typically requires an increased number of metallization layers, which in turn, in addition, contribute to reduced overall mechanical strength. In addition, the contact structure 140 z. B. based on suitable dielectrics, such as. As silicon dioxide, silicon oxynitride, polyamide and the like, implemented as by 141 to provide the required I / O performance. This material is suitably structured designed to make contact with the metal areas 132 the very last metallization layer 130 as a result, in conjunction with contact elements 142 how contact surfaces act. These typically comprise a brazing material suitable for bonding to the metal areas 162 of the package substrate 160 must be melted. It is noted that the contact surfaces 162 for the sake of clarity, they are shown in a suitable dielectric 161 of the package substrate 160 while any other metal portions and metal line are for connection to other other terminals of the package substrate 160 are not shown. In addition, in the in 1a illustrated example, the contact elements 142 presented in the form of solder bumps or solder balls on a suitable metallization system 143 are formed. The metallization system 143 is often referred to as underbump metallization (UBM) metallization and includes any suitable number and type of material layers to provide the desired electrical and mechanical characteristics to form an interface between the pads or metal regions 132 provide, which are often formed of copper, and the actual contact elements 142 provide. It is noted that in complex assembly techniques, a significant portion of the contact elements 142 in the form of metal columns, such. As copper pillars, is provided to the packing density of the contact structure 140 to increase and also provide above average electrical performance. On the other hand, there may be provision of metal columns in the contact structure 140 the likelihood of significant damage occurring in one or more of the underlying metallization layers of the system 115 due to the increased stiffness of the metal columns in comparison with contact elements that are substantially completely formed of a solder material.

The semiconductor chip 100 based on any established process strategy for implementing semiconductor-based circuit elements in and on the substrates 101 be formed, the highly complex process techniques such as lithography, etching, implantation techniques, deposition techniques, annealing techniques and the like include. If copper-based metal regions are to be provided, then the metallization layers 110 . 120 . 130 be formed using complex in-laid techniques. In this case, the dielectric or material system is on the substrate 101 formed and further configured such that it forms suitable openings, which in turn are filled with suitable metal systems, such. Metal systems comprising a conductive barrier material or material system and a highly conductive metal such as copper, a copper alloy, and the like. As previously explained, in order to increase overall electrical performance, typically at least one in the metallization system may be used 115 region of the dielectric to be provided have significantly reduced mechanical stability compared to established conventional dielectrics. After the very last metallization layer 130 has been completed, the contact structure 140 for example, by deposition of the one or more dielectrics 141 and structuring them, followed by deposition of the material system 143 , Thereafter, wet-chemical deposition techniques may be employed to provide a suitable material system for the contact elements 142 to provide which For example, highly conductive materials such. As copper and the like, if metal columns are to be formed, followed by the deposition of a solder material. In other cases, the contact elements 142 be made entirely on the basis of a solder material. Thereafter, established lithographic and deposition techniques are used. Then any mask material is removed and the layer 143 is structured such that electrically insulating contact elements in the structure 140 to be provided. A reflow process can be applied, if necessary, to the final shape of the contact elements 142 For example, in the form of solder balls and the like, form.

The housing substrate 160 may be formed on the basis of established process techniques to provide a complementary contact structure in the form of contact surfaces depending on the overall process strategy 162 which may also contain a solder material. After the separation of individual semiconductor chips from a semiconductor wafer, the chip can 100 on the housing substrate 160 by mechanical contacting of the contact surfaces 162 with the contact elements 142 and by using elevated temperatures for melting the contact material containing the solder material 142 or at least a portion thereof, to ultimately form an intermetallic bond between the contact surfaces 162 and the contact elements 142 to obtain. After solidification of the molten solder material in the contact elements 142 may typically have excessive mechanical stress in the metallization system 115 be induced as will be explained in detail later.

1b schematically represents the semiconductor element 150 according to another illustrative example, in which a three-dimensional or stacked chip configuration on the package substrate 160 is appropriate. A first chip 100a is, as shown, with the housing substrate 160 by means of the contact structure 140 connected, which may have a configuration as described above with respect to in 1a illustrated component 100 is explained. Furthermore, another semiconductor chip 100b with the chip 100a for example, based on a suitable dielectric 102 in which any suitable contact regime may be implemented to provide electrical contacts between the chips 100a and 100b provide. The chip 100b For example, it may comprise a suitable metallization system which may have suitable contact elements. These contact elements in turn make a connection with on the back of the chip 100a formed contact surfaces, with the front of the chip 100a a complex metallization system includes, as z. B. above with respect to the device 100 is explained. In addition, another semiconductor chip 100c for a contact with the chip 100b be provided. Contact is achieved by providing suitable contact structures, typically with the electrical contacts embedded in a dielectric, such as silicon dioxide, polyamide, and the like. After at least the stacked configuration of the device 150 that the two or more semiconductor chips 100a , ..., 100c includes, on the housing substrate 160 is attached, at least the contact elements of the contact structure 140 Consequently, melted and solidified, resulting in a significant mechanical stress within the semiconductor chip 100a and also especially on the contact materials 102 . 102b which can result between the subsequent semiconductor chips 100b and 100c are provided. When implementing a stacked chip configuration, the complexity of the respective metallization systems in each individual semiconductor chip can typically be reduced to a certain degree, for example, in terms of the number of metallization layers, the dielectrics used, and the like, possibly giving better mechanical robustness to the individual metallization system. On the other hand, significant stress forces in the contact materials 102 . 102b whereby these also with a certain probability to the emergence of device errors in the solidification of the solder material at least in the contact structure 140 and possibly in other provided contact structures between the individual semiconductor chips of the stacked configuration.

1c schematically illustrates a typical reflow process 170 where the horizontal axis represents the time in arbitrary units while the vertical axis represents the temperature in ° C. In a first phase 171 of the process 170 the compound semiconductor component is heated to a temperature above the melting temperature of the solder material. Thereafter, the actual reflow phase may be initiated by further exposing the compound semiconductor device to temperatures above the melting temperature to cause the solder material to melt and to form an intermetallic compound with the contact surfaces of the complementary contact structure. In the example shown, the with 172 designated soldering or Aufschmelzphase represented by a substantially constant temperature, wherein also other temperature profiles during the phase 172 can be applied. It should generally be acknowledged that in 1c Temperature profile is to be understood as a determined at different positions along the compound semiconductor device average temperature, the temperature in a central region of the compound semiconductor device may typically be different than the temperature at a peripheral region. After the soldering phase 172 , which can range from a few seconds to 30 seconds or more, becomes a cool down phase 173 applied. During the cooling phase 173 For example, a desired temperature gradient is applied to obtain a desired cooling rate, whereby the previously molten solder material increasingly solidifies. The electrical performance of the ultimate intermetallic compound may generally be for a given overall material composition of the contact element 142 (please refer 1a ) depend to a large extent on the grain structure, ie the average grain size of corresponding grain and the size distribution of the grain. For example, after the molten solder material cools rapidly, the highly disordered state of the molten solder material may be maintained to a certain degree during the solidification phase, and consequently may also be present in the finished contact elements 142 be present, creating relatively small grain sizes with a relatively narrow distribution centered around an average grain size. In principle, such a configuration of the contact elements 142 considered to be advantageous in terms of above-average uniformity of electrical and thermal conductivity. On the other hand, the relatively steep course of the cooling phase 173 result in significant mechanical stress caused by the very different coefficient of thermal expansion (CTE) of the one or more semiconductor chips and the package substrate. Moreover, solidification of the molten solder material along the compound semiconductor device may not be uniform, but may be e.g. B. an early solidification of the arranged on the periphery of the semiconductor chip solder material occur because there during the relatively steep cooling phase 173 a much more efficient heat dissipation can occur. In this case, the periphery of the compound semiconductor device may already be strongly mechanically coupled while the central area is still solidifying and, consequently, additional thermal stress may result, which may then not be compensated due to the reduced elasticity of the peripheral surface of the compound semiconductor device. The excessive mechanical stress induced in the sensitive metallization systems and / or in any intervening contact areas of a stacked chip configuration can lead to an increased number of damages, such For example, to form cracks that form in the sensitive dielectrics, material exfoliation, and the like, which may thus contribute to damage to the device, or at least to significantly reduced reliability of the compound semiconductor device. This is particularly true for processes in which lead-free solder materials must be used, since typically higher soldering temperatures are required, and the resulting solidified solder materials have significantly reduced elasticity compared to established lead-containing solder materials. For this reason, it was suggested the cooling phase 173 considerably elongated to allow the solidifying solder material to conform to the resulting thermal stress, thus significantly reducing the likelihood of device damage. However, it has been found that the reduced cooling rate during the phase 173 may result in an undesirable grain structure of the resulting solder joints, while generally reducing the overall throughput of the reflow process.

In the US 2009/0298206 A1 For example, a method for measuring wafer deflection during a soldering operation is described which allows a good comparison between two applied cooling profiles. In the US Pat. No. 6,228,680 B1 describes a method for producing an integrated circuit, in which a cooling of the processed semiconductor structure with alternately falling, increasing or constant cooling rates takes place. In the EP 1 569 272 A2 For example, a chip bonding method is described in which a chip carrier is moved by a heater and temperatures of the processed semiconductor structure can be represented as a function of the position in the heating device. In the WO 2009/044958 A1 a 3D chip stack is described.

In view of the situation described above, the present invention relates to methods in which compound semiconductor devices based on reflow methods can be formed while preventing or at least reducing the effects of at least one of the problems outlined above.

Overview of the invention

In general, the present invention provides fabrication techniques in which a reflow process may be used to bond one or more semiconductor chips to a package substrate by means of a solder material using a suitably designed cooling phase that reduces the resulting mechanical stress while simultaneously providing a cooling process desired grain structure of the solder joints is provided. Thus, a two-stage or multi-stage cooling phase can be implemented, in which a rapid cooling and consequently a moderately high cooling rate after the actual Soldering phase can be applied to allow it to give a desired improved grain structure upon solidification. Thereupon, at least a second cooling phase can take place with a significantly reduced cooling rate, in which thermal stress can be relaxed efficiently. This can be done, for example, by allowing the metal of the contact elements to flow, so that a gradual adaptation to the preceding induced thermal stress can be achieved. In this way, reduced reliability or various damage of the assembly in complex metallization systems can be reduced, while also connecting three-dimensional configurations with a housing can be made less critical due to the improved cooling process regime.

An exemplary method according to the invention relates to the mounting of at least one semiconductor chip and one package substrate. The method comprises heating a composite device above a melting temperature of a solder material formed between a contact structure of the package substrate and a contact structure of the at least one semiconductor chip, the composite device comprising at least one semiconductor chip and the package substrate; Applying a first cooling phase having at least one time-averaged first cooling rate for cooling to a grain stabilization temperature of the composite component and causing solidification of the solder material, wherein the spatially averaged temperature of the at least one semiconductor chip is in the range of 80 ° C to 150 ° C at the end of the first cooling phase such that an average grain size of the contact structure is in a range of 1 μm to 39 μm; and applying a second cooling phase near the first cooling phase at a second time-averaged cooling rate that is less than the first cooling rate, wherein the first cooling rate is at least twice the second cooling rate, and wherein the second cooling phase reduces mechanical stress in the contact structure of the at least one semiconductor chip ,

Another illustrative method according to the invention comprises fusing a solder material formed between a contact structure of a semiconductor chip and a contact structure of a package substrate, wherein the semiconductor chip and the package substrate form a compound semiconductor device; Allowing the solidification of the molten solder material by cooling the compound semiconductor device to a grain stabilization temperature of the compound semiconductor device during a first cooling phase to adjust a grain structure of the solder material such that an average grain size of the contact structure is in a range of 1 μm to 39 μm, and wherein the cooling rate is applied during the first cooling phase, is substantially constant; and cooling the compound semiconductor device from the grain stabilization temperature to ambient temperature during a second cooling phase, wherein the second cooling phase reduces mechanical stress of the compound semiconductor device without substantially affecting the grain structure of the solder material, wherein the cooling rate applied during the second cooling phase is substantially constant is.

Brief description of the drawings

Further embodiments of the present invention are defined in the appended claims and will become apparent from the following detailed description made with reference to the accompanying drawings, in which:

1a and 1b schematically show a cross-sectional view of a compound semiconductor device comprising a complex metallization system ( 1a ) and / or a stacked chip configuration ( 1b );

1c schematically illustrates the temperature profile of a reflow process according to conventional strategies;

2a schematically illustrates a cross-sectional view of a compound semiconductor device including, for example, a complex metallization system and / or a stacked chip configuration during a reflow process;

2 B schematically illustrates a temperature profile comprising a modified cooling phase for setting a desired grain structure while reducing the thermally induced stress forces in the compound semiconductor device according to exemplary embodiments;

2c - 2e schematically represent temperature profiles of other cooling phases according to exemplary embodiments; and

2f - 2i schematically represent a reflow system during different phases of a process for implementing an improved cooling phase.

Detailed description

In general, the present invention relates to methods in which the attachment based on a reflow process of one or more semiconductor chips on a package substrate can be improved by using a cooling phase. On the one hand, the application can a cooling phase may allow for the formation of desired grain structures by reacting a rapid cooling rate or cooling rate during a first phase while on the other hand providing improved relaxation of the stress during a moderate cooling phase with a significantly reduced cooling rate in which the solder material is allowed to adapt to the present thermal stress forces such that after a final ambient temperature has been reached, the remaining mechanical stress is significantly reduced without substantial modification of the previously formed grain structure. For example, the first rapid quenching phase may be reacted immediately after completion of the actual soldering phase to achieve a grain stabilization temperature which may be about 80 ° C or higher, for example 130 ° C or higher, with the solder material sufficiently solidified, however further provides sufficient resiliency to provide the resulting tensile mechanical forces without, however, significantly modifying the previously formed grain structure. In the subsequent moderate cooling phase with a reduced average cooling rate, accordingly, the corresponding creep of the solder material and consequently a relaxation can be achieved. In this way, the tension forces occurring in a metallization system and / or in any interposed material system provided between stacked semiconductor chips can be significantly reduced, thereby reducing the yield losses observed in typical conventional process strategies, as described above.

With reference to the 2a - 2i Now, further exemplary embodiments will be described in more detail, wherein also, if appropriate, on the 1a - 1c and in particular that with reference to 1a and 1b described compound semiconductor device is referred to.

2a schematically describes a cross-sectional view of a compound semiconductor device comprising a package substrate 260 which may be a suitable contact structure formed thereon 240 having. This contact structure 240 may include suitable dielectrics, pads or contact elements, and the like, as appropriate for a connection with a contact structure 240 a semiconductor chip 200 is required. The contact structure 240 can be considered a final layer of a metallization system 215 be formed when a single chip is connected to the housing substrate. In other cases, the contact structure 240 within a suitable dielectric for connection to the package substrate 260 be provided while any complex metallization system on an opposite side of the semiconductor chip 200 is provided. For example, at least one further semiconductor chip 200a be provided for forming a stacked chip configuration, wherein any intermediately stored material system 210a for connection to the semiconductor chip 200 can be provided. In this case, suitable contact structures (not shown) may be provided, for example, in the form of contact elements comprising solder material, which in turn may be embedded in a suitable dielectric. In the illustrated example, a substrate 201 of the semiconductor chip 200 represent any suitable substrate within, and above, its semiconductor-based circuit elements followed by the metallization system 215 and the contact structure 240 can be provided. On the other hand, the substrate can 201 Also, a suitable contact structure, for example in the form of through-hole joints and the like, which with a back of the substrate 201 may be connected, whereby a contact structure for connecting the semiconductor chip 200a by means of the intermediately stored material or layer system 210a is provided. It is noted that the semiconductor chip 200a is not necessarily provided in some exemplary embodiments, thus typically resulting in a complex structure of the metallization system 215 is required, while in other cases one or more semiconductor chips on the semiconductor chip 200a be attached, depending on the overall complexity of the composite component 250 , As a result, at least the contact structure 240 contact elements 242 include, for example in the form of metal columns, solder balls or solder balls or the like, wherein the contact elements 242 at least a certain amount of solder material, such as. B. a lead-free solder material may contain, to an intermetallic compound with the contact structure 240 train.

It is noted that any details of the contact structure 240 and the structure 140 concerning the same criteria referred to above in relation to 1a and 1b discussed semiconductor device 150 can be applied. Any suitable manufacturing strategy can be equally applied to the semiconductor chips 200 . 200a and the case substrate 260 form, as previously explained, for example. After the one or more semiconductor chips 200 . 200a on the housing substrate 260 was attached / n, a reflow process can be performed. However, this process may be significantly modified, at least with respect to the cooling phase, to provide a desired grain structure while preventing or at least significantly reducing device damage and the overall reliability of the compound semiconductor device 250 is improved.

2 B schematically shows the temperature profile of at least part of a reflow process 270 , It is noted that the horizontal axis representing time is shown in arbitrary units while the temperature axis shows the temperature in ° C. As shown, the composite component 250 initially during a phase 272 over the melting temperature of one in the contact elements 242 used solder material to be heated. As explained above, the in 2 represented temperature along the semiconductor chip 200 . 200a spatially averaged temperature, for example, using a detected in the center and at the periphery of one or both of these semiconductor chips temperature value. After the phase 272 can be a fast high-temperature cooling phase 273f which is to be understood as a phase which directly adjoins the actual soldering phase 272 or at the solidification or at least at the beginning of the solidification of a solder material of the contact elements 242 can connect. In exemplary embodiments, the cooling phase 273f Accordingly, at least one formation of a particular grain structure include, with 242g is designated. The specific grain structure 242g Typically, due to the rapid cooling phase, it may give a moderately small average grain size and a relatively narrow distribution of grain sizes with respect to the average grain size. An average grain size may be, for example, about 1 .mu.m to 39 .mu.m, depending on the material composition and the actually selected cooling rate. It is noted that a cooling rate or cooling rate is understood as the temperature difference between an initial temperature and an end temperature divided by the time required to reach the final temperature. During the soldering phase 272 For example, a temperature of about 230 to 270 ° C may be used, depending on the type of solder material and the process strategy, during a final temperature of the cooling phase 273f may be selected to be about 130-150 ° C, or in other cases 80 ° C to 150 ° C or higher, the final temperature also being designated T _G and may represent a grain stabilization temperature, since at this temperature a basic configuration of the rim in the contact elements 242 like through 242g can be formed, which may depend on the cooling rate, the material composition and other conditions. It is noted that a suitable grain structure can be determined by having a plurality of different initial and final temperatures of the cooling phase 273f and experimented with various cooling rates, which are implemented by a suitable adjustment of the heat dissipation capacity of a corresponding reflow system, as will be explained in detail later.

In addition, in the illustrated embodiment, a further cooling phase 273r applied, following the achievement of the grain stabilization temperature T _G , the average cooling rate being significantly less than that of the cooling rate of the phase 273f , That is, the temperature difference, in particular the difference between the grain stabilization temperature T _G and the ambient temperature divided by the time period is at least 50% or less, as compared with the cooling rate of the phase 273f , In other exemplary embodiments, the average cooling rate is the fast cooling phase 273f at least twice the cooling rate of the moderate flash cooling rate 273r , It is noted that this is true for the time-averaged cooling rates obtained using the initial temperature and the end temperature of any corresponding cooling phase and dividing the corresponding temperature difference by the amount of time spent.

Using the in 2 B shown temperature profile is thus the grain structure of the contact elements 242 or at least the solder material of the contact elements 242 or at least during the phase 273f thermally stabilized while the subsequent reduced cooling rate maintains the previously reacted grain structure and allows creep of the solder material. In doing so, the reduced cooling rate, and consequently the extended time, provides sufficient latitude to accommodate the resulting thermally induced mechanical stress forces.

2c schematically illustrates a temperature profile of a reflow process 270 in which the relaxation cooling phase 273r which may have the desired reduced average cooling rate which results from the reaction of a temperature plateau 273p , followed by an actual temperature drop during one phase 273s , can be obtained. In the embodiment shown, the temperature plateau corresponds 273p the final temperature and, consequently, the grain stabilization temperature of the phase 273f , thus allowing suitable adaptation to any existing thermally induced stress components. Thereafter, for example, the temperature may be decreased by any suitable rate such that the average cooling rate throughout the phase 273r especially during the plateau 273p and the temperature drop 273s corresponding time is significantly less than in comparison with the cooling rate during the phase 273f , It will noted that the duration of the plateau 273p can be adjusted on the basis of experiments, so that it becomes possible to determine a desired degree of stress relaxation without significantly affecting the previously implemented grain structure.

2d schematically illustrates the temperature profile of the reflow process 270 According to further exemplary embodiments in which a plurality of temperature plateaus 273n . 2730 . 273p , are reacted at appropriate temperatures together with intervening cooling phases, as by 273s is shown. In this case, the time-averaged cooling rate during the phase is also 273r compared to the cooling rate of the phase 273f As explained above, various temperature plateaus may result in an above-average fit to the previously induced stress in the metallization system and / or any intervening material layer, as previously explained. It is noted that the temperature difference between the various plateaus is not necessarily constant but may be varied while also the number of plateaus may be determined on the basis of experiments or the like.

2e schematically illustrates a temperature profile of the method 270 in which the relaxation phase 273r may be implemented as a phase in which a continuous change in temperature may occur over at least an extended portion of this phase. For example, a substantially "exponential" drop in temperature may be implemented, while in other cases any other substantially continuous variation may be employed. Also in this case, the time-averaged cooling rate during the phase 273r significantly lower than compared to the cooling rate of the phase 273f ,

With reference to the 2f - 2i Examples will now be described in which a reflow system has a temperature profile-forming mechanism implemented therein having a first cooling phase and a second expansion cooling phase with a significantly reduced cooling rate, as previously explained.

2f schematically represents a reflow system 290 which is a substrate carrier mechanism 291 comprising, for receiving the individual parts of the compound semiconductor component 250 is configured to allow mechanical contact of the components. One or more suitable process areas 292 are to implement the reflow process 270 provided as above with respect to the 2c - 2e was declared. In the in 2f shown working section is in the process area 292 a heating zone formed to a heating method 271 apply the reflow method, so that the various components of the composite component 250 be brought in a suitable manner to the desired soldering temperature. Until then, a conventional heating mechanism can be used.

2g represents the system 290 in a more advanced phase of the reflow process, in which in the process area 292 a soldering zone may be formed to the soldering phase 272 perform.

2h schematically represents the system 290 in a more advanced phase of the reflow process, based on the process area 292 a cooling zone is formed to the rapid cooling phase 273f implement, in which of the composite component 250 Heat is efficiently dissipated. In this case, a corresponding temperature gradient is generated between the compound semiconductor component 250 and the surrounding cooling zone in the area 252 designed to obtain the desired cooling rate, as previously explained. Thus, in this phase, a desired grain structure can be formed and stabilized based on the rapid cooling rate.

2i schematically represents the system 290 when another cooling zone by means of the process area 292 is implemented to the relaxation cooling phase 273r implement, which may have a suitable temperature profile, as previously explained.

It is noted that at least some of the processing zones based on the processing zone 292 implemented as spatially separate processing zones may be provided, wherein the compound semiconductor device 250 can be moved from one zone to the other zone, whereby a moderately high throughput is achieved. In other cases, the process area 292 physically the same process area, while the desired temperature profile after the formation of different heating and cooling zones can be implemented by a suitable control of any heating and cooling devices, wherein the arbitrary heating and cooling devices (not shown in the figures for clarity) in the process area 292 are provided.

The present invention thus provides techniques for implementing an improved cooling structure in attaching one or more semiconductor chips to a package substrate such that a desired grain structure may be formed in the solder material of the contact structure or structures while the resulting thermally induced stress is present in sensitive metallization systems and / or intermediate layers between stacked semiconductor chips may be significantly reduced at the same time. To accomplish this, rapid cooling is implemented to define the desired grain structure, while a moderate flash-down phase ensures proper matching of the previously induced strain.

Claims (14)

A method of assembling at least one of a semiconductor chip and a package substrate, comprising: Heating a composite device above a melting temperature of a solder material formed between a contact structure of the package substrate and a contact structure of the at least one semiconductor chip, the composite device comprising at least a semiconductor chip and the package substrate; Applying a first cooling phase having at least one time-averaged first cooling rate for cooling to a grain stabilization temperature of the composite component and causing solidification of the solder material, wherein the spatially averaged temperature of the at least one semiconductor chip is in the range of 80 ° C to 150 ° C at the end of the first cooling phase such that an average grain size of the contact structure is in a range of 1 μm to 39 μm; and Applying a second cooling phase near the first cooling phase at a second time averaged cooling rate that is less than the first cooling rate, wherein the first cooling rate is at least twice the second cooling rate and wherein the second cooling phase reduces mechanical stress in the contact structure of the at least one semiconductor chip. The method of claim 1, wherein the contact structure of the semiconductor chip is formed as part of a metallization system, wherein the metallization system comprises a low-ε dielectric. The method of claim 1 or 2, wherein the composite device comprises a first semiconductor chip and a second semiconductor chip, which are connected by means of a formed on a back side of the first and / or second semiconductor chip dielectric. Method according to one of claims 1 to 3, wherein the first cooling rate, which is applied during the first cooling phase, is substantially constant. Method according to one of claims 1 to 4, wherein the second cooling rate, which is applied during the second cooling phase, is substantially constant. The method of any one of claims 1 to 5, wherein the second cooling rate applied during the second cooling phase is varied. The method of claim 1, wherein the second cooling phase comprises a time period during which a profile of a spatially averaged temperature of the at least one semiconductor chip has a substantially constant plateau. The method of claim 1, wherein the second cooling phase comprises two or more periods of time, wherein during a period of time a profile of a spatially averaged temperature of the at least one semiconductor chip has a substantially constant plateau, wherein each plateau corresponds to a different spatial temperature , Method, comprising: Fusing a solder material formed between a contact structure of a semiconductor chip and a contact structure of a package substrate, the semiconductor chip and the package substrate forming a compound semiconductor device; Allowing the solidification of the molten solder material by cooling the compound semiconductor device to a grain stabilization temperature of the compound semiconductor device during a first cooling phase to adjust a grain structure of the solder material such that an average grain size of the contact structure is in a range of 1 μm to 39 μm, and wherein the cooling rate is applied during the first cooling phase, is substantially constant; and Cooling the compound semiconductor device from the grain stabilization temperature to ambient temperature during a second cooling phase, wherein the second cooling phase reduces mechanical stress of the compound semiconductor device without substantially affecting the grain structure of the solder material, wherein the cooling rate applied during the second cooling phase is substantially constant , The method of claim 9, wherein cooling the compound semiconductor device from the grain stabilization temperature to an ambient temperature during a second cooling phase comprises decreasing the time averaged cooling rate during the second cooling phase. The method of any one of claims 9 to 10, wherein the grain stabilization temperature is selected to be about 80 ° C or more. The method of any one of claims 9 to 11, wherein the solder material is a lead-free solder material. The method of any one of claims 9 to 12, wherein the semiconductor chip comprises a metallization system formed on the basis of copper and a low ε dielectric. The method of any one of claims 9 to 13, further comprising attaching at least one second semiconductor chip by means of a back side thereof to provide a stacked chip configuration prior to reflowing the solder material.

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