DE102011004810A1 - Method for digitally controlling voltage converter by frequency adjustable pulse width modulation of microcontroller, involves utilizing pulse/period combination as control variable up to alteration of nearest reference value - Google Patents

Abstract

The method involves computing a target duty factor from a given reference value, and computing pulse/period combinations, which represent duty factors. One of the pulse/period combinations is selected from finite number of pulse/period combinations whose duty factor has smallest deviation. The pulse/period combination is used as a control variable up to alteration of the nearest reference value. The reference value is computed from relevant output of a voltage converter, and the reference value is assigned as one pulse duration.

Description

Technical area

The invention relates to a method for the digital control of a voltage converter by means of a frequency-variable pulse width modulation. The inventive method is particularly suitable for simple and low-power microcontroller.

background

The invention is based on the methods for the digital control of a voltage converter by means of a pulse duration and frequency adjustable pulse modulation according to the preamble of the main claim.

The pulse modulation is based on that the arithmetic mean of a pulsed output voltage can be controlled by changing the ratio of voltage pulse duration to voltage pause duration. The arithmetic mean corresponds to the duty cycle, ie the ratio between pulse duration and period duration. This quotient has a value between 0 and 1.

In the pulse width modulation, a fixed-frequency rectangular voltage is used, in which the duty cycle is controlled by varying the pulse duration. Pulse width modulation is well known in the field of voltage transformers. Many voltage transformers known from the prior art regulate the output voltage with this principle. Examples include power adapters, laboratory power supplies and chargers. Examples from other areas are digital-to-analog converters and LED driver stages.

In addition to pulse width modulation (PWM) with a fixed period, methods for pulse-frequency modulation (PFM) with fixed pulse duration and variable period duration are also used. The underlying principle is the same, except that not the pulse duration, but the period is changed here to set the duty cycle.

Also known but not so widely used is a modulation method in which both the pulse duration and the period are varied to change the duty cycle. This modulation method is sometimes referred to as pulse-period modulation, because here just the pulse duration as well as the period is changed. In most cases, the period duration is modulated over time in the known methods.

What these methods have in common is that they determine, for the desired average value of the pulsed voltage, a suitable duty cycle which approximates this mean value. In digital modulation methods, the pulse pattern is generated by means of a digital counter. The unavoidable deviations of the duty cycle from the required mean value due to the digitization can be calculated for the different methods depending on the number of bits of the counter. With increasing number of bits of the counter increases the time resolution and thus the accuracy. However, with the counter resolution at the same frequency of the counter clock, the period increases, which leads to a higher outlay for a downstream filter.

In practice, PWM and PFM predominate because they can be implemented with low computational effort and therefore also with simple microcontrollers. Simple microcontrollers usually have only 8-bit pulse pattern generation counters whose accuracy is limited in these methods.

task

It is an object of the invention to provide a method for digital control of a voltage converter by means of a frequency-adjustable pulse width modulation, which calculates the best possible pulse / period combination for a given duty cycle, which represents the duty cycle with the lowest error at a given counter resolution. It is a further object of the invention to provide a method for the digital determination of this pulse / period combination, which can be carried out in real time in cost-effective microcontrollers.

Presentation of the invention

• – Auswahl der Puls/Periode-Kombination aus einer endlichen Anzahl von Puls/Periode-Kombinationen, deren Tastverhältnis die geringste Abweichung zum Soll-Tastverhältnis aufweist,
• – Verwendung dieser Puls/Periode-Kombination als Steuergröße bis zur nächsten Berechnung.

The object is achieved according to the invention with a method for digital control of a voltage converter with the following steps:

• Selecting the pulse / period combination from a finite number of pulse / period combinations whose duty cycle has the least deviation from the target duty cycle,
• - Use of this pulse / period combination as a control variable until the next calculation.

With digital pulse width modulation (PWM), the width of voltage pulses and thus the duty cycle of a digital signal are changed at a constant pulse frequency. The mean value of the output voltage corresponds to the duty cycle and can, for. For example, be measured at the output of a downstream, appropriately sized low-pass filter.

In the method according to the invention, with otherwise the same ratios (i.e., number of bits of the counter and frequency of the counter clock), a substantially more accurate adjustment of the mean voltage with simultaneous or higher carrier frequency of the modulation signal is achieved than is possible with PWM. The modulation method according to the invention is also referred to below as optimized pulse-period modulation.

If one not only varies the pulse duration but also the period duration, one can use the method according to the invention to find a pulse / period combination which achieves a significantly better approximation of the generated mean value to the desired value than would be possible with a pulse width modulation with the same number of bits. So z. For example, for an 8-bit counter, the resolution at a pulse width modulation is 1/256 = 0.39%. In the method according to the invention, due to the large number of available pulse / period combinations, a significantly smaller deviation of the set value from the desired average value can be achieved. For a setpoint value less than 1 / maximum counter value, the period duration is set greater than the maximum counter value for a pulse duration of one clock period.

Analytical methods for calculating the optimal pulse and period value for a given setpoint are not yet known. Therefore, this method is particularly suitable for digital control systems that have a microprocessor, z. B use a microcontroller.

In the method according to the invention, the desired duty cycle is preferably calculated from a given desired value. In a further step, the finite number of pulse / period combinations representing different duty cycles is calculated, from which a selection is then made.

Neither the number of possible duty cycles as a function of the number of bits of the counter nor the best possible pulse / period combination is analytically easily determinable. In order to determine the optimum pulse / period combinations, many possible pulse / period combinations would have to be calculated, the results compared, and the search for the optimum pulse / period combinations made using a search algorithm to be found. However, such an algorithm is usually too slow for real-time control in a microcontroller. This method requires many divisions for the calculation in order to find the possible pulse / period combinations. This takes a long time in many low-cost microcontrollers because they have no hardware division units and a division must be carried out consuming in software.

An offline calculation and storage of the optimum pulse / period combinations can only be used sensibly if the number of duty cycles to be set during operation is limited, since interpolation between support points is not possible.

• – Multiplizieren eines Sollwertes S mit verschiedenen möglichen ganzzahligen Werten T_I, die repräsentativ für die möglichen Periodendauern T_PD des Spannungswandlers sind,
• – Berechnung der Abweichungen der Ergebnisse der Multiplikationen P_G = S·T_I zum nächsten ganzzahligen Wert P_D,
• – Speichern des ganzzahligen Wertes T_I als repräsentativen Wert für die Periodendauer der nächsten Periode T_PD, der als Ergebnis der Multiplikation S·T_I mit dem Sollwert die geringste Abweichung zum nächsten ganzzahligen Wert aufweist,
• – Speichern des nächsten ganzzahligen Wertes P_D der vorigen Berechnung als Pulsdauer der nächsten Periode.

For the implementation in digital arithmetic units, therefore, a preferred embodiment of the method according to the invention for the digital control of a voltage converter is proposed, the control being carried out by means of a frequency-adjustable pulse width modulation, the method performed by a digital arithmetic unit comprising the following steps:

• Multiplying a setpoint value S by different possible integer values T _I , which are representative of the possible period lengths T _{PD of} the voltage converter,
• Calculation of the deviations of the results of the multiplications P _G = S * T _I to the next integer value P _D ,
• Storing the integer value T _I as a representative value for the period of the next period T _PD , which as a result of the multiplication S · T _I having the desired value has the least deviation from the next integer value,
• - Store the next integer value P _{D of} the previous calculation as the pulse duration of the next period.

The inventive method is achieved with simple 8-bit microcontrollers averaging with high resolution. It is clearly superior to 12-bit pulse width modulation and achieves the accuracy of 16-bit pulse width modulation. At the same time, the carrier frequency remains high, so that a possibly required effort for subsequent filters remains low. The modulation method can, for. B. for precise digital-to-analog conversion or for a light control for light emitting diodes can be used.

In a preferred embodiment of the method, each setpoint value S is assigned exactly one period duration. As a result, the computational effort can be further reduced, since the same or very similar results can be hidden from the outset.

This embodiment of the method describes an algorithm which mostly finds the optimal pulse / period pair, sometimes only slightly worse. It can also be implemented in simple microcontrollers, and is particularly suitable for mass production with low controller performance.

In the method according to the invention, a relevant output variable of the voltage converter is preferably detected, and from this a setpoint value S for regulating this output variable of the voltage converter is calculated as a duty cycle.

Further advantageous developments and refinements of the method according to the invention for the digital regulation of a voltage converter will become apparent from further dependent claims and from the following description.

Short description of the drawing (s)

Further advantages, features and details of the invention will become apparent from the following description of exemplary embodiments and with reference to the drawings, in which the same or functionally identical elements are provided with identical reference numerals. Showing:

1 a flow chart of the method according to the invention for the digital control of a voltage converter by means of a frequency-adjustable pulse width modulation,

2 a table with all possible pulse / period combinations for a method according to the invention, which is carried out with 4-bit counters.

Preferred embodiment of the invention

The method according to the invention selects the respectively most favorable pulse / period pair for a required mean value of the output voltage. In the following, the principal advantages of the method according to the invention will be explained with reference to a pulse pattern generated using a 4-bit counter.

The mathematically exact effort to determine the optimal pulse / period combination is very high and is due to the many divisions to be performed with a conventional microcontroller only in exceptional cases.

With the method according to the invention for optimizing pulse-period modulation, a significant reduction in the maximum relative error is achieved with the same number of counter bits as is possible with pulse width modulation. The method according to the invention therefore offers advantages, in particular for such applications, which require a low maximum relative error over the entire operating range. Such an application is z. As the generation of an exponential DALI characteristic.

DALI (Digital Addressable Lighting Interface, DIN EN 60929 ) is a control protocol for controlling digital lighting equipment in buildings (eg electronic transformers, electronic ballasts (ECGs), electronic power dimmers, etc.). Each operating device that has a DALI Interface can be individually controlled via DALI short addresses. Through a bidirectional data exchange, a DALI control unit or a DALI gateway can query the status of lamps or operating devices of a luminaire or set the state. DALI uses a serial, asynchronous data protocol with a transfer rate of 1200 bps.

The method according to the invention corresponds to small mean values up to 2 / counter resolution = 1 / half counter resolution of the PFM (pulse frequency modulation, pulse is always 1). For larger setpoints, a pulse / period combination is sought that achieves the best possible approximation to the setpoint. Simple analytical methods for the calculation are not known. According to the invention, an optimized search algorithm is proposed which finds the best pulse / period combinations for a given desired value and can thus be carried out in real time.

The normalized mean value of a pulse pattern, characterized by the value pair (pulse duration, period duration) corresponds to the quotient pulse duration / period duration, which is also referred to as duty cycle. For any normalized mean value S (with 0 <S <1) to be set, the following applies:

For the error, ie the deviation of the set duty cycle from the required setpoint, generally applies:

The larger the possible selection of quotients, the more precisely the required mean value S can be set. In pulse width modulation, there are exactly 2 ^{counter bits} possible quotients, since only the counter is varied. If one not only varies the pulse duration, as with pulse width modulation, but also the period, one can additionally generate many intermediate values. This is the basic idea of the method according to the invention.

berechnet und der minimale bestimmt werden. Nur Wertepaare für Quotienten aus Pulsdauer und Periodendauer, die durch Kürzen/Erweitern aus bereits berechneten abgeleitet sind, brauchen dabei nicht betrachtet zu werden, da sie demselben Wert entsprechen.In order to find the "optimal" quotient of the multiplicity of possible quotients, the value pair of pulse duration and period duration is determined in which ΔS is minimal. Since no simple analytical solution is known about this problem, all quotients and their difference from the setpoint must be used

calculated and the minimum will be determined. Only value pairs for quotients of pulse duration and period duration, which are derived by shortening / expanding from already calculated ones, need not be considered, since they correspond to the same value.

The method according to the invention does not calculate the error ΔS but the value pulse duration _fractional as a measure of the error: pulse duration = S * T _I = P _D + pulse duration _fractional , where T _{I is} an integer value which is representative of the period lengths of the voltage converter, and P _{D stands} for the integer part of the pulse duration, and pulse duration _{fractional is} a value which corresponds to the rated decimal part of the result. Rated because it always considers the smallest distance to the next integer. Pulse duration _fractional thus corresponds to the rounding error which one would make if the result P _G were rounded to an integer number P _D.

For an 8-bit microcontroller, the higher 8 bits of the product S · T _I correspond to the integer pulse duration P _D , the following to the pulse duration _fractional . In a preferred embodiment, S has a resolution of 16 bits, so pulse _{width fractional is} also 16 bits long. All 16 bits are used for the minimum search of the difference to the setpoint ΔS described below.

The embodiment of the method according to the invention is as follows: bill explanation T _{I, OPT} = 2 ^{counter bits} ; T _I = 2 ^{counter bit} pulse duration _{fractional, MIN} = fractional (S * T _I ) P _{D, OPT} = Int (S * T _I ) Calculation of the start values for the search algorithm (starting with maximum period duration) REPEAT T _I = T _I -1 P _G = S * T _I pulse duration _{fractional, MIN} = fractional (S * T _I ) Loop: At each step, the period is reduced by 1 and the fractional part is calculated IF pulse duration _fractional <pulse duration _{fractional, MIN} : pulse duration _{fractional, MIN} = pulse duration _fractional P _{D, OPT} = INT (S · T _I ) T _{I, OPT} = T _I ENDIF If the new fractional part is smaller than the previously found one, it will be saved as a new reference value. The associated value pair (pulse duration / period duration) is saved as a new optimum UNTIL T _I = 2 ^{counter bits} / 2 + 1 The values of quotients with period <= 2 ^{counter bits} / 2 corresponding to those extended by 2.

In this table, the inventive method is shown, as well as from the flowchart of 1 can be seen. It is started at the largest period T _PDMax , which corresponds to T _I = 2 ^{counter bit} . The period T _I is an integer period, so it is the largest binary displayable period. For a microcontroller with 8-bit counter this is 2 ⁸ = 256. The 256 stands for a real period T _PDMax , which _depends on various factors such. B. the clock frequency of the microcontroller used depends. The pulse duration _Fractional is the weighted decimal part of the pulse duration and is thus a measure of the abovementioned error ΔS. The pre-comma part of the pulse duration is the integer value P _D. The pulse duration _{Fractional, MIN} is the smallest evaluated decimal part of the pulse duration and thus represents the pulse / period combination which comes closest to the setpoint. The inventive algorithm is based on the knowledge that the sought optimized pulse / period combination is found when the fractional part of the multiplication of the setpoint S with the integer period T _{I is} as small as possible. The fraction of this result then corresponds to the integer pulse duration P _D. The integer period T _I used in the multiplication is the period required for the optimal pulse / period combination. In a loop, the products of the same period ^lengths and the setpoint value S are calculated for all integer period ^lengths T _I from 2 ^{counter bits} to 2 ^{counter bits} / 2 + 1. The smallest evaluated decimal part, ie the decimal part with the smallest difference to the next integer number is determined, and the pulse duration P _D from the Vorkommaanteil and the integer period T _I stored. These two values are then used for the next period of the voltage converter. The integer period T _I corresponds to a real period T _{PD of} the voltage converter.

For the method according to the invention, it is important to know that, for period ^lengths less than 2 ^{counter bits} / 2 + 1, only quotients with an already calculated value are found (for the one with an extension of 2). They therefore do not need to be calculated. Even with periods longer than 2 ^{meter bits} / 2 + 1 quotients with already calculated value can occur, but it would be more expensive to recognize this double calculation than to consider them in the loop calculation.

The 2 shows a table with all possible pulse / period combinations for a method according to the invention, which is carried out with 4-bit counters. In the rows the integer pulse lengths are plotted, in the columns the integer period lengths.

How the optimum pulse / period combination is set in operation for setting a required setpoint is illustrated in the table below using 0.5800 as the required setpoint. The algorithm starts with the largest integer period T _I = 16.

The table also shows that not all possible pulse / period combinations have to be calculated:

Even with the reduction of the number of calculated quotients according to the table above, the computational effort to determine the optimal pulse / period combination will be too large in most applications. In the following, therefore, an algorithm is presented which usually leads to the same result with much less effort. However, even in the few cases where only a suboptimal pulse / period combination is found, the difference between the required set point and the quotient remains small.

In the first step, the multiplication of the setpoint value S with the largest integer period T _I = 16 is performed. It is checked whether the fractional part of the result is the smallest to the nearest integer. Since this is the first calculation, so it is. Therefore, the period 16 and the pulse duration 9 are stored. The pulse duration 9 is the fractional part of the result of the multiplication 9,28. This corresponds to the first line of the table. The pulse / period combination leads to a value of 0.5625, which is already quite close to the setpoint 0.58.

In the next step, the calculation is made with a period of 15 reduced by one. Since the fractional part 0.7 with thirty hundredths (8.7 => 9) is greater than the previously stored value of twenty-eight hundredths (9.28 => 9), this combination is discarded. This corresponds to the second line of the table.

In the third step, corresponding to the third row of the table, the result of the fractional part of the twelve hundredths less than the previously stored. Thus, the value 14 is now stored as the period duration and the value 8 as the pulse duration.

In the fourth step, corresponding to the fourth row of the table, the result of the fractional part of the fraction is much larger, therefore nothing is stored and this combination is discarded.

In the fifth step, the result of the fractional part with four hundredths (6.96 => 7) is the smallest so far. Thus, the value 12 is now stored as the period duration and the value 7 as the pulse duration.

The sixth, seventh and eighth step again bring larger values of the fractional part of the decimal point, so it remains at the values from step five. The combinations are discarded. At the end of the loop, the values from step five, that is 12 as the period duration and 7 as the pulse duration, remain as optimal values for the setpoint of 0.5800.

With this method according to the invention, therefore, it is easy to find the optimum pulse / period combination. Since this can be calculated very quickly, the method can also be performed with simple and low-power microcontrollers in real time for each period of the voltage converter. Thus, for each period of the voltage converter, the optimum pulse / period combination corresponding to the desired value is calculated.

LIST OF REFERENCE NUMBERS

• S

  setpoint

  .DELTA.S

  Difference to setpoint, error value

  T _I

  Various possible integer values, representative of the period lengths T _{PD of} the voltage converter

  T _{I, OPT}

  integer value, representative of the optimal period

  T _PD

  Period of the voltage transformer

  P _D

  Next integer value to the result of the multiplications U _OS · T _B ; integer pulse duration

  P _{D, OPT}

  optimal integer pulse duration

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited non-patent literature

• DIN EN 60929 [0030]

Claims (7)

Method for the digital control of a voltage converter by means of a frequency-adjustable pulse width modulation with the following steps: a) selecting a pulse / period combination from a finite number of pulse / period combinations whose duty cycle has the smallest deviation from a desired duty cycle (S), b) Use of this pulse / period combination as a control variable until the next setpoint change. A method according to claim 1, characterized by the following additional steps, before the step a) are carried out: Calculation of the target duty cycle (S) from a given setpoint, - Calculation of multiple pulse / period combinations representing different duty cycles. Method according to claim 1 or 2, comprising the following steps: - multiplying the desired duty cycle (S) by various possible integer values (T _I ) which are representative of possible duration periods (T _PD ) of the voltage converter, - calculating deviations of the results (P _G ) of the multiplications P _G = S * T _I to the next integer value (P _D ), - storing the integer value (T _{I, OPT} ) as a representative value for the period of the next period (T _PD ), which as a result (P _G ) of the multiplication P _G = S * T _I with the setpoint having the least deviation of the result from the next integer value (P _D ), - storing the next integer value (P _{D, OPT} ) of the previous calculation as the pulse duration of the next period. A method according to claim 3, characterized in that the desired duty cycle S is calculated from the given setpoint value. A method according to claim 4, characterized in that the desired value is calculated from a relevant output of the voltage converter. Method according to one of the preceding claims, characterized in that each setpoint S exactly one period is assigned. A method according to claim 6, characterized in that each setpoint S exactly one pulse duration is assigned.

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