DE102011001691B4 - Transistor switch arrangement with improved turn-off characteristic - Google Patents

Abstract

Circuit arrangement (10), in particular for inverter circuits, having a field-effect transistor (12), the source electrode (17) having a reference potential (14), the drain electrode (18) having a load (11) and the gate electrode (15 ) is connected to a drive circuit (24), wherein the drive circuit comprises a driver circuit (19) and a clearing circuit (23) which is connected to the driver circuit (19), the gate electrode (15) and the reference potential (14) and which comprises a controlled current path (27) between the gate electrode (15) and the reference potential (14), characterized in that the clearing circuit (23) comprises a first resistor (31) arranged in a first clearing current path (26) from the gate Electrode (15) to the drive circuit (19), and a second resistor (32) disposed in a second drain current path (27) from the gate electrode (15) to the reference potential (14), and an amplifier (29 ), which the Spannungsab case over the second resistor (32) based on the voltage drop across the first resistor (31) controls, wherein the amplifier is a bipolar transistor (30) with ...

Description

The invention relates to a circuit arrangement with a switching transistor, in particular for inverter circuits.

Inverter circuits and other circuits in which switching transistors are operated in the switch mode, should generate the steepest possible turn-on and turn-off to keep as low as possible on the switching transistor dissipated power dissipation. As switching transistors today usually field effect transistors or bipolar transistors with insulated control electrode (IGBTs) are used. In both types of transistors, the control electrode is a capacitive load for an upstream driver circuit. In order to achieve steep switching edges, this capacitive load must be charged and discharged as quickly as possible. This is especially true when an inductive load is connected to the switching transistor.

The JP02113622 discloses a scavenging circuit in which the scavenging current is applied to a small extent by a circuit output and, to a large extent, by a current amplifier. The current amplifier is formed by a collector circuit, ie used as emitter follower pnp transistor.

A similar circuit is from the US 2003/0021073 A1 known.

Next it is from the EP 1 581 999 B1 It is known to provide current sources for charging and discharging the gate capacitance of a MOSFET switching transistor.

At higher switching frequencies and / or larger switching transistors, conventional driver circuits, which are available as integrated circuits, can quickly reach their limits or be overloaded. An example of a driver circuit is, for example, the commercially available integrated circuit TDA 4862. It has a gate driver output GTDRV which has a potential which oscillates between reference potential and operating voltage and is set up for the direct connection of MOSFETs.

For performance-critical applications, it is particularly important to make the turn-off slope as steep as possible. If an excessively large clearing stream of the connected MOSFET is allowed in this case, overloading of the driver circuit can occur.

On this basis, it is an object of the invention to provide a concept with which the scope of conventional driver circuits can be extended.

This object is achieved with the circuit arrangement according to claim 1:
The circuit arrangement according to the invention contains a drive circuit for the field effect transistor, wherein the drive circuit includes a driver circuit and a clearing circuit. The scavenging circuit has a controlled current path that leads from the gate electrode of the field effect transistor to a reference potential. This current path is preferably controlled by the current flowing from the gate electrode to the driver circuit and relieves the driver circuit. In addition, it accelerates the discharge of the gate capacitance of the field effect transistor, so that its Abschaltflanke is steepened. In particular, it is thus possible to very quickly achieve low voltages at the gate at which the field effect transistor switches off. For inductive loads, where the current to be disconnected can be quite different from zero at least in some operating modes at the turn-off, a low-loss shutdown is achieved.

The field effect transistor may be a MOSFET, an IGBT, a junction field effect transistor or other field effect transistor. Its source electrode is connected directly to the reference potential (ground) directly or with the interposition of other components, such as a shunt resistor for current control, a current transformer or the like. The current transformer may, for example, for this purpose have a preferably only a few or only one turn comprehensive winding that belongs to a current transformer or transformer.

The field effect transistor switches a load which is formed, for example, by an ohmic resistance, an inductive impedance or another linear or nonlinear impedance which leads from a supply voltage to the drain electrode of the field effect transistor. Alternatively, another switching transistor may be arranged at this point. The load is then, for example, a lamp branch with a gas discharge lamp and a preferably inductive impedance, the z. B. is formed by a current limiting reactor. The field effect transistor in this case belongs to an inverter half-bridge. The lamp branch can lead to a capacitive voltage divider, a fixed supply potential or another inverter half-bridge. In the latter case, it is thus part of a full bridge circuit. Both in the half-bridge circuit as well as in the full bridge circuit of the field effect transistor can be connected as a reference potential to ground or another, even time-varying voltage. The invention can thus be both for the lower, mass-related as well as for the apply upper non-ground field effect transistor.

The evacuation circuit is preferably connected in parallel with a resistor which connects the driver circuit to the gate electrode. This resistor serves to limit the gate charging current during the switch-on process. In this case, the evacuation circuit is preferably inactive. To achieve this, the scavenging circuit preferably includes a diode between the driver circuit and the gate electrode. In the case of positive operating voltage and negative reference potential, the cathode of the diode is poled to the driver circuit.

The scavenging circuit has a circuit node at which the scavenging flow splits into a component flowing directly to the driver circuit and into a component flowing to the reference potential. The latter part flows over the controlled current path. Preferably, this current component is limited by a resistor, wherein an amplifier controls the voltage drop across this resistor by means of the voltage drop which drops across the resistor leading from the gate of the field effect transistor to the driver circuit. In this way, z. Example, the current flowing to the driver circuit Ausräumstrom and flowing to the reference potential Ausräumstrom be divided into a fixed ratio or at least in a ratio range. This allows a very reliable current distribution even in adverse environmental conditions, such as very low or very high temperatures possible. It can be ensured that even with worst-case considerations, a clearing stream, which would be too high for the driver circuit, never leads to overloading of the driver circuit, because always a sufficient portion is dissipated directly against the reference potential. On the other hand, a relatively weak transistor can be used for dissipation to the reference potential, because conversely it is ensured that even this transistor never has to take over the entire evacuation stream. This circumstance provides double benefits. On the one hand the reliability is increased and on the other hand small and inexpensive components can be used.

Further details of advantageous embodiments of the invention will become apparent from the drawings, the description or subclaims. Show it:

1 the circuit arrangement according to the invention in a schematic representation,

2 - 4 modified embodiments of the circuit according to the invention and

5 and 6 Voltage and current waveforms on the circuit according to the invention as a time chart.

In 1 is a circuit arrangement 10 that illustrates a load 11 fed with a pulsed current. Weight 11 may be an ohmic resistance or other impedance. It may be actuators such as magnets, motors or the like, as well as other power consumers such as heating elements, light sources, lamps, LEDs or the like. Weight 11 can also symbolize a combination of several elements, such as multiple light emitting diodes, a gas discharge lamp with ballast and freewheeling diode or the like.

To operate the load 11 serves a field effect transistor 12 , over which, starting from an operating voltage 13 , a current path to a reference potential 14 leads. The reference potential 14 is assumed here as mass zero potential. However, they can also be other temporally constant or variable potentials. The operating voltage 13 Depending on the application, it can be in the range of a few volts, for example 10 or 15 volts up to several hundred volts, for example 300 or 400 volts. The field effect transistor 12 is shown here as an n-MOS transistor. However, they may also be other transistors that use field effects, such as junction field effect transistors, insulated gate bipolar transistors (IGBTs) or the like. In particular, it may be field effect transistors with high control electrode capacity. By way of illustration is in 1 to the gate electrode 15 in dashed lines, a mass effective capacitor as the gate capacitance 16 entered the capacity of the gate electrode 15 to symbolize mass. This gate capacity 16 does not represent an independent component.

With its source electrode 17 is the field effect transistor 12 directly or with the interposition of further elements with ground zero potential 14 (or any other reference potential). His drain electrode 18 is with the load 11 connected.

The control pulses for the field effect transistor 12 be from a driver circuit 19 generated, which is preferably in the form of an integrated circuit. This may be any standard driver IC, such as the TDA 4862 or IR 2153 act. The data of these integrated circuits are available from the manufacturer. The source is referenced at http://datasheetcatalog.com. The driver circuit 19 contains output driver transistors 20 . 21 , both with the output 22 the driver circuit 19 are connected. Of the Output driver transistor 20 leads with its emitter against reference potential 14 ,

Between the exit 22 and the gate electrode 15 is a clearing circuit 23 arranged by an inrush current path 24 is bridged. This is in the simplest case of an ohmic resistance 25 formed, which may have a resistance of some 10 ohms, for example, 47 ohms. At a gate capacity 16 of, for example, 3 nF and an operating frequency of 47 kHz, for example, sufficiently steep switch-on edges on the field-effect transistor can be achieved 12 achieve.

To the evacuation circuit 23 heard a first Ausraumstrompfad 26 from the gate electrode 15 to the exit 22 leads, as well as a second Ausräumstrompfad 27 from the gate electrode 15 against the reference potential 14 leads. The first Ausraumstrompfad 26 serves to control the second Ausräumstrompfads. So that the two Ausräumstrompfade 26 . 27 the clearing circuit 23 when turning on the field effect transistor 12 are inactive, is in the first scavenging path 26 a diode 28 arranged. This is poled so that the Ausraumstrompfad 26 only when switching off the field effect transistor 12 Electricity leads. In a simplified embodiment, this diode 28 but also omitted.

In the second Ausräumstrompfad 27 is an amplifier component 29 arranged, in the preferred Ausfuhrungsfalle as a bipolar transistor, for example as a PNP transistor 30 is trained. The first Ausraumstrompfad 26 preferably contains between the diode 28 and the gate electrode 15 a first resistance 31 , In addition, the second Ausraumstrompfad contains 27 a second ohmic resistance 32 , The second resistance 32 is preferably less than the first resistance 31 , For example, it is preferably about half the size of this one. At the above gate capacity 16 of 3 nF can be the resistance 31 for example, have 25 ohms while the second resistor 32 , 12 ohms can have.

The pnp transistor 30 is preferably with its emitter with the resistor 32 and with its collector, preferably with the reference potential 14 connected. Thus, the emitter-collector path of this pnp transistor forms 30 a part of the second Ausraumstrompfads 27 , The gate of the pnp transistor 30 is preferably at the connection point between the resistor 31 and the diode 28 connected. The amplifier component 29 picks up the voltage difference between the two resistors 31 . 32 from. In other words, the base emitter voltage U _{BE of} the pnp transistor 30 corresponds to the difference between the two on the resistors 31 . 32 falling voltages. This turns the current in the second resistor 32 corresponding to the current in the first resistor 31 regulated.

The circuit arrangement described so far 10 works as follows:
At a given time t1, as in 5 illustrates the field effect transistor 12 switched on. This requires the gate voltage U _G at its gate 15 from zero (reference potential) to a given value of, for example, 15 volts. Thereby the gate capacity becomes 16 about the resistance 25 charged. This is accompanied by a certain increase, the field effect transistor 12 already turns on at relatively low voltages of, for example, 5 or 6 volts. In 5 This is symbolized by a dashed, horizontal line leading from the leading edge 33 of the U _G pulse is passed through relatively quickly. In addition, the switch-on edge steepness is uncritical for inductive loads and the load current zero at the switch-on time.

After a certain period of time, the field effect transistor 12 be switched off again at a time t2 to lock the load current. To the low cut-off voltage (dashed horizontal line in 5 ) to reach as quickly as possible, the shutdown must be carried out quickly. That's the resistance 25 too high impedance. The shutdown is from the clearing circuit 23 executed. It gets up to it 6 directed. At a time t2, the potential jumps at the output 22 to zero, that is, the output driver transistor 21 becomes conductive. At the gate electrode 15 is still the previously held high potential of, for example, 15 volts or more. The diode 28 becomes conductive and flows through the resistor 31 limited current through the first Ausraumstrompfad 26 , This current i1 is greatest at time t2 and then stops (see 6 ). It is limited (with appropriate circuit layout of the evacuation circuit) to a value that is from the output driver transistor 21 is well tolerated. He is not too low. It is set to such a value that in the driver circuit 19 possibly existing monitoring circuits can determine the flowing Ausraumstrom and signal no malfunction.

The voltage drop across the resistor 31 is reduced by the base-emitter voltage U _BE , also at the comparatively lower resistance 32 enforced. As far as the amplifier works 29 as an emitter follower. According to the resistance ratio of the two resistors 31 . 32 thus flows a higher current i2 ( 6 ) through the second Ausräumstrompfad 27 directly against mass. Thus, the gate capacity becomes 16 discharged by the sum of the two currents i1, i2, in the present exemplary embodiment, only about one Third of the discharge current or Ausräumstroms in the output 22 flows. By appropriate change of the ratio of the resistors 31 . 32 to each other also significantly higher or lower power ratios can be achieved.

6 illustrates the shutdown process in extreme time. The shutdown process started at t2 ends at t2 'when the gate voltage U _G falls below the cutoff voltage U0. It is achieved a very steep switching edge, which alone with the driver circuit 19 at least with field effect transistors 12 high capacity, not sure to reach.

2 illustrates a modified embodiment of the circuit arrangement 10 , To clarify the structure and the function, reference is made in full to the previous description on the basis of the introduced reference numerals. Again, the load can 11 be designed as an inductance. The circuit arrangement 10 is here for example part of a boost converter. The drain electrode 18 of the field effect transistor 12 is for example via a diode 35 with a capacitor polarized to ground 36 connected. Again, the particularly steep trailing edge 34 be used to the power loss at the field effect transistor 12 minimize and the efficiency of the entire circuit 10 to improve.

3 illustrates that in all the circuits described above 1 or 2 the source electrode 17 of the field effect transistor 12 for example, about a shunt 37 with ground reference potential 14 can be connected. It becomes such a tap 38 provided, over that of the field effect transistor 12 flowing electricity can be measured as a voltage drop.

4 illustrates the application of the presented circuit arrangement 10 in the context of a half-bridge circuit or bridge circuit. The field effect transistor 12 is in turn directly or with the interposition of the shunt 37 with reference potential 14 connected. Instead of the load 11 now sets an upper switching transistor 39 the connection to the operating voltage 13 ago. The connection point of the two transistors 39 . 12 can with the load 11 be connected. The other end of the load 11 can be connected to a fixed potential lying between zero and operating voltage, to a capacitive voltage divider or to another inverter half-bridge. Regarding the load 11 all apply in connection with the 1 made statements. Otherwise, the following applies to the function of the exemplary embodiments 3 and 4 the description of the embodiment according to 1 in its entirety.

It should also be noted that the gate of the transistor 39 can be connected to a clearing circuit, with the Ausraumschaltung 23 structurally consistent. It may also agree with the component values. Such a removal circuit, not pictorially shown, is then input side with a corresponding, not further illustrated output of the driver circuit 19 connected. The amplifier component, z. B. a corresponding transistor, for. B. turn be a pnp transistor. The current-carrying branch of the amplifier component, ie z. B. its collector, is connected to a reference potential. This may be the ground zero potential 14 or even at the reference electrode of the transistor 39 potential. In the case of an n-MOS transistor, as in 4 is shown, this is that at the connection point between the two transistors 12 . 39 attached potential. If a p-MOS transistor is used as the upper transistor, the reference potential with which the Ausraumschaltung 23 connected, the operating voltage 13 ,

The use of an exhaust circuit for the upper transistor 39 is regardless of whether the lower transistor 12 connected to a clearing circuit. In the case of a half bridge, at least one of the transistors 12 . 39 about a clearing circuit 23 driven. In the case of a full bridge circuit, one, two, three or all transistors of the full bridge are each driven via a corresponding clearing circuit.

In all the aforementioned embodiments, parallel-connected transistors can also be driven via the space circuit. In this case, the gates of transistors connected in parallel can each be individually connected to a separate room circuit. However, it is also possible to connect the gates of transistors connected in parallel to each other and to control them via a common, designed according to one of the embodiments described above Ausraumschaltung.

To relieve a driver circuit for a switch with a capacitive control electrode, the invention provides a Ausraumschaltung 23 with two Ausgäumstrompfaden 26 . 27 before, wherein the current in the second Ausräumstrompfad 27 based on the current in the first Ausgestäumstrompfad 26 is controlled to guarantee a constant at least within limits ratio of the two flowing in the Ausräumstrompfaden Ausräumströme. In this way, the overload of individual components is avoided even in adverse conditions such as high or low temperatures, high component tolerances and the like.

LIST OF REFERENCE NUMBERS

10

circuitry

11

load

12

Field effect transistor (MOSFET, IGBT or others)

13

operating voltage

14

Ground zero potential

15

Gate electrode

16

capacitor

17

Source electrode

18

Drain

19

driver circuit

20

Output driver transistor

21

Output driver transistor

22

output

23

Ausräumschaltung

24

Einschaltstrompfad

25

resistance

26

first Ausgäumstrompfad

27

second clearing path

28

diode

29

amp device

30

PNP transistor

31

first resistance

32

second resistance

33

leading edge

34

trailing edge

35

diode

36

capacitor

37

shunt

38

tap

39

Switching transistor (MOSFET, IGBT or similar)

Claims (7)

Circuit arrangement ( 10 ), in particular for inverter circuits, having a field effect transistor ( 12 ) whose source electrode ( 17 ) with a reference potential ( 14 ) whose drain electrode ( 18 ) with a load ( 11 ) and its gate electrode ( 15 ) with a drive circuit ( 24 ), wherein the drive circuit comprises a driver circuit ( 19 ) and a clearing circuit ( 23 ) connected to the driver circuit ( 19 ), the gate electrode ( 15 ) and the reference potential ( 14 ) and between the gate electrode ( 15 ) and the reference potential ( 14 ) a controlled current path ( 27 ), characterized in that the clearing circuit ( 23 ) a first resistor ( 31 ), which in a first Ausräumstrompfad ( 26 ) from the gate electrode ( 15 ) to the driver circuit ( 19 ), and a second resistor ( 32 ), which is in a second Ausräumstrompfad ( 27 ) from the gate electrode ( 15 ) to the reference potential ( 14 ), and an amplifier ( 29 ), which detects the voltage drop across the second resistor ( 32 ) based on the voltage drop across the first resistor ( 31 ), wherein the amplifier comprises a bipolar transistor ( 30 ) comprising an emitter and a collector, the emitter being connected to the second resistor ( 32 ) and the collector with the reference potential ( 14 ) connected is. Circuit arrangement according to Claim 1, characterized in that the field-effect transistor ( 12 ) is a MOSFET, an IGBT or a junction field effect transistor. Circuit arrangement according to Claim 1, characterized in that the source electrode ( 17 ) via a shunt resistor ( 37 ) or a current transformer with the reference potential ( 14 ) connected is. Circuit arrangement according to claim 1, characterized in that the clearing circuit ( 23 ) a resistor ( 25 ) is connected in parallel, the driver circuit ( 19 ) with the gate electrode ( 15 ) connects. Circuit arrangement according to Claim 1, characterized in that the clearing circuit ( 23 ) one between the driver circuit ( 19 ) and the gate electrode ( 15 ) arranged diode ( 28 ) having. Circuit arrangement according to Claim 1, characterized in that the bipolar transistor is a pnp transistor ( 30 ). Circuit arrangement according to Claims 5 and 6, characterized in that the base of the bipolar transistor ( 30 ) with the diode ( 28 ) connected is.

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