DE102010045580A1 - Circuit arrangement for use in microprocessor for e.g. smart card, has identification circuit producing key for encrypting data value to be written or decrypting data value to be read, where key depends on arrangement inherent properties - Google Patents

Abstract

The arrangement (100) has a memory (20) e.g. ROM, coupled with a processing unit (10) i.e. CPU, for executing a reading and/or writing access. A cryptographic unit (40) i.e. memory encryption decryption unit, encrypts a data value to be written into the memory or decrypts the data value to be read from the memory. An identification circuit (50) i.e. physical unclonable function (PUF) circuit, produces a key (S1) for encrypting the data value to be written or decrypting the data value to be read. The key depends on inherent properties of the arrangement. An independent claim is also included for a method for operating a circuit arrangement.

Description

The present invention relates to a circuit arrangement and a microprocessor having a processing unit and a memory which is coupled to the processing unit for the purpose of a read or write access.

The present invention also relates to a method of operating a circuit arrangement with such a memory.

Microprocessors have memory to store persistent or volatile data or programs. During execution of a program, the microprocessor accesses the memory to load currently needed program parts or data. Among other things, microprocessors are used in safety-critical systems, for example in chip cards. Among other things, the microprocessor is used there to encrypt the data traffic or to handle other security-critical applications for the chip card holder. Safety-critical data and programs are stored in or read from the volatile and non-volatile memory units of the microprocessor. In order to prevent this information being spied on and visualized, such data is sent in encrypted form via the bus lines to the memory and stored there encrypted. Encryption methods are usually complex and require appropriate hardware complexity and computing time.

Microprocessors for, for example, chip cards or components for embedded security are exposed to a variety of attacks. Among other things, the attackers try to spy data from the chip. This is done for example by means of so-called observing or physical attacks. One manifestation of this is the placement of fine needles on the data bus between the integrated memories and the processing unit CPU. The signals picked up by the needles are recorded and evaluated, so that the internally stored and secret data get into the hands of the attacker. This type of attack can be prevented or made more difficult by encrypting the data. Encryption makes the data worthless to the attackers. An attack described above would initially only encrypted and thus unrecognizable data bring.

Encryption is known using an encryption algorithm (comparable to encryption standards such as DES (Data Encryption Standard) or AES (Advanced Encryption Standard)). In this case, as close as possible to the processing unit, the CPU, a cryptographic module is implemented. The cryptographic module encrypts the data using a key, typically based on a random number. All data to be stored are then transported in encrypted form over a data bus to a memory and stored encrypted in this.

From the EP 1118941 B1 is a microprocessor arrangement comprising a processing unit, a memory coupled to the processing unit for performing a read or write access, a cryptographic unit for encrypting and decrypting data values written or read into the memory, and means for providing a variable key.

A disadvantage of the above-mentioned method, however, is that the encryption key must be stored. Although it is sometimes tediously trying not to save the key centrally in one place, to divide the key, to change or to hide, an attacker can find the key with appropriate effort or composed and read and after determining the encryption method, the encrypted Translate data back to plain text. The attacker would thus be at the target and would have, by the subsequent decryption, successfully spied out the data to be protected.

Furthermore, an encryption based on chip-individual parameters, so-called "Physical Unclonable Functions" (PUFs) known. PUFs may be circuits, components, processes, or other physical systems in a device that make it possible to obtain an individual, non-clonable identification code or key from a plurality of identification bits. Such a key can be derived over and over again from the inherent properties of the block and does not have to be stored. PUFs are based on variations in the manufacturing process, material fluctuations or the like and are not specifically adjustable during production. The bandwidth of the fluctuations and the number of identification bits used ensures that each block in a series receives an individual key. Due to the individuality of the keys, there is a decisive disadvantage. It can not be predicted whether the encryption corresponds to a sufficient cryptographic strength. In the worst case, the key is so bad that virtually no encryption of the data is made or the data can be translated back into plain text with little effort, without knowing the specific function. Even for an often necessary safety certification this is an unacceptable condition.

The present invention is therefore based on the object of providing a circuit arrangement and a method for operating a circuit arrangement, which offers a higher level of security against attacks by spying.

This object is achieved by a circuit arrangement with the features of claim 1 and by a method for operating a circuit arrangement having the features of claim 9.

In one embodiment, the circuitry includes a processing unit, a memory coupled to the processing unit for performing read and / or write access, a cryptographic unit for encrypting a data value to be written to the memory, or decrypting a data value read from the memory Identification circuit, wherein the identification circuit is adapted to generate a first key for encrypting, the data to be written into the memory or decrypting the data read from the memory, the first key depending on the inherent characteristics of the circuit. The identification circuit may be, for example, a PUF circuit.

The generation of the first key from the inherent properties of the circuit arrangement, for example from the so-called "Physical Unclonable Functions" (PUFs), has the advantage that the first key is reproducible. Since the first key can be derived time and time again from the inherent properties of the circuit arrangement, it does not have to be stored, which represents a significant gain in security against attacks from outside. PUFs are based on variations in the manufacturing process, material fluctuations or the like and are not specifically adjustable during production. The bandwidth of the fluctuations and the number of identification bits used ensures that each circuit arrangement of a series receives an individual key.

The encryption of the data values can take place, for example, by means of block ciphers such as Feistelchiffre / Feistelnetzwerk or a substitution-permutation network (SPN) in the cryptographic unit. In a further embodiment, the encryption takes place in accordance with one of the known encryption standards such as DES (Data Encryption Standard) or AES (Advanced Encryption Standard).

In a further embodiment, the circuit arrangement furthermore has a key generation device, wherein the key generation device is set up to generate a second key by means of a random number and / or in the circuit arrangement (FIG. 100 ), wherein the cryptographic unit is arranged to use the first key and the second key to encrypt the data value to be written into the memory or to decrypt the data value read from the memory.

By using two differently generated keys for encryption, the quality / strength of the encryption of the data values is significantly increased. Since the first key results from the inherent properties of the circuit arrangement and therefore does not have to be stored or is not determined by specific algorithms, it is practically impossible to determine. For example, the second key may be generated using a random number, where the random number may be generated, for example, by a Random Number Generator (RNG). But it is also possible that the second key has at least partially a date which is hidden in a memory, such as a read only memory (ROM) or a non-volatile memory (NVM) or by synthesis on the circuit arrangement, hidden or open. However, the second key can also be based in part on a random number and on another part on a date stored in the circuit arrangement.

The first and second keys can either be merged into a common key, or two separate encryptions of the data value take place by means of one or two cryptographic units. One of the cryptographic units can be, for example, a so-called Memory Encryption Decryption Unit (MED).

In one embodiment, the key generation means may generate a third and / or a further key, by means of a random number and / or a value stored in the circuitry, the cryptographic unit being arranged to write the first key, the second key, the third and / or or another key to encrypt the data value to be written into memory or to decrypt the data value read from the memory.

The first, second, third and possibly further keys can be combined as desired to form one or more shared keys. This can be done, for example, by bit-wise XOR. In another In accordance with an embodiment, multiple encodings of the data value may be performed sequentially by means of different keys, the order being arbitrarily changeable. For encryption one or more cryptographic units can be used.

In one embodiment of the circuit arrangement, the memory has one or more areas for storing one or more keys or one or more parts of a key. The keys or parts of a key can also be stored in different stores, hidden or open, whereby the key or keys can be generated and stored during the manufacturing process or during operation. However, it is also possible for a value which can be used as a key to be stored outside the memory in the circuit arrangement.

Furthermore, the circuit arrangement can also be used in a microprocessor or in a security controller, for example for chip cards. Especially in safety-critical applications, the circuit arrangement according to the invention provides good protection against attacks.

An embodiment of a method of operating a circuit arrangement comprises the steps of generating a first key, wherein the first key depends on inherent characteristics of the circuitry, encrypting a data value to be written to a memory using the first key, or decrypting one from a memory read data value using the first key. The first key can be generated based on a PUF function.

Since the first key over and over again from the inherent properties, such as a PUF function of the circuit can be derived, it does not need to be stored, which represents a significant gain in security against attacks.

A further embodiment of the method for operating a circuit arrangement has the following additional steps: generating a second key, wherein the second key depends on a random number and / or on a value stored in the circuit arrangement, encrypting the data value to be written into the memory using of the first and second keys or decrypting the data read from the memory using the first and second keys.

By using two differently generated keys for encryption, the quality / strength of the encryption of the data values is significantly increased. The first and second keys can either be combined to form a common key, for example by means of an XOR function, or two separate codifications of the data value take place by means of one or two cryptographic units. One of the cryptographic units can be, for example, a so-called Memory Encryption Decryption Unit (MED).

In one embodiment of the method for operating a circuit arrangement, the data value to be written into the memory is encrypted in a first step with the first key and in a second step with the second key. The steps can also be swapped so that the data value to be written into the memory is encrypted in a first step with the second key and in a second step with the first key.

A further exemplary embodiment of the method for operating a circuit arrangement has the following additional steps: generating a third and / or a further key, wherein the third and / or further key depends on a random number and / or on a value stored in the circuit arrangement, encrypting the data value to be written into the memory using the first, second, third and / or further keys or decrypting the data read from the memory using the first, second, third and / or further key.

The first, second, third and possibly further keys can be combined as desired to form one or more shared keys. This can be done for example by bitwise XOR. In a further embodiment, the encryption of the data value by several, successive, encryption steps and by means of different keys can be done, the order of the encryption steps is arbitrarily changeable. For encryption one or more cryptographic units can be used.

In one embodiment of the method for operating a circuit arrangement, the data value to be written into the memory is encrypted in a first step with the first key and in a second step with the second, third and / or another key or in a further embodiment in a first Step with the second, third and / or one another key and encrypted in a second step with the first key.

In one embodiment of the method for operating a circuit arrangement, the memory has one or more areas for storing one or more keys or one or more parts of a key. The first, second, third and / or another key or part of the first, second, third and / or another key can be stored, for example, in a memory. However, the keys or parts of a key can also be stored in different stores, hidden or open, wherein the key can be generated and stored during the manufacturing process or during operation. It is also possible to store a value which can be used as a key outside of the memory in the circuit arrangement.

Hereinafter, preferred embodiments of the circuit arrangement will be explained in more detail with reference to FIGS. Show it:

1 an embodiment of a circuit arrangement 100 ,

2 a further embodiment of a circuit arrangement 100 ,

In 1 is an embodiment of a circuit arrangement 100 shown. The circuit arrangement 100 has a processing unit 10 , for example, a CPU, a memory 20 that with the processing unit 10 for performing a read and / or write access, is a cryptographic unit 40 to encrypt one in memory 20 to write data or decrypt one from memory 20 read data value and an identification circuit 50 on. The identification circuit 50 is set up to encrypt a first key S1 in the memory 20 to write data value or decrypt the memory 20 data value to be generated, wherein the first key S1 of the inherent properties of the circuit arrangement 100 depends. The coupling between the processing unit 10 and the memory 20 can for example via a bus 30 respectively. The processing unit 10 , the cryptographic unit 40 and the identification circuit 50 may, for safety reasons, be arranged in close proximity in one embodiment. The identification circuit 50 may be a PUF circuit, for example.

The generation of the first key S1 from the inherent properties of the circuit arrangement 100 , For example by means of PUF function, has the advantage that the first key S1 is reproducible and thus does not need to be stored, which represents a significant gain in security against attacks from outside. PUFs are based on variations in the manufacturing process, material fluctuations or the like and are not specifically adjustable during production. The bandwidth of the fluctuations and the number of identification bits used ensures that each circuit arrangement of a series receives an individual key.

The encryption of the data values can take place, for example, by means of block ciphers such as Feistelchiffre / Feistelnetzwerk or a substitution-permutation network (SPN) in the cryptographic unit.

In 2 is another embodiment of a circuit arrangement 100 shown. The circuit arrangement 100 also has a key generator 70 on, with the key generator 70 is arranged to generate a second key S2 by means of a random number and / or one in the circuit arrangement ( 100 ) stored value, the cryptographic unit 40 is set up to the first key S1 and the second key S2 for encryption of the memory 20 to write data or to decrypt the memory 20 read data value to use.

By using two differently generated keys S1, S2 for encryption, the quality / strength of the encryption of the data values is significantly increased. Since the first key S1 is the inherent properties of the circuit arrangement 100 results and therefore does not need to be stored, it is practically impossible to determine. The second key S2 may be generated, for example, using a random number. But it is also possible that the second key S2 at least partially has a date which in the memory 20 , hidden or open, is deposited. The memory 20 may be, for example, a read only memory (ROM) or a nonvolatile memory (NVM). However, the second key S2 may also be based in part on a random number and on a further part on one in the circuit arrangement 100 deposited date.

The first key S1 and the second key S2 can either be combined to form a common key or two separate encryptions of the data value can be found by means of one or two cryptographic units 40 instead of. One of the cryptographic units 40 can for example a so-called Memory Encryption Decryption Unit (MED).

In one embodiment, the key generator may 70 generate a third and / or another key, by means of a random number and / or a stored value in the circuit arrangement, wherein the cryptographic unit 40 is set up to the first key S1, the second key S2, the third and / or further key for encryption of the memory 20 to write data or to decrypt the memory 20 read data value to use.

The first key S1, the second key S2, the third key and possibly further keys can be combined as desired to form one or more shared keys. This can be done for example by bitwise XOR. In a further embodiment, multiple encryption of the data value can be performed sequentially by means of different keys, wherein the sequence is arbitrarily changeable. For encryption, one or more cryptographic units 40 be used.

In the circuit arrangement 100 The memory may have one or more areas for storing one or more keys or one or more parts of a key. The keys or parts of a key can also be stored in different stores 20 hidden or open, where the key (s) can be generated and stored during the manufacturing process or during operation. However, it is also possible to use a value which can be used as a key outside the memory in the circuit arrangement 100 be filed.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• EP 1118941 B1 [0006]

Claims (19)

Circuit arrangement ( 100 ), comprising, - a processing unit ( 10 ), - a memory ( 20 ) connected to the processing unit ( 10 ) is coupled to perform a read and / or write access, - a cryptographic unit ( 40 ) to encrypt one in the memory ( 20 ) data to be written or decrypting one from memory ( 20 ) read data value, characterized in that the circuit arrangement ( 100 ) an identification circuit ( 50 ), wherein the identification circuit ( 50 ) is set up to encrypt a first key (S1) into the memory (S1). 20 ) data to be written or decrypting from the memory ( 20 ), wherein the first key (S1) depends on the inherent properties of the circuit arrangement ( 100 ) depends. Circuit arrangement ( 100 ) according to claim 1, wherein the identification circuit ( 50 ) is a PUF circuit. Circuit arrangement ( 100 ) according to one of claims 1 or 2, wherein the circuit arrangement ( 100 ) a key generating device ( 70 ), wherein the key generation device ( 70 ) is adapted to a second key (S2), by means of a random number and / or in the circuit arrangement ( 100 ) value, whereby the cryptographic unit ( 40 ) is arranged to the first key (S1) and the second key (S2) for encryption of the memory in the memory (S1) 20 ) data to be written or for decrypting from the memory ( 20 ) data value to be used. Circuit arrangement ( 100 ) according to claim 3, wherein the key generating means ( 70 ) is adapted to a third key and / or another key, by means of a random number and / or in the circuit arrangement ( 100 ) value, whereby the cryptographic unit ( 40 ) is set up to store the first key (S1), the second key (S2), the third key and / or a further key for encryption of the key into the memory (S1). 20 ) data to be written or for decrypting from the memory ( 20 ) data value to be used. Circuit arrangement ( 100 ) according to one of claims 3 or 4, wherein the circuit arrangement ( 100 ) is submitted to the encryption of the memory ( 20 ) to be written data with the first key (S1) and the encryption of the memory ( 20 ) to be written data to be written sequentially with the second key (S2) and / or another key. Circuit arrangement ( 100 ) according to one of the preceding claims, wherein the memory ( 20 ) has an area for storing a key (S1, S2). Circuit arrangement ( 100 ) according to one of claims 1 to 5, wherein the memory ( 20 ) has at least two areas for storing a key (S1, S2) and / or a key part. Microprocessor, comprising a circuit arrangement ( 100 ) according to one of claims 1 to 7. Method for operating a circuit arrangement ( 100 ), comprising the following steps: generating a first key, wherein the first key of an inherent properties of the circuit arrangement ( 100 ), - encrypt one into a memory ( 20 ) data to be written using the first key (S1) or decrypting one from a memory ( 20 ) read data using the first key (S1). The method of claim 9, wherein the first key (S1) is generated based on a PUF function. Method according to one of Claims 9 to 10, with the following steps: generating a second key (S2) based on a random number and / or in the circuit arrangement ( 100 ) stored value, - Encrypt the memory ( 20 ) data to be written using the first key (S1) and the second key (S2) or decrypting from the memory ( 20 ) using the first key (S1) and the second key (S2). Method according to one of claims 9 to 11, with the following steps: generating a third key and / or another key, wherein the third key and / or the further key of a random number and / or one in the circuit arrangement ( 100 ) deposited value, - encrypting the memory ( 20 ) data to be written using the first key (S1), the second key (S2), the third key and / or another key or decrypting from the memory ( 20 ) using the first key (S1), the second key (S2), the third key and / or another key. Method according to one of Claims 9 to 11, in which the memory ( 20 ) to be written data in a first step with the first key (S1) and in a second step with the second key (S2) is encrypted. Method according to one of Claims 9 to 11, in which the memory ( 20 ) to be written data in a first step with the second key (S2) and in a second step with the first key (S1) is encrypted. The method of claim 12, wherein the memory ( 20 ) to be written data in a first step with the first key (S1) and in a second step with the second key (S2), the third key and / or another key is encrypted. The method of claim 12, wherein the memory ( 20 ) to be written data in a first step with the second key (S2), the third key and / or another key and in a second step with the first key (S1) is encrypted. Method according to one of claims 9 to 16, wherein a first key (S1) and / or a part of the first key (S1) in the memory ( 20 ) is stored. Method according to one of claims 11 to 17, wherein a second key (S2) and / or a further key and / or a part of the second key (S2) and / or another key in the memory ( 20 ) get saved. Method according to one of claims 11 to 16, wherein a first key (S1) or a part of the first key (S1) is stored in a first area of the memory (S1). 20 ) and at least one further key and / or at least part of a further key in a second area of the memory ( 20 ) is stored.

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