DE102010040377B4 - Lambda probe with sigma-delta analogue/digital converter - Google Patents

Abstract

A sigma-delta analog-to-digital converter including a sigma-delta modulator, a clock generator for generating a plurality of clocks for the sigma-delta analog-to-digital converter, and a decimation filter connected to an output of the sigma-delta modulator , wherein the sigma-delta modulator is constructed using switched-capacitor circuit technology and has at least one integrator (7, 11) with a reset switch connected in parallel with an integrator capacitance (22) of the integrator (7, 11), the clock generator being formed to generate at least a first and a second clock (Φ1, Φ11; Φ2, Φ22) for the sigma-delta modulator, the first and the second clock (Φ1, Φ11; Φ2, Φ22) being non-overlapping clocks, characterized in that the clock generator has an input for a start signal (S) and is designed to output a reset signal (R) to a reset line connected to the reset switch synchronously on receipt of the start signal (S). isation with the first clock (Φ1, Φ11) for the sigma-delta modulator, the sigma-delta modulator containing a quantizer (12) which is designed depending on a level of an input signal of the quantizer (12) and a threshold value of the quantizer to feed back either a first reference voltage or a second reference voltage to an input of the at least one integrator (7, 11) of the sigma-delta modulator, the quantizer (12) being designed for a first level which is greater than the Threshold is to feed back the first reference voltage when a selection signal (M) is inactive, and to feed back the second reference voltage when the selection signal (M) is active, and for a second level, which is less than the threshold value, to feed back the second reference voltage, when the selection signal (M) is inactive, and feeding back the first reference voltage when the selection signal (M) is active.

Description

The present invention relates to a sigma-delta analogue/digital converter and a sensor for measuring a residual oxygen content in an exhaust gas with such a sigma-delta analogue/digital converter.

State of the art

Lambda probes are used in particular in vehicle construction in sensors for measuring the residual oxygen content in an exhaust gas in order to be able to set an optimal mixing ratio between fuel and oxygen or air for the cleanest and most efficient possible combustion based on these measurements. A lambda probe usually measures the oxygen partial pressure in different spaces connected to the exhaust gas space in different ways and emits an electrical signal for each space corresponding to the oxygen partial pressures, from which the content of nitrogen oxides or free oxygen, for example, can be determined. In this case, the oxygen partial pressure in a reference chamber of the lambda probe is also set by applying appropriate electrical signals. So far, the associated regulation has been implemented purely analogously; digital controllers, which would require the use of an analog/digital converter, have not been used to date. One of the reasons for this is that the signals from the various electrodes of the lambda probe are only valid for a short period of time and must be recorded as simultaneously as possible so that the recorded values are correlated with one another. In the prior art, this requires either the use of a fast and expensive analog/digital converter, such as a flash converter, or several analog/digital converters that can be implemented more cheaply, which usually only allow a slower analog/digital conversion.

The document U.S. 2008/0 074 303 A1 discloses incremental delta-sigma data converters with improved stability over a wide input voltage range.

The font US 2004/0 263 370 A1 describes an incremental delta analog-to-digital conversion.

The document U.S. 6,570,519 B1 describes switched capacitor buzzer circuits, methods and systems for using such.

Disclosure of Invention

According to the invention, therefore, a sigma-delta analog/digital converter with a sigma-delta modulator, a clock generator for generating a plurality of clocks for the sigma-delta analog/digital converter and with an output of the sigma-delta Modulators associated decimation filter introduced. The sigma-delta modulator is constructed using switched-capacitor circuit technology and has at least one integrator with a reset switch connected in parallel with an integrator capacitance of the integrator. The clock generator is designed to generate at least a first and a second clock for the sigma-delta modulator, the first and the second clock being non-overlapping clocks. According to the invention, the clock generator has an input for a start signal and is designed to end the output of a reset signal to a reset line connected to the reset switch in synchronization with the first clock for the sigma-delta modulator upon receipt of the start signal.

The invention has the advantage that a single conversion, i.e. the conversion of an analog input value into a digital output value, can also be carried out with a fundamentally rather slow sigma-delta analog/digital converter by starting the conversion as precisely as possible with the Clocks for the operation of the sigma-delta analog / digital converter is synchronized. The greatest possible conversion precision is achieved by keeping the integrator capacitance in a discharged state until the very beginning of a conversion cycle. This prevents an internal state of a component of the sigma-delta modulator from being influenced by the previous history of the measurement signal, which is still invalid at this point in time, and the conversion and measurement from being falsified as a result. In this way, the sigma-delta analogue/digital converter can be “triggered”, i.e. a conversion can be triggered by a start signal.

The triggerability of the sigma-delta analog/digital converter of the invention also makes it possible to use a single sigma-delta analog/digital converter for measuring a plurality of measurement signals, such as those given in a lambda probe, because the conversion can be triggered and thus several measurements can be carried out precisely in terms of time within a period of time in which the measurement signals are to be regarded as static and thus correlated with one another. A sigma-delta analog/digital converter according to the prior art, on the other hand, would have to measure each of the measurement signals over a longer period of time in order to ensure that a digital output value can be determined that depends on invalid internal states of the components of the sigma-delta analog /digital converter is independent. Therefore, the invention makes it possible for the first time to use the sigma-delta modulation technology, which can be implemented inexpensively as an integrated circuit, in a single analog/digital converter for converting and measuring the signals of a lambda sensor, so that the control algorithms associated with the operation of the lambda sensor can be implemented digitally . This brings with it the further advantage that the control algorithms can be programmed, for example coefficients of the algorithms or the algorithms themselves can be modified or adapted to different designs of lambda sensors. However, the sigma-delta analog/digital converter of the invention is of course not limited to use in conjunction with lambda sensors, but can also be used in other environments.

The decimation filter preferably has a reset input connected to the reset line and is designed to set an internal state of at least one register of the decimation filter to a predetermined state when the reset signal is present. This additional measure ensures that the decimation filter is also initialized before each conversion, so that the output value of the decimation filter also becomes independent of any outputs of the sigma-delta modulator or previous measurements before the end of the outputting of the reset signal.

The decimation filter can be constructed as a cascaded integrator comb filter (CIC filter), in which case the at least one register is a register of an integrator of the cascaded integrator comb filter. In contrast to the comb stages of a CIC filter, the integrators of the CIC filter have their output fed back to their input and are therefore infinite impulse response filters (IIR filters). As a result, a value in the integrator that is invalid or not related to the current conversion can in principle affect all future values and thus falsify them, so that the initialization of the integrator or integrators of the CIC filter by the reset signal is advantageous.

In contrast, the comb stages of the CIC filter have no feedback and therefore do not necessarily have to be initialized for each triggered conversion. Under certain circumstances, values that are still present in the comb stages can mean that a valid result of the decimation is only available after a few bars. However, this can be taken into account in the processing following the decimation and the invalid values can be ignored.

The clock generator can be designed to end the output of the reset signal with or after the end of an active phase of the first clock and before the beginning of an active phase of the second clock. The first clock is preferably used in the sigma-delta modulator constructed as switched-capacitor circuit technology for sampling the input for the measurement signal, i.e. during the active phase of the first clock, an input capacitor of the sigma-delta modulator is connected between the Input of the measurement signal and a reference potential connected. The conversion actually begins during the active phase of the first clock pulse, which is immediately before the end of the reset signal output. The reset signal is no longer output until the input capacitor is decoupled from the input for the measurement signal and connected to the input of the integrator of the sigma-delta modulator and the integrator capacitance of the integrator of the sigma-delta modulator is no longer due to the reset signal be short-circuited by the reset switch.

The clock generator is particularly preferably designed to output the reset signal after each analog/digital conversion. As a result, the sigma-delta modulator - and in certain embodiments the decimation filter - is initialized after each conversion, making subsequent conversions independent of one another. Such an analog/digital converter is also referred to as an incremental analog/digital converter. The main advantage of the initialization between individual conversions is that the decimation filter can be set up less complex. In particular, if the sigma-delta modulator is of N order, then the decimation filter need only be of N order. On the other hand, without the continuously repeating initialization, the decimation filter would have to have an order of N+1. An embodiment of a sigma-delta analog/digital converter that is both triggerable and incremental is unknown in the prior art.

The sigma-delta modulator preferably contains a quantizer, which is designed to feed back either a first reference voltage or a second reference voltage to an input of the at least one integrator of the sigma-delta modulator, depending on a level of an input signal of the quantizer and a threshold value of the quantizer . The fed-back reference voltage represents a voltage value assigned to the digitized output value of the quantizer, which voltage value is fed back into the sigma-delta modulation. The quantizer is designed to feed back the first reference voltage for a first level, which is greater than the threshold value, if a selection signal is inactive, and to feed back the second reference voltage, when the select signal is active and for a second level less than the threshold, feeding back the second reference voltage when the select signal is inactive and feeding back the first reference voltage when the select signal is active. This means that the voltage values associated with the logic levels of the quantizer output value can be swapped depending on the state of the selection signal.

The sigma-delta analog/digital converter is particularly preferably designed to carry out a first conversion with an inactive selection signal and a second conversion with an active selection signal, and an error-compensated result from a first result of the first conversion and a second result of the second conversion derive the overall result. Since a conversion is carried out once with one of the two possible states of the selection signal, the measurement or conversion becomes independent of static errors because these are taken into account in the individual measurements with different signs. Therefore, for example, offsets of the individual components of the sigma-delta modulator can be compensated.

The clock generator can be designed to generate a gate signal for an output stage of the sigma-delta modulator and to output it to the output stage of the sigma-delta modulator, the output stage of the sigma-delta modulator being designed to respond to the receipt of the gate signal to switch through a signal present at an input of the output stage. In this case, the gate signal preferably has an active phase which coincides with an active phase of the first clock for the sigma-delta modulator, particularly preferably beginning after the start of the active phase of the first clock. In this way, the gate signal switches through a valid output value of the sigma-delta modulator and/or the integrator(s) of the sigma-delta modulator to the respective output. In embodiments of the invention, the output stage can be integrated into the quantizer, so that the quantizer is designed to output an output value upon receipt of the gate signal.

The clock generator can also be designed to generate a clock signal for the decimation filter, which has an active phase that runs during an active phase of the gate signal. The clock signal for the decimation filter can also be a gating signal for a clock for the decimation filter. Since the decimation filter only receives one clock while the gate signal for the output stage of the sigma-delta modulator is active, it is ensured that the decimation filter only works if there is a valid output value from the sigma-delta modulator.

A second aspect of the invention relates to a sensor for measuring a residual oxygen content in an exhaust gas. The sensor has a lambda probe and a sigma-delta analog/digital converter connected to electrodes of the lambda probe according to the first aspect of the invention.

character list

• 1 die Struktur eines Ausführungsbeispiels eines Sigma-Delta-Modulators zum Einsatz in der Erfindung,
• 2 ein Ausführungsbeispiel eines Integrators in Switched-Capacitor-Schaltungstechnik zum Einsatz in dem Sigma-Delta-Modulator,
• 3 ein erstes Beispiel für ein Taktschema zum Betrieb des Sigma-Delta-Analog/Digital-Umsetzers der Erfindung, und
• 4 ein zweites Beispiel für ein Taktschema zum Betrieb des Sigma-Delta-Analog/Digital-Umsetzers der Erfindung.

Exemplary embodiments of the invention are explained in more detail with reference to the drawings and the following description. Show it:

• 1 the structure of an embodiment of a sigma-delta modulator for use in the invention,
• 2 an embodiment of an integrator in switched-capacitor circuit technology for use in the sigma-delta modulator,
• 3 a first example of a timing scheme for operation of the sigma-delta analogue/digital converter of the invention, and
• 4 a second example of a timing scheme for operating the sigma-delta analog-to-digital converter of the invention.

Embodiments of the invention

1 Figure 1 shows the structure of an embodiment of a sigma-delta modulator for use in the invention. The sigma-delta modulator has an input 1 for an analog input signal that is to be converted into a digital equivalent. The sigma-delta modulator also has an output 2 for a digital data stream with a high signal rate, which is usually converted by a subsequent decimation filter into a data stream with a lower signal rate and simultaneously increased resolution. According to the invention, a reset input 3 is provided.

A measurement signal present at the input 1 is multiplied in a multiplier 4 by a first coefficient α ₁ . A feedback value multiplied by a second coefficient −β ₁ in a further multiplier 6 is added to the output value of the multiplier 4 in a subsequent adder 5 . The result of this operation is integrated in an integrator 7 or accumulated.

The sigma-delta modulator from 1 is designed as a second-order sigma-delta modulator in the example and therefore has two integrators 7 and 11. Alternatively, the sigma-delta modulator can also have a higher order own. The structure of multiplier 4, adder 5, multiplier 6 and integrator 7 is repeated with multiplier 8, adder 9, multiplier 10 and integrator 11 using coefficients α ₂ and -β ₂ . Correspondingly more such structures would be cascaded in a higher-order sigma-delta modulator.

The two integrators 7 and 11 are also connected to the reset input 3. If a reset signal is present on the reset line, an integration capacitor of the integrator 7 or 11 is initialized. In the example shown, the output of the integrator 11 is connected to a quantizer 12 which digitizes an output signal of the integrator 11 . In the simplest case of a 1-bit quantizer, the quantizer 12 can be designed as a flip-flop, for example. The output of the quantizer 12 is connected to the output 2 of the sigma-delta modulator and to an input of a digital-to-analog converter 13, which performs an inverse function to the function of the quantizer 12 and converts the digital output signal of the quantizer 12 into an analog feedback signal implements. In the case of a 1-bit quantizer, the digital-to-analog converter 13 can be omitted under certain circumstances, or it can be replaced by a simple multiplexer that switches through one of two reference voltages depending on the digital input signal.

2 shows an embodiment of an integrator in switched-capacitor circuit technology for use in the sigma-delta modulator. The integrators 7 and 11 of the sigma-delta modulator from 1 can as in 2 shown to be constructed. The circuit of 2 However, in addition to the function of the integrator 7 or 11, it also assumes the functions of the multipliers 4, 6 or 8, 10 and the adder 5 or 9.

The integrator has two inputs 23 and 24, which represent an input for the input signal and an input for a feedback signal. The integrator of 2 essentially corresponds to the structure of an analog integrator with two inputs, but is constructed using switched-capacitor technology. In switched-capacitor technology, the resistors commonly used in analog circuits are replaced with switched capacitors. The advantage of this approach is that capacitors can be manufactured more easily and precisely in integrated circuits. Analysis of the resulting circuits also shows that their transfer function depends on the ratios of the capacitors used, which means that so-called matching can be used to advantage. In integrated circuits, like components arranged in close proximity to one another have the property that their characteristics change in proportion to one another with process variations. As a result, the effects of the process variations are approximately canceled out when the characteristic values are set in relation to one another. Thus, the coefficients α ₁ and β ₁ or α ₁ and β ₂ are set by the ratio of the capacitance of an input capacitor 20 to that of an integrating capacitor 22 or a reference capacitor 21 to that of the integrating capacitor 22 .

According to switched-capacitor technology, the input capacitor 20 and the reference capacitor 21 are connected alternately between the respective input signal and a reference potential or between a reference potential and the output of the respective stage. In the first phase, the respective capacitor is charged to the level of the input signal, so that an amount of charge proportional to the input signal reaches the capacitor. In the second phase, this charge is passed on to the next stage. If this operation is carried out very quickly, the function of a resistor is approximately fulfilled. The actual integrator has an integration capacitor 22, which - is arranged in the feedback of a differential amplifier 26 - as is known. A reset switch is provided in parallel with the integration capacitor 22 which discharges and thus initializes the integration capacitor 22 when it is closed. The integrator of 2 is controlled by clock signals Φ ₁ , Φ ₁₁ , Φ ₂ , Φ ₂₂ and R, which are illustrated by way of example in the following figures.

3 Figure 12 shows a first example of a timing scheme for operating the sigma-delta analogue/digital converter of the invention. The signal S designates a start signal, ie the sigma-delta analog/digital converter of the invention is intended to convert an analog signal present at its input at this time into a digital value. The start signal S is preferably synchronized with a system clock CLK, from which the clock generator derives further clocks, and with the beginning of the active phases of the clock signals Φ ₁ and Φ ₁₁ , so that the input signal with the in 2 structure shown is sampled. The clock signals Φ ₁ and Φ ₁₁ overlap each other for the most part, while the clock signal Φ ₁ has, however, an active phase that is half a cycle longer than the system clock CLK. The clock signals Φ ₂ and Φ ₂₂ are designed similarly, but their active phases are time-shifted so that they fall into inactive phases of the clock signals Φ ₁ and Φ ₁₁ . An additional clock signal Φ ₃ can be provided, which switches through a valid output value of the sigma-delta modulator as a gate signal. The clock signal Φ ₃ preferably has an active phase with a final phase of active phase of the clock signals Φ ₁ and Φ ₁₁ coincide.

A decimation filter following the sigma-delta modulator can receive a clock signal G for the decimation filter. So that the decimation filter becomes active for each conversion at a point in time at which a valid output value of the sigma-delta modulator is present, an active phase of the clock signal G preferably falls in the active phase of the clock signal Φ ₃ . In addition to the clock signal G, the decimation filter can also receive the system clock CLK. In this case, the clock signal G can be used as a gate signal for the clock.

The reset signal R is preferably synchronized with the clock signals Φ ₁₁ and Φ ₂ or Φ ₂₂ such that the end of its active phase falls between the end of the active phase of the clock signal Φ ₁₁ and the beginning of the active phase of the clock signal Φ ₂ or Φ ₂₂ . If the start signal S is therefore synchronized with the start of the active phase of the clock signal Φ ₁ or Φ ₁₁ , the reset signal R is preferably switched inactive later by at least the duration of the active phase of the clock signal Φ ₁₁ .

4 Figure 12 shows a second example of a timing scheme for operating the sigma-delta analogue to digital converter of the invention. 4 illustrates two consecutive conversions. Thus, several periods of the clock signal G for the decimation filter are shown. Also shown is a selection signal M that specifies a sign of the feedback in the sigma-delta modulator. After a conversion, the selection signal M is preferably inverted for the next conversion. The results of the two consecutive opposite sign conversions can be used to derive an error compensated overall result. This is possible because static errors such as offsets of a differential amplifier or the quantizer are included in the partial result with each conversion with correspondingly different signs and are thus canceled out in the overall result. In addition, the reset signal R is preferably briefly active between two successive conversions in order to allow the sigma-delta analog/digital converter to work as an incremental analog/digital converter.

Claims (9)

A sigma-delta analog-to-digital converter including a sigma-delta modulator, a clock generator for generating a plurality of clocks for the sigma-delta analog-to-digital converter, and a decimation filter connected to an output of the sigma-delta modulator , the sigma-delta modulator being constructed using switched-capacitor circuit technology and having at least one integrator (7, 11) with a reset switch connected in parallel with an integrator capacitance (22) of the integrator (7, 11), the clock generator being formed , to generate at least a first and a second clock (Φ ₁ , Φ ₁₁ ; Φ ₂ , Φ ₂₂ ) for the sigma-delta modulator, wherein the first and the second clock (Φ ₁ , Φ ₁₁ ; Φ ₂ , Φ ₂₂ ) are non-overlapping clocks, characterized in that the clock generator has an input for a start signal (S) and is designed, upon receipt of the start signal (S), to output a reset signal (R) to a resetle connected to the reset switch in synchronization with the first clock (Φ ₁ , Φ ₁₁ ) for the sigma-delta modulator, the sigma-delta modulator including a quantizer (12) which is formed depending on a level of an input signal of the quantizer (12) and a threshold value of the quantizer to feed back either a first reference voltage or a second reference voltage to an input of the at least one integrator (7, 11) of the sigma-delta modulator, the quantizer (12) being designed for a first level, which is greater than the threshold, to feed back the first reference voltage when a selection signal (M) is inactive, and to feed back the second reference voltage when the selection signal (M) is active, and for a second level, which is less than the threshold, the to feed back the second reference voltage when the selection signal (M) is inactive, and to feed back the first reference voltage when the selection signal (M) is active. The sigma-delta analogue to digital converter according to FIG claim 1 , in which the decimation filter has a reset input connected to the reset line and is designed to set an internal state of at least one register of the decimation filter to a predetermined state when the reset signal (R) is present. The sigma-delta analogue to digital converter according to FIG claim 2 , in which the decimation filter is constructed as a cascaded integrator comb filter and the at least one register is a register of an integrator of the cascaded integrator comb filter. The sigma-delta analogue/digital converter according to one of the preceding claims, in which the clock generator is designed to output the reset signal (R) at or after the end of an active phase of the first clock (Φ ₁ , Φ ₁₁ ) and before beginning of an active phase of the second clock (Φ ₂ , Φ ₂₂ ). The sigma-delta analog/digital converter according to one of the preceding claims, in which the clock generator is designed to output the reset signal (R) after each analog/digital conversion. The sigma-delta analogue to digital converter according to FIG claim 5 , designed to carry out a first conversion with an inactive selection signal (M) and a second conversion with an active selection signal (M) and to derive an error-compensated overall result from a first result of the first conversion and a second result of the second conversion. The sigma-delta analog/digital converter according to any one of the preceding claims, in which the clock generator is arranged to generate a gating signal (Φ ₃ ) for an output stage of the sigma-delta modulator and to the output stage of the sigma-delta modulator output, the output stage of the sigma-delta modulator being designed to switch through a signal present at an input of the output stage upon receipt of the gate signal (Φ ₃ ). The sigma-delta analogue to digital converter according to FIG claim 7 , in which the clock generator is also designed to generate a clock signal (G) for the decimation filter which has an active phase which runs during an active phase of the gate signal (Φ ₃ ). A sensor for measuring a residual oxygen content in an exhaust gas with a lambda probe and a sigma-delta analogue/digital converter connected to electrodes of the lambda probe according to one of the preceding claims.

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