DE102010037904A1 - Method for controlling e.g. combustion process in engine in industrial applications, involves combining two hyper planes into inner multi-face node forming inner node of transformed tree that has reduced height with respect to binary tree - Google Patents

Abstract

The method involves defining a control law on polyhedrons (16) in bits and pieces, where the polyhedrons are described by two hyper planes (12). The hyper planes are arranged in a binary tree (14) to allow evaluation of the law, where each hyper plane represents an inner node in the binary tree that ends in a finite non-empty polyhedron. The polyhedron is an external node of the binary tree. The two hyper planes are combined into an inner multi-face node that forms an inner node of a transformed tree, where the transformed tree has reduced height with respect to the binary tree. An independent claim is also included for a device comprising an adder unit.

Description

The invention relates to a control method for controlling a technical process based on a previously defined explicit control law, which describes one or more control variables or control parameters of the technical process as a function of one or more state variables of the technical process, wherein the control law is defined piece by piece on polyhedra, wherein the Polyhedra are described by at least two hyperplanes and the hyperplanes can be arranged in a binary tree that allows the evaluation of the tax law, each hyperplane representing an internal node in the binary tree and the binary tree ending in at least one finite nonempty polyhedron; Polyhedron is an external node of the binary tree, according to the preamble of claim 1. Furthermore, the invention relates to a device on which the control method is operated, according to the preamble of claim 8.

State of the art

mit Anfangswerten

betrachtet, wobei die Grenzen y_min ≤ y(t) ≤ y_max, u_min ≤ u(t) ≤ u_max Gleichung (2) für t ≥ 0 eingehalten werden müssen und eine typische Regelungsaufgabe darin besteht, den technischen Prozess im Zustand, der x = 0 entspricht, zu stabilisieren. In Gleichung (1) sind

Zustandsgrößen, Eingangs- und Ausgangsgrößen und die Matrizen

beschreiben den zu regelnden technischen Prozess. Der hohe Aufwand eines Regelungsverfahrens der MPC fällt an, weil zu jedem Abtastzeitpunkt t ein Optimierungsproblem gelöst werden muss. Ein typischer Vertreter eines solchen Optimierungsproblems ist ein beschränktes quadratisches Problem der Form

mit U = {U_t|t,..., u_t+N–1|t) und Gewichtungsmatrix R. Weiterhin bezeichnet x_t+k|t den prädizierten Zustandsvektor, h_y, h_u ≤ h_y, und h_c < h_y – 1 bezeichnen den Ausgangs-, Eingangs- und Beschränkungshorizont und die Matrix

beschreibt die Rückkopplung für Zeitpunkte jenseits des Eingangshorizonts.Regulations of technical processes based on state space models of the technical process are state of the art in many industrial applications. Some of these regulations require a high amount of computation during the operation of the technical system. This class of control methods includes the model predictive control (MPC), in which a high computational effort is incurred during operation, because in order to determine control and control variables in each time step with the state space model, an optimization problem must be solved. For better illustration, a time-discrete linear time-invariant system of the form

with initial values

considering the limits y _min ≦ y (t) ≦ y _max , u _min ≦ u (t) ≦ u _max Equation (2) for t ≥ 0 and a typical control task is to stabilize the technical process in the state corresponding to x = 0. In equation (1) are

State variables, input and output variables and the matrices

describe the technical process to be regulated. The high cost of a control method of the MPC is due, because at each sampling time t an optimization problem must be solved. A typical representative of such an optimization problem is a limited quadratic problem of the shape

with U = {U _{t | t} , ..., u _{t + N-1 | t} ) and weighting matrix R. Furthermore, x _{t + k | t} denotes the predicted state vector, h _y , h _u ≦ h _y , and h _c <h _y -1 denote the output, input and restriction horizons and the matrix

describes the feedback for times beyond the input horizon.

Equations (3) and (4) represent a quadratic program (QP) with constraints consistent with existing methods, e.g. As active set method or inside points method can be solved. In this case, the QP must be solved again in each time step of a sampling control taking into account the current state x (t) in order to determine the quantity u (t + 1) for the next time step of the control. The time for solving the QP must be less than the sampling time. An implementation of the described method of model predictive control fails if the QP can not be solved fast enough. To make matters worse, no guarantee can be given about the maximum time required to solve the QP.

Obviously, regulatory procedures are of interest which have as little time as possible for the duration of the system to be regulated and in which a guarantee can be given for the maximum time required. In the case of model predictive control and QP, these methods are given by the explicit model predictive control (EMPC).

wobei eine endliche Anzahl von mindestens n_x + 1 Ungleichungen für jeden Polyeder P_i auftaucht und wobei die Anzahl abhängig von i ist. Gleichungen der Form h_i(x) = a T / i x + b_i, Gleichung (6) mit

werden im Folgenden Hyperebenengleichungen oder kurz Hyperebenen genannt, weil h_i(x) = 0 eine Hyperebene definiert. Die Zahl der Hyperebenen, die zur Beschreibung der n_p Polyeder benötigt werden, wird mit n_h bezeichnet. Dasselbe Regelgesetz u(x), das sich durch wiederholtes Lösen des oben beschriebenen QP punktweise in x ergibt, kann mit Hilfe der Verfahren der EMPC durch eine explizite stückweise affine Gleichung der Form

dargestellt werden, wobei

ist. Regelgesetze dieser Form werden im Folgenden als stückweise affine Regelgesetze bezeichnet.It can be shown that the solution of the QP can be represented in the following structure. There are a finite number of n _p of polyhedra P _i of the form

wherein a finite number of at least n _x + 1 inequalities for each polyhedron P _i appears and wherein the number is dependent on i. Equations of form h _i (x) = a T / ix + b _i , equation (6) With

are called hyperebenes equations, or hyperplanes for short, because h _i (x) = 0 defines a hyperplane. The number of hyperplanes needed to describe the n _p polyhedra is called n _h . The same law of control u (x), which is obtained by repeatedly solving the above-described QP point by point in x, can be determined by the methods of EMPC by an explicit piecewise affine equation of the form

be represented, wherein

is. Rules of this form are referred to below as piecewise affine rules.

In contrast to the repeated complex solving of the QP from equations (3) and (4), an EMPC control law in the form of equation (7) can be evaluated in two steps, which require considerably less effort than solving the QP. In the first step, a polyhedron P _j must be identified so that the current value x (t) lies in P _j . Then the law of rules, which applies to all values x ∈ P _j according to equation (7), has to be evaluated in order to obtain u _{t + l | t} .

The first step, the search for the valid P _j can be implemented using a binary tree. In this binary tree, each internal node has a hyperplane h _i (x) as in equation (6) is defined. Each external node of the binary tree corresponds to a polyhedron P _j as defined in Equation (5). In particular, it follows that the binary tree has n _h internal and n _p external nodes. The number of internal nodes is also denoted by N _int , where N _int = n _h .

It can be shown that a polyhedron P _j in which the given x (t) lies can be found by branching to its left child node in each internal node if h _j (x) ≤ 0 for the hyperplane equation h _j which corresponds to these nodes and branches to the right child node if h _j (x)> 0. It should be noted that the assignment that h _j (x) ≤ 0 corresponds to the left child node was chosen freely.

Methods for constructing a suitable binary tree from a control law (7) are state of the art. Methods for constructing a law of control (7) that solves a QP consisting of equations (3) and (4) are also prior art.

Polyhedra, as defined in equation (5), can be described using index sets. This presentation is introduced below because it is the basis for the invention to be described. There are index quantities

definiert, wobei

ist. Dann ist x ∈ P_j, genau dann wenn

für alle j ∈ I – / i ∪ I + / i ist.This presentation suggests evaluating each hyperplane only once for a given x and recording the sign of the result to store information about where x is located relative to each hyperplane. For this purpose, for a given binary tree T is an illustration

defined, where

is. Then x ∈ P _j , if and only if

for all j ∈ I - / i ∪ I + / i is.

The prior art described so far relates to the model predictive control, with quadratic cost functions (3) and the corresponding explicit solution. For model predictive control with linear cost functions, there are also methods for calculating explicit solutions, which also lead to piecewise affine control laws. Piecewise affine control laws that are based on a partitioning of the state space of the technical process in polyhedra, also result in other control approaches, including z. B. gain scheduling.

Disclosure of the invention

It is therefore an object of the invention to provide a control method and a device for controlling a technical process based on an explicit piecewise affine control law, which reduces the process complexity for controlling the technical process and thus brings with it time savings. Furthermore, it is also an object of the present invention to regulate faster-running technical processes than is possible with existing methods.

To solve this problem, a control method according to the features of claim 1 and an apparatus with the features of claim 8 is proposed, in particular with the features of the respective characterizing part. In the dependent claims preferred developments of the invention are listed.

The term regulation in the sense of this invention also includes a control and vice versa. This is mainly about being able to control or control the existing technical process with the help of technology. The technical process is a technical process on a technical plant, apparatus or a device such. Refinery process in a refinery, combustion process in a combustion chamber or the like.

According to the invention, at least two hyperplanes are combined to form an internal multiple node, each internal multiple node forming an internal node of a transformed tree and the transformed tree having a reduced height compared to the binary tree.

The gist of the invention is to replace the binary tree representing the piecewise law of Form (7) defined by polyhedra with a new approach based on a different type of tree. The following two characteristics are important for the new approach. First, several binary tree nodes are transformed into a new node type, the so-called m node. By doing so, the binary tree can be replaced by a tree of m-nodes, hereafter referred to as the M-tree, called the M-tree, the M-tree being a lesser height than the original binary Tree can have. Due to the lower height of the M-tree, the valid control law can be found in fewer steps with the M-tree than with the binary tree. Second, an m-node can be evaluated as fast as a binary node if m-fold concurrency can be achieved for the evaluation of hyperplanes in the manner of equation (6). The m-fold concurrency can be achieved with a device that is the subject of the invention. It is advantageous that the concurrency is not equated with a parallelization in the sense of a parallel execution of an algorithm on a microprocessor, but that the concurrent circuits can be constructed much simpler compared to a very simple microprocessor.

Central to the invention is that an upper limit of the steps required by the proposed method of evaluating the law of control can be given, and that this upper limit can be related to the number of steps taken in existing, on binary trees based methods are needed. The searched upper limit is derived below.

A. Terminology and terminology

Let T be a binary tree with N nodes n ₁ , ..., n _N. The length of the path from the root node to a node n _i is referred to as the depth of the node n _i , where the depth of the root node is defined as zero. The height of the tree T is the greatest depth of a knot that can be found in the tree. A tree consisting of only one root node has by definition the height zero. The set of nodes in a binary tree that have the same depth d is called the d-th plane of the tree. A node without children is called an external node or leaf. All other nodes are called internal nodes. If the following is the node of a tree, so are both its internal as well as its external nodes, unless otherwise expressly agreed. The internal height of the tree T is the height of the tree T, which results from removing all external nodes of T. A binary tree is called full if all nodes except for the external nodes have two children. A binary tree is called perfect when it is full and all external nodes are at the same level. A binary tree is called complete if all levels contain the maximum number of nodes, or if all levels down to the lowest level contain the maximum number of nodes. A binary tree is called height-balanced if, for each node, the height of the left and right sub-tree of this node differ by at most one. A binary tree is called left-oriented if, for each node, the height of the left sub-tree of the node is not less than the height of the right sub-tree of the node.

B. M-trees

As an extension of the binary tree, a tree with certain properties is introduced. A tree is hereafter called m-när, if its root node has more than one and not more than (m + 1) outgoing edges, if all internal nodes of the tree except for the root node exactly one incoming edge and at least one and at most (m + 1) have outgoing edges, and if the tree's external nodes have exactly one inbound and no outbound edge. A m-nary tree is called height-balanced if, for each internal node, the height of any two of its subtrees differ by at most one. Hereinafter, height-balanced full m-nary trees will be referred to as M-trees of order m for the sake of brevity. Unless the order m plays a role or is known from the context, M-trees of order m are referred to as M-trees for short.

The aim of the following considerations is to construct a M-tree from a binary tree that satisfies a piecewise affine law of control, which can be evaluated faster than the binary tree, but represents the same law of rules. For the sake of brevity, two trees, each of which may be binary-type or M-tree trees, are called equivalent if they represent the same law of control, that is, if, for all permissible states x of the technical system, the search for a polyhedron P _i , for the x ∈ P _i , and the subsequent evaluation of equation (7) leads to the same u (x).

C. Upper barrier to the height of the M-tree

Conditions 1: Let T be a height-balanced, left-oriented binary tree representing a piecewise affinitive law of rules defined on polyhedra such that each internal node of T represents a hyperplane of the form (6) and each external node of T is a polyhedron of the form (5). represents. Let the number of internal nodes of TN _int ≥ 1.

It should be noted that each subtree of T satisfies conditions 1. It should also be noted that the condition of leftwardness is introduced for convenience only. For each height-balanced binary tree T that satisfies condition 1, there is a height-balanced left-oriented binary tree T ~ that is equivalent to T. T ~ can be obtained from T by taking advantage of the fact that multiplying a hyperplane by -1 while simultaneously swapping the left and right sub-tree at the node to which the hyperplane is associated leaves the control law representing the binary tree unchanged.

gilt. Darin bezeichnet floor(x) für jedes

die größte ganze Zahl, die nicht größer als x ist.Theorem 1: Let T be an arbitrary binary tree satisfying condition 1. Let the internal height and the number of internal nodes of T be denoted by h _int and N _int . Then there exists a T-equivalent M-tree T _M of order m and the height h _M , where

applies. It denotes floor (x) for each

the largest integer not larger than x.

The first sentence is proved in several steps. It is anticipated that an M-tree node with the circuit described below can be evaluated at the same time in a computing unit, such as a node of a binary tree. It follows that the piecewise affine law of control for a given state x of the technical system to be controlled can be done with a number of steps which is of the order log _{m + 1} (N + 1), where N is the number of nodes in the equivalent binary tree from which the M-tree is generated has been.

D. Proof of Theorem 1

Lemma 1 and 2 summarize basic results.

Lemma 1:

Let T be a perfect binary tree of height h with N nodes. Then N = ^2h-1 - 1. Proof: Since all planes of a perfect binary tree are full, the i-th plane of a perfect binary tree has 2 ⁱ nodes. The sum over all levels gives

Lemma 2:

Let T be a binary tree of height h with N nodes. Then applies h ≥ log ₂ (N + 1) - 1 ≥ floor (log ₂ (N + 1)) - 1. Equation (12)

Proof: T can contain at most as many nodes as a perfect tree of height h. With N _perfect = 2 ^{h + 1} - 1 from Lemma 1, N ≤ 2 ^{h + 1} - 1 or equivalent h ≥ log ₂ (N + 1) - 1 equation (13).

Aus Gleichungen (13) und (14) folgt das gewünschte Ergebnis.Furthermore, log ₂ (N + 1) ≥ floor (log ₂ (N + 1)) Equation (14) because we have floor (x) ≤ x for all

From equations (13) and (14), the desired result follows.

The following algorithm 1 constructs m nodes of a binary tree into a sub-tree S together, with which an m-node of an M-tree is subsequently formed.

Algorithm 1: Let T be a binary tree that satisfies conditions 1. Let m be a positive natural number. The following steps provide a subtree S of T and a list of nodes (λ ₁ .... λ _k).

gilt. Fasse die auf diese Weise besuchten Knoten von T als die internen Knoten von S auf. Fasse die Knoten von T, die die ausgehenden Kanten der Knoten von S als eingehende Kanten haben, als die externen Knoten von S auf. Bezeichne die externen Knoten von S mit λ₁, ....,λ_k, wobei die Nummerierung beliebig aber fest ist.Construct a subtree S of the binary tree T, starting from the root node of T, traversing the nodes of T as in the breadth-first search, traversing continuing until min (m, N _int ) internal nodes of T have been visited,

applies. Record the nodes of T visited in this way as the internal nodes of S. Take the nodes of T that have the outgoing edges of the nodes of S as incoming edges as the external nodes of S. Denote the external nodes of S with λ ₁ , ...., λ _k , where the numbering is arbitrary but fixed.

Algorithm 1 results in a subtree that is summarized in a new type of node defined as follows.

Definition 1:

Let T and m be as in Algorithm 1. The tree S that results from applying Algorithm 1 is called the m-sub-tree. The m-nary node, which contains the internal nodes of S and whose outgoing edges lead into the external nodes of S, is called m-node.

An m-node is also called a multiple-node if the value of m is known from the context, or if the concrete value of m does not matter.

It should be noted that the algorithm may yield 1 m nodes containing at least one and up to m nodes of the binary tree T. In particular, not every m-node must contain exactly m nodes of the binary tree T.

Definition 2:

An m-node is called full if it contains m nodes of the binary tree from which it was constructed. An m-node is called partially when it is not full.

The terms m-node and m-sub-tree have so far been introduced only to summarize parts of a binary tree. An m-node only hides a subtree of the binary tree. In order to prove theorem 1, a lower bound to the height of the sub-tree of T, which has been converted to an m-node, is needed. Lemma 3 summarizes the statement you are looking for.

Lemma 3:

Given a full m-node resulting from the application of algorithm 1 to a binary tree T satisfying condition 1. Let S be the m-sub-tree belonging to the considered m-node and denote h _S the internal height of S.

Then each internal node of T, which is an external node of S, belongs to a plane of S of height h _S + 1 or h _S.

Proof: Suppose that the claim is false. Then there exists a binary tree T which satisfies the conditions 1, so that Algorithm 1 results in an m-sub tree S with an external node at a height l <h _S in S, which is an internal node of T. Let this node be denoted by ν.

By definition of h _S and since l <h _S is by hypothesis, there exist internal nodes of S that have a height greater than 1. It follows that the traversal of T in the breadth-first search manner described in Algorithm 1 has not yet ended when this traversal had completely grasped the lth level of T and was going to the (l + 1) th level switch. Since ν, by assumption, belongs to the lth level, Algorithm 1 has detected ν. This is in contradiction to the assumption that ν does not belong to S. Therefore, the assumption is wrong and the claim holds.

Based on the definitions of the m-node and the m-subtree, a simple algorithm for constructing an M-tree can be introduced. As a reminder, it is pointed out that each internal node of a binary tree T corresponds to a hyperplane and each external node corresponds to a polyder of an affine law of control of the form of equation (7) when T satisfies condition 1.

• 1.) Setze R := T.
• 2.) Wende Algorithmus 1 auf R an. Ersetze die inneren Knoten des resultierenden Unterbaums S von T durch den resultierenden m-Knoten. Bezeichne die externen Knoten von S mit λ₁, ..., λ_k.
• 3.) Führe für ν λ₁, ... λ_k folgende Schritte durch:
• 3.1) Wenn v ein externer Knoten von T ist, überspringe ihn und fahre mit dem nächsten λ_i, fort.
• 3.2) Wende den Algorithmus 2 auf den Unterbaum von R an, der ν als Wurzelknoten hat.
• 4.) Setze T_M := R und gebe T_M zurück.

Algorithm 2: Let T be a binary tree satisfying condition 1. Let m be a positive natural number. The following steps result in an M-tree called T _M.

• 1.) Set R: = T.
• 2.) Apply Algorithm 1 to R. Replace the inner nodes of the resulting subtree S of T with the resulting m node. Denote the external nodes of S with λ ₁ , ..., λ _k .
• 3.) Carry out the following steps for ν λ ₁ , ... λ _k :
• 3.1) If v is an external node of T, skip it and go to the next λ _i, continued.
• 3.2) Apply algorithm 2 to the sub-tree of R, which has ν as the root node.
• 4.) Set T _M : = R and return T _M.

After the construction of the M-tree is described by means of Algorithm 2, a few more concepts and simple relationships are introduced which are necessary for the proof of Theorem 1.

Definition 3: An m-node of an M-tree is finally called if none of its children is an m-node. Otherwise, an m-node is called non-terminating. This terminology is introduced to avoid confusion with the terms internal and external. In the next step, it is noted that each non-terminating m-node of an M-tree resulting from Algorithm 2 is full.

Lemma 4: Let T be a binary tree that satisfies conditions 1. Let m be a positive natural number. Let T _{M be} the M-tree resulting from applying Algorithm 2 to T. Then every non-terminating m-node of T _{M is} full.

Proof: Let ν be an arbitrary non-terminating node of T _M. It is shown that the assumption that ν is not full leads to a contradiction. Let _{Nν be} the number of nodes of T that are internal nodes of ν. Let S _{ν be} the subtree of T, which includes the N _ν nodes of the m-node. Let S be the subtree of T, which has the same root node as S _ν . In contrast to S _ν S comprise more than m internal node.

Since ν is not final by assumption, ν has at least one child, which is the root node of another m-node. Let this m-node be called μ. Since μ according to Definition 1 contains at least one node of T, S contains a number of N _S ≥ N _ν + 1 internal nodes of T. In the application of Algorithm 1 to S, one therefore obtains an m-node ν ', the same root node as ν has, but N _ν '> N _ν internal nodes. It follows, however, that ν can not be the result of Algorithm 1 and therefore does not correspond to Definition 1 of an m-node. This shows that no non-terminating m-node can exist that is not full.

For the proof of Theorem 1, a lower limit is needed for the height of the m sub-tree of a full m-node. This limit is shown in Lemma 5.

Lemma 5:

Let T be a binary tree that satisfies conditions 1. Let μ be a non-terminating m-node with the corresponding m-sub-tree S, where μ and S result from the application of Algorithm 2 to T. Let p be a path from the root node of S to any external node of S which is an internal node of T. Then the length l is equal to p l ≥ floor (log ₂ (m + 1)) Equation (15) limited.

Gleichung (16) erhält man durch Substituierung von N = m und h_S = h in Lemma 1. Da m + 1 eine natürliche Potenz von 2 gemäß der Gleichung (16) ist, folgt

Weiterhin folgt h_S = log₂(m + 1) –1 = floor(log₂(m + 1)) – 1, da floor(n) = n für jede natürliche Zahl n. gilt. Da S nach Annahme ein perfekter Baum ist und daher jeder seiner externen Knoten auf der Ebene h_S + 1 liegt, folgt, dass jeder Pfad vom Wurzelknoten von S zu einem beliebigen externen Knoten von S die Länge l = h_S + 1 = floor(log₂(m + 1)) hat, was die Aussage im Fall (i) beweist.Proof: Three cases are distinguished: (i) μ is a perfect node, (ii) μ is a complete node but not a perfect node, and (iii) μ is not a complete node. Let h _{S be} the internal height of S.
Case (i): Since μ is perfect, holds

Equation (16) is obtained by substituting N = m and h = _S h in 1. Lemma Since m + 1 is a natural power of 2 according to the equation (16) follows

Furthermore, h _S = log ₂ (m + 1) -1 = floor (log ₂ (m + 1)) - 1, since floor (n) = n holds for any natural number n. Since S is a perfect tree by assumption, and therefore each of its external nodes is at the level h _S + 1, it follows that each path from the root node of S to any external node of S has the length l = h _S + 1 = floor ( log ₂ (m + 1)), which proves the statement in case (i).

für das ein

existiert, sodassCase (ii): In preparation, it is stated that for each

for the one

exists, so

oder äquivalentSince S is complete but not perfect, we obtain a perfect tree S 'with height h _S ' = h _S - 1 and m '<m node by omitting all external nodes of S and all internal nodes of S of plane h _S become. Since S 'is perfect, the results derived in case (i) can be applied. In particular, applies

or equivalent

sodass m = m' + t.Since S is complete but not perfect, S contains at least one and at most 2 ^hS - 1 knots at the depth h _{S level} . Therefore, there is one

so that m = m '+ t.

From this relationship between m and m 'follows (m + 1) = (m' + 1) + t, 1 ≤ t ≤ 2 ^hS - 1 or equivalently (m + 1) ∈ [2 ^hS + 1,2 ^{hS + 1} - 1]. Since the interval [2 ^hs , 2 ^{hS + 1} - 1] is contained in the above interval, the result is floor (log ₂ (m + 1)) = h _S Equation (19) with equation (17). Since S is complete but not perfect, at least one external node exists at the level h _S , but there are no external nodes on a plane with a depth d <h _S. Therefore, every path from the root node of S to any external node of S has at least the length h _S , which together with equation (19) gives the sought statement.

Case (iii): It is assumed that S is not complete. Let μ 'be such an m-node of the same order m as μ that the m-sub-tree S' belonging to μ 'is complete. S 'can be perfect or not perfect. Two cases are considered: (iii.a) and (iii.b). In case (iii.a), it is assumed that S 'is complete but not perfect. Since S 'is complete but S is not complete, holds h _S ≥ h ' _S equation (20).

Since μ 'is a complete but not a perfect tree, case (ii) can be applied. Since μ 'is supposed to be of order m, then floor (log ₂ (m + 1)) = h ' _S equation (21) corresponding to equation (19) of case (ii). Furthermore, according to Lemma 3, every external node of S which is an internal node of T is at the level h _S or h _S + 1. Therefore, applies l ≥ h _S equation (22) for the length of the path from the root node of S to any node that is an internal node of T. Equations (20), (21) and (22) together give l ≥h _S ≥ h ' _S = floor (log ₂ (m + 1)), proving the result sought in case (iii.a).

In case (iii.b), it is assumed that S 'is perfect. Then applies h _S ≥ h ' _S + 1. Equation (23) Further, l '= h _S ' + 1, since S 'is perfect and since l ≥ h _S as in the previous case, l ≥h _S ≥h _S ' + 1 = l ', which is the proof for the case (iii.b) completes.

With the completion of the proof of Lemma 5, all preparations for the proof of Proposition 1 are made.

wobei die zweite Ungleichung gilt, weil wie oben erläutert l_qk+1 – 1 ≥ 0 ist. Die Länge l_p des Pfades p ist nach oben durch die interne Höhe h_int von T beschränkt. Dies beinhaltet, dass l_p – 1 ≤ h_int – 1 < h_int. Durch Substituieren in Gleichung (26) und Addition von 1 auf beiden Seiten ergibt sich

Proof of Theorem 1: Algorithm 2 recursively replaces subtrees of the binary tree T by m-nodes that summarize subtrees of T. The recursion in Algorithm 2 is performed for all subtrees until an m-node terminates in an external node that is an external node of a binary tree T (see Step 3.2 of Algorithm 2). It follows that, for a path p through T from its root node to any of its external nodes, a sequence q = (q ₁ , ..., q _k , q _{k + i} ) of m nodes of T _M exists, that of p is going through. According to Definition 3, the m-nodes q ₁ ,..., Q _k are non-terminating nodes, since each of these nodes has at least one child, which itself is an m-node. It follows from Lemma 4 that the nodes q ₁ , ..., q _{k are} full nodes. The node q _{k + 1} may be a terminating or non-terminating node. Therefore, the node q _{k + 1 may be} full or not full. In both cases, the m-node q _{k + 1 contains} at least one internal node of T according to definition 1. It should be noted that q has the length k + 1. The numbering is chosen so that the nodes are full up to index k. Let the length of the subpath of p, which lies in q _{i be} denoted by l _qi . Let l _{p be} the number of internal nodes of T that are traversed along path p. Then applies l _p = 1 _q1 + ... + 1 _qk + 1 _{qk + 1} Equation (24) Furthermore, according to Lemma 5 l _qi ≥ floor (log ₂ (m + 1)) for all i = 1, ..., k, equation (25) since the q _i , i = 1, ..., k are non-terminating m-nodes. Equations (24) and (25) give l _p ≥ k (floor (log ₂ (m + 1))) + 1 _{qk + 1} , from which follows

wherein the second inequality is true because, as explained above _{qk + 1} - 1 ≥ 0. The length l _{p of} the path p is limited upwards by the internal height h _int of T. This implies that 1 _p - 1 ≤ h _int - 1 <h _int . Substituting in equation (26) and adding 1 on both sides gives

Since this estimate applies to any path p through T and the corresponding path q through the M-tree T _M , it also holds for the longest path through T _M to an external node of T _M. By definition, the length k + 1 of the longest path through T _M is equal to the height h _{M of} the M-tree T _M. Therefore, from equation (27), the assertion follows

IV. Fast evaluation of an m-node

As already mentioned, the m-node is the key to speeding up the evaluation of the rule law. The acceleration is achieved by a concurrent evaluation of the m binary nodes contained in each m node. Each binary node of an m-node can be evaluated by a simple circuit that can be operated independently of the circuits of the remaining m-1 binary nodes. The degree of concurrency, i. H. the number m of binary nodes that are simultaneously evaluated is only limited by the resources available to implement the circuits.

To introduce the concurrent evaluation of an m-tree T _M , the following maps σ and π must be introduced. Recall that each external node of a binary tree satisfying condition 1 represents a polyhedron of affine law of law of the form (7), which may be, in particular, an EMPC law of control.

Definition 4:

m ≥ 1 resultiert. Sei ohne Einschränkung n_i1 die Wurzel von S. Seien λ₁, ..., λ_m+1 die externen Knoten von S, die aus Algorithmus 1 resultieren.Let T be a binary tree satisfying conditions 1 with N _int internal nodes n ₁ , ..., N _Nint with corresponding hyperplanes h ₁ , ..., h _{Nint of} the form (6). Let S be an m sub-tree that is T by applying Algorithm 2

m ≥ 1 results. Without limitation n _i1, let be the root of S. Let λ ₁ , ..., λ _{m + 1 be} the external nodes of S resulting from Algorithm 1.

definiert ist, wobei j = 1, ..., m ist.Then, each external node may λ _k of S with a unique path p are identified by n _i1 to λ _k, said path clearly σ by a mapping _S (k) with the components

is defined, where j = 1, ..., m.

It suffices to consider only the entries of σ _S (k) that are either 1 or 0. The mapping σ ' _S (k) defined as follows serves this purpose.

Definition 5:

für alle l = 1, ..., m' gilt. Die Abbildung σ'_S(k) sei durch ihre m' Komponenten

m' definiert.Be the assumptions and σ _S as in Definition 4. For an arbitrary but firmly selected k in {1, ..., m} be with (j _1, ..., j _{m ')} the longest subsequence of 1 .. ., m denotes, so

for all l = 1, ..., m 'holds. The mapping σ ' _S (k) is given by its m' components

m 'defined.

wobei j = 1, ..., m ist. In Analogie zu σ'_S wird π'_S durch die Komponenten

Definiert. Die Suche nach dem für einen gegebenen Zustand x des technischen Systems gültigen Regelgesetz resultiert im Knoten λ_k, genau dann wenn für alle j = 1, ..., m mit σ_S,j(k) ≠ – 1 gilt

oder äquivalent für alle l = 1, ..., m' gilt σ'_S,l(k) = π'_S,l(x). Gleichung (31) As discussed in the Background section, the search on the binary tree T can be represented by π _T (x) for each binary tree T satisfying the conditions 1. For the sub-tree S from Definition 4, the mapping π _S (x) is defined by

where j = 1, ..., m. In analogy to σ _'S is π' _S by the components

Are defined. The search for the control law valid for a given state x of the technical system results in the node λ _k , if and only if for all j = 1, ..., m with σ _{S, j} (k) ≠ - 1 holds

or equivalently for all l = 1, ..., m 'holds σ ' _{S, l} (k) = π' _{S, l} (x). Equation (31)

ausgewertet werden. Da diese Hyperebenengleichungen unabhängig voneinander sind, ändert sich das Ergebnis des Vergleiches der Gleichung (30) oder der Gleichung (31) nicht, wenn die m Hyperebenengleichungen anstatt sequenziell simultan evaluiert werden. Dadurch ergibt sich der folgende Algorithmus zur nebenläufigen Evaluierung eines m-Knotens. Since the left-hand sides of equations (30) and (31) are independent of x, they can be evaluated in advance, ie before the start-up of the regulatory process. To evaluate the right-hand side of equations (30) and (31), m have hypertext equations

be evaluated. Since these hyperplane equations are independent of each other, the result of the comparison of equation (30) or equation (31) does not change when the m hyperplane equations are evaluated simultaneously rather than sequentially. This results in the following algorithm for concurrent evaluation of an m-node.

den zugehörigen Hyperebenen

den externen Knoten λ_k, k = 1, ..., (m + 1) und der Abbildung σ_S gemäß Definition 4. Sei x der aktuelle Zustand des zu regelnden technischen Systems. Der folgende Algorithmus ergibt einen externen Knoten λ_k von S, sodass das zu diesem Knoten gehörige Polyeder x enthält.

• 1) Für j = 1, ..., m berechne π_S,j(x), j = 1, ..., m simultan für alle j und bezeichne das Ergebnis mit Π = (πS,1(x), ..., π_S,m(x))
• 2) Für k = 1,..., m + 1 nehme folgende Vergleiche simultan für alle k vor:
• 2.1) Ermittle die Teilfolge σ'_S(k) = (σ'_S1(k), ..., σ'_Sm'(k)) von σ_S gemäß Definition 5.
• 2.2) Ermittle die Teilfolge π'_S(x) = (π'_S1(x), ..., π_Sm'(x)) von π_S(x) gemäß der Gleichung (29).
• 2.3) Falls σ'_S(k) = π'_S(x), gebe k zurück, denn λ_k ist der gesuchte Knoten.

Algorithm 3: Let S be an m sub-tree with the nodes

the associated hyperplanes

the external node λ _k , k = 1, ..., (m + 1) and the mapping σ _S according to definition 4. Let x be the current state of the technical system to be controlled. The following algorithm results in an external node λ _k of S, so that the polyhedron associated with this node contains x.

• 1) For j = 1, ..., m compute π _{S, j} (x), j = 1, ..., m simultaneously for all j and denote the result with Π = (πS, 1 (x),. .., π _{S, m} (x))
• 2) For k = 1, ..., m + 1, make the following comparisons simultaneously for all k:
• 2.1) Find the subsequence σ ' _S (k) = (σ' _S1 (k), ..., σ '_Sm' (k)) of σ _S according to Definition 5.
• 2.2) Find the subsequence π ' _S (x) = (π' _S1 (x), ..., π _{Sm '} (x)) of π _S (x) according to equation (29).
• 2.3) If σ ' _S (k) = π' _S (x), return k, because λ _k is the sought node.

It is particularly advantageous that the concurrent evaluation of an M-node of the M-tree lasts only insignificantly longer than the evaluation of a single node of the original binary tree. Furthermore, it is particularly advantageous that the time necessary for the evaluation of an m-node does not increase with increasing m, as long as the evaluation of the m hyperplane equations of the m-node can be implemented concurrently. Together with the reduction of the height of the M-tree compared to the original binary tree, the concurrent evaluation of the m-nodes allows a faster evaluation of the control law by the method according to the invention. It can thereby high sampling rates are well above 50 MHz, can be achieved, which may be necessary for an application for fast technical processes. The use of the control method according to the invention in portable devices is conceivable.

Furthermore, it is advantageous that the evaluation of the m-node takes place on an arithmetic logic unit. Thus, the implementation can be carried out with the aid of a digital circuit, which can be designed without microprocessor so microprocessor-free. The degree of concurrency is limited only by the resources (logical blocks, multipliers, etc.) available for the circuit. Furthermore, it should be noted that the achieved speed increase is maintained even if the performance of microprocessors will increase in the future because the resources available on FPGA (field programmable logic arrays) or PLD (programmable logic devices), and the complexity of application specific integrated circuits (ASIC) will also increase. Furthermore, because of the simplicity of the circuit, power consumption can be reduced over previous microprocessor-based solutions.

durch wenigstens zwei Multipliziereinheiten simultan bzw. nebenläufig evaluierbar sind, wobei die Produkte

mit wenigstens einer Addierereinheit in einem ersten Schaltungsblock zu einer Summe

aufsummierbar ist und anschließend die Summe

mit in einer Größe

in einem zweiten Schaltungsblock vergleichbar ist, wobei der erste Schaltungsblock und der zweite Schaltungsblock zu einem dritten Schaltungsblock zusammenfassbar sind.The object of the invention is also achieved by a device on which the control method is operated, which for the evaluation of hyperplanes products of real numbers

can be simultaneously or concurrently evaluated by at least two multiplier units, the products

with at least one adder unit in a first circuit block to a sum

is summable and then the sum

with in one size

in a second circuit block is comparable, wherein the first circuit block and the second circuit block are summarized to form a third circuit block.

It is particularly advantageous that the aforementioned circuit blocks can be arranged on a semiconductor device. The semiconductor device may be an ASIC or programmable logic device, wherein the programmable logic device may be in the form of a PLD (programmable logic device) or in the form of an FGPA (Field Programmable Array). The programmable logic device may accordingly be a programmable arithmetic logic unit. With programmable logic devices advantageously the digital circuit for the technical process to be controlled or for the machine to be controlled can be tailored. Programmable logic devices such as FPGAs can provide a large number of dedicated integer multiplication circuits which can be efficiently used to carry out the concurrent multiplications.

Furthermore, it has proven to be advantageous that the digital circuit design for the programmable logic device by a hardware description language, preferably by VHDL or Verilog done. It can be ensured that the implementation is not limited to FPGA, so that the circuit design to be mapped can also be used by a hardware description language such as VHDL to map the design of a hardwired integrated circuit.

Further measures and advantages of the invention will become apparent from the claims, the following description and the drawings. Likewise, the disclosed features of the device according to the invention also apply to the method according to the invention and vice versa. In the drawings, the invention is shown in several embodiments. The features mentioned in the claims and in the description may each be essential to the invention individually or in any desired combination.

Show it:

1 a schematic view of a rectangular state space region with n _p = 8 polyhedra,

2 a schematic view of a binary tree based on 1 .

3 a schematic view of a height-balanced binary tree with an m-node of order m = 7,

4 a schematic view of an M-tree with m-node of order m = 4,

5 a schematic view of the circuit for the concurrent evaluation of a scalar product with n multiplications,

6 a schematic view of 5 in a compact presentation,

7 3 is a schematic view of a comparison block which is used to calculate π _{S, j} (x),

8th a schematic view for the calculation of π _{S, j} ,

9 a schematic view of a concurrent evaluation of π _{S, j} ,

10 a simplified notation of 9 .

11 a schematic view of a comparison block,

12 a schematic view of a comparison block with m + 1 concurrent circuits,

13 a simplified notation of 12 .

14 a schematic view of a circuit with n _x + 1 multipliers,

15 a simplified notation of 14

16 a schematic view of a circuit for calculating u (x),

17 a simplified notation of 16 .

18 a schematic view of the steps of an automatic hardware design synthesis,

19 a schematic view of a binary tree and

20 a schematic view of the M-tree, which stands for m = 2 from the in 19 shown binary tree yields.

In the 1 Fig. 12 shows an example of a subdivision of a rectangular state space region into n _p = 8 polyhedra P ₁ , ..., P ₈ . This is a binary tree 14 clamped. In this binary tree 14 Each internal node of the binary tree represents a hyperplane 12 h _i (x), and each external node corresponds to a polyhedron 16 P _i . In doing so, the search for a polyhedron 16 P _i , in which the current state x of the process to be controlled is located, as a search within the binary tree 14 be performed. It starts with the root node in each internal node of the binary tree 14 branched into the left child node when h _j (x) ≤ 0 for the hyperplane 12 h _j , which corresponds to these nodes and branches to the right child node if h _j (x)> 0. It can be the binary tree 14 be derived from an affine control law of the form (7) with known methods. This procedure can be done in a height-balanced binary tree 14 result if such a tree exists.

In the 2 is the binary tree 14 out 1 Each internal node is represented by a filled circle, which is a hyperplane 12 h _i (x) is assigned and each external node is represented by an open circle which is a polyhedron 16 represents.

In the 3 an example for the formation of an m-node is shown. 3a shows an example of a left-oriented height-balanced binary tree 14 , In 3b become m = 7 internal nodes of the binary tree 14 summarized in a subtree. The internal nodes are selected according to a breadth-first search method as explained in Definition 1. The 3c and 3d show like a subtree to an m-node 18 is summarized. It is pointed out that an m-node or an m-sub-tree of a height-balanced left-oriented binary tree 14 does not have to start at the root node of the binary tree. Because every sub-tree of the height-balanced left-oriented binary tree 14 itself a height-oriented left-oriented binary tree 14 algorithm 1 can be applied to any subtree of the binary tree originating at an internal node.

In the 4 is the algorithm 2 and the resulting transformed tree 30 shown. In this transformed tree 30 that's from m-node 18 exists, you can now between final m-node 18 and non-terminating m-node 18 of the transformed tree 30 differ.

Description of an exemplary implementation with FPGA

wobei i = 1, ..., m ist, ausgewertet wird. Jede der m Gleichungen (32) beinhaltet n Produkte mit jeweils zwei reellen Faktoren und m Additionen von m + 1 reellen Summanden. Da die Multiplikationen für ein beliebiges aber festes i unabhängig voneinander sind, können sie simultan in n nebenläufigen Schaltungen ausgeführt werden.In step 1 of Algorithm 3, m hyperplane equations (6) must be evaluated by taking an equation of the form for each hyperplane

where i = 1, ..., m is evaluated. Each of the m equations (32) contains n products with two real factors and m additions of m + 1 real summands. Since the multiplications for any but fixed i are independent of each other, they can be performed simultaneously in n concurrent circuits.

mit der in der 5 beschriebenen Schaltung ermittelt worden sind, kann die Variable Π aus Schritt 1 des Algorithmus 3 ermittelt werden.In the 5 and 6 It is shown how simultaneous multiplications can be performed in concurrent circuits. So z. B. the MULI switching units 40 , as in 5 shown, implemented with 18-bit integer multipliers, which are present on typical representatives of the FPGA type of an arithmetic logic unit. In 6 is a compact representation of a first circuit block 44 of the 5 shown. Alternatively, the multipliers may be implemented with configurable logic blocks (CLBs) and look up tables (LUTs) present on typical FPGAs. Real numbers can be z. B. be represented by fixed point numbers in two's complement. If the expressions

with the in the 5 can be determined, the variable Π from step 1 of the algorithm 3 can be determined.

wie in Schritt 1 des Algorithmus 3 definiert, zu erhalten. Dies wird in 9 gezeigt. Eine kompakte Darstellung der gleichen Schaltung ist in 10 dargestellt. Es sei darauf hingewiesen, dass diese Schaltung die nebenläufige Evaluierung von m·n Multiplikationen von zwei Festkommazahlen beinhaltet, da m Blöcke

wie in 9 dargestellt, existieren und jeder dieser Blöcke eine dieser Schaltungen mit n MULT Blöcke 40 beinhaltet, wie in 5 dargestellt.In the 7 is a second circuit block 46 to compare two real numbers of the type smaller-or-equal. The combination of the comparison block with the circuit 6 results in a third circuit block 48 , as in 8th which provides π _{S, ij} as defined in step 1 of Algorithm 3. Finally, m blocks of the type as in 8th shown to be executed simultaneously

as defined in step 1 of algorithm 3. This will be in 9 shown. A compact representation of the same circuit is in 10 shown. It should be noted that this circuit involves the concurrent evaluation of m * n multiplications of two fixed-point numbers, since m blocks

as in 9 , and each of these blocks is one of these circuits with n MULT blocks 40 includes, as in 5 shown.

For an arbitrary but fixed value k ∈ {1, ..., m + 1}, the steps 2.1 to 2.3 of the algorithm 3 can be implemented as in 11 described. Since σ _S , as defined in Definition 4, is not dependent on x, σ _S can be calculated in advance as described above, ie before the startup of the control process. In particular, since the elements of σ _{S, 1} (k), ..., σ _{S, m} (k) can be determined in advance for σ _S, l (k) = - 1, the map σ ' _S , as in Definition 5 defined before commissioning of the regulatory procedure. This will be in 11 illustrated, where σ _S (k) and π _S (x) in the circuit block 54 can flow and the operation within the block with σ _'S (k) and π' _S (x) can be performed. The logical operation, as in 11 is executed, is to understand bitwise. The external nodes λ _{k of} the m sub-tree S are identified by the concurrent comparisons as in FIG 12 shown selected when β _k = 1. If more than one such k exists, each resulting value is a valid result.

12 shows as m + 1 blocks of the type as in 11 shown, can be executed concurrently. This corresponds to the execution of steps 2.1 to 2.3 of algorithm 3 for all k = 1,..., M + 1. 13 shows a short notation for the circuit block 58 from 12 , The node λ _k resulting from the steps described corresponds to either an external node of the binary tree T or an internal node. In the first case became a polyhedron 16 P _i found applies to the x ∈ P _i. In this case, the circuit must evaluate the law of control according to equation (7), which is valid on P _i . This step is detailed below. In the case where λ _{k is} an internal node, this node is the root node of m sub-tree or m-node, in which the search for the valid polyhedron 16 will continue.

Eine kompakte Darstellung des calcu-Blocks ist in 16 definiert und in 17 dargestellt.Is a polyhedron 16 P _i has been found such that x ∈ P _i , then u (x) can be determined with a suitable circuit according to equation (7). The evaluation of equation (7), like the evaluation of equation (32), requires the calculation of products and sums of real numbers in Fixed-point representation. The law of control can therefore be evaluated by a circuit similar to that for the hyperplanes 12 is. 14 shows a circuit block 64 , which performs n multiplications of two real numbers in fixed-point representation and n additions of n + 1 real numbers in fixed-point representation. These operations yield a component u _j (x) of the desired control law u (x). 15 shows the shorthand for the circuit of 14 , By combination of m circuits of the type as in 14 and 15 shown results in a circuit as in 16 shown for the calculation of

A compact representation of the calcu block is in 16 defined and in 17 shown.

The proposed circuit architecture may be suitably implemented on a programmable arithmetic logic unit. While the circuit blocks described can, in principle, be constructed by hand, automatic hardware synthesis is indispensable in order to be able to carry out the design of the device required for regulation without errors. 18 gives an overview of an automatic design procedure, which is used here. The balanced binary tree can be generated with existing tools in the case of an affine law of rules, which is an EMPC law of rules. This step corresponds to the left block in 18 , The second and third block in 18 Perform manipulations on the binary tree that transform the binary tree into the searched M-tree. The M-tree is then automatically translated into a circuit description, as in the right-hand block in 18 shown. This circuit description may be used to fabricate an ASIC (application specific integrated circuit) or to program a programmable arithmetic logic unit, e.g. As a PLD (programmable logic device) or FPGA (field programmable gate array) can be used. The programming of programmable arithmetic logic circuits can be performed with existing commercial hardware development tools.

By way of example, the method according to the invention and the device according to the invention for implementing a control law were used for a typical test case. In this case, a FPGA (field programmable gate array) is used, in this case a Vertex 6 XC6VSX475T, which is manufactured by the company Xilinx. Hardware programming is done with the Xilinx design tool ISE Webpack. Circuit designs are mapped in VHDL. An FPGA has been chosen because current FPGAs provide a large number of dedicated circuits for integer multiplication, which are efficient for performing the concurrent multiplications, as in 5 and 14 represented, can be used. The Vertex FPGA (Virtex XC6VSX475T Board) has such multipliers in 2016. If more concurrent multiplications have to be performed than multipliers are available, further multipliers can be formed from configurable logic blocks (CLBs) and look up tables (LUTs), which are available on the FPGA.

It should be emphasized that the implementation does not rely on FPGA, but that the depicted circuit design can also be used by a hardware description language such as VHDL to produce an ASIC (Application Specific Integrated Circuit). Furthermore, the implementation is not limited to the Xilinx FPGA and / or the Xilinx design tool. Furthermore, it is possible for VHDL to be replaced by another hardware description language, such as VHDL. Verilog.

gewählt werden und wobei n = 2, m = 1, und p = 1 ist. Das System ist den Eingangsbeschränkungen – 1 ≤ u(t) ≤ 1 unterworfen und die Horizonte der MPC werden auf 2 gesetzt. Die Lösung des EMPC-Optimierungsproblems ergibt n_P = 7 Polyeder P₁, ..., P₇), der Form (5) und n_h = 13 Hyperebenen 12 h₁(x), ..., h₁₃(x) der Form (6). Dieses Ergebnis kann durch einen höhenbalancierten binären Baum repräsentiert werden mit N_int = 13 internen Knoten und 14 externen Knoten, der in 19 dargestellt ist.In the following, the method according to the invention is applied to a time-invariant linear time-discrete system of the form of equation (1), the matrices to

and where n = 2, m = 1, and p = 1. The system is subject to the input constraints - 1 ≤ u (t) ≤ 1 and the MPC horizons are set to 2. The solution of the EMPC optimization problem yields n _P = 7 polyhedra P ₁ , ..., P ₇ ), the form (5) and n _h = 13 hyperplanes 12 h ₁ (x), ..., h ₁₃ (x) of the form (6). This result can be represented by a height-balanced binary tree with N _int = 13 internal nodes and 14 external nodes included in 19 is shown.

When applying Algorithm 2 to the binary tree 19 for m = 2 you get an m-tree like in 20 shown. This tree and the corresponding evaluation of the EMPC law in the form (7) can be implemented in a circuit on a Virtex 6 FPGA board. The resulting circuit was successfully tested by computing the randomized state control law x and comparing the results to the results obtained with the original EMPC control law, which was independently implemented in a commercial software tool for purposes of comparison.

Claims (13)

A control method for controlling a technical process based on a previously defined explicit control law, which describes one or more control variables or manipulated variables of the technical process as a function of one or more state variables of the technical process, wherein the control law on polyhedra 16 piecewise defined, the polyhedra 16 through at least two hyperplanes 12 be described and the hyperebenes 12 in a binary tree 14 arrange for the evaluation of the tax law, each hyperplane 12 an internal node in the binary tree 14 represents and the binary tree 14 in at least one finite non-empty polyhedron 16 ends, where the polyhedron 16 an external node of the binary tree 14 is, characterized in that at least two hyperplanes 12 to an internal multiple node 18 be summarized, each internal multiple node 18 an internal node of a transformed tree 30 forms and the transformed tree 30 one opposite the binary tree 14 having reduced height. Control method according to claim 1, characterized gekennzeichet that the binary tree 14 into a left-oriented binary tree 14 is converted, with internal multiple nodes 18 be formed by internal nodes 12 of the binary tree 14 summarized at one level until no further internal nodes 12 exist at the same level and then with the leftmost internal node 12 the next level of the binary tree 14 is continued. Control method according to claim 1 or 2, characterized in that the previously defined explicit control law results as a solution, in particular explicit solution of a problem of a model predictive control results. Control method according to claim 1 to 3, characterized in that the evaluation of the internal multiple node 18 the period is limited and predictable, the period not depending on the state of the controlled technical process or technical system. Control method according to claim 4, characterized in that the period for evaluating the internal multiple node 18 of the transformed tree 30 in the range of the period that is responsible for the evaluation of an internal node 12 of the binary tree 14 is necessary. Control method according to claim 4 or 5, characterized in that the period for the evaluation of an internal multiple node 18 regardless of the number of internal multiple nodes 18 contained hyperplanes 12 is. Control method according to one of the preceding claims, characterized in that the height of the transformed tree 30 is limited and the height of the transformed tree 30 less than or equal to the height of the binary tree 14 is. Device on which a control method according to claim 1 to 7 implemented, characterized in that for the evaluation of hyperplanes 12 Products of real numbers

by at least two multiplier units 40 can be evaluated simultaneously or concurrently, the products

with at least one adder unit 42 in a first circuit block 44 to a sum

is summable and then the sum

with in one size

in a second circuit block 46 is comparable, wherein the first circuit block 44 and the second circuit block 46 to a third circuit block 48 are summarized. Device according to claim 8, characterized in that all hyperplanes 12 an internal multiple node 18 through the circuit block 48 are simultaneously evaluable and then in a circuit block 52 with one unit 50 to a result

be summarized. Device according to claim 8 or 9, characterized in that the search for the control law valid for a given state vector x is executable by the result Π of the circuit block 52 is compared by logical operations with pre-calculated vectors σ _S (k), these comparisons being made by concurrent circuit blocks 54 within a circuit block 58 are feasible, which can be determined by these comparisons, in which child of the internal multiple node 18 within the transformed tree 30 is branched, wherein the child searched for another internal multiple node 18 of the transformed tree 30 or the child you are looking for is an external node 16 of the transformed tree 30 is that represents a polyhedron. Device according to one of claims 8 to 10, characterized in that corresponding to the evaluation of a hyperplane 12 the products of the affine rule of law, which on the polyhedron 16 apply, by concurrent multiplier units 60 are simultaneously solvable and then in one or more adder units 62 in a circuit block 64 to one of the n _u components u _i (x) of a control law u (x) are added, these components then in a circuit block 68 with the unit 66 to the control law u (x) are joined together. Device according to one of claims 8 to 11, characterized in that the circuit blocks 44 . 46 . 48 . 52 . 54 . 58 . 64 and or 68 can be arranged on a semiconductor device. A device according to claim 12, characterized in that the semiconductor device is an application specific integrated circuit (ASIC) or the semiconductor device is a programmable logic device, wherein the logic device is a programmable logic device (PLD) or a field programmable gate array (FPGA) and the Logic block with a hardware description language such as VHDL or Verilog is programmable.

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