DE102010031290B4 - Circuit device with integrator circuits - Google Patents

Abstract

Circuit device (6) which has at least two integrator circuits (20, 22, 24) which are clocked successively in successive clock phases (T1, T2, T3), each integrator circuit (20, 22, 24) having an operational amplifier (8th ) and further components (Cin1; Cin2; Cin3; Cfb1; Cfb2; Cfb3; Ccomp; SW1; SW2; SW3; SW4), characterized in that at least one operational amplifier (8) in at least two integrator circuits (20th , 22, 24) is used jointly, the plurality of integrator circuits (20, 22, 24) each consisting entirely of the common operational amplifier (8) and an SC structure of capacitances (Cin1; Cin2; Cin3; Cfb1; Cfb2; Cfb3 ; Ccomp) and switches (SW1; SW2; SW3; SW4), the SC structure having:- an input SC structure (10) with switches (SW1, SW2_3), at least one input capacitance (Cin1) and input terminals (19a, 19b, 19c, 19d) for an input voltage (Uin) and ei ne reference voltage (Vref1),- a feedback SC structure (12) with feedback capacitances (Cfb1, Cfb2, Cfb3), input capacitances (Cin2, Cin3) and switches (SW1, SW2, SW3), and- an output -SC structure (14) with at least one comparison capacitance (Ccomp) and switches (SW1, SW2, SW3), wherein the comparison capacitances (Ccomp) of an output SC structure (14) with its two connections each- on the one hand via a second switch (SW2) to one of the two feedback parts (12a, 12b) and a connection of a quantizer (16), and- on the other hand via a first switch (SW1) to an input connection (19a, 19b) of input voltage (Uin) are connected.

Description

State of the art

The invention relates to a circuit device with a plurality of successively clocked integrator circuits, in which case the circuit device can in particular be a delta-sigma converter.

Delta-sigma converters are used in particular for AD (analog-to-digital) conversion and essentially have integrators and quantizers. Quantizers are usually implemented with latched comparators and are known as such; their power consumption is relatively low. A large part of the power consumption of delta-sigma converters is thus caused by the integrators.

The integrators are usually each designed by a circuit with an operational amplifier, switches and capacitors; Such circuits are also called SC (switch, capacity) structures and, in particular, manage without resistors. The switches can B. be designed as MOSFETS and are used in particular to set the charging cycles of the capacitors or capacities accordingly.

The document U.S. 5,870,048 A describes an oversampled sigma-delta modulator.

The font U.S. 2008/0 258 951 A1 discloses a hybrid delta-sigma/SAR analog-to-digital converter and methods of using such.

In 1 a simple form of an SC integrator 1 is shown, with an operational amplifier 2, an input capacitance Cin, a feedback capacitance Cfb in the feedback path from the output 2c to the negative input 2a of the operational amplifier 2, and switches SW1, SW2, SW3 and SW4, with which the different cycles are controlled, generally by clock phases of a clock cycle. During a first clock phase T1, the switches SW1 and SW3 are closed, so that the input capacitance Cin is charged to an input voltage Uin or Uin(+) that is present. The operational amplifier 2 drives no output load in this clock phase T1. However, the amplifier structures usually used in delta-sigma converters also result in a continuous transverse current through the operational amplifier 2 in this clock phase T1, so that there is power consumption.

In the subsequent clock phase T2, SW2 and SW4 are closed, operational amplifier 2 becoming active. Through a charge exchange, the charge previously transferred to the input capacitance Cin is transferred to the feedback capacitance (feedback capacitance) Cfb; For this purpose, the operational amplifier 2 amplifies the voltage occurring at its input terminals 2a, 2b, as a result of which a current flow occurs at the output 2c of the operational amplifier 2.

At the in 2 conventional integrator 3 shown, the operational amplifier 2 is fed back in the first clock phase T1 via the switch SW3. The consequence of this is that the voltage occurring at the input terminals 2a, 2b of the operational amplifier 2 corresponds to the offset voltage. In this structure, the input capacitance Cin is not charged against ground, but against the offset voltage. In the subsequent clock phase, a charge is then transported to the feedback capacitance Cfb. The advantage of the structure 2 , which is also referred to as a correlated double sampling or autozeroing structure, is that the offset of the amplifier is compensated here. This or a similar structure is often used for the first integrator of a delta-sigma converter in order to minimize the offset of the system.

In the case of multi-stage operational amplifiers, in particular MASH (multi-stage noise shaping) structures are used, which are significantly more stable than simple single-loop structures. Thus, a third-order delta-sigma converter 5 as in 3 shown schematically z. B. consist of three integrators 5-1, 5-2 and 5-3, an adder 5-4 and two quantizers 5-5 and 5-6, which emit output signals O1 and O2, the integrators 5-1, 5- 2 and 5-3 each have a suitably dimensioned operational amplifier 4-1, 4-2, 4-3 and an SC structure, not shown here, and the adder can be constructed entirely as an SC structure without an operational amplifier or any other active component.

The three integrators 5-1, 5-2, 5-3 can then be clocked successively. Here, the first integrator 5-1 z. B. an offset compensation and the two following integrators 5-2, 5-3 no offset compensation. Since the accuracy essentially depends on the noise of the first integrator 5-1, this has the largest capacitance values. This is because noise power is inversely proportional to capacitance. The noise of the second and third integrators 5-2 and 5-3 is shifted into the upper frequency ranges by the noise shaping behavior of the converter and only insignificantly influences the performance or power properties of the low-pass converter.

Due to the different load capacitances, in such a three-stage delta-sigma converter 5 in MASH structure, the first operational amplifier 4-1 is usually dimensioned larger than the operational amplifiers 4-2, 4-3 of the second and third stage. Thus e.g. B. the first amplifier have a cross current of 600 uA and the other two get along with 200 uA.

A disadvantage of such delta-sigma converters is their energy consumption, in particular due to the operational amplifiers 4-1, 4-2, 4-3 used in the integrators.

Disclosure of Invention

According to the invention, in a circuit device with a plurality of successively clocked integrators, at least one operational amplifier is multiply, i. H. used for at least two integrators. The circuit device can in particular be a multi-stage delta-sigma converter device.

The invention is based on the idea that in a higher-order delta-sigma converter, the integrators of the successive stages are not or not necessarily used simultaneously, but the operational amplifiers in the clock phases in which they are not actively working or for serve to drive an output load, yet consume a non-negligible cross-current, which determines the overall consumption of the circuit.

According to the invention, it is recognized that multiple use of an operational amplifier is possible through suitable shading. Suitable switches are to be provided for this; in the case of a delta-sigma converter device with an SC structure, switches are already provided which are switched in the corresponding clock phases; the additional outlay according to the invention therefore lies at most or essentially in additional switches in order to connect the inputs and outputs of the operational amplifier to the relevant structural parts in the corresponding clock phase.

It has been shown that with such solutions according to the invention, the actual additional expense for additional switches is low and multiple uses are possible, so that not only at least one operational amplifier can be saved in terms of hardware, but possibly also further components of the respective SC structures.

Thus, according to the invention, not only can energy consumption be reduced, but also significant savings in terms of hardware can be achieved, and the hardware costs can thus be reduced and integration increased.

According to the invention, an operational amplifier for more than two integrators, z. B. be used for three or all integrators of a delta-sigma converter. Thus e.g. B. a third-order delta-sigma converter can be equipped with only one operational amplifier and suitable shading; in the operational amplifier are then z. B. several feedback capacitors are connected in parallel and are suitably switched on or off by appropriate switches in the respective clock phases.

According to the invention, the time for the conversion process is preferably divided into three time segments or clock phases. The length of the individual clock phases or clock phases can be determined from the ratio of the length of the clock phase to be calculated to the total time of all clock phases.

According to the invention, z. B. a common quantizer can be used instead of two quantizers used in conventional 2-1 MASH structures. For this purpose, suitable control signals for controlling one quantizer can be input at the end of the corresponding clock phases.

character list

• 1 shows how a conventional SC integrator works;
• 2 shows the operation of a conventional SC integrator with offset compensation;
• 3 the basic, highly schematic design of a circuit structure of a conventional third-order delta-sigma converter;
• 4 a DSC circuit structure of a third-order delta-sigma converter according to the invention;
• 5 the timing scheme of the SC structure 4 ;
• 6 the relevant structure 4 during clock phase 1;
• 7 the relevant structure 4 during clock phase 2;
• 8th the relevant structure 4 during the clock phase 3.

Description of the embodiments

To explain the delta-sigma converter according to the invention, reference is also expressly made to that already described in connection with the prior art functionality of the circuits 1 until 3 Reference is made, which is thus part of the disclosure of the invention.

In the drawings, the same or similar reference symbols describe the same or similar features or the same or similar functions.

4 describes a delta-sigma converter 6 according to the invention, which has only a single operational amplifier, here an OTA (operational transconductance amplifier) 8, which is designed to be fully differential or double-ended, ie with a plus input 8a and a minus input 8b , and a minus output 8c and a plus output 8d. The delta-sigma converter 6 corresponds functionally to the schematic delta-sigma converter 5 from FIG 3 , but it only requires a single operational amplifier, namely the OTA 8, and a suitable SC structure, which can be functionally subdivided into an input SC structure 10, a middle SC structure or feedback structure formed in the feedback path of the OTA 8 SC structure 12 and an output SC structure 14 to which a quantizer 16 is connected, which functionally consists of the quantizer stages 5-5 and 5-6 3 is equivalent to; however, only a single quantizer 16 is required in this embodiment of the invention. In principle, however, two or more quantizers can also be used according to the invention.

The structure of the delta-sigma converter 6 is first described in more detail below 4 described and then explained the functionality in the clock phases T1, T2, T3.

The input SC structure 10 has input connections 19a, 19b for the input voltage Uin (+) and Uin (-), both polarities being permissible at both input connections 19a, 19b, and input connections 19c and 19d for the positive and negative first reference voltage Vref, i.e. thus connections for +Vref1 and -Vref1. Ground connections are marked in the usual way. Furthermore, switches SW1 are provided for activation with the clock signal T1, SW2 for activation with the control signal T2, and SW3 for activation with the clock signal T3, each of these switches closing at the HIGH level of the activating clock signal T1, T2, T3. Furthermore, switches SW2_3 are provided for activation with both the clock signal T2 and T3, which therefore close at T2 HIGH OR T3 HIGH. For the sake of clarity, some of the switches are only designated in the usual way by the closing clock signal.

The middle SC structure or feedback SC structure 12 has, in principle, a parallel connection of some capacitances, which can optionally be connected by suitable switches to the input terminals 8a and 8b of the OTA 8, the output terminals 8c, 8d of the OTA 8, or to ground or a reference voltage can be closed in order to suitably set the capacitances (capacitors) to a potential or to charge them with respect to ground or a reference voltage.

In the feedback SC structure 12, in a symmetrical manner (in 4 top and bottom) parallel circuits of feedback branches provided. Between the plus input 8a and the minus output 8c of the OTA 8, these form a first (in 4 upper) partial structure 12a, and between the minus input 8b and the plus output 8d a second (in 4 lower ) partial structure 12b, the formation of which is symmetrical, with the top path SW3 being connected to -/+ Vref2 and the bottom path SW3 being connected to +/- Vref2.

• - wie in 4 gezeigt ganz trennen, oder
• - zum Aufladen an ein Bezugspotential, d.h. Masse oder +Vref2 oder -Vref2 legen, oder
• - an einen Eingang 8a oder 8b oder einen Ausgang 8c oder 8d des OTA 8 und somit auch an eine parallel geschaltete Rückkopplungskapazität Cfb1, Cfb2, Cfb3 legen.

Here, the top and bottom of the inner three feedback branches each have a series connection of a feedback capacitance with a switch, ie Cfb1 and SW1, Cfb 2 and SW2, Cfb 3 and SW3, in a basically similar functional manner as in FIG 2 . The outer two feedback branches are formed at the top and bottom by a second feedback capacitance Cin2 and a third feedback capacitance Cin3 with switches SW1, SW2 and SW3, the switches SW1, SW2 and SW3 connecting the two terminals of each input capacitance, respectively

• - as in 4 shown entirely separate, or
• - connect to a reference potential for charging, ie ground or +Vref2 or -Vref2, or
• - Connect to an input 8a or 8b or an output 8c or 8d of the OTA 8 and thus also to a feedback capacitance Cfb1, Cfb2, Cfb3 connected in parallel.

The output SC structure 14 is in symmetrical design (in 4 above and below) connected to the outputs 8c and 8d and in turn has switches SW1, SW2, SW3, which are closed accordingly in the clock phases T1, T2 or T3, and comparison capacitances Ccomp, the upper comparison capacitance Ccomp being connected via a switch SW1 is connected to Uin(-) and the lower comparison capacitance Ccomp is connected to Uin(+) via a switch SW1. The quantizer 16 is controlled by control signals tad2 and tad3 since it is used twice in this embodiment. It will output an output signal Sa as a bit stream.

5 shows the clock scheme according to the invention with three alternating clock phases T1, T2 and T3, furthermore the clock phase T2_3, the content represents a superposition of T2 and T3: T2_3 is HIGH when T2 or T3 is HIGH. T2_3 thus corresponds to an OR circuit or two parallel switches to which T2 or T3 is applied.

According to the invention, the control signals tad2 and tad3 are used to control the quantizer 16, with tad2 corresponding to a control signal or "HIGH" level at the end of the clock phase T2 and tad3 corresponding to a control signal or "HIGH" level at the end of the clock phase T3, as below in the description of the functionality of the 4 is explained in more detail. The individual clock phases are described with additional representation in the following 6 until 8th , which consist of the relevant structures 4 show during the respective clock phase.

Clock phase T1:

During T1 = HIGH, an in 6 first integrator 20 shown by means of the OTA 8 and the components of the SC structures 10, 12 and 14 switched on by T1=HIGH. Thus, in this phase the input voltage Uin is applied to the connections 19a, 19b, ie Uin(+) and Uin(- ) at 19a and 19b, as well as the reference voltage between the terminals 19c, 19d, in order to achieve a charge exchange from Cin1 to the first feedback capacitance Cfb1. Furthermore, the input capacitance Cin2 for the second integrator to be formed subsequently, as well as the comparison capacitance Ccomp, are charged. Ccomp is required in order to form a sum consisting of the input voltage Uin, the voltage of the first integrator 20 and also, as will be explained below, that of the second integrator, in order to then send it to the quantizer 16.

Clock phase T2:

7 shows the elements active here. In the second period of time T2=HIGH, the integration of the second integrator 22, which is formed by the OTA 8 together with the connected components, takes place. Since the switches SW1 are open at the output of the input SC structure 10, ie before the inputs 8a and 8b of the OTA 8, in the second clock phase T2 and third clock phase T3, an integrator 22 and 24 respectively without the input SC - Structure 10 formed.

In T2, the capacitance Cin2 previously charged in the clock phase T1 is now connected to ground via the switch SW2, which is closed in T2, and is thus integrated onto the feedback capacitance Cfb2. The resulting output voltage is given to Ccomp. The resulting voltage at the inputs of the comparators of the quantizer 16 is now used to compare it with a reference voltage. After activation of the quantizer 16 bzw. of its comparators through tad2 the analog voltage is digitized. This digital data is then output as an output signal Sa1 to a digital decimation filter (not shown here), which is known as such in delta-sigma converters. In addition, during the clock phase T1, a voltage proportional thereto is fed back to the input of the first integrator, ie thus to the voltage Vref1 which is present at the connections 19c, 19d. According to the invention, it is recognized that this feedback can take place on the first integrator, although the first integrator 20 in 7 is not trained.

Clock phase T3:

The following is the clock phase T3 = HIGH, in accordance with 8th the third integrator 24 is formed. The previously charged input capacitance Cin3 is additionally charged with the reference voltage Vref2 and used for a charge exchange on the feedback capacitance Cfb3. At the end of the third clock phase T3, the quantizer 16 is again activated via the control signal tad3 in order to output the digital output signal Sa2. A voltage Vref2 proportional thereto is fed back during the next clock phase T3.

Ti

i= 1, 2 oder 3, Länge der zu berechnenden Taktphase T1, T2, T3

Tges

Gesamtzeit aller Taktphasen, d. h. T_ges = T1 + T2 + T3

Cges

Summe aller Lastkapazitäten

Ci,last

Lastkapazität der zu berechnenden Taktphase.

The length of the individual clock phases can be B. can be calculated with the following formula: $$\text{Ti}=\left({\text{T}}_{\text{total}}/{\text{C}}_{\text{total}}\right)\text{ci}{,}_{\text{load}}\text{With}$$

Ti

i= 1, 2 or 3, length of the clock phase T1, T2, T3 to be calculated

daily

Total time of all clock phases, ie T _tot = T1 + T2 + T3

ctotal

Sum of all load capacities

Ci, last

Load capacitance of the clock phase to be calculated.

The larger the capacity Ci, _last , the more time is required for the reloading process. has e.g. B. the capacity of the first integrator 20 from 5 If the value is 3.0 pF, but that of the second and third integrators 22, 24 is only 1.0 pF each, then 60% of the total time Tges is required for the first clock phase T1. The duration of T2 and T3 is sufficiently dimensioned with 20% each.

The cycle then starts again from the beginning in clock phase T1. If additional offset compensation is required, the additional ones known per se to those skilled in the art can be used for this purpose certain measures or procedures are used.

In T2 and T3, a series connection of a capacitance with a feedback capacitance Cfb2 or Cfb3 always means a charge transfer to this feedback capacitance Cfb2 or Cfb3, which therefore always corresponds to an integration on this feedback capacitance Cfb2 or Cfb3. However, there is no additional charging at the output in T3, as is the case in T2.

In 4 an embodiment is shown in which an operational amplifier 8 is used in triplicate. In principle, further embodiments of circuits with several integrators as delta-sigma converters are also possible. So e.g. For example, other AD converters also have several successively clocked integrators, and according to the invention use at least one integrator several times.

Claims (8)

Circuit device (6) which has at least two integrator circuits (20, 22, 24) which are clocked successively in successive clock phases (T1, T2, T3), each integrator circuit (20, 22, 24) having an operational amplifier (8th ) and further components (Cin1; Cin2; Cin3; Cfb1; Cfb2; Cfb3; Ccomp; SW1; SW2; SW3; SW4), characterized in that at least one operational amplifier (8) in at least two integrator circuits clocked in different clock phases ( 20, 22, 24) is used together, the plurality of integrator circuits (20, 22, 24) each consisting entirely of the common operational amplifier (8) and an SC structure of capacitances (Cin1; Cin2; Cin3; Cfb1; Cfb2; Cfb3; Ccomp) and switches (SW1; SW2; SW3; SW4), the SC structure having: - an input SC structure (10) with switches (SW1, SW2_3), at least one input capacitance (Cin1 ) and input terminals (19a, 19b, 19c, 19d) for an input voltage (Uin) and nd a reference voltage (Vref1), - a feedback SC structure (12) with feedback capacitances (Cfb1, Cfb2, Cfb3), input capacitances (Cin2, Cin3) and switches (SW1, SW2, SW3), and - a Output SC structure (14) with at least one comparison capacitance (Ccomp) and switches (SW1, SW2, SW3), wherein the comparison capacitances (Ccomp) of an output SC structure (14) with its two terminals, respectively - for one via a second switch (SW2) to one of the two feedback parts (12a, 12b) and a connection of a quantizer (16), and - the other via a first switch (SW1) to an input connection (19a, 19b) connected to the input voltage (Uin). Circuit device according to one of the preceding claims, characterized in that it has switches (SW1, SW2, SW3, SW2_3) which are closed in different clock phases (T1, T2, T3, T2_3) to form the at least two integrator circuits (20 , 22, 24). Circuit device according to one of the preceding claims, characterized in that it is a delta-sigma converter device (6) and has at least one quantizer (16) with comparator circuits connected to the integrator circuits (20, 22, 24). circuit device claim 3 , characterized in that it has at least three integrator circuits (20, 22, 24) which share the common operational amplifier (8) and are connected in successive successive clock phases (T1, T2, T3), the first integrator circuit Circuit (20) for integrating an applied input voltage (Uin) and at least one reference voltage (Vref1) is provided, the second integrator circuit (22) for integration or superimposition in a feedback capacitance (Cfb2) and the third integrator circuit (24) for integrating a reference voltage (Vref2) onto a feedback capacitance (Cfb3), at least the last integrator circuit (24) being provided for outputting an analog signal to the quantizer (16). circuit device claim 4 , characterized in that it is third-order and has exactly three integrator circuits (20, 22, 24) which are clocked in successive, cyclically repeating three clock phases (T1, T2, T3), with exactly one quantizer (16) which is activated at the end of the second clock phase (T2) and at the end of the third clock phase (T3) by control signals (tad2, tad3) in order to output digital output signals (Sa1, Sa2). Circuit device according to one of the preceding claims, characterized in that each integrator circuit (20, 22, 24) has in its feedback path at least one series circuit made up of a feedback capacitance (Cfb1, Cfb2, Cfb3) and a switch (SW1, SW2, SW3) having, wherein the feedback paths of the plurality of integrator circuits (20, 22, 24) are connected in parallel to the common operational amplifier (8). circuit device claim 6 , characterized in that the operational amplifier (8) is designed as a fully differential operational transconductance amplifier (8) whose negative output (8c) is connected via a first feedback part (12a) to its plus input (8a) and whose plus output ( 8d) is fed back via a second feedback part (12b) to its negative input (8b), the feedback parts (12a, 12b) being essentially symmetrical and being connected to different terminals of a reference voltage (Vref2), with in each feedback part (12a, 12b) has a parallel connection of at least the following feedback paths: - three series connections each consisting of a first, second or third feedback capacitance (Cfb1, Cfb2, Cfb3) and a switch (SW1, SW2, SW3) for closing in the first, second or third clock phase (T1, T2, T3), - a second input connected via a first switch (SW1) and a second switch (SW2). s-capacitance (Cin2), the connections of which can also be grounded via switches (SW2, SW3), - a third input capacitance (Cin3) connected via a second switch (SW2) and a third switch (SW3), whose connections continue can be connected to a second reference voltage (Vref2) and ground via switches (SW2, SW3). circuit device claim 7 , characterized in that the outputs of the input SC structure (10) are connected to the two input terminals (8a, 8b) of the operational amplifier (8) by first switches (SW1) closed in the first clock phase (T1) and in a second and/or the third clock phase (T2, T3, T2_3) are grounded.

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