DE102009052031A1 - Method for operating large presses for vehicle body parts, involves utilizing modified control signal for synchronizing control device to control electrical devices, where modified signal is rectangle signal - Google Patents

Abstract

The method involves collecting a part of periodically changing electrical voltage in form of an electrical signal, and filtering the electrical signal. A modified control signal is formed from the filtered electrical signal of the voltage. The network voltage is used for forming the modified control signal of periodically returning points of the electric signal, where the points are zero crossovers. The modified signal is used for synchronizing a control device to control electrical devices i.e. large presses, for vehicle body parts, where the modified signal is a rectangle signal. An independent claim is also included for a device for supplying current to electrical devices.

Description

The present invention relates to a method and a device for operating machines on disturbed voltage networks and in particular disturbed low-voltage networks. The invention will be described with reference to machines such as large presses for body parts which are connected to low voltage networks. Such mains voltages have in part disturbances caused by harmonics and commutation dips. These faults, in turn, can lead to the disconnection of power supply units for these machines during operation.

From the internal state of the art of the Applicant regenerative supply units for supplying such machines are known. The disadvantage of these previously known solutions, however, is their susceptibility to interference. Since the voltage of industrial networks is not always sinusoidal and free of glitches, it often comes in such cases to error messages and machine downtime.

Furthermore, it is known from the prior art, more precisely, the drive technology known to use so-called pulse inverters. These can be used both on the motor side and on the network side. In a network-side use, with which the present invention is particularly concerned, the pulse inverter is used to generate a DC link voltage with which the one or more drives are supplied. An energy flow is possible in both directions.

The present invention is therefore an object of the invention to provide a method and an apparatus available, which allows safe operation even with disturbed mains voltages. These objects are achieved according to the invention by a method and a device according to the independent claims. Advantageous embodiments and further developments are the subject of the dependent claims.

In a method according to the invention for the operation of electrical devices connected to an electrical voltage, a part of the periodically changing electrical voltage is first removed or branched off in the form of an electrical signal. Subsequently, this electrical signal is filtered and from the filtered electrical signal, a modified control signal is formed, being used to form this modified control signal periodically recurring points of the electrical signal of the mains voltage. Subsequently, the modified control signal is used for synchronizing a control device which controls the electrical device. In this context, a control device is understood as meaning any device which controls or influences the electrical device or also the voltages supplying it.

It is therefore proposed that for synchronization or operation of such control devices such as a pulse inverter no longer the original mains voltage signal, which may have strong interference is used, but a derived signal derived from this modified signal. By using this modified signal, it can be ensured that disturbances of the mains voltage no longer affect the operation of the machine, since these can be eliminated in particular by filtering and forming the modified control signal. In particular, however, the electrical device itself is operated by itself with the full mains voltage.

The present invention can be used in particular in cases where a signal curve with a fixed relation to a network phase angle is to be generated. Thus, with the method according to the invention, those types of power converters which are to be operated on a low-voltage network can be synchronized. The invention is particularly suitable in the field of drive technology or in the field of solar inverters and the like.

Preferably, the periodically recurring points of the electrical signal are zero crossings of the electrical signal. These zero crossings are suitable in a special way, since these are particularly characteristic points of the electrical signal. However, it would also be possible in principle to use other characteristic points of the signal, for example the exceeding of certain voltage values. Preferably, the filtering of the electrical signal achieves that the voltage profile is smoothed such that only the actual zero crossings or in general the periodically recurring points of the electrical signal are detected and used further.

A periodically changing electrical signal is understood to mean a signal which, especially in a smoothed state, assumes a periodically recurring course, the disturbances of this signal not being taken into account in the assessment of this periodically recurring profile.

In a further preferred method, the modified signal is a square wave signal. This Square wave signal is used - as mentioned above - to control said control device.

Particularly preferably, the modified signal is a square wave signal derived from the zero crossings of the electrical signal, and more preferably a digital signal which varies between exactly two states or values with each zero crossing.

Preferably, a correction of a phase error of the modified control signal is made. This phase error can occur in particular due to the filtering performed. This correction is particularly preferably a digital correction of the said phase error.

In a further advantageous method, the periodically changing voltage is related to a floating star point.

In a further advantageous method, the correction takes place as a function of a mains frequency of the electrical signal. In this way, it is possible that the method can also be used for different network frequencies or even for completely different from a network operation applications. The inventive method is thus a high robustness against disturbances of the mains voltage allows. Furthermore, any phase shift is possible, so that when operated with power converters and a reactive power compensation can be done. In a further preferred method, the control device is a converter and in particular a pulse converter and / or a particularly digital PLL (phase locked loop).

The present invention is further directed to a device for supplying electrical equipment. This device has a voltage decrease device, which decreases an electrical signal from an electrical voltage source. Furthermore, the device has a modification device, which forms a modified control signal from the electrical signal, wherein the modification device forms the modified control signal on the basis of periodically recurring points of the electrical signal. Furthermore, a control device is provided which is synchronized or operated by the modified control signal and controls the electrical device.

Advantageously, the device also has a filtering device for filtering the electrical signal. The voltage drop device may, for example, be a resistor on which a small part of the mains voltage is removed to form the modified signal. The modifying device is in particular a circuit device or processor device which analyzes the periodically recurring signal and, as mentioned above, forms a modified signal, in particular from the zero crossings. This modified signal is in turn used to synchronize the pulse inverter.

In a further advantageous embodiment, the device has a correction device for correcting phase errors. In general, the device has a device for changing phase positions. In this way, phase errors caused by the filtering can be corrected again. It should be noted that, for example, the modification device, the filter device and also the correction device can be implemented in a common processor device.

Advantageously, the device also has an analysis device for analyzing the electrical signal, wherein this analysis device determines, for example, the periodically recurring points such as zero crossings. Thus, reliable synchronization is achieved even in faulty networks, but advantageously unique errors, such as a phase failure, must nevertheless be recognized.

In addition to the classic TN-S network, the synchronization proposed according to the invention also works with so-called IT networks and phase-earthed networks. In order to simplify the mains voltages are divided down and greatly filtered and formed from the zero crossings a square wave signal, which synchronizes a digital PLL, advantageously here by the filtering conditional phase errors are digitally corrected again. A PLL (Phase Locked Loop) is a fed-back control system that automatically adjusts the phase of a signal to match the phase of an input signal.

Thus, it is possible that such PLLs generate an oscillator frequency to adjust the frequency of an input signal. In a closed-loop situation, any small change in the input signal will affect a phase change between the input signal and the oscillator frequency. This phase shift then acts as an error signal to change the frequency of the PLL oscillator so as to adjust the input signal.

Further advantages and embodiments will become apparent from the accompanying drawings.

Show:

1 a basic circuit of a pulse inverter;

2 an example of a faulty mains voltage;

3 a circuit for generating a mains synchronous sine signal;

4 a logic network;

5 a circuit diagram for a digital signal processing;

6 Phases of a fault-free three-phase network;

7 a comparison of the disturbed input signal and the filtered signal;

8th an illustration for illustrating the network clock;

9 an illustration of the occurrence of an error message;

10 a representation of a resulting signal;

11 a comparison of the disturbed input signal and the synchronization signal;

12 a representation of the signal of the phase controller; and

13 a representation of the network synchronization on a real device.

1 shows a basic circuit of a pulse inverter for a three-phase network. More specifically, it refers 1 to a pulse inverter for a 3-phase network operation. It can be seen that in this case the mains voltage is tapped and in each case with the help of six IGBTs 102 (Insolated Gate Bipolar Transistor) is split into three phases. It would also be possible to replace the respective IGBTs with thyristors. By cleverly driving these IGBTs, a 3-phase voltage can be generated. More precisely, the pulse-controlled inverter is able to remove sinusoidal currents from the network at a defined phase position. To implement the necessary control method, however, the knowledge of the respective network phase angle, ie the angle of the network phase shift is required.

As mentioned above, occurs in this synchronization, the difficulty that industrial networks due to harmonic loads often have no sinusoidal voltage and that the timing of particular zero crossings due to Kommultierungseinbrüche or other glitches, which z. B. can be triggered by switching operations, is irregular.

2 shows an example of such a faulty mains voltage. The point marked B here has a multiple zero crossing. Since the zero crossings are easy to detect, they are preferably used for synchronization. In an advantageous method, the respective zero crossings are also used in the context of the present invention. However, in the case of the in 2 shown faulty network lead to errors.

If the synchronization works incorrectly, the pulse inverter can no longer be optimally regulated. This can lead to over- or under-voltages in the DC link and thus also to excessive currents in the network phases up to a network short-circuit. If these phenomena are detected by higher-level protection devices, they can be switched off with the appropriate error message so that "only" the system is shut down.

In other cases, these disturbed voltages can inevitably lead to the destruction of components and thus to longer plant failure with corresponding costs. For this reason, interference-free network synchronization is of great importance for the operation of pulse-controlled inverters.

3 illustrates a circuit which serves to generate a mains synchronous sine signal. The three network phases P1, P2, P3 are processed electrically isolated and preferably by means of voltage dividers 2 divided down to an analog signal range of -10V to + 10V. This is done by a in their entirety 4 designated filter means a strong filtering (t ~ 0.2 T _network ). In addition, the respective voltages on an artificial potential-free neutral point 6 based. This is advantageous so that the synchronization can also be operated on IT networks or networks with outer conductor grounding.

By means of downstream comparators 8th there is a detection of the zero crossings, wherein the output signal of these comparators first an opto-separator 12 and finally Schmitt triggers 14 is supplied. These Schmitt triggers 14 bring the output signal to a logical level.

This is at the outputs of the Schmitt trigger 14 in each case a square wave signal whose edges coincide in time with the zero crossings of the associated phase voltages. The frequency of this square wave signal corresponds in particular to twice the mains frequency.

In 4 1 illustrates a logic network which combines the three square-wave signals TU_IMP and TV-IMP and TW_IMP into a signal, referred to herein as network clock NT. This network clock NT has at each point an edge at which one of the network phases has a zero crossing. In this way, the network clock NT has six times the network frequency. In order to continue to suppress edge jitter, the network clock is via an RC element 22 with an adjoining Schmitt trigger 24 guided.

Therefore, a plurality of square-wave signals are preferably initially formed on the basis of the individual zero crossings and these square-wave signals are combined to form a network clock signal, this network clock signal preferably having six times the network frequency.

5 illustrates the now subsequent (advantageously digital) signal processing. This processing is preferably carried out with the aid of a microcontroller or by means of a programmable logic module. 5 more precisely illustrates the signal flow plan.

If that is in 6 faultless three-phase system shown in more detail, a corresponding flawless waveform is present, ie the undisturbed phases P1, P2, P3, as is also the duty cycle of the network clock, which is also the control signal S _control, constant and uniform 1: 1. Any unbalance which affects the zero crossings of the individual phases P1, P2, P3 or else a complete phase failure changes the duty cycle, so that a network fault detection can also be carried out therefrom.

For this purpose and also for further signal processing, the duty cycle of the network clock is detected. For this purpose, a so-called gated timer 42 used ( 5 ). Each edge of the network clock secures the current meter reading, sets the gated timer 42 then 0 and start a new counting process. The greater the time interval between the individual network clock edges, the higher the meter reading. Therefore, the gated timer delivers 42 a sequence of numerical values that show the time interval between the individual network clock edges. If the network and thus the network clock fails completely, the timer overflows after a preselectable time, so that a power failure monitoring is possible.

The numerical values obtained from the gated timer now undergo a plausibility check. Thus, for example, an upper and lower limit can be set for the network frequency, so that it is possible to derive therefrom Min values and max values for the numbers which can be sorted out as false when exceeding or falling below (reference symbol) 44 ). Furthermore, a subtraction takes place 46 two consecutive numbers. In the case of an immaculate network, this difference ideally results in 0. If the difference exceeds a predetermined tolerance, the associated numerical value is also regarded as defective and is not further processed.

Every error event triggers an error counter 48 , which can trigger an error message when a certain counter reading is reached. After acquiring a certain number of correct numerical values, the error counter can be completely deleted or also counted down step by step. By varying these modes, a corresponding choice of the differential amount tolerance and a suitable determination of the reporting threshold of the error counter, the error sensitivity can be set very sensitive for different applications. Therefore, a detection of the network clock edges (of the control signal) preferably takes place with a plausibility check.

Only the numerically recognized values of the gated timer 42 become an averaging 52 fed. Thus, the ripple of the number sequence existing in the case of strongly disturbed networks and correspondingly high set fault tolerance is sufficiently smoothed, as described with reference to FIG 8th is shown. In 8th S_NT denotes the signal of the network clock and S_gegl indicates the corresponding smoothed signal. Averaging is done by reading in a mean value memory a certain number of numerical values, the oldest value always falling out when a new one is added. The values in the memory are added up and divided by the number. The thus-averaged value is then divided, the divisor being governed by the selected resolution of the timers used and the sinusoidal signal synthetically generated as a result of the entire process. It is therefore preferred to average the network clock lengths or the network clock signal.

The value from this division is an input to the now following digital PLL, which in their entirety 70 is designated at the output of a synthetically generated sinusoidal sine wave (ωt + φ _K ) is formed. The value of the PLL input signal is proportional to the mains frequency. By means of the PLL 70 Now the phase reference to the net for the synthetic sine signal is established. This happens in the subsequent adder 56 by adding a correction value to the input signal, which is thus the frequency of the subsequent reload counter 58 affected. The generation of the correction value will be described later.

This turns the value from the adder 56 in the reload counter 58 loaded. This counts down and each underflow triggers a new reload impulse. The frequency of the reload pulses is thus dependent on the reload value. Is this z. B. large, the counter takes longer to count down, resulting in a lower output frequency. The output frequency, ie the frequency of the reload pulses is proportional to the mains frequency and serves as an input signal for the subsequent address counter 62 , It counts upwards the address area of the sine table 64 by. Thus, its output signal corresponds to the phase angle of the synthetically generated sinusoidal signal.

The address counter 62 must be set once to a defined starting value. This happens in the initialization during the positive zero crossing of the U-phase. It usually takes several cycles to fill the mean value memory and lock the PLL. During this initialization time, the AND gate becomes 72 kept open and at the positive zero crossing of the U phase, a reset pulse for the address counter 62 generated. Upon completion of the initialization, the AND gate becomes 72 blocked.

The production of the phase reference to the network phase angle also takes place during the positive zero crossing of the U-phase. If the phase angle φ at the output of the address counter is in a tolerance window specified by φ _Tol , then the window comparator switches 74 , with which the phase comparison takes place, the AND gate 76 for activating the Sample & Hold link 78 free. In this way, the zero-crossing pulse can start a sample process. The stored value in the S & H member 78 is used as a correction value to the input value of the reload counter 58 adds and thus influences its output frequency, resulting in a phase shift of the address counter 62 becomes possible.

If the zero crossing pulse is outside the phase angle tolerance window in time, then the AND gate is 76 locked and the pulse is ineffective. In this way, glitches occurring at any time are hidden.

The input value for the S & H element 78 is the one at the respective sample time from the sine table 64 extracted sine value which previously had a P-member 66 to be led. Is the synthetically generated sine z. B. too slow, ie, its phase is trailing, so the sine value at the time of the zero crossing pulse is negative. In this way, a negative correction value, which the input value of the reload counter 58 reduced. In this way, its output frequency increases and the lag is caught up. Since for small angles: sin φ ^~ φ results in a nearly linear control behavior.

The gain of the P-member 66 has significant influence on the control behavior of the PLL. If it is too large results in strong phase jitter of the synthetic sine, it is too small, increases the lock time of the PLL and the permanent phase difference.

Although a permanent phase difference could be interrupted by means of an I or PI element, this results in a significantly higher jitter. The most favorable solution is a P-element, which has a moderate gain and an additional phase correction. The phase correction takes place via a larger φ _k value!

Preference is given to a phase correction anyway required by the above-mentioned strong filtering of the mains voltages. However, the phase correction is very simple, because only to the input value of the address counter 62 a correction value must be added or subtracted from this, and any desired network-synchronous phase position can be produced thereby.

The sinusoidal signal thus addressed from the sine table can now be z. B. are used to generate a setpoint for a current regulator of a pulse inverter.

It is therefore preferably proposed a control of the PLL, preferably also a generation and feedback of the control variable and particularly preferably an interference pulse suppression.

7 shows a comparison of the electrical signal S _electrically on the one hand and the filtered electrical signal or the filtered mains Sine _filtered on the other. In particular, the phase shift between these two signals resulting from the filtering can be seen.

9 shows an illustration of the occurrence of an error message. In this case, the reference character SF denotes the value of an error counter. According to the setting, an error message should be given with a value of 6. It can be seen here that despite a severely disturbed network, only a short response takes place during the initialization phase.

10 shows a representation of a resulting signal. In this case, the reference symbol S _Synch denotes a synchronized sine signal which is present at the output of the sine table 64 (see. 6 ). The _filtered S signifies in turn the filtered line sinusoidal to the input of the comparator 8th (see. 3 ) is created. One recognizes a small remaining phase difference. This is on the in 6 shown P-controller 66 but can be read from the sine table 64 be easily corrected.

11 shows a comparison of the original electrical signal S _electrical and the resulting (preferably phase- _corrected ) sinusoidal signal S _output , which can be used to synchronize a pulse converter.

12 shows a further illustration, wherein the signal shown there S _{phase controller} to the output to the phase controller (S & H member 78 ) in 6 represents. Despite a severely disturbed network, only small correction values are required after the initialization phase, which also results in a low phase jitter.

13 Finally, an illustration of the network synchronization performed on a real device is shown. In this case, the real input voltage S _electrical as well as the resulting control signal can be recognized again.

The Applicant reserves the right to claim as claimed in the invention one or more of the disclosed features, insofar as they are novel, individually or in combination with respect to the prior art.

LIST OF REFERENCE NUMBERS

2

voltage dividers

6

potential-free star

8th

comparators

12

Opto-separator

14

Schmitt trigger

22

RC element

42

gated timer

44

Min / Max detection

46

differencing

48

error count

52

Averaging calculation

56

adder

58

Reload Counter

62

Address counter

64

sine table

66

P element

70

PLL

72

AND gate

74

window

76

AND gate

78

Sample & Hold member

S _tax

control signal

S _Synch

synchronized sinusoidal signal

S _filtered

filtered net sine

S _electric

electrical signal

S _exit

sinewave

S _{phase controller}

output

S_NT

Signal of the network

S_gegl

smoothed signal

P1, P2, P3

phases

S

Job

Claims (13)

Method for operating electrical devices connected to an electrical voltage, comprising the steps of: - removing at least part of the periodically changing electrical voltage in the form of an electrical signal (S _electr ); - filtering the electrical signal (S _elektr ); Forming a modified control signal (S _tax) from the filtered electrical signal (S _elec) of the voltage, whereby to form the modified control signal (S _Control) periodically recurring points of the electrical signal (S _Electric) used the mains voltage - the use of the modified control signal ( S _control) for synchronizing a control device which controls the electric appliance. A method according to claim 1, characterized in that the periodically recurring points of the electrical signal (S _electr ) are zero crossings of the electrical signal (S _electr ). A method according to at least one of the preceding claims, characterized in that the modified signal (S _control) is a square wave signal. A method according to claim 4, characterized in that the modified signal (S _control) a from the zero crossings of the electrical signal (S _elec) is derived square wave signal. A method according to at least one of the preceding claims, characterized in that a correction of a phase error of the modified control signal (S _control) is performed. Method according to at least one of the preceding claims, characterized in that the periodically changing voltage of the electrical signal (S _electrical ) is related to a floating star point. A method according to claim 6, characterized in that the correction is a digital correction. A method according to claim 6, characterized in that the correction of the phase error takes place as a function of a mains frequency of the electrical signal. Method according to at least one of the preceding claims, characterized in that a detection of the Netztaktflanken (the control signal) takes place with a plausibility monitoring. Method according to at least one of the preceding claims, characterized in that the control device is a converter and in particular a pulse converter. Device for supply of electrical devices with a voltage decrease means that decreases from an electrical voltage source an electric signal (S _Electric) with a modifying means, which forms a modified control signal from the electrical signal (S _Electric) (S _control), said modifying means the modified control signal (S _control) forms based on periodically recurring points of the electrical signal (S _electric) and with a control device, which of the modified control signal (S _control) is synchronized and which controls the electrical devices. Apparatus according to claim 11, characterized in that the device comprises a filtering device ( 8th ) for filtering the electrical signal (S _electr ). Apparatus according to claim 11, characterized in that the device comprises a correction device for the correction of phase errors.

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