DE102009013085A1 - Method for arranging and connecting electronic component on substrate, involves producing electrical contact of electronic component following from front end of substrate on front-side metallization or openings - Google Patents
Method for arranging and connecting electronic component on substrate, involves producing electrical contact of electronic component following from front end of substrate on front-side metallization or openings Download PDFInfo
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Abstract
Description
Die vorliegende Erfindung betrifft ein Verfahren gemäß dem Oberbegriff des Hauptanspruchs und eine Vorrichtung gemäß dem Oberbegriff des Nebenanspruches und eine Verwendung gemäß einem weiteren Nebenanspruch.The The present invention relates to a method according to the preamble of the main claim and a device according to the preamble the additional claim and a use according to another additional claim.
In der Aufbau- und Verbindungstechnik von elektronischen Bauelementen, insbesondere von LED-Bauelementen, werden herkömmlicherweise Substrate hybrid mit dem elektronischen Bauelement und einer Schutzdiode über Flip-Chip- oder Drahtbondtechnik auf Keramiksubstraten montiert. Diese Modulbauart erfordert eine große Fläche, weist ein befriedigendes Entwärmungsverhalten auf und erfordert aber einen weiteren Prozessschritt durch die Montage einer Schutzdiode.In the assembly and connection technology of electronic components, In particular of LED components, substrates are conventionally hybrid with the electronic component and a protective diode via flip-chip or wire bonding technique mounted on ceramic substrates. This modular design requires a big one Area, has a satisfactory cooling behavior but requires a further process step through the assembly a protection diode.
Herkömmlicherweise
werden Leuchtdioden drahtgebondet oder per Flip-Chip-Technologie
auf Keramiksubstraten montiert. Ein Ausführungsbeispiel gemäß dem Stand
der Technik zeigt
Es ist Aufgabe der vorliegenden Erfindung die Aufbau- und Verbindungstechnik von elektronischen Bauelementen, insbesondere Leuchtdioden, mit Dioden, insbesondere Schutzdioden, auf Substraten derart zu verbessern, dass der Flächenbedarf und die Anzahl der Prozessschritte für die Bauelemente-Montage verringert werden sowie insbesondere eine wirksame Entwärmung im Betrieb bereitgestellt ist.It The object of the present invention is the construction and connection technology of electronic components, in particular light-emitting diodes, with Diodes, in particular protection diodes, to improve on substrates such that the space requirement and the number of process steps for the component mounting can be reduced and in particular a effective heat dissipation is provided during operation.
Die Aufgabe wird durch ein Verfahren gemäß dem Hauptanspruch, eine Vorrichtung gemäß dem Nebenanspruch und eine Verwendung gemäß dem weiteren Nebenanspruch gelöst.The The object is achieved by a method according to the main claim, a device according to the secondary claim and a use according to the others Side claim solved.
Gemäß einem ersten Aspekt wird ein Verfahren zum Aufbauen und Verbinden mindestens eines elektronischen Bauelements auf einem Substrat mit mindestens einer mit dem Bauelement elektrisch verschalteten Diode beansprucht. Es erfolgt ein Erzeugen von durch das Substrat hindurch geschaffenen metallisierten Durchführungen von Rückseitenmetallisierungen durch das Substrat hindurch zu Vorderseitenmetallisierungen. Die Rückseitenmetallisierungen sind auf einer Rückseite und die Vorderseitenmetallisierungen sind auf einer Vorderseite des Substrats ausgebildete Oberflächenmetallisierungen. Mit anderen Worten erfolgt ein Erzeugen von auf dem Substrat ausgebildeten metallischen Rückseitenkontakten und metallisierten Durchkontaktierungen von den Rückseitenkontakten durch das Substrat hindurch insbesondere zu dem Bauelement. Es erfolgt ein elektrisches Kontaktieren des elektronischen Bauelements an Vorderseitenmetallisierungen und/oder Durchführungen des Substrats. Die Erfindung zeichnet sich dadurch aus, dass als Substrat ein dotierter Substratwafer verwendet wird, die metallisierten Durchführungen und die Oberflächenmetallisierungen teilweise mittels einer Isolation zum Substratwafer elektrisch isoliert erzeugt werden und die Diode in den Substratwafer integriert ist.According to one The first aspect is a method of building and connecting at least an electronic device on a substrate with at least a claimed electrically connected to the device diode claimed. There is produced a metallized created by the substrate bushings of backside metallizations through the substrate to front side metallizations. The rear-side are on a back and the front side metallizations are on a front side surface metallizations formed on the substrate. With others Words are generated by forming on the substrate metallic Back contacts and metallized vias from the backside contacts through the substrate, in particular to the device. It takes place electrically contacting the electronic component to front side metallizations and / or bushings of the substrate. The invention is characterized in that as Substrate, a doped substrate wafer is used, the metallized bushings and the surface metallizations partially electrically isolated by means of an insulation to the substrate wafer are generated and the diode is integrated into the substrate wafer.
Gemäß einem zweiten Aspekt wird eine Vorrichtung mit mindestens einem elektronischen Bauelement auf einem Substrat mit mindestens einer mit dem Bauelement elektrisch verschalteten Diode beansprucht. Die Erfindung zeichnet sich dadurch aus, dass durch das Substrat hindurch geschaffene metallisierte Durchführungen von Rückseitenmetallisierungen durch das Substrat hindurch zu Vorderseitenmetallisierungen erzeugt sind, wobei die Rückseitenmetallisierungen auf einer Rückseite und die Vorderseitenmetallisierungen auf einer Vorderseite des Substrats ausgebildete Oberflächenmetallisierungen sind und dass das elektronische Bauelement an Vorderseitenmetallisie rungen und/oder Durchführungen elektrisch angeschlossen ist. Die Erfindung zeichnet sich dadurch aus, dass das Substrat ein dotierter Substratwafer ist, die metallisierten Durchführungen und die Oberflächenmetallisierungen teilweise mittels einer Isolation zum Substratwafer elektrisch isoliert erzeugt sind und die Diode in den Substratwafer integriert ist.According to one second aspect is a device with at least one electronic Device on a substrate with at least one with the device claimed electrically connected diode. The invention draws characterized in that provided by the substrate through metallized bushings of backside metallizations produced through the substrate to Vorderseitenmetallisierungen are, with the backside metallizations on a back and the front side metallizations on a front side of the substrate trained surface metallizations are and that the electronic device to Vorderseitenmetallisie ments and / or feedthroughs electrically connected. The invention is characterized in that the substrate is a doped substrate wafer that metallized Performances and the surface metallizations partially electrically isolated by means of an insulation to the substrate wafer are generated and the diode is integrated into the substrate wafer.
Gemäß einem dritten Aspekt erfolgt eine Verwendung einer erfindungsgemäßen Vorrichtung als Fahrzeugscheinwerfer oder zur Innenraumbeleuchtung, wobei das elektronische Bauelement eine Leuchtdiode ist.According to one The third aspect is a use of a device according to the invention as a vehicle headlight or interior lighting, the electronic component is a light emitting diode.
Das Aufbau und Verbindungstechnikkonzept wird weiter miniaturisiert, der Flächenbedarf, insbesondere für die Leuchtdioden-Montage, wird weiter reduziert und insbesondere die Entwärmungsmöglichkeiten verbessert. Gemäß der vorliegenden Erfindung wird ein Aufbau- und Verbindungstechnik-Konzept weiter monolithisch miniaturisiert.The Construction and connection technology concept is further miniaturized, the area required, especially for The light-emitting diode assembly, is further reduced and in particular the cooling possibilities improved. According to the present Invention will continue a construction and connection technology concept miniaturized monolithic.
Es ist ein wesentliches Merkmal eine Integration einer Diode, insbesondere einer Schutzdiode, in einen Substratwafer auszuführen. Der Flächenbedarf, beispielsweise für ein Leuchtdioden-Modul, wird um etwa 20% reduziert, wobei die Substratkosten sich um einen Faktor 4 verringern.It an essential feature is an integration of a diode, in particular a protection diode to perform in a substrate wafer. The area required, for example a light-emitting diode module, is reduced by about 20%, with the substrate costs themselves reduce by a factor of 4.
Weitere vorteilhafte Ausgestaltungen werden in Verbindung mit den Unteransprüchen beansprucht.Further advantageous embodiments are claimed in conjunction with the subclaims.
Gemäß einer vorteilhaften Ausgestaltung können folgende Schritte ausgeführt werden: Ein Dotieren des Substratwafers. Dabei kann der Substratwafer bereits ursprünglich vollständig einheitlich dotiert erzeugt worden sein. Dabei kann der Substratwafer n- oder p-dotiert sein. Es folgt ein Erzeugen zweier integrierter Schottky-Dioden mittels zweier Übergänge von Oberflächenmetallisierungen und/oder metallisierten Durchführungen zum dotierten Substratwafer. Eine Oberflächenmetallisierung kann auf einer Vorderseite des Substratwafers auf der Seite des elektronischen Bauelements als Vordersei tenmetallisierung erzeugt sein. Die Flächen beider Übergänge sind unterschiedlich groß. Die beiden Schottky-Dioden können ein Schutz für das elektronische Bauelement sein.According to one advantageous embodiment can following steps are performed Be: doping the substrate wafer. In this case, the substrate wafer already originally Completely have been generated uniformly doped. In this case, the substrate wafer be n- or p-doped. It follows a generation of two integrated Schottky diodes by means of two transitions from Surface metallization and / or metallized feedthroughs to the doped substrate wafer. A surface metallization may occur a front side of the substrate wafer on the side of the electronic Component be produced as Vordersei tenmetallisierung. The surfaces of both transitions are different sized. The two Schottky diodes can a protection for be the electronic component.
Gemäß einer weiteren vorteilhaften Ausgestaltung kann das Verfahren folgende Schritte ausführen: Dotieren des Substratwafers. Dabei kann der Substratwafer bereits ursprünglich vollständig einheitlich dotiert erzeugt worden sein. Der Substratwafer kann entweder n-leitend oder p-leitend bereitgestellt sein. Es erfolgt ein Erzeugen mindestens eines Bereichs einer zusätzlichen zur gesamten einheitlichen Dotierung des Substratwafers entgegen gesetzten lokalen Dotierung auf mindestens einer Seite des Substratwafers. Ist die Dotierung des Substratwafers beispielsweise p-leitend, so ist die lokale Dotierung n-leitend. Die lokale Dotierung kann beispielsweise als n-Topf, oder „n-well”, bereitgestellt sein. Es erfolgt ein Erzeugen einer integrierten Diode mittels eines Übergangs des Bereiches zum dotierten Substratwafer.According to one Further advantageous embodiment, the method can be the following Perform steps: Doping the substrate wafer. In this case, the substrate wafer already originally Completely have been generated uniformly doped. The substrate wafer can be provided either n-type or p-type. It takes place generating at least a portion of an additional to the overall uniform Doping the substrate wafer opposite local doping on at least one side of the substrate wafer. Is the doping of the substrate wafer, for example p-type, then the local doping n-type. The local doping may be, for example, as an n-pot, or "n-well". An integrated diode is generated by means of a transition of the region to the doped substrate wafer.
Gemäß einer weiteren vorteilhaften Ausgestaltung kann die lokale Dotierung mittels Innenimplantation und/oder mittels Diffusionsprozesse erzeugt werden. Ein Übergang des Bereichs zum dotierten Substratwafer kann entweder ein pn-Übergang oder ein np-Übergang sein. Die integrierte Diode kann eine Schutzdiode sein.According to one Another advantageous embodiment, the local doping means Internal implantation and / or generated by diffusion processes. A transition of the doped substrate wafer region may be either a pn junction or a np transition be. The integrated diode can be a protection diode.
Gemäß einer weiteren vorteilhaften Ausgestaltung kann ein Erzeugen von elektrischen Kontaktierungen der integrierten Diode mittels einer auf dem Bereich ausgebildeten Oberflächenmetallisierung und einer weiteren Oberflächenmetallisierung und/oder einer metallisierten Durchführung erfolgen.According to one Another advantageous embodiment, a generation of electrical Contacts of the integrated diode by means of one on the area trained surface metallization and another surface metallization and / or a metallized execution respectively.
Gemäß einer weiteren vorteilhaften Ausgestaltung kann das elektronische Bauelement eine Leuchtdiode sein. Es kann die integrierte Diode als Schutzdiode bereitgestellt sein.According to one Further advantageous embodiment, the electronic component be a light emitting diode. It can be the integrated diode as a protective diode be provided.
Gemäß einer weiteren vorteilhaften Ausgestaltung kann der Substratwafer ein Siliziumwafer sein.According to one Further advantageous embodiment, the substrate wafer Be silicon wafer.
Gemäß einer weiteren vorteilhaften Ausgestaltung kann das Bauelement auf dem Substratwafer mittels Flip-Chip-Kontaktierung kontaktiert werden.According to one Another advantageous embodiment, the device on the Substrate wafer by means of flip-chip contacting be contacted.
Gemäß einer weiteren vorteilhaften Ausgestaltung können Durchgänge, die ebenso als Via-Strukturen bezeichnet werden können, für die metallisierten Durchführungen mittels anisotropen nasschemischen Ätzungen, insbesondere Kaliumhydroxiod-Ätzungen, erzeugt werden.According to one Further advantageous embodiment can passages, as well as via structures can be designated for the metallized ones bushings by means of anisotropic wet-chemical etching, in particular potassium hydroxide etches, be generated.
Gemäß einer weiteren vorteilhaften Ausgestaltung können KOH-Ätzungen mit einem Ätzwinkel im Bereich von 50° bis 60° erzeugt, insbesondere 54°, ausgeführt werden.According to one Further advantageous embodiment can KOH etchings with an etching angle in the Range from 50 ° to Generated 60 °, in particular 54 °, accomplished become.
Gemäß einer weiteren vorteilhaften Ausgestaltung können Via-Strukturen für die metallisierten Durchführungen mittels Plasmaätzungen und/oder Laserstrukturierung erzeugt werden. Der Ätzwinkel kann im Bereich von 50 bis 90° bereitgestellt sein.According to one Another advantageous embodiment can via structures for the metallized feedthroughs by plasma etching and / or laser structuring. The etching angle can ranging from 50 to 90 ° be.
Gemäß einer weiteren vorteilhaften Ausgestaltung können die Rückseitenmetallisierungen und/oder der Substratwafer an ein weiteres Substrat elektrisch ankontaktiert werden. Damit kann der Substratwafer als ein sogenannter Interposerwafer bezeichnet werden. Das weitere Substrat kann ebenso Oberflächenmetallisierungen und/oder metallisierte Durchführungen aufweisen.According to one Another advantageous embodiment, the back side metallizations and / or the substrate wafer is electrically contacted to another substrate become. Thus, the substrate wafer as a so-called Interposerwafer be designated. The further substrate may also have surface metallizations and / or metallized feedthroughs exhibit.
Die Erfindung wird anhand von Ausführungsbeispielen in Verbindung mit den Figuren näher beschrieben. Es zeigen:The Invention is based on embodiments closer in connection with the figures described. Show it:
A1 ist ungefähr 3 × 400 μm2 =
48000 μm2
A2 ist ungefähr 6 × 8 μm2 = 48 μm2.
A 1 is approximately 3 × 400 μm 2 = 48000 μm 2
A 2 is about 6 × 8 μm 2 = 48 μm 2 .
Daraus
folgt, dass das Verhältnis
der Flächen
A1/A2 ungefähr 1000
ist. Der Übergang
der Oberflächenmetallisierung
Gemäß
Die
Anordnungen gemäß
Claims (21)
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DE102009013085A DE102009013085A1 (en) | 2009-03-13 | 2009-03-13 | Method for arranging and connecting electronic component on substrate, involves producing electrical contact of electronic component following from front end of substrate on front-side metallization or openings |
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DE102009013085A DE102009013085A1 (en) | 2009-03-13 | 2009-03-13 | Method for arranging and connecting electronic component on substrate, involves producing electrical contact of electronic component following from front end of substrate on front-side metallization or openings |
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DE102009013085A1 true DE102009013085A1 (en) | 2010-09-16 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102010027679A1 (en) * | 2010-07-20 | 2012-01-26 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
WO2012110365A1 (en) * | 2011-02-16 | 2012-08-23 | Osram Opto Semiconductors Gmbh | Carrier substrate and method for producing semiconductor chips |
US8482026B2 (en) | 2009-07-09 | 2013-07-09 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
WO2015154956A1 (en) * | 2014-04-11 | 2015-10-15 | Osram Opto Semiconductors Gmbh | Semiconductor chip, optoelectronic component with a semiconductor chip, and method for producing a semiconductor chip |
EP3035385A1 (en) * | 2014-12-16 | 2016-06-22 | IMEC vzw | Semiconductor interposer comprising a schottky diode and a method for fabricating the interposer |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6876008B2 (en) * | 2003-07-31 | 2005-04-05 | Lumileds Lighting U.S., Llc | Mount for semiconductor light emitting device |
US20080290535A1 (en) * | 2007-05-24 | 2008-11-27 | Molock Jr Frank F | Reduction of excess polymeric flash ring |
-
2009
- 2009-03-13 DE DE102009013085A patent/DE102009013085A1/en not_active Ceased
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6876008B2 (en) * | 2003-07-31 | 2005-04-05 | Lumileds Lighting U.S., Llc | Mount for semiconductor light emitting device |
US20080290535A1 (en) * | 2007-05-24 | 2008-11-27 | Molock Jr Frank F | Reduction of excess polymeric flash ring |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8482026B2 (en) | 2009-07-09 | 2013-07-09 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
US9000476B2 (en) | 2010-07-20 | 2015-04-07 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
DE102010027679A1 (en) * | 2010-07-20 | 2012-01-26 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
US9704945B2 (en) | 2011-02-16 | 2017-07-11 | Osram Opto Semiconductors Gmbh | Carrier substrate and method for producing semiconductor chips |
US10224393B2 (en) | 2011-02-16 | 2019-03-05 | Osram Opto Semiconductors Gmbh | Method of producing semiconductor chips that efficiently dissipate heat |
TWI491084B (en) * | 2011-02-16 | 2015-07-01 | Osram Opto Semiconductors Gmbh | Carrier substrate and method for producing semiconductor chip |
CN103370779B (en) * | 2011-02-16 | 2015-09-16 | 奥斯兰姆奥普托半导体有限责任公司 | Support substrate and the method for the manufacture of semiconductor chip |
CN103370779A (en) * | 2011-02-16 | 2013-10-23 | 奥斯兰姆奥普托半导体有限责任公司 | Carrier substrate and method for producing semiconductor chips |
WO2012110365A1 (en) * | 2011-02-16 | 2012-08-23 | Osram Opto Semiconductors Gmbh | Carrier substrate and method for producing semiconductor chips |
WO2015154956A1 (en) * | 2014-04-11 | 2015-10-15 | Osram Opto Semiconductors Gmbh | Semiconductor chip, optoelectronic component with a semiconductor chip, and method for producing a semiconductor chip |
DE102014105188A1 (en) * | 2014-04-11 | 2015-10-15 | Osram Opto Semiconductors Gmbh | Semiconductor chip, optoelectronic component with semiconductor chip and method for producing a semiconductor chip |
DE112015001786B4 (en) | 2014-04-11 | 2022-02-10 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Semiconductor chip and optoelectronic component with semiconductor chip |
CN106170860A (en) * | 2014-04-11 | 2016-11-30 | 欧司朗光电半导体有限公司 | Semiconductor chip, has the opto-electronic device of semiconductor chip and for the method manufacturing semiconductor chip |
US10424565B2 (en) | 2014-04-11 | 2019-09-24 | Osram Opto Semiconductor Gmbh | Semiconductor chip for protecting against electrostatic discharges |
CN106170860B (en) * | 2014-04-11 | 2018-12-14 | 欧司朗光电半导体有限公司 | Semiconductor chip, the opto-electronic device with semiconductor chip and the method for manufacturing semiconductor chip |
CN105702667A (en) * | 2014-12-16 | 2016-06-22 | 台湾积体电路制造股份有限公司 | Interposer and method for fabricating the interposer, electronic device and production device |
CN105702667B (en) * | 2014-12-16 | 2018-08-21 | 台湾积体电路制造股份有限公司 | Intermediary layer and its manufacturing method, electronic device and protective device |
EP3035385A1 (en) * | 2014-12-16 | 2016-06-22 | IMEC vzw | Semiconductor interposer comprising a schottky diode and a method for fabricating the interposer |
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