DE102008064702B4 - Forming strained semiconductor material involves forming stack of layers, forming mask, forming first spacer element, forming first and second cavities, and first and second strained semiconductor material - Google Patents
Forming strained semiconductor material involves forming stack of layers, forming mask, forming first spacer element, forming first and second cavities, and first and second strained semiconductor material Download PDFInfo
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
Description
Gebiet der vorliegenden ErfindungField of the present invention
Im Allgemeinen betrifft die vorliegende Erfindung integrierte Schaltungen und betrifft insbesondere die Herstellung unterschiedlicher Transistorarten mit verformten Kanalgebieten unter Anwendung eines eingebetteten verformungsinduzierenden Materials, um die Ladungsträgerbeweglichkeit in den Kanalgebieten zu verbessern.In general, the present invention relates to integrated circuits, and more particularly relates to the fabrication of different types of strained channel region transistors using an embedded strain-inducing material to enhance charge carrier mobility in the channel regions.
Beschreibung des Stands der TechnikDescription of the Related Art
Integrierte Schaltungen werden in vielen Gebieten auf Grund der zunehmenden Funktionsvielfalt, die auf einer vorgegebenen Chipfläche bereitgestellt wird, eingesetzt. Integrierte Schaltungen sind aus zahlreichen einzelnen Schaltungskomponenten, etwa Transistoren, aufgebaut, wobei mehrere Millionen oder sogar mehrere hundert Millionen einzelner Transistoren in komplexen Bauelementen vorgesehen ist. Allgemein werden mehrere Prozesstechnologien eingesetzt, wobei für komplexe Schaltungen, etwa Mikroprozessoren, Speicherchips und dergleichen, die CMOS-Technologie aktuell eine der vielversprechendsten Lösungen auf Grund der guten Eigenschaften im Hinblick auf die Arbeitsgeschwindigkeit und/oder Leistungsaufnahme und/oder Kosteneffizienz ist. Während der Herstellung komplexer integrierter Schaltungen unter Anwendung der CMOS-Technologie werden Millionen Transistoren, d. h. n-Kanaltransistoren und p-Kanaltransistoren, auf einem Substrat hergestellt, das eine kristalline Halbleiterschicht aufweist. Ein MOS-Transistor enthält, unabhängig davon, ob ein n-Kanaltransistor oder ein p-Kanaltransistor betrachtet wird, sogenannte pn-Übergänge, die durch eine Grenzfläche stark dotierter Drain- und Sourcegebiete mit einem invers dotierten Kanalgebiet gebildet sind, das zwischen dem Draingebiet und dem Sourcegebiet angeordnet ist. Die Leitfähigkeit des Kanalgebiets, d. h. der Durchlassstrom des leitenden Kanals, wird durch eine Gateelektrode gesteuert, die in der Nähe des Kanalgebiets ausgebildet und davon durch eine dünne isolierende Schicht getrennt ist. Die Leitfähigkeit des Kanalgebiets beim Aufbau eines leitenden Kanals auf Grund des Anlegens einer geeigneten Steuerspannung an die Gateelektrode hängt von der Dotierstoffkonzentration, der Beweglichkeit der Ladungsträger und – für eine gegebene Abmessung des Kanalgebiets in der Transistorbreitenrichtung – von dem Abstand zwischen dem Sourcegebiet und dem Draingebiet ab, der auch als Kanallänge bezeichnet wird. Somit ist die Verringerung der Kanallänge und damit verknüpft die Verringerung des Kanalwiderstands ein wichtiges Entwurfskriterium, um eine Zunahme der Arbeitsgeschwindigkeit integrierter Schaltungen zu erreichen.Integrated circuits are used in many fields due to the increasing variety of functions provided on a given chip area. Integrated circuits are made up of numerous individual circuit components, such as transistors, with several millions or even hundreds of millions of individual transistors in complex components. In general, multiple process technologies are used, with complex circuits such as microprocessors, memory chips, and the like, CMOS technology currently being one of the most promising solutions due to its good performance in terms of operating speed and / or power consumption and / or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i. H. n-channel transistors and p-channel transistors, fabricated on a substrate having a crystalline semiconductor layer. Regardless of whether an n-channel transistor or a p-channel transistor is considered, a MOS transistor includes pn junctions formed by an interface of heavily doped drain and source regions having an inversely doped channel region disposed between the drain region and the source region is arranged. The conductivity of the channel region, i. H. the forward current of the conductive channel is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region in the construction of a conductive channel due to the application of a suitable control voltage to the gate electrode depends on the dopant concentration, the mobility of the carriers and, for a given dimension of the channel region in the transistor width direction, on the distance between the source region and the drain region , which is also referred to as channel length. Thus, reducing the channel length and, associated with it, reducing the channel resistance is an important design criterion for achieving an increase in the speed of operation of integrated circuits.
Die ständige Verringerung der Transistorabmessungen zieht jedoch eine Reihe damit verknüpfter Probleme nach sich, die es zu lösen gilt, um nicht in unerwünschter Weise die Vorteile aufzuheben, die durch das stetige Verringern der Kanallänge von MOS-Transistoren gewonnen werden. Ein wichtiges Problem in dieser Hinsicht ist die Entwicklung aufwendiger Photolithographie- und Ätzstrategien, um zuverlässig und reproduzierbar Schaltungselemente mit kritischen Abmessungen, etwa der Gateelektrode der Transistoren, für eine neue Schaltungsgeneration zu schaffen. Ferner sind äußerst aufwendige Dotierstoffprofile in der vertikalen Richtung sowie in lateraler Richtung in den Drain- und Sourcegebieten erforderlich, um den geringen Schichtwiderstand und Kontaktwiderstand in Verbindung mit einer gewünschten Kanalsteuerbarkeit zu erreichen.However, the continual reduction in transistor dimensions entails a number of associated problems that need to be addressed so as not to undesirably cancel out the advantages gained from continuously reducing the channel length of MOS transistors. An important problem in this regard is the development of sophisticated photolithography and etching strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new generation of circuits. Furthermore, extremely expensive dopant profiles in the vertical direction as well as in the lateral direction in the drain and source regions are required in order to achieve the low sheet resistance and contact resistance in conjunction with a desired channel controllability.
Die ständige Größenreduzierung der kritischen Abmessungen, d. h. der Gatelänge von Transistoren, macht die Anpassung und möglicherweise die Neuentwicklung äußerst komplexer Prozesstechniken im Hinblick auf die oben genannten Prozessschritte erforderlich. Es wurde daher vorgeschlagen, die Kanalleitfähigkeit der Transistorelemente zu verbessern, indem die Ladungsträgerbeweglichkeit in dem Kanalgebiet für eine vorgegebene Kanallänge erhöht wird, wodurch die Möglichkeit geschaffen wird, eine Leistungssteigerung zu erreichen, die vergleichbar ist dem Voranschreiten zu einen zukünftigen Technologiestandard, wobei viele der oben genannten Prozessanpassungen, die mit der Bauteilgrößenreduzierung verknüpft sind, vermieden oder zumindest zeitlich verschoben werden. Ein effizienter Mechanismus zum Erhöhen der Ladungsträgerbeweglichkeit ist die Modifizierung der Gitterstruktur in dem Kanalgebiet, indem beispielsweise eine Zugverspannung oder eine kompressive Verspannung in der Nähe des Kanalgebiets hervorgerufen wird, um damit eine entsprechende Verformung in dem Kanalgebiet zu erzeugen, die zu einer modifizierten Beweglichkeit für Elektronen bzw. Löcher führt. Beispielsweise erhöht das Erzeugen einer Zugverformung in dem Kanalgebiet mit einer standardmäßigen (100) Oberflächenorientierung die Beweglichkeit von Elektronen, was sich wiederum direkt in einer entsprechenden Zunahme der Leitfähigkeit ausdrückt. Andererseits erhöht eine kompressive Verformung in dem Kanalgebiet die Beweglichkeit von Löchern, wodurch die Möglichkeit geschaffen wird, das Leistungsverhalten von p-Transistoren zu verbessern. Die Einführung einer Verspannungs- oder Verformungstechnologie in den Herstellungsprozess für integrierte Schaltungen ist ein äußerst vielversprechender Ansatz für weitere Bauteilgenerationen, da beispielsweise verformtes Silizium als eine „neue” Art an Halbleitermaterial betrachtet werden kann, die die Herstellung schneller und leistungsfähiger Halbleiterbauelemente ermöglicht, ohne dass teuere Halbleitermaterialien erforderlich sind, wobei dennoch viele der gut etablierten Fertigungstechniken weiterhin eingesetzt werden können.The constant size reduction of the critical dimensions, ie, the gate length of transistors, necessitates the adaptation and possibly the redesign of extremely complex process techniques in view of the above-mentioned process steps. It has therefore been proposed to improve the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby providing the opportunity to achieve an increase in performance comparable to advancing to a future technology standard, many of the above mentioned process adjustments that are associated with the component size reduction, avoided or at least postponed. An efficient mechanism for increasing the charge carrier mobility is to modify the lattice structure in the channel region by, for example, inducing a tensile stress or compressive strain near the channel region, thereby creating a corresponding strain in the channel region that results in a modified mobility for electrons or holes leads. For example, creating a tensile strain in the channel region with a standard (100) surface orientation increases the mobility of electrons, which in turn directly translates into a corresponding increase in conductivity. On the other hand, compressive deformation in the channel region increases the mobility of holes, thereby providing the opportunity to improve the performance of p-type transistors. The introduction of a bracing or deformation technology into the integrated circuit manufacturing process is a highly promising approach for other generations of devices, as, for example, deformed silicon can be considered a "new" type of semiconductor material that enables the production of fast and efficient semiconductor devices without costly ones Semiconductor materials are required, while still many of the good established production techniques can continue to be used.
In einer Vorgehensweise wird die Löcherbeweglichkeit von PMOS-Transistoren erhöht, indem eine verformte Silizium/Germaniumschicht in den Drain- und Sourcegebieten der Transistoren hergestellt wird, wobei die kompressiv verformten Drain- und Sourcegebiete eine uniaxiale Verformung in dem benachbarten Siliziumkanalgebiet hervorrufen. Dazu wird selektiv in den Drain- und Sourcegebieten der PMOS-Transistoren eine Aussparung geschaffen, während die NMOS-Transistoren maskiert sind und nachfolgend wird die Silizium/Germanium-Schicht selektiv in dem PMOS-Transistor durch epitaktisches Aufwachsen gebildet. Somit müssen komplexe Fertigungsschritte, etwa ein Ätzprozess, die Herstellung einer geeigneten Ätz- und Wachstumsmaske und selektive epitaktische Wachstumstechniken in den CMOS-Prozessablauf eingebunden werden.In one approach, the hole mobility of PMOS transistors is increased by making a strained silicon / germanium layer in the drain and source regions of the transistors, where the compressively deformed drain and source regions cause uniaxial deformation in the adjacent silicon channel region. For this purpose, a recess is selectively created in the drain and source regions of the PMOS transistors, while the NMOS transistors are masked, and subsequently the silicon / germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Thus, complex manufacturing steps, such as an etching process, the production of a suitable etching and growth mask and selective epitaxial growth techniques have to be integrated into the CMOS process flow.
In anderen Vorgehensweisen wird Silizium/Kohlenstoffmaterial für NMOS-Transistoren verwendet, um eine gewünschte Gitterfehlanpassung speziell in den Kanalgebieten der NMOS-Transistoren hervorzurufen, was häufig durch Ionenimplantation von Kohlenstoff in die Drain- und Sourcegebiete erreicht wird. Eine Leistungszunahme für Transistoren unterschiedlicher Leitfähigkeitsart auf der Grundlage von Silizium/Kohlenstofflegierungen kann jedoch zu einen noch komplexeren Prozessablauf führen, da diversen Schritte für die Herstellung entsprechender Verformungsschichten in geeigneter Weise in den komplexen Fertigungsablauf eingebunden werden müssen, was zu einem weniger ausgeprägten Leistungszuwachs führt, als dies erwartet wird.In other approaches, silicon / carbon material is used for NMOS transistors to cause a desired lattice mismatch, especially in the channel regions of the NMOS transistors, which is often achieved by ion implantation of carbon into the drain and source regions. However, increasing the performance of transistors of different conductivity type based on silicon / carbon alloys can lead to an even more complex process flow, since various steps for the production of corresponding deformation layers must be appropriately incorporated into the complex manufacturing process, which leads to a less pronounced performance increase than this is expected.
In der
Ein ähnliches Verfahren mit der Ausbildung unterschiedlicher verformter Halbleitermaterialien in Source-/Draingebieten wird in der
In der
Angesichts der zuvor beschriebenen Situation betrifft die vorliegende Erfindung Techniken und Halbleiterbauelemente mit Transistoren unterschiedlicher Leitfähigkeitsart mit eingebetteten verformungsinduzierenden Materialien, wobei eines oder mehrere der oben erkannten Probleme vermieden oder zumindest verringert werden.In view of the situation described above, the present invention relates to techniques and semiconductor devices with transistors of different conductivity type with embedded strain-inducing materials, wherein one or more of the problems identified above are avoided or at least reduced.
Überblick über die ErfindungOverview of the invention
Die vorliegende Erfindung stellt ein Verfahren zur Herstellung eines verformten Halbleitermaterials in einem ersten Transistor einer ersten Leitfähigkeitsart und in einem zweiten Transistor einer zweiten Leitfähigkeitsart bereit, wobei das Verfahren umfasst:
Bilden eines Schichtstapels über einer ersten Gateelektrodenstruktur des ersten Transistors und über einer zweiten Gateelektrodenstruktur des zweiten Transistors, wobei die erste und die zweite Gateelektrodenstruktur eine entsprechende Deckschicht aufweisen und wobei der Schichtstapel eine Abstandshalterschicht und eine Ätzstoppschicht, die über der Abstandshalterschicht gebildet ist, aufweist;
Bilden einer Maske über dem zweiten Transistor und über der Ätzstoppschicht;
Bilden eines ersten Abstandshalterelements an der ersten Gateelektrodenstruktur aus der Abstandshalterschicht;
Bilden erster Aussparungen in Drain- und Sourcebereichen des ersten Transistors unter Anwendung des ersten Abstandshalterelements als eine Maske;
Einführen einer oder mehrerer erster Implantationssorten in freigelegte Oberflächenbereiche der ersten Aussparungen;
Bilden eines ersten verformten Halbleitermaterials in den ersten Aussparungen;
Bilden zweiter Aussparungen in Drain- und Sourcebereichen des zweiten Transistors unter Anwendung eines zweiten Abstandshalterelements, das aus der Abstandshalterschicht gebildet wird, als eine Maske; und
Bilden eines zweiten verformten Halbleitermaterials in den zweiten Aussparungen, wobei das erste und das zweite verformte Halbleitermaterial eine unterschiedliche Materialzusammensetzung besitzen.The present invention provides a method of making a deformed semiconductor material in a first transistor of a first conductivity type and in a second transistor of a second conductivity type, the method comprising:
Forming a layer stack over a first gate electrode structure of the first transistor and over a second gate electrode structure of the second transistor, the first and second gate electrode structures having a respective cap layer, and wherein the layer stack comprises a spacer layer and an etch stop layer formed over the spacer layer;
Forming a mask over the second transistor and over the etch stop layer;
Forming a first spacer element on the first gate electrode structure from the spacer layer;
Forming first recesses in drain and source regions of the first transistor using the first spacer element as a mask;
Introducing one or more first implant varieties into exposed surface areas of the first recesses;
Forming a first deformed semiconductor material in the first recesses;
Forming second recesses in drain and source regions of the second transistor using a second spacer element formed from the spacer layer as a mask; and
Forming a second deformed semiconductor material in the second recesses, the first and second deformed semiconductor materials having a different material composition.
Kurze Beschreibung der ZeichnungenBrief description of the drawings
Weitere Ausführungsformen der vorliegenden Erfindung sind in den angefügten Patentansprüchen definiert und gehen deutlicher aus der folgenden detaillierten Beschreibung hervor, wenn diese mit Bezug zu den begleitenden Zeichnungen studiert wird, in denen:
und zwar in Verbindung mit einer Implantation, z. B. dem Einbau einer Dotierstoffsorte, einer nicht dotierenden Sorte und dergleichen, um die gesamten Transistoreigenschaften zu verbessern.Further embodiments of the present invention are defined in the appended claims and will become more apparent from the following detailed description when considered with reference to the accompanying drawings, in which:
in connection with an implantation, z. The incorporation of a dopant species, a non-doping species, and the like to improve overall transistor properties.
Detaillierte BeschreibungDetailed description
Im Allgemeinen betrifft die vorliegende Erfindung Fertigungstechniken und entsprechende Halbleiterbauelemente, in denen Feldeffekttransistoren unterschiedlicher Leitfähigkeitsart ein verformtes Halbleitermaterial in den Drain- und/oder Sourcegebiet erhalten, um damit eine gewünschte Größe und/oder Art an Verformung in den entsprechenden Kanalgebieten dieser Transistoren zu schaffen. Zu diesem Zweck werden in einigen anschaulichen Ausführungsformen unterschiedliche Halbleiterlegierungen verwendet, etwa Silizium/Germanium und Silizium/Kohlenstoff auf der Grundlage eines geeigneten Fertigungsschemas, in welchem beide Materialien in die Drain- und Sourcebereiche der jeweiligen Transistoren unter Anwendung eines geeignet gestalteten Schichtstapels mit einer Abstandshalterschicht und einer Ätzstoppschicht eingebettet werden. Des weiteren wird das gesamte Transistorverhalten für zumindest eine Art an Transistoren verbessert, indem eine gewünschte Art an Implantationssorte, etwa Dotierstoffe, nicht dotierende Sorten und dergleichen, vor dem Bilden eines entsprechenden verformten Halbleitermaterials durch epitaktische Aufwachstechniken eingebaut wird. In diesem Falle können die elektronischen Eigenschaften der Drain- und Sourcegebiete auf der Grundlage der zusätzlichen Implantationssorte verbessert werden, die ohne das Erzeugen weiterer Implantationsschäden eingebaut werden, da der Implantationsprozess vor dem Aufwachsen des verformten Halbleitermaterials ausgeführt wird. Folglich können für n-Kanaltransistoren geringere Source/Drain-Übergangswiderstände auf Grund des speziell optimierten Dotierstoffprofils erreicht werden. Des weiteren könnten die Effekte des potentialfreien Körpers in SOI-Transistoren auf Grund der Anwesenheit höhere Leckströme der jeweiligen pn-Übergänge verringert werden, was wiederum zu einer geringeren Ladungsträgeransammlung in dem Körpergebiet der SOI-Transistoren führt. Eine entsprechende Einstellung der Eigenschaften von pn-Übergängen kann erreicht werden, indem eine geeignete Implantationssorte vor dem eigentlichen Herstellen des verformten Halbleitermaterials eingebaut wird. Des weiteren kann die Elektronenbeweglichkeit auf Grund der eingebetteten Silizium/Kohlenstoff-Legierung in den Drain- und Sourcebereichen des n-Kanaltransistors erhöht werden. In ähnlicher Weise kann in p-Kanaltransistoren ein geringerer Source- und Drainwiderstand auf Grund des geringeren inhärent spezifischen Widerstands des Silizium/Germanium-Materials erreicht werden, und es können auch moderat hohe Leckströme in den pn-Übergängen eingestellt werden, wobei dies von den gesamten Transistoreigenschaften abhängt, wodurch ebenfalls die Ladungsträgeransammlung in SOI-Transistoren verringert wird. Schließlich kann die größere Löcherbeweglichkeit in dem Kanalgebiet, die durch die eingebettete Silizium/Germanium-Legierung hervorgerufen wird, zusätzlich zur gesamten Leistungssteigerung des Bauelements beitragen. Da beide verformungsinduzierenden Halbleitermaterialien in einer moderat frühen Fertigungsphase eingebaut werden, können weitere verformungsinduzierende Mechanismen in den Gesamtfertigungsablauf integriert werden, ohne dass im Wesentlichen zusätzliche Prozessschritte erforderlich sind. Beispielsweise können verformungsinduzierende Abstandshalterelemente und/oder verformungsinduzierende dielektrische Deckschichten vorgesehen werden, um die Verformung in zumindest einer Art an Transistor weiter zu erhöhen.In general, the present invention relates to fabrication techniques and corresponding semiconductor devices in which field effect transistors of different conductivity type receive a deformed semiconductor material in the drain and / or source region to provide a desired size and / or type of strain in the respective channel regions of these transistors. For this purpose, in some illustrative embodiments, different semiconductor alloys are used, such as silicon / germanium and silicon / carbon, based on a suitable fabrication scheme in which both materials enter the drain and source regions of the respective transistors using a suitably designed layer stack with a spacer layer and embedded in an etch stop layer. Furthermore, overall transistor performance for at least one type of transistor is improved by incorporating a desired type of implantation species, such as dopants, non-doping species, and the like, prior to forming a corresponding deformed semiconductor material by epitaxial growth techniques. In this case, the electronic properties of the drain and source regions can be improved based on the additional implantation grade that is incorporated without creating further implantation damage since the implantation process is performed prior to the growth of the deformed semiconductor material. Consequently, lower source / drain contact resistances due to the specially optimized dopant profile can be achieved for n-channel transistors. Furthermore, the effects of the floating body in SOI transistors could be reduced due to the presence of higher leakage currents of the respective pn junctions, which in turn leads to less charge accumulation in the body region of the SOI transistors. An appropriate adjustment of the properties of pn junctions can be achieved by incorporating an appropriate implantation type prior to the actual fabrication of the deformed semiconductor material. Furthermore, the electron mobility due to the embedded silicon / carbon alloy in the drain and source regions of the n-channel transistor can be increased. Similarly, in p-channel transistors, lower source and drain resistance can be achieved due to the lower intrinsic resistivity of the silicon germanium material, and moderately high leakage currents can be set in the pn junctions, of which the total Transistor properties, which also reduces the charge carrier accumulation in SOI transistors. Finally, the increased hole mobility in the channel region caused by the embedded silicon / germanium alloy can add to the overall performance of the device. Since both deformation-inducing semiconductor materials are incorporated in a moderately early manufacturing stage, further deformation-inducing mechanisms can be integrated into the overall manufacturing process without essentially requiring additional process steps. For example, deformation-inducing spacer elements and / or strain-inducing dielectric cover layers may be provided to further increase deformation in at least one type of transistor.
Mit Bezug zu den begleitenden Zeichnungen werden nunmehr weitere anschauliche Ausführungsformen detaillierter beschrieben.With reference to the accompanying drawings, further illustrative embodiments will now be described in more detail.
Ferner sind geeignete aktive Gebiete in der Halbleiterschicht
Das in
In den erfindungsgemäßen Ausführungsformen werden nach dem Ätzprozess
Das Halbleiterbauelement
Beispielsweise besitzt die Abstandshalterstruktur
Das in
Folglich können die verformten Halbleitermaterialien
Es gilt also: Die vorliegende Erfindung stellt ein Verfahren zur Herstellung von Halbleiterbauelementen bereit, wobei verformte Halbleitermaterialien, etwa Silizium/Germanium und dergleichen einerseits und Silizium/Kohlenstoff andererseits in die Drain- und Sourcegebiete auf der Grundlage eines sehr effizienten Fertigungsablaufs eingebaut werden, und zwar in Verbindung mit zusätzlichen Implantationssorten, um die gesamten Transistoreigenschaften.Thus, the present invention provides a method of fabricating semiconductor devices incorporating deformed semiconductor materials such as silicon germanium and the like on the one hand and silicon carbon on the other hand into the drain and source regions based on a very efficient manufacturing process in conjunction with additional implant varieties to the overall transistor properties.
Claims (11)
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US20070018252A1 (en) * | 2005-07-21 | 2007-01-25 | International Business Machines Corporation | Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same |
DE102006015087A1 (en) * | 2006-03-31 | 2007-10-11 | Advanced Micro Devices, Inc., Sunnyvale | A method of fabricating buried drain / source regions based on a process of combined spacer etch and recess etching |
US20070252204A1 (en) * | 2006-04-28 | 2007-11-01 | Andy Wei | Soi transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same |
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US20070018252A1 (en) * | 2005-07-21 | 2007-01-25 | International Business Machines Corporation | Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same |
DE102006015087A1 (en) * | 2006-03-31 | 2007-10-11 | Advanced Micro Devices, Inc., Sunnyvale | A method of fabricating buried drain / source regions based on a process of combined spacer etch and recess etching |
US20070252204A1 (en) * | 2006-04-28 | 2007-11-01 | Andy Wei | Soi transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same |
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