DE102008064702B4 - Forming strained semiconductor material involves forming stack of layers, forming mask, forming first spacer element, forming first and second cavities, and first and second strained semiconductor material - Google Patents

Forming strained semiconductor material involves forming stack of layers, forming mask, forming first spacer element, forming first and second cavities, and first and second strained semiconductor material

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DE102008064702B4
DE102008064702B4 DE200810064702 DE102008064702A DE102008064702B4 DE 102008064702 B4 DE102008064702 B4 DE 102008064702B4 DE 200810064702 DE200810064702 DE 200810064702 DE 102008064702 A DE102008064702 A DE 102008064702A DE 102008064702 B4 DE102008064702 B4 DE 102008064702B4
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forming
transistor
semiconductor material
layer
gate electrode
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Jan Hoentschel
Vassilios Papageorgiou
Belinda Hannon
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GlobalFoundries Dresden Module One LLC and Co KG
GlobalFoundries Inc
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GlobalFoundries Dresden Module One LLC and Co KG
GlobalFoundries Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

Forming a strained semiconductor material involves forming a stack of layers above a first gate electrode structure; forming a mask above (105) the second transistor and above the etch stop layer; forming a first spacer element (104S) at the first gate electrode structure; forming first cavities (103P) in drain and source areas of the first transistor (150P); forming a first strained semiconductor material (153P); forming second cavities (103N) in drain and source areas of the second transistor (150N); and forming a second strained semiconductor material (153N) in the second cavities. Forming a strained semiconductor material in a first transistor (150P) of a first conductivity type and a second transistor (150N) of a second conductivity type, involves: process A: forming a stack of layers above a first gate electrode structure of the first transistor and a second gate electrode structure of the second transistor, the first and second gate electrode structures comprising a respective cap layer (15K), the stack of layers comprising a spacer layer (104A) and an etch stop layer (104B) formed above the spacer layer (104A); forming a mask above (105) the second transistor and above the etch stop layer; forming a first spacer element (104S) at the first gate electrode structure from the spacer layer (104A); forming first cavities (103P) in drain and source areas of the first transistor (150P) using the first spacer element (104S) as a mask; forming a first strained semiconductor material (153P) in the first cavities (103P); forming second cavities (103N) in drain and source areas of the second transistor (150N) using a second spacer element (104R) formed from the spacer layer (104A) as a mask; forming a second strained semiconductor material (153N) in the second cavities, (103N) the first and second strained semiconductor materials (153P, 153N) having a different material composition; and introducing first implantation species into exposed surface portions of the first cavities (103P); or process B: forming first cavities adjacent to a first gate electrode structure of a first transistor and second cavities adjacent to a second gate electrode structure of a second transistor, the first and second transistors being of different conductivity type; forming a semiconductor material in the first and second cavities, the semiconductor material having a first type of strain; creating lattice damage in the semiconductor material selectively in the first transistor to form a substantially relaxed semiconductor material; and re-crystallizing the substantially relaxed semiconductor material in a strained state, the strained state corresponding to a second type of strain that is opposite to the first type of strain. The semiconductor material comprises a silicon/carbon alloy.

Description

  • Field of the present invention
  • In general, the present invention relates to integrated circuits, and more particularly relates to the fabrication of different types of strained channel region transistors using an embedded strain-inducing material to enhance charge carrier mobility in the channel regions.
  • Description of the Related Art
  • Integrated circuits are used in many fields due to the increasing variety of functions provided on a given chip area. Integrated circuits are made up of numerous individual circuit components, such as transistors, with several millions or even hundreds of millions of individual transistors in complex components. In general, multiple process technologies are used, with complex circuits such as microprocessors, memory chips, and the like, CMOS technology currently being one of the most promising solutions due to its good performance in terms of operating speed and / or power consumption and / or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i. H. n-channel transistors and p-channel transistors, fabricated on a substrate having a crystalline semiconductor layer. Regardless of whether an n-channel transistor or a p-channel transistor is considered, a MOS transistor includes pn junctions formed by an interface of heavily doped drain and source regions having an inversely doped channel region disposed between the drain region and the source region is arranged. The conductivity of the channel region, i. H. the forward current of the conductive channel is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region in the construction of a conductive channel due to the application of a suitable control voltage to the gate electrode depends on the dopant concentration, the mobility of the carriers and, for a given dimension of the channel region in the transistor width direction, on the distance between the source region and the drain region , which is also referred to as channel length. Thus, reducing the channel length and, associated with it, reducing the channel resistance is an important design criterion for achieving an increase in the speed of operation of integrated circuits.
  • However, the continual reduction in transistor dimensions entails a number of associated problems that need to be addressed so as not to undesirably cancel out the advantages gained from continuously reducing the channel length of MOS transistors. An important problem in this regard is the development of sophisticated photolithography and etching strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new generation of circuits. Furthermore, extremely expensive dopant profiles in the vertical direction as well as in the lateral direction in the drain and source regions are required in order to achieve the low sheet resistance and contact resistance in conjunction with a desired channel controllability.
  • The constant size reduction of the critical dimensions, ie, the gate length of transistors, necessitates the adaptation and possibly the redesign of extremely complex process techniques in view of the above-mentioned process steps. It has therefore been proposed to improve the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby providing the opportunity to achieve an increase in performance comparable to advancing to a future technology standard, many of the above mentioned process adjustments that are associated with the component size reduction, avoided or at least postponed. An efficient mechanism for increasing the charge carrier mobility is to modify the lattice structure in the channel region by, for example, inducing a tensile stress or compressive strain near the channel region, thereby creating a corresponding strain in the channel region that results in a modified mobility for electrons or holes leads. For example, creating a tensile strain in the channel region with a standard (100) surface orientation increases the mobility of electrons, which in turn directly translates into a corresponding increase in conductivity. On the other hand, compressive deformation in the channel region increases the mobility of holes, thereby providing the opportunity to improve the performance of p-type transistors. The introduction of a bracing or deformation technology into the integrated circuit manufacturing process is a highly promising approach for other generations of devices, as, for example, deformed silicon can be considered a "new" type of semiconductor material that enables the production of fast and efficient semiconductor devices without costly ones Semiconductor materials are required, while still many of the good established production techniques can continue to be used.
  • In one approach, the hole mobility of PMOS transistors is increased by making a strained silicon / germanium layer in the drain and source regions of the transistors, where the compressively deformed drain and source regions cause uniaxial deformation in the adjacent silicon channel region. For this purpose, a recess is selectively created in the drain and source regions of the PMOS transistors, while the NMOS transistors are masked, and subsequently the silicon / germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Thus, complex manufacturing steps, such as an etching process, the production of a suitable etching and growth mask and selective epitaxial growth techniques have to be integrated into the CMOS process flow.
  • In other approaches, silicon / carbon material is used for NMOS transistors to cause a desired lattice mismatch, especially in the channel regions of the NMOS transistors, which is often achieved by ion implantation of carbon into the drain and source regions. However, increasing the performance of transistors of different conductivity type based on silicon / carbon alloys can lead to an even more complex process flow, since various steps for the production of corresponding deformation layers must be appropriately incorporated into the complex manufacturing process, which leads to a less pronounced performance increase than this is expected.
  • In the DE 10 2006 015 087 A1 "A method of fabricating a semiconductor device is described by introducing different deformed semiconductor material into recesses in source / drain regions of an NMOS and a PMOS transistor to enhance performance by following the steps set forth in claim 1, except introducing one or more first implant varieties be carried out in exposed surface areas of the first recesses.
  • A similar process with the formation of different deformed semiconductor materials in source / drain regions is described in US Pat US 2007/0018252 A1 described.
  • In the US 2007/0252204 A1 For example, a method of forming suitable dopant profiles in embedded stress-inducing source / drain regions is described, wherein implantation is performed after formation of recesses and prior to growth of the stress inducing material in a variant.
  • In view of the situation described above, the present invention relates to techniques and semiconductor devices with transistors of different conductivity type with embedded strain-inducing materials, wherein one or more of the problems identified above are avoided or at least reduced.
  • Overview of the invention
  • The present invention provides a method of making a deformed semiconductor material in a first transistor of a first conductivity type and in a second transistor of a second conductivity type, the method comprising:
    Forming a layer stack over a first gate electrode structure of the first transistor and over a second gate electrode structure of the second transistor, the first and second gate electrode structures having a respective cap layer, and wherein the layer stack comprises a spacer layer and an etch stop layer formed over the spacer layer;
    Forming a mask over the second transistor and over the etch stop layer;
    Forming a first spacer element on the first gate electrode structure from the spacer layer;
    Forming first recesses in drain and source regions of the first transistor using the first spacer element as a mask;
    Introducing one or more first implant varieties into exposed surface areas of the first recesses;
    Forming a first deformed semiconductor material in the first recesses;
    Forming second recesses in drain and source regions of the second transistor using a second spacer element formed from the spacer layer as a mask; and
    Forming a second deformed semiconductor material in the second recesses, the first and second deformed semiconductor materials having a different material composition.
  • Brief description of the drawings
  • Further embodiments of the present invention are defined in the appended claims and will become more apparent from the following detailed description when considered with reference to the accompanying drawings, in which:
    1a to 1k schematically cross-sectional views of a semiconductor device with transistors of different conductivity during various manufacturing stages, creating a different type of deformed semiconductor material based on an efficient manufacturing process with improved masking schemes,
    in connection with an implantation, z. The incorporation of a dopant species, a non-doping species, and the like to improve overall transistor properties.
  • Detailed description
  • In general, the present invention relates to fabrication techniques and corresponding semiconductor devices in which field effect transistors of different conductivity type receive a deformed semiconductor material in the drain and / or source region to provide a desired size and / or type of strain in the respective channel regions of these transistors. For this purpose, in some illustrative embodiments, different semiconductor alloys are used, such as silicon / germanium and silicon / carbon, based on a suitable fabrication scheme in which both materials enter the drain and source regions of the respective transistors using a suitably designed layer stack with a spacer layer and embedded in an etch stop layer. Furthermore, overall transistor performance for at least one type of transistor is improved by incorporating a desired type of implantation species, such as dopants, non-doping species, and the like, prior to forming a corresponding deformed semiconductor material by epitaxial growth techniques. In this case, the electronic properties of the drain and source regions can be improved based on the additional implantation grade that is incorporated without creating further implantation damage since the implantation process is performed prior to the growth of the deformed semiconductor material. Consequently, lower source / drain contact resistances due to the specially optimized dopant profile can be achieved for n-channel transistors. Furthermore, the effects of the floating body in SOI transistors could be reduced due to the presence of higher leakage currents of the respective pn junctions, which in turn leads to less charge accumulation in the body region of the SOI transistors. An appropriate adjustment of the properties of pn junctions can be achieved by incorporating an appropriate implantation type prior to the actual fabrication of the deformed semiconductor material. Furthermore, the electron mobility due to the embedded silicon / carbon alloy in the drain and source regions of the n-channel transistor can be increased. Similarly, in p-channel transistors, lower source and drain resistance can be achieved due to the lower intrinsic resistivity of the silicon germanium material, and moderately high leakage currents can be set in the pn junctions, of which the total Transistor properties, which also reduces the charge carrier accumulation in SOI transistors. Finally, the increased hole mobility in the channel region caused by the embedded silicon / germanium alloy can add to the overall performance of the device. Since both deformation-inducing semiconductor materials are incorporated in a moderately early manufacturing stage, further deformation-inducing mechanisms can be integrated into the overall manufacturing process without essentially requiring additional process steps. For example, deformation-inducing spacer elements and / or strain-inducing dielectric cover layers may be provided to further increase deformation in at least one type of transistor.
  • With reference to the accompanying drawings, further illustrative embodiments will now be described in more detail.
  • 1a schematically shows a cross-sectional view of a semiconductor device 100 that has a first transistor 150p and a second transistor 150n in an early manufacturing phase. The semiconductor device 100 includes a substrate 101 which represents any suitable carrier material over which a semiconductor layer 103 to form, for example, a silicon-based layer, its electronic properties locally by generating a desired type of strain in the first and second transistors 150p . 150n be adjusted. The semiconductor layer 103 For example, a silicon-based layer, ie, a semiconductor material having a pronounced proportion of silicon, may also include other components, such as germanium, carbon, dopant species, and the like. Furthermore, in the embodiment shown, a buried insulating layer 102 between the substrate 101 and the semiconductor layer 103 arranged, whereby an SOI (silicon on insulator) architecture is formed, it should be noted that in other component areas of the device 100 a full substrate configuration may be provided, depending on the overall device requirements. It should be noted that the principles described herein are extremely advantageous with respect to an SOI architecture, as efficient strain-inducing mechanisms are provided in conjunction with additional measures to reduce charge carrier accumulation, thus generally increasing the performance of SOI devices. Transistors with respect to the effects of the floating body and hysteresis effects is improved, ie, in terms of a threshold fluctuation in response to the "switching history" of a corresponding transistor element. In other illustrative embodiments, the principles described herein are advantageously applied to a solid substrate configuration, ie, a configuration in which a thickness of the semiconductor layer 103 is greater than a depth of the drain and source regions that are still in the transistors 150p . 150n are to be formed.
  • Furthermore, suitable active regions are in the semiconductor layer 103 formed on the basis of corresponding isolation structures, such as shallow trench isolations (not shown), between the transistors 150p . 150n can be provided. Furthermore, the transistors have 150p . 150n a gate electrode structure 151 , which in this manufacturing phase is an electrode material 151a having on a gate insulation layer 151b is formed, which in turn is the electrode material 151a from a canal area 152 separates. The gate electrode material 151a Any suitable material, such as polysilicon and the like, may even be replaced by a material having better conductivity in a later manufacturing stage, depending on the overall process and device requirements. Similarly, the gate insulation layer 151b may be constructed of any suitable dielectric material, such as silica-based materials, silicon nitride, silicon oxynitride, high-k dielectric materials, such as hafnium oxide, zirconium oxide, and the like. Furthermore, the gate electrode structures contain 151 a cover layer composed of silicon nitride and the like. Furthermore, the semiconductor component comprises 100 a layer stack 104 that over the transistors 150p . 150n is formed and in the embodiment shown, a first layer or spacer layer 104a over which a second layer or etch stop layer 104b is formed. In one illustrative embodiment, the spacer layer is 104a made of silicon nitride, while the etch stop layer 104b is formed of silicon dioxide. Thus, in the embodiment shown, the spacer layer 104a and the topcoat 151c of material with similar properties with respect to a subsequent etching process, so that these components can be removed during a common etching sequence. Furthermore, the etch stop layer has 104b a thickness sufficient to provide the desired etch stop characteristics during an etch process for locally providing an etch and growth mask over the transistor 150n provide. For example, the etch stop layer becomes 104b provided with a thickness of about 20 to 50 nm or more when provided in the form of a silica material. On the other hand, the spacer layer becomes 104a fabricated with a suitable thickness in a highly conformable manner to a desired distance during an etch process for making recesses in the semiconductor layer 103 to create in a later manufacturing phase. For example, there is a thickness of the spacer layer 104a in the range of about 1 to 20 nm in demanding applications, where a gate length, ie the horizontal dimension of the gate electrode material 151a in 1a is about 50 nm or less, about 30 nm and less. It should be noted, however, that a greater thickness can be selected if a greater distance is required during further processing.
  • This in 1a shown semiconductor device 100 can be made on the basis of the following processes. After fabricating corresponding isolation structures (not shown) and forming corresponding fundamental dopant profiles for the transistors 150p . 150n in the semiconductor layer 103 , becomes the gate electrode structure 151 produced by well-established techniques, including oxidation and / or deposition of a gate dielectric, followed by deposition of the gate electrode material 151a and the material of the cover layer 151c followed. The corresponding material stack is structured by complex lithography and etching techniques. Next is the stack 104 formed by, for example, the spacer layer 104a using some thermally activated CVD (chemical vapor deposition), optionally with a thin oxide layer for oxidation of the exposed area of the gate electrode material 151a and the semiconductor layer 103 can be formed. Thereafter, the etching stopper layer becomes 104d produced by, for example, CVD and the like, wherein the material density and thickness of the etching stop layer 104b are chosen so that the desired Ätzstoppeigenschaften be achieved. Subsequently, a masking material (not shown) is deposited, for example, by plasma assisted CVD, thermally activated CVD, and the like, which material is subsequently patterned by photolithography and appropriate selective etching techniques.
  • 1b schematically shows the semiconductor device 100 with a mask 105 that the second transistor 150n covering, while the first transistor 150n ie the layer stack formed above it 104 , is free. The mask 105 In one illustrative embodiment, a hard mask, such as silicon nitride or other suitable material, selectively with respect to the etch stop layer 104b can be etched. In other illustrative embodiments, another suitable material, such as resist, is selectively over the second transistor 150n educated and becomes the structuring of the layer stack 104 in the first transistor 150p used.
  • 1c schematically shows the semiconductor device 100 during an etching sequence 106 comprising a first etching step for selectively removing the etch stop layer 104b which can be achieved on the basis of well-established etching techniques, for example using hydrofluoric acid (HF), and then an anisotropic etching step is performed to form the spacer layer 104a selective to the material of the semiconductor layer 103 In other cases, a thin oxide layer (not shown) is provided to serve as an etch stop material during the anisotropic etch process. Thus, after the etching process 106 a sidewall spacer element 104s on sidewalls of the gate electrode structure 151 formed, wherein a width of the spacer 104s essentially by the initial layer thickness of the spacer layer 104a and the conditions in the etching sequence 106 is determined. In the embodiment shown, a certain amount of material removal in the mask may also be present 105 take place, as indicated by the dashed line, when the spacer layer 104a and the mask 105 are made of materials with similar etching behavior or if they are made of substantially the same material. In other illustrative embodiments, the mask represents 105 a resist material, at least during the first etching step of the sequence 106 to selectively remove the etch stop layer 104b above the first transistor 150p to remove. Thereafter, if necessary, the resist mask is removed and the anisotropic etch step of the sequence 106 can be performed on the basis of a selective etch recipe, wherein the etch stop layer 104b the remaining part of the shift 104a over the second transistor 150n protects.
  • 1d schematically shows the semiconductor device 100 in a more advanced manufacturing stage, in which another etching process 107 Running to depressions or recesses 103p adjacent to the gate electrode structure 151 in the semiconductor layer 103 of the first transistor 150p to build. The etching process 107 can be performed on the basis of well-established etch recipes, such as isotropic recipes, anisotropic recipes, or a combination thereof, depending on the shape and size of the cutouts desired 103p depends. For example, a variety of etch chemistries are available to selectively ablate silicon material with respect to silicon nitride material, oxide material, and the like, and these recesses for making the recesses 103p can be used. During the etching process 107 For example, appropriate process parameters, such as plasma power, pressure, type and amount of polymer materials for controlling a horizontal rate of removal, and the like can be adjusted to provide a desired shape of the recesses 103p is reached. For example, spacing of the recesses 103p from the channel area 152 essentially by the width of the spacer 104s be determined. If a more or less pronounced degree of undercut is desired, the process parameters and / or the etch chemistry may be suitably selected, for example at the beginning of the etch process 107 or during a certain stage of the process, this being of the desired size and shape of the recesses 103p depends. In the embodiment shown, the mask protects 105 the layer stack 104 that over the second transistor 150n is formed. In other cases, the mask 105 be removed in an earlier manufacturing stage, if this is provided as a paint material and the like, so that in this case the etch stop layer 104b reliable the spacer layer 104a protects.
  • In the embodiments according to the invention, after the etching process 107 and before or after removing the mask 105 one or more implantation processes 108 performed to one or more implantation varieties 108a through the exposed surface areas of the recess 103p introduce. For example, the one or more implantation processes include 108 one or more steps performed on the basis of a non-zero tilt angle, which is an angle of non-zero with respect to a normal of the semiconductor layer 103 or the buried insulating layer 102 to understand. Consequently, any desired implantation variety may be incorporated, with the positioning of the implantation variety 108a by the process parameters of the one or more implantation processes 108 , energy, dose, angle of inclination, type of implantation variety, and the like. In some illustrative embodiments, the implantation variety includes 108a a Dotierstoffsorte, for example, for counter-doping material of the layer 103 with respect to drain and source regions to be formed in a later stage of fabrication based on a deformed semiconductor material, into the recesses 103p is introduced. Furthermore, in some illustrative embodiments, the implantation variety includes 108a a dopant for forming at least a portion of drain and source regions, such as an expansion region, to thereby provide additional implantation steps in a later manufacturing stage after providing a deformed semiconductor material in the recesses 103p to avoid. In other illustrative embodiments, corresponding drain and source extension regions are made in an early manufacturing stage, for example, before or after deposition of the spacer layer 104a this being from the initial one Layer thickness depends. In still other illustrative embodiments, the implantation variety includes 108a corresponding components, such as nitrogen, carbon and the like, which lead to a lower diffusion activity of a corresponding dopant species, such as boron, which is provided in a later manufacturing phase. In this way, the finally achieved pn junctions of the drain and source regions can be better accurately based on one or more components of the implantation species 108a be formed. The level of leakage through the pn junctions still to be formed may also be based on the implantation variety 108a can be adjusted, resulting in a very efficient stabilization of the threshold voltage of the transistor 105p in terms of effects of the floating body is achieved. During the implantation process 108 may be an unwanted implantation of the implantation variety 108a into the gate electrode material 151a through the spacers 104s and the topcoat 151c be suppressed or at least reduced. In embodiments in which the mask 105 has been removed in an early manufacturing stage, the appropriate shielding effect during a tilted implantation step of the process 108 be reduced.
  • 1e schematically shows the semiconductor device 100 during a selective epitaxial growth process 109 performed on the basis of well-established process recipes to selectively deposit a semiconductor alloy on exposed surfaces of the recesses 103p (please refer 1d ), while substantially avoiding significant deposition of material on dielectric surface areas. During the growth process 109 For example, silicon / germanium is deposited with a desired amount of germanium, such that growth on the silicon layer 103 a deformed state is reached, the size of which depends on the proportion of germanium. For example, about 15 to 35 atomic percent germanium may be incorporated into the silicon germanium alloy to form a deformed semiconductor material 153P to build. It should be noted that in other illustrative embodiments, in addition to or as an alternative to germanium, other atomic species having a larger covalent radius may be used compared to silicon, such as tin, also incorporated in the material 153P can be installed. In this case, a significantly smaller proportion of non-silicon material can be incorporated, but still a desired difference of the natural lattice constant of the material 153P with respect to the surrounding stencil material of the layer 103 is reached. In some illustrative embodiments, during the growth process 109 also a dopant species in the material 153P incorporated, such as boron, in order to avoid further implantation processes or to reduce these with regard to the implantation dose, so that caused by implantation damage of the material 153P be kept low. Thereafter, the further processing is continued by the mask 105 is removed, which can be accomplished by well established selective etching recipes, using, for example, hot phosphoric acid, whereby the mask 105 is efficiently removed when it is made of silicon nitride, this selective to etch stop layer 104b takes place, including the spacers 104s and the topcoat 151c in the transistor 150p be removed.
  • 1f schematically shows the semiconductor device 100 after the process sequence described above. The component 100 is also the action of an etching environment 110 For selective removal of the exposed etch stop layer 104b is configured while the spacer layer 104a is maintained. For this purpose, well-established selective etching recipes, for example based on hydrofluoric acid (HF) can be used. Subsequently, another etching process is performed to remove the exposed spacer layer 104a selectively etch, as well as with respect to the etching process 106 (please refer 1c ) is explained.
  • 1g schematically shows the semiconductor device 100 after the previously described process sequence with another mask 111 that the first transistor 150p covering, while the second transistor 150n the gate electrode structure 151 , now spacer elements 104r due to the previously performed anisotropic etching process. The mask 111 may be constructed of silicon nitride or other material that is compatible with further processing.
  • 1h schematically shows the semiconductor device 100 during an etching process 112 based on similar process parameters as the etching process 107 (please refer 1d ) can be performed. That is, process parameters and etch chemistry of the etch process 112 be according to a desired size and shape of recesses 103n set adjacent to the gate electrode structure 151 be generated, the spacers 104r protect the side length of it and also a distance of the recesses 103n to the canal area 152 define, as similar in connection with the first transistor 150p is explained. Consequently, the size and shape of the recesses 103n regardless of a size and shape of the corresponding recesses 103p (please refer 1d ). Further, in some illustrative embodiments, an implantation process or sequence 113 performed to one or more implantation varieties 113a through exposed Surface areas of the recesses 103n introduce. Also in this case, the implantation process 113 include one or more implantation steps having a non-zero tilt angle to suitably select the one or more implantation varieties 113a to arrange. For example, a counter-doped region is formed, or a dopant species or other implantation species, such as a non-doping species in the form of carbon, nitrogen, and the like, are incorporated to adjust the overall electronic properties, for example with respect to leakage currents and the like, as well also previously with respect to the transistor 105p It should be noted that due to the different conductivity type of the transistors 150n and 150p the implantation process 113 away from the corresponding process 108 (please refer 1d ) in relation to the implantation parameters and implantation variety.
  • 1i schematically shows the semiconductor device 100 during another selective epitaxial growth process 114 which is designed to be a deformed semiconductor material 153n is deposited. In another illustrative embodiment, the semiconductor material includes 153n a silicon / carbon alloy that has a natural constant that is less than the lattice constant of silicon, thus growing up in a tensile state that results in a tensile strain in the adjacent channel region 152 leads. For example, a suitable amount of carbon material in the silicon material becomes the deposition environment 114 for example, one to several atomic percent, depending on the desired degree of tensile stress and other electronic properties of the drain and source regions present in the second transistor 150n are to be formed. As indicated previously, a suitable dopant species, ie, an n-type, can be incorporated into the material 153n during the growing process 114 can be installed in order to avoid further implantation processes or at least the degree of ion bombardment during subsequent implantation processes to form the finally desired dopant profile for the second transistor 150n to reduce. After the selective epitaxial growth process 114 For example, an etching process, for example based on hot phosphoric acid and the like, is carried out around the mask 111 and the spacers 104r and the topcoat 151c to remove.
  • 1j schematically shows the semiconductor device 100 after the process sequence described above. Thus, the gate electrode structures 151 both transistors 150p . 150n exposed before further processing of the device 100 begins, while in other embodiments, as indicated by the dashed line, a protective layer 115 , such as a silicon dioxide layer and the like, is provided before further fabrication processes to complete the transistors 150p . 150n be executed.
  • 1k schematically shows the semiconductor device 100 in a more advanced manufacturing phase. As shown, there are drain and source regions 154 adjacent to the canal area 152 formed, wherein the drain and source regions 154 at least a portion of the deformed semiconductor material 153P respectively. 163N exhibit. That is, depending on the component requirements, the deformed materials become 153n . 153P completely in the drain and source areas 154 as also shown, which can be accomplished by incorporation of a high concentration of the corresponding dopant species and by performing a bake process to initiate diffusion of the dopant species. In other cases, some of the pn junctions extend 154P by the deformed semiconductor material, at least in one of the transistors 150p . 150n , It should be noted that, as previously related to the implantation processes 108 (please refer 1d ) and 113 (please refer 1h ) which explains the additional implantation variety 108a and or 110a can be present, for example, the total transistor characteristics with respect to the leakage current in the pn junctions 154P to adjust the dopant gradient, for example, by reducing the overall diffusion activity of dopant species, such as boron, thus resulting in a better confinement of the dopant species and thus to better defined drain and source regions 154 for the transistor 150p leads, which represents, for example, a p-channel transistor.
  • The semiconductor device 100 further comprises a spacer structure 156 adjacent to the gate electrode material 151a is formed, wherein the spacer structure 156 several individual spacer elements 156a . 156b may have depending on the process and Bauteilerfodernissen. For example, the drain and source areas become 154 at least for one of the transistors 150p 150n adjusted based on further implantation processes during which the respective spacer elements 156a . 156b serve as implantation masks. In other illustrative embodiments, additional implantation processes are substantially avoided after the deformed semiconductor materials 153P respectively. 153n are made so that the degree of lattice damage in these materials remains low. In this case, the spacer structure becomes 156 designed to be a mask for the production of a metal silicide region 155 in a self-aligned manner. In some illustrative embodiments, the spacer structure 156 a high internal stress level, which improves the transistor behavior of one of the transistors 150p . 150n suitable is.
  • For example, the spacer structure has 156 a high tensile stress level, causing additional deformation in the channel region 152 of the transistor 150n is taken care of. On the other hand, a negative influence of the internal stress level in the transistor 150p be overcompensated by additional stress-inducing mechanisms, such as strain-inducing dielectric layers 116 and 117 , which are provided with a high internal tensile stress or compressive stress. For example, silicon nitride with high internal stress can be applied depending on the corresponding process parameters of a plasma enhanced CVD technique. For example, stress levels up to a GPA and higher are achieved for a tensile strained silicon nitride material, while stress levels up to 2 GPa and higher are achieved for a compressively strained silicon nitride material. By providing a high internal compressive stress level in the layer 117 Thus, an internal tensile stress of the spacer structure 156 in the transistor 150p be compensated. In other illustrative embodiments, a compressive stress level in the spacer structure becomes 156 generated when another significant power increase in the transistor 150p he wishes.
  • This in 1k shown semiconductor device 100 can be made on the basis of the following processes. The drain and source areas 154 are formed, for example, by ion implantation to produce shallow drain and source extension regions (not shown), wherein the damage caused by implantation in the materials 153P . 153n less pronounced. In other cases, as previously explained, corresponding extension regions may be provided prior to growing the materials 153P respectively. 153n be formed. If necessary, further implantation processes are carried out to incorporate additional dopant species and / or the appropriate dopant species became during the growth processes for the materials 153P . 153n built-in. Suitable anneal processes may then be performed to achieve the desired dopant profile for the drain and source regions 154 including the corresponding implantation varieties 113a . 108a allow a more precise control of the finally achieved electronic properties. Then the metal silicide areas become 155 prepared according to well-established techniques, wherein the spacer structure 156 can serve as a silicidation mask. Below are the layers 116 and 117 deposited, wherein one or both layers can have a high internal stress level, as explained above, which can be achieved on the basis of corresponding structuring schemes in which one of the layers 116 . 117 deposited and subsequently from one of the transistors 150p . 150n is removed, what is the deposition of the other of the two layers 116 . 117 connects and removing this layer from the other transistor 150p . 150n follows.
  • Consequently, the deformed semiconductor materials 153P . 153n based on selective epitaxial growth techniques, with suitable mask and etch stop layers, such as the layers 104a . 104b (please refer 1a ), possibly in conjunction with the incorporation of a suitable implant variety, such as the varieties 113a . 108a so that improved electronic properties and deformation conditions are provided, as also explained above.
  • Thus, the present invention provides a method of fabricating semiconductor devices incorporating deformed semiconductor materials such as silicon germanium and the like on the one hand and silicon carbon on the other hand into the drain and source regions based on a very efficient manufacturing process in conjunction with additional implant varieties to the overall transistor properties.

Claims (11)

  1. Method for producing a deformed semiconductor material in a first transistor ( 150p ) of a first conductivity type and in a second transistor ( 150n ) of a second conductivity type, the method comprising: forming a layer stack ( 104 ) over a first gate electrode structure ( 151 ) of the first transistor ( 150p ) and over a second gate electrode structure ( 151 ) of the second transistor ( 150n ), wherein the first and the second gate electrode structure ( 151 ) a corresponding cover layer ( 151c ) and wherein the layer stack ( 104 ) a spacer layer and an etch stop layer ( 104b ) above the spacer layer ( 104a ) is formed; Forming a mask ( 111 ) over the second transistor ( 150n ) and over the etch stop layer ( 104b ); Forming a first spacer element on the first gate electrode structure ( 151 ) from the spacer layer ( 104a ); Forming first recesses ( 103n ) in drain and source regions of the first transistor ( 150p ) using the first spacer element as a mask; Introducing one or more first implant varieties into exposed surface areas of the first recesses ( 103n ); Forming a first deformed semiconductor material ( 153n ) in the first recesses ( 103n ); Forming second recesses ( 103p ) in drain and source regions of the second transistor ( 150n ) using a second spacer element consisting of the spacer layer ( 104a ) is formed as a mask; and forming a second deformed semiconductor material ( 153P ) in the second recesses ( 103p ), wherein the first and the second deformed semiconductor material ( 153n . 153P ) have a different material composition.
  2. The method of claim 1, wherein the one or more first implant varieties comprise a non-doping species for modifying a diffusion behavior of a dopant species of drain and source regions of the first transistor. 150p ) exhibit.
  3. The method of claim 1, wherein the one or more first implant varieties comprise a dopant species to form drain and source regions of the first transistor. 150p ) exhibit.
  4. The method of claim 1, further comprising: introducing one or more second implant varieties into exposed surface areas of the second recesses ( 103p ).
  5. The method of claim 4, wherein the one or more second implant varieties comprise a non-doping species.
  6. The method of claim 4, wherein the one or more second implantation species comprises a dopant species to form drain and source regions of the second transistor. 150n ) exhibit.
  7. The method of claim 1, wherein forming the second recesses ( 103p ) comprises: forming a second mask over the first transistor ( 150p ), Removing the etch stop layer ( 104b ) from above the second transistor ( 150n ) and forming the second spacer element.
  8. The method of claim 4, wherein the first deformed semiconductor material ( 153n ) by a first selective epitaxial growth process and the second deformed semiconductor material ( 153P ) is formed by a second epitaxial growth process.
  9. The method of claim 1, further comprising: forming one or more stress-inducing spacer elements on sidewalls of the first and second gate electrode structures. 151 ) after forming the first and second deformed semiconductor materials ( 153P ).
  10. The method of claim 1, further comprising: forming a first strain-inducing layer over the first transistor ( 150p ) and forming a second strain-inducing layer over the second transistor ( 150n ), wherein the first and second strain-inducing layers exhibit a different type of strain in channel regions of the first and second transistors ( 150n ) cause.
  11. The method of claim 1, wherein the first deformed semiconductor material ( 153n ) a silicon / germanium alloy and the second deformed semiconductor material ( 153P ) has a silicon / carbon alloy.
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Publication number Priority date Publication date Assignee Title
US20070018252A1 (en) * 2005-07-21 2007-01-25 International Business Machines Corporation Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same
DE102006015087A1 (en) * 2006-03-31 2007-10-11 Advanced Micro Devices, Inc., Sunnyvale A method of fabricating buried drain / source regions based on a process of combined spacer etch and recess etching
US20070252204A1 (en) * 2006-04-28 2007-11-01 Andy Wei Soi transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070018252A1 (en) * 2005-07-21 2007-01-25 International Business Machines Corporation Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same
DE102006015087A1 (en) * 2006-03-31 2007-10-11 Advanced Micro Devices, Inc., Sunnyvale A method of fabricating buried drain / source regions based on a process of combined spacer etch and recess etching
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