DE102008060372B4 - Method for producing a silicon carbide epitaxial layer and a silicon carbide component - Google Patents

Abstract

A method for producing a silicon carbide epitaxial layer on a silicon carbide substrate, comprising the steps of: providing (100) a monocrystalline silicon carbide substrate having a (0001) - or misorientation

Description

The present invention relates to a method of manufacturing a silicon carbide epitaxial layer on a silicon carbide substrate and to a silicon carbide device having a silicon carbide epitaxial layer that has a low basal area dislocation density.

The outstanding material properties of silicon carbide, such. B. its large band gap allows in silicon carbide (SiC) devices to achieve significantly higher operating temperatures than in components of conventional semiconductors. The heat loss of a SiC device can be dissipated better than in conventional semiconductor devices because of the high thermal conductivity of SiC. Due to the larger band gap can also achieve much higher blocking voltages than conventional semiconductor devices. For this reason, silicon carbide, for example, for power semiconductors and high-temperature electronic components is a promising manufacturing material.

For the production of silicon carbide components, such. B. of SiNi diodes of silicon carbide (SiC), n- and p-type epitaxial layers are needed, which should have the lowest possible number of crystal defects.

Such silicon carbide diodes z. B. used in high voltage applications, can be designed for reverse voltages (V _Br ) of more than 3 kV. During operation, current loads of several 100 A / cm ² may occur in such diodes. The electrical characterization of such silicon carbide diodes can show that after a current load of 100 A / cm ² for a period of 30 minutes some of these diodes have an unstable current-voltage behavior in the forward characteristic curves (V _F drift). On the other hand, other diodes built on the same silicon carbide substrate can not exhibit this unstable behavior. The cause of this unstable current-voltage behavior may be specific defects in the silicon carbide substrate and the propagation of these defects into the epitaxial layer of the silicon carbide device; and the emergence of new defects during the deposition of the silicon carbide epitaxial layer.

An example of the complex interaction between crystal defects and the reliability of silicon carbide devices is so-called basal plane dislocations (BPD). It is known that these dislocations can significantly affect the long-term stability of (bipolar) devices. The basal surface dislocations may already arise during the production of the base material during crystal growth. Typically, a silicon carbide wafer has a basal plane dislocation density on the order of about 10,000 cm ^-2 . During operation of the component, this type of crystal defect, ie the basal plane displacement, can be converted into a new defect, which is much more critical in terms of its electrical properties. This new type of defect can be a stacking fault, which can then lead to a degradation of the component under current load. As a result, for example, the above-mentioned instabilities of the silicon carbide devices can be caused.

In the US patent US Pat. No. 7,018,554 B2 For example, a method is described in which such basal plane dislocations in the active zone of a device can be reduced or eliminated. However, the process shown in the above patent is relatively costly and time consuming. According to the method of the above patent, the epitaxial layers for the silicon carbide device are deposited on silicon carbide substrates whose (0001) surface has a misalignment of 8 ° in the <11-20> direction. The wafer, ie the silicon carbide substrate, is immersed in molten potassium hydroxide (KOH) before the subsequent epitaxy. As a result, on the surface of the silicon carbide substrate, the defects such. B. dislocations and microtubes etched selectively. This is followed by the generation of a thick epitaxial layer, which then has a smaller number of basal area dislocations (BPD). The generation of the epitaxial layer can be effected by means of a chemical vapor deposition (CVD). By etching the silicon carbide wafer with potassium hydroxide, the wafer surface is heavily roughened. This roughness of the wafer surface can be transferred to the epitaxial layer, so that the epitaxial layer with this surface is not suitable for further processing. According to the method of the above patent, this epitaxial layer must be chemo-mechanically polished (CMP) so as to obtain an epitaxial-capable surface in so-called "epi-ready" quality. In order to make this possible, it may be necessary to deposit the epitaxial layer with a thickness of at least 30 μm.

In the publication by Friedrich et al. (Influence of Substrate Preparation and Epitaxial Growth Parameters on the Dislocation Defects in 4H-SiC Epitaxial Layers, Conference on Silicon Carbide and Related Materials 2007), the influence of substrate preparation and epitaxial growth parameters on basal plane dislocation density is investigated.

In the publication by Shrivastava et al. (Study of triangular effects and inverted pyramids in 4H-SIC 4 ° cut-off (0001) Face Epilayers J. Crystal Growth 310 (2008) 4443-4450) is a method for growing a silicon carbide epitaxial layer on a silicon carbide substrate with a (0001) surface showing 3.5 ° -4 ° in [11 2 0] Direction is inclined. Corresponding growth parameters which are responsible for the development of defects are identified and optimized.

The patent JP 2008 004 888 A also shows a method of producing a silicon carbide epitaxial layer with a small number of dislocation errors.

The publication by Wada et al. (Epitaxial growth of 4H-SiC on 4 ° off-axis (0001) and (000 1 ) substrates by hot - wall chemical vapor deposition. J. Crystal Growth 291 (2006) 370-374) describes the growth of a 4H-SiC epitaxial layer on a tilted by 4 ° (0001) and (000 1 ) Substrate at different growth conditions using a hot wall CVD plant.

In the US 4,912,064 is the production of epitaxially grown α-SiC films, which are suitable for the production of electronic components described. There is described a high degree of freedom in terms of growth parameters so as to adjust growth rate, surface morphology or other film characteristics.

In the WO 2007 100 364 A1 is a silicon carbide epitaxial layer PiN diode for high-power applications described.

In order to facilitate the market introduction of (bipolar) silicon carbide components, it is desirable to produce silicon carbide epitaxial layers with a low basal area dislocation density, inexpensively, with little expenditure of time and in as few process steps as possible.

The object of the present invention is to provide a method for producing a silicon carbide epitaxial layer on a silicon carbide substrate having a low basal plane dislocation density and, based thereon, to provide silicon carbide components which have both a stable performance and a very low cost, relatively simple and can be realized with a small number of process steps.

This object is achieved by the method according to claim 1 and 13, as well as the silicon carbide component according to claim 22.

The finding of the present invention is that by combining the use of a silicon carbide substrate having a misorientation of the (0001) - or (000 1 )-Surface from 2 ° to 6 °, so for example 4 ° and special process parameters for the deposition of a silicon carbide epitaxial layer from the gas phase, despite a smaller number of manufacturing steps compared to conventional methods improved quality of the silicon carbide epitaxial layer can be achieved.

In embodiments, a method for producing a silicon carbide epitaxial layer on a silicon carbide substrate is shown. The method includes providing a silicon carbide substrate having a misorientation of (0001) - or the (000 1 )-Surface from 2 ° to 6 °. Further, the method comprises depositing a silicon carbide epitaxial layer from the gas phase having a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 μm / h to 30 μm / h.

The present invention further includes a method of manufacturing a silicon carbide device on a single crystal silicon carbide substrate by providing a single crystalline silicon carbide substrate having a misalignment of 2 ° to 6 ° and depositing two different conductive silicon carbide epitaxial layers of gas phase with a carbon / Silicon ratio of 0.6 to 1 and a growth rate of 5 .mu.m / h to 30 .mu.m / h, so that a PN junction zone is formed between the two differently conductive silicon carbide epitaxial layers.

The invention also provides a silicon carbide device having a silicon carbide epitaxial layer which has a basal plane dislocation density of less than 10 cm ^-2 . The silicon carbide epitaxial layer is disposed on a single crystal silicon carbide substrate having a misorientation of the surface of the silicon carbide substrate of 2 ° to 6 °.

Preferred embodiments are explained below with reference to the accompanying drawings.

Show it:

1 a flow diagram of the method for producing a silicon carbide epitaxial layer on a silicon carbide substrate according to an embodiment of the present invention;

2 a flowchart of the method for producing a silicon carbide device having a conductive silicon carbide epitaxial layer on a single-crystal silicon carbide substrate according to another embodiment of the present invention;

3a a silicon carbide epitaxial layer on a silicon carbide substrate according to an embodiment of the present invention;

3b a PN silicon carbide diode having a first silicon carbide epitaxial layer on a silicon carbide substrate and a second silicon carbide epitaxial layer disposed immediately above the first silicon carbide epitaxial layer and wherein the first and second silicon carbide epitaxial layers have a different conductivity type; that a PN junction zone is formed;

3c a PiN silicon carbide diode according to another embodiment of the present invention; and

3d a silicon carbide MOSFET according to another embodiment of the present invention.

Before referring to the drawings, the present invention will be explained in more detail by means of exemplary embodiments, it is pointed out that the same elements or similar elements in these figures are given the same or similar reference numerals, and a repeated description of these elements is avoided.

1 FIG. 10 shows a flowchart of the method for producing a silicon carbide epitaxial layer on a silicon carbide substrate according to an embodiment of the present invention. The method has a provision 100 a monocrystalline silicon carbide substrate with a misorientation of the (0001) surface or the (000 1 )-Surface of the silicon carbide substrate from 2 ° to 6 °. Furthermore, the method has a deposition 110 a gas phase silicon carbide epitaxial layer having a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 μPm / h to 30 μm / h.

The surface can therefore at an angle of 2 ° to 6 ° relative to the (0001) - or the (000 1 )-Surface be tilted. For example, the surface may be tilted in the direction of one of the <11-20> crystal directions.

In a monocrystalline silicon carbide crystal, each atom is surrounded by 4 atoms of the other element, so that a tetrahedral structure can be formed. Silicon carbide (SiC) has a polytype, i. H. it exists in different crystal structures. In all previously known polytypes of silicon carbide, each silicon atom is linked by atomic bonding with 4 carbon atoms and vice versa.

The so-called cubic phase β-SiC with a layer sequence ABC - hence also called 3C (cubic) - crystallizes in a zincblende structure. Other polytypes of the silicon carbide have a hexagonal or rhombohedral structure, for example 15R (rhombohedral) silicon carbide, 21R silicon carbide, etc. For the production of silicon carbide components, the polytypes 4H (hexagonal) silicon carbide with the layer sequence ABCB, 6H (hexagonal) are frequently used. Silicon carbide with the layer sequence ABCACB, as well as the above-mentioned 3C and 15R modification application. In the crystal modification of the 4H silicon carbide, the cubic changes with the hexagonal stack shape, and the crystal modification 6H silicon carbide is followed by a hexagonal stack shape after every two cubic stacked layers. Other known modifications of the silicon carbide are, for example, 2H, 8H and 9R.

Thus, for example, in accordance with some embodiments of the present invention, a 4H silicon carbide substrate or a 6H silicon carbide substrate may be provided wherein the silicon carbide substrate has a misorientation of its (0001) or (000 1 )-Surface from 2 ° to 6 °, from 3 ° to 5 ° or for example from 4 °. The misorientation can z. B. with respect to the crystal direction <10 1 0> or <11- 2 0> Be pronounced.

For example, according to an embodiment of the present invention, misorientation may be 4 ° to the <11-20> direction of the silicon carbide substrate. According to embodiments of the present invention, if the (0001) surface is used, this surface is terminated with silicon atoms. When using the back, so the (000 1 )-Surface, this is terminated by carbon atoms.

Basal plane dislocations may be located in the so-called c-plane of the SiC crystal given by the stacking direction (c-axis). If such basal plane dislocations lying in the basal plane (c-plane) intersect the surface of a silicon carbide substrate, then the dislocation may be transferred to a subsequent epitaxial growth layer at these sites. This should be prevented as far as possible, since, as already mentioned above, these basal surface dislocations can lead to stacking faults and these can lead to a degradation of a silicon carbide component at current load. In addition to the basal surface dislocations, silicon carbide single crystals contain other crystal defects such as stacking faults, microtubes, screw dislocations, Polytype inclusions, as well as other crystal defects known from crystallography or disorders.

The separation 110 A silicon carbide epitaxial layer on a single crystal silicon carbide substrate may be made of the gas phase having a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 μm / h to 30 μm / h.

The chemical vapor deposition (CVD) technique can be used to deposit the silicon carbide epitaxial layer. The chemical vapor deposition can be carried out in a CVD reaction chamber. It is at the heated surface of a substrate in the reaction chamber, ie z. B. the silicon carbide substrate due to a chemical reaction from the gas phase, the epitaxial silicon carbide deposited or grown. For example, chlorine-containing carbon silanes with the basic chemical formula C _n H _{2n + 1} Si _n Cl _{2n + 1} can be used as starting materials or precursor substances for the deposition of the silicon carbide epitaxial layer.

For example, in embodiments of the present invention, propane (C ₃ H ₈ ) and silane (SiH ₄ ) may also be used as starting materials for depositing silicon carbide epitaxial layers by CVD technique. In general, the use of silanes with the sum formula Si _n H _{2n + 2 is} conceivable. At a temperature which is important for the epitaxial deposition, the silane and the propane can then decompose in the CVD chamber and the silicon carbide epitaxial layer form or deposit on the monocrystalline silicon carbide substrate.

The quality of the silicon carbide epitaxial layer and thus, for example, the basal plane dislocation density depends not only on the exact misorientation of the silicon carbide substrate but also on the exact process parameters or process parameter ranges and the corresponding settings for the deposition of the silicon carbide epitaxial layer on the silicon carbide substrate.

According to the method of the invention, a very low basal area dislocation density can now be achieved by using a silicon carbide substrate with a misalignment of 2 ° to 6 ° and by applying optimized epitaxial process parameters or epitaxial layer deposition process parameter areas.

According to some embodiments of the present invention can now from the gas phase, the silicon carbide epitaxial layer, for example by means of CVD method with a carbon / silicon ratio of 0.6 to 1, from 0.7 to 0.8, or z. B. of 0.75 can be deposited. The growth rate can be 5 .mu.m / h to 30 .mu.m / h, 6 .mu.m / h to 10 .mu.m / h, or z. B. 7 microns / h. Starting materials for the silicon carbide epitaxy may be, for example, silane and propane. In embodiments of the present invention, the deposition 110 the silicon carbide epitaxial layer from the gas phase at a temperature of 1550 ° C to 1650 ° C or at a temperature of 1580 ° C to 1620 °, ie z. B. at 1600 ° C. In further embodiments of the present invention, the deposition 110 further at a pressure of 50 hPa to 200 hPa, from 100 hPA to 150 hPA, or z. B. at 125 hPA. The total gas flow can be 40 l / min to 70 l / min, 50 l / min to 65 l / min, ie z. B. 60 l / min.

In some embodiments, the method of forming a silicon carbide epitaxial layer on a silicon carbide substrate may be accomplished by providing 100 a monocrystalline silicon carbide substrate having a defect orientation of the (0001) surface or the (000 1 )-Surface of the silicon carbide substrate from 2 ° to 6 ° and by the deposition 110 the silicon carbide epitaxial layer has a basal area dislocation density of less than 50 cm ^-2 or less than 10 cm ^-2 . According to some embodiments, the method described above can also achieve a basal area dislocation density in the silicon carbide epitaxial layer of less than 3 cm ^-2 .

In the method according to the invention, it is possible, for example, to use a silicon carbide substrate which has a p or n line and a corresponding doping. For a p-type line, the silicon carbide substrate or the silicon carbide epitaxial layer may have the typical doping atoms boron (B), aluminum (Al) or indium (In). For the n-type conductivity, the silicon carbide, that is to say the substrate and the epitaxial layers, can be doped, for example, with phosphorus (P), arsenic (As), antimony (Sb) or nitrogen (N). Of course it is also conceivable doping with other atoms or ions to produce a corresponding p or n-line. For doping the silicon carbide epitaxial layers and the silicon carbide substrate common in semiconductor technology methods such. B. use of gaseous precursors during the sublimation of the crystal or the epitaxy process, diffusion, ion implantation can be used.

The silicon carbide substrate layer may be an n-type or p-type semiconductive or conductive layer. The separation 110 can now be carried out according to an embodiment of the present invention so that the silicon carbide epitaxial layer is also conductive or has semiconducting properties. A second conductive silicon carbide epitaxial layer can now be deposited onto this first conductive or semiconducting silicon carbide epitaxial layer in accordance with a further exemplary embodiment of the present invention. The deposition may be performed such that the second silicon carbide epitaxial layer has a different doping density from the (first) silicon carbide epitaxial layer. That is, the conductivity or doping density in the first and second silicon carbide epitaxial layers may be different. Thus, for example, a silicon carbide epitaxial layer may have an n ⁺ doping and the second silicon carbide epitaxial layer an n ^- doping.

According to another embodiment of the present invention, the deposition 110 may be performed such that a second silicon carbide epitaxial growth layer is grown on the first silicon carbide epitaxial growth layer, the second silicon carbide epitaxial growth layer having a conductivity type having a conductivity type opposite to the first silicon carbide epitaxial layer. In other words, therefore, for example, the first silicon carbide epitaxial layer can have p-type conduction and the second silicon carbide epitaxial layer can have n-type conduction, or vice versa. It is thus possible to form a pn junction or a pn junction zone between the two silicon carbide epitaxial layers.

In some embodiments of the present invention, it is not necessary to immerse the wafer or silicon carbide substrate in molten potassium hydroxide. Also, no intermediate epitaxial layer needs to be produced, which is then polished back by chemical mechanical polishing (CMP) to achieve a surface in so-called "epi-ready" quality.

In some embodiments of the present invention, the providing 100 be carried out such that an epitaxial ready ("epi-ready"), single-crystal silicon carbide substrate is immediately provided and then the deposition of the silicon carbide epitaxial layer is performed with the epitaxy process parameters mentioned above without intermediate steps. According to some embodiments of the present invention, by using a silicon carbide substrate having a misorientation of the (0001) surface (000 1 )-Surface from 2 ° to 6 °, a reduction of the basal plane dislocation density by about two orders of magnitude can be achieved. For example, at a typical basal plane dislocation density of 10,000 per cm ² in the wafer, a reduction to 100 per cm ² can be achieved. For epitaxy, the misorientation of the silicon carbide substrate can be reduced from 8 ° to 4 °. Using 8 ° misoriented silicon carbide wafers, the basal plane dislocation density in the epitaxial layer is reduced by about an order of magnitude. On the other hand, if 4 ° defect-oriented wafers are used, they are reduced by about two orders of magnitude. The misorientation of the substrate can thus in embodiments of the present invention, for. B. 4 °.

Further, by adjusting the available epitaxial process parameters, a generated silicon carbide epitaxial layer, which may serve as an active layer in, for example, a silicon carbide device, may have few or no basal plane dislocations. For example, in one embodiment, the deposition of the silicon carbide epitaxial layer or deposition of silicon carbide epitaxial layer sequences may be performed such that the carbon / silicon (C / Si) ratio in the gas phase is 0.75 and the growth rate is 7 μm / h. The layer growth of the silicon carbide epitaxial layer can be carried out, for example, at a temperature of 1600 ° C. and at a pressure of 125 hPa with a total gas flow of 60 l / min. In accordance with some embodiments of the present invention, a basal plane dislocation density of less than 3 cm ^-2 can then be achieved in the epitaxial layer. The basal area dislocation density in the silicon carbide epitaxial layer is then comparable to or less than that of substrates etched with potassium hydroxide prior to epitaxial growth and where, after depositing and repolishing an interlayer, the actual silicon carbide epitaxial layer has been deposited.

In 2 FIG. 4 is a flowchart of the method for manufacturing a silicon carbide device having a conductive silicon carbide epitaxial layer on a single crystal silicon carbide substrate according to another embodiment of the present invention. The method has a step of providing 100 , a monocrystalline silicon carbide substrate with a misorientation of the (0001) - or (000 1 )-Surface from 2 ° to 6 °. Furthermore, the method has a deposition 110a an n-type silicon carbide epitaxial layer from the gas phase, with a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 .mu.m / h to 30 .mu.m / h on. In a further step, the method has a deposition 110b a p-type second silicon carbide epitaxial layer on the n-type silicon carbide epitaxial layer from the gas phase, with a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 .mu.m / h to 30 .mu.m / h. Thus, a pn junction zone can form between the p-type and the n-type silicon carbide epitaxial layer.

In a further embodiment of the present invention, the deposition 110a be performed so that a p-type silicon carbide epitaxial layer is formed, and the deposition 110b can be performed so that a second n-type silicon carbide epitaxial layer is formed on the then p-type silicon carbide epitaxial layer.

Deploying 100 According to one embodiment, it may be carried out such that the monocrystalline silicon carbide substrate has a misorientation in the direction <11-20>. Deploying 100 For example, according to some embodiments, the silicon carbide substrate may be an epitaxial ("epi-ready") silicon carbide substrate. The separation 110a . 110b The n- or p-type silicon carbide epitaxial layers can each be carried out at a temperature of 1550 ° C to 1650 ° C, a pressure of 50 hPa to 200 hPa and a total gas flow of 5 l / min to 70 l / min. In the silicon carbide substrate used in the step of providing 100 used to deposit the silicon carbide epitaxial layer may be an n-type silicon carbide substrate, but may also be a p-type silicon carbide substrate. In other embodiments, the silicon carbide substrate may also be an insulating or semi-insulating substrate.

For producing a silicon carbide component, such as. For example, a PN diode, a Schottky diode, a PiN diode, an insulated gate bipolar transistor (IGBT) or a field effect transistor (FET), it may also be necessary, a deposition 120 conduct a conductive contact on a surface of the p- or n-type silicon carbide epitaxial layer or the substrate. The separation 120 a conductive contact, for example, be carried out so that a metal such. As aluminum (Al), nickel (Ni), titanium (Ti), platinum (Pt), gold (Au), silver (Ag) or an alloy of these metals is applied to a contact region of the SiC. Also conceivable is the deposition of conductive polysilicon or other conductive contact materials. For this purpose, the common in semiconductor technology methods can be used, such. Sputtering, vapor deposition, as well as chemical (CVD) or any other physical vapor deposition (PVD) process. After the application of the contact, a tempering step can furthermore take place.

By the method described above, both bipolar silicon carbide devices and unipolar silicon carbide devices can be manufactured. For example, the method can be used to fabricate silicon carbide PiN diodes, PN diodes, Schottky diodes, insulated gate bipolar transistors (IGBT), bipolar transistors, or a junction field effect transistor (JFET). The field effect transistors may be, for example, a metal oxide semiconductor field effect transistor (MOSFET) or a metal-semiconductor field effect transistor (MESFET). The silicon carbide device may be a power device for power applications, such as power devices. B. a silicon carbide PiN diode with a reverse voltage of, for example, more than 3 kV.

Through the use of silicon carbide epitaxial layers, which were prepared according to some embodiments of the method described above, z. B. bipolar silicon carbide components are cheaper, faster and made with a higher reliability. By the production of silicon carbide epitaxial layers having a small basal area dislocation density enabled by the above method, the stability, for example, the SiC-PiN diodes, can be increased under current load and early degradation of the devices can be prevented.

The separation 120 Conductive contact on a surface of the silicon carbide substrate or the silicon carbide epitaxial layer can be carried out in such a way that forms a blocking Schottky contact or an ohmic contact. Depending on the doping and band gap of the SiC, titanium, Ni, Al, Pt, other metals or alloys of these metals can be used in a known manner, for example.

3a shows the schematic cross section of a silicon carbide component 1 with a silicon carbide epitaxial layer 5 wherein the silicon carbide epitaxial layer has a basal area dislocation density of less than 10 cm ^-2 and the silicon carbide epitaxial layer on a single crystal silicon carbide substrate 10 is arranged. The silicon carbide substrate 10 indicates a misorientation of the (0001) surface or the (000 1 )-Surface from 2 ° to 6 °. The misorientation of the surface from 2 ° to 6 ° may be for example 4 ° and be given in the direction <11-20>. In some embodiments, the c-axis may be tilted to the wafer surface by, for example, 2 ° to 6 °. According to a further exemplary embodiment of the present invention, the silicon carbide component 1 (please refer 3a ) be formed so that the silicon carbide epitaxial layer 5 directly on the monocrystalline silicon carbide substrate 10 is arranged. Ie. In this embodiment, there is no epitaxial interlayer between the silicon carbide substrate 10 and the actual active silicon carbide epitaxial layer 5 as for example in a production of the device after the above mentioned US patent would be necessary. The silicon carbide component 1 Thus, in this exemplary embodiment, it can be distinguished by the fact that the silicon carbide epitaxial layer 5 directly onto the "epi-ready" silicon carbide substrate layer 10 is applied.

As in the schematic cross-section in FIG 3b 1, the silicon carbide component may comprise a second silicon carbide epitaxial layer 7 on the first silicon carbide epitaxial layer 5 is arranged and the one, to the first silicon carbide epitaxial layer 5 having opposite conductivity type. Between the first silicon carbide epitaxial layer 5 and the second silicon carbide epitaxial layer 7 Thus, a pn transition zone can be formed. The silicon carbide substrate 10 For example, it may have a high n ⁺ doping while the silicon carbide epitaxial layer 5 has a lower n-type doping and the second silicon carbide epitaxial layer 7 a p-doping. The silicon carbide substrate 10 and the second silicon carbide epitaxial layer 7 may now have contacts (not shown in FIG 3b ), so that a PN diode is made of silicon carbide.

3c shows the schematic cross section of a PiN silicon carbide diode according to another embodiment of the present invention. In this embodiment, the first silicon carbide epitaxial layer 5 a zone 8th on, which has a lower doping than the rest of the layer 5 or has an intrinsic doping, so that a PiN diode is formed. In this embodiment are also schematically the metallic contacts 9a and 9b for the second silicon carbide epitaxial layer 7 and the silicon carbide substrate 10 shown. The intrinsic region 8th The first silicon carbide epitaxial layer in this example may have less or no n-doping than the remainder 5a the first silicon carbide epitaxial layer 5 , It may therefore also be an intrinsic SiC material.

In 3d is shown in accordance with another embodiment of the present invention, the schematic cross-sectional view of a silicon carbide MOSFETs. This silicon carbide device 1 may be a heavily n-doped SiC substrate 10 exhibit. The SiC substrate has a misorientation of the (0001) surface of 2 ° to 6 °. On this SiC substrate 10 may be a weakly n-type silicon carbide epitaxial layer 5 be arranged. This silicon carbide epitaxial layer has a basal plane dislocation density of less than 10 cm ^-2 . Arranged therein are double-diffused p-type wells 12 with heavily n-type regions 14 , The heavily n-type regions 14 serve as contact zones for the source or source connection 16 , An insulating layer 18 , z. B. a gate oxide is over the controllable channel 20 of the FET arranged. Above this is the control or gate electrode 22 of the FET arranged. The sink or drain connection 24 is on the SiC substrate 10 appropriate. In a SiC bipolar transistor, with a corresponding device configuration, the terminals would accordingly be referred to as collector, base and emitter terminals.

The scope of such SiC devices may, for. B. in the automotive sector, in industrial applications or in aerospace engineering. Such SiC devices can be used for high load switches.

In exemplary embodiments of the method for producing a silicon carbide epitaxial layer on a silicon carbide substrate or on the method for producing a silicon carbide component, it is shown that the use of, for example, 4 ° misoriented silicon carbide substrates and the deposition of a silicon carbide epitaxial layer According to optimized epitaxy process parameters on the SiC substrate several previously used technology steps, such. Example, the etching of the silicon carbide substrate with potassium hydroxide, the subsequent application of an intermediate epitaxial layer and the chemical mechanical polishing to produce an epi-ready surface can be omitted. In this case, a basal area dislocation density of less than 10 cm ^-2 can be achieved. This can advantageously lead to considerable cost and time savings for the production of silicon carbide epitaxial layers on a silicon carbide substrate and corresponding silicon carbide components. For example, in the fabrication of PiN diodes, the fabrication steps of external pretreatment of the wafer (etching), epitaxial growth of an interlayer, and back polishing of the epitaxial layer to obtain an "epi-ready" surface can be saved.

By using 4 ° misoriented silicon carbide substrate wafers, the basal plane dislocation density can be reduced by two orders of magnitude, whereas with a misorientation of the substrates of 8 ° this is only about an order of magnitude. According to an embodiment of the present invention, the silicon carbide epitaxial process parameters for depositing an epitaxial layer on the silicon carbide substrate may be adjusted so that the silicon carbide active layers or layer sequences produced involve little or no basal area dislocations. Silicon carbide devices manufactured by the above-described method of producing silicon carbide epitaxial layers may have, for example, basal plane dislocation densities of less than 10 cm ^-2 or even less than 3 cm ^-2 .

Claims (29)

Method for producing a silicon carbide epitaxial layer on a silicon carbide substrate, comprising the following steps: 100 ) of a monocrystalline silicon carbide substrate with a misorientation of the (0001) - or (000 1 )-Surface the silicon carbide substrate from 2 ° to 6 °; and deposition ( 110 ) of a gas phase silicon carbide epitaxial layer having a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 μm / h to 30 μm / h, wherein the deposition ( 110 ) at a temperature of 1550 ° C to 1650 ° C, at a pressure of 50 hPA to 200 hPA and at a total gas flow of 40 l / min to 70 l / min is performed. Method according to claim 1, wherein the deposition ( 110 ) in the silicon carbide epitaxial layer, a basal area dislocation density of less than 10 cm ^-2 and especially less than 3 cm ^{-2 is} obtained. Method according to one of claims 1 to 2, which comprises depositing ( 110 ) comprises a second conductive silicon carbide epitaxial layer on the silicon carbide epitaxial layer such that the second silicon carbide epitaxial layer has a different dopant concentration than the first silicon carbide epitaxial layer. Method according to one of Claims 1 to 3, in which the deposition ( 110 ) is performed so that the silicon carbide epitaxial layer is n- or p-type, and further comprising depositing ( 110 ) comprises a second conductive silicon carbide epitaxial layer on the n- or p-type silicon carbide epitaxial layer so that the second silicon carbide epitaxial layer has a conductivity type having a conductivity type opposite to the n- or p-type silicon carbide epitaxial layer. Method according to one of claims 1 to 4, wherein the providing ( 100 ) of a single-crystalline silicon carbide substrate is performed so as to provide a single-crystal n-type or p-type silicon carbide substrate. Method according to one of claims 1 to 5, wherein the providing ( 100 ) is performed so as to provide an epitaxial (epi-ready) monocrystalline silicon carbide substrate. Method according to one of Claims 1 to 6, in which the deposition ( 110 ) of a silicon carbide epitaxial layer is performed so that the silicon carbide epitaxial layer is n-type, and depositing a second conductive silicon carbide epitaxial layer is performed so that the second silicon carbide epitaxial layer is p-type to form a pn junction is formed between the conductive n-type silicon carbide epitaxial layer and the second conductive p-type silicon carbide epitaxial layer. Method according to one of claims 1 to 7, wherein the providing ( 100 ) is performed so that the single crystal silicon carbide substrate has a misorientation in the crystal direction <11-20>. Method according to one of Claims 1 to 8, in which the deposition ( 110 ) the silicon carbide epitaxial layer is carried out from the gas phase by chemical vapor deposition (CVD). Method according to one of Claims 1 to 9, in which the deposition ( 110 ) of a gas phase silicon carbide epitaxial layer having a carbon / silicon ratio of 0.75 and a growth rate of 7 μm / h. Method according to one of Claims 1 to 9, in which the deposition ( 110 ) in a temperature range of 1580 ° C to 1620 ° C, in a pressure range of 100 hPA to 150 hPA and at a total gas flow of 40 l / min to 65 l / min is performed. Method according to one of Claims 1 to 11, in which the deposition ( 110 ) at a temperature of 1600 ° C, at a pressure of 125 hPA and a total gas flow of 60 l / min. A method of manufacturing a silicon carbide device having a conductive silicon carbide epitaxial layer on a single crystal silicon carbide substrate, comprising the steps of: providing ( 100 ) of a monocrystalline silicon carbide substrate with a misorientation of the (0001) - or (000 1 )-Surface the silicon carbide substrate from 2 ° to 6 °; Separating ( 110a ) an n-type silicon carbide epitaxial layer of the gas phase, having a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 μm / h to 30 μm / h; and deposition ( 110b ) a p-type second silicon carbide epitaxial layer on the n-type silicon carbide epitaxial layer from the gas phase, having a carbon / silicon ratio of 0.6 to 1 and a growth rate of 5 .mu.m / h to 30 .mu.m / h, wherein the deposition ( 110a ; 110b ) of the n-type silicon carbide epitaxial layer and the p-type silicon carbide epitaxial layer each at a temperature of 1550 ° C to 1650 ° C, a pressure of 50 hPA to 200 hPA and a total gas flow of 40 l / min to 70 l / min is carried out. The method of claim 13, wherein the providing ( 100 ) is performed so that the single crystal silicon carbide substrate has a misorientation in the crystal direction <11-20>. Method according to one of claims 13 and 14, wherein the providing ( 100 ) of a single crystal silicon carbide substrate is performed so as to provide an n-type or a p-type silicon carbide substrate. A method according to any one of claims 13 to 15, further comprising depositing ( 120 ) has a conductive contact on a surface of an n- or p-type silicon carbide epitaxial layer. Method according to one of claims 13 to 16, wherein the silicon carbide component is a PiN diode, a PN diode, a Schottky diode, an insulated gate bipolar transistor (IGBT) or a field effect transistor (Field -Effect transistor (FET)). Method according to one of Claims 13 to 17, in which the silicon carbide component is a PiN diode with a blocking voltage greater than 3 kV. Method according to claim 13, in which the deposition ( 110a ) the n-type silicon carbide epitaxial layer is carried out from the gas phase, with a carbon / silicon ratio of 0.75 and a growth rate of 7 μm / h; and in which the deposition ( 110b ) of the p-type second silicon carbide epitaxial layer is performed on the n-type silicon carbide epitaxial layer from the gas phase with a carbon / silicon ratio of 0.75 and a growth rate of 7 μm / h. Method according to one of claims 13 to 19, in which the deposition ( 110a ; 110b ), the n-type silicon carbide epitaxial layer and the p-type silicon carbide epitaxial layer each in a temperature range of 1580 ° C to 1620 ° C, in a pressure range of 100 hPA to 150 hPA and a total gas flow of 40 l / min to 65 l / min is performed. Method according to one of Claims 13 to 20, in which the deposition ( 110a ; 110b ), the n-type silicon carbide epitaxial layer and the p-type silicon carbide epitaxial layer are each conducted at a temperature of 1600 ° C, a pressure of 125 hPa and a total gas flow of 60 l / min. Silicon carbide component ( 1 ) produced by the method according to one of claims 1 to 21, comprising: a silicon carbide epitaxial layer ( 5 ), with a basal plane dislocation density of less than 10 cm ^-2 and in particular less than 3 cm ^-2 , arranged on a monocrystalline silicon carbide substrate ( 10 ) with a misorientation of (0001) - or (000 1 )-Surface of the single-crystal silicon carbide substrate of 2 ° to 6 °. Silicon carbide component ( 1 ) according to claim 22, wherein the silicon carbide epitaxial layer ( 5 ) directly onto the monocrystalline silicon carbide substrate ( 10 ) is arranged. Silicon carbide component ( 1 ) according to one of claims 22 to 23, in which the silicon carbide substrate ( 10 ) has a misorientation in the crystal direction <11-20>. Silicon carbide component ( 1 ) according to one of claims 22 to 24, comprising a second silicon carbide epitaxial layer ( 7 ) deposited on the first silicon carbide epitaxial layer ( 5 ) and the one, to the first silicon carbide epitaxial layer ( 5 ), so that between the first silicon carbide epitaxial layer ( 5 ) and the second silicon carbide epitaxial layer ( 7 ) is formed a pn junction zone. Silicon carbide component ( 1 ) according to claim 25, wherein the second silicon carbide epitaxial layer ( 7 ) has a Basalflächenversetzungsdichte less than 10 cm ^-2 and in particular less than 3 cm ^-2 . The silicon carbide component ( 1 ) according to one of claims 22 to 26, wherein the silicon carbide component 1 ) is designed as a PiN diode, as a PN diode, as a Schottky diode, as an insulated gate bipolar transistor (IGBT), as a junction field effect transistor (JFET), as a MOSFET, as a MESFET or as a bipolar silicon carbide component , Silicon carbide component ( 1 ) according to one of claims 22 to 27, in which the monocrystalline silicon carbide substrate ( 10 ) has a higher doping than the silicon carbide epitaxial layer ( 5 ). Silicon carbide component ( 1 ) according to claim 22 with a misorientation of 4 °.

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